Electrostatic discharge circuit

Abstract

The embodiment of the invention discloses an electrostatic discharge circuit. The circuit comprises a first-stage protection circuit which is connected with a signal bonding pad and is used for protecting a human body model; the second-stage protection circuit is connected with the first-stage protection circuit and the signal port and is used for carrying out charging device model protection; the first-stage protection circuit and the second-stage protection circuit are not connected with the power line. According to the technical scheme, parasitic resistance introduced by long layout wiring in the electrostatic discharge circuit can be avoided, the electrostatic discharge protection performance can be improved, the circuit layout can be simplified, and the chip area can be optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic discharge protection circuits, and in particular to an electrostatic discharge circuit. Background Art

[0002] Electrostatic Discharge (ESD) is a circuit used to protect electronic devices from damage caused by electrostatic discharge.

[0003] The existing electrostatic discharge circuit design needs to be connected to the power port. Generally, the chip has more IO pins and fewer power supply pins, which will cause the power port of the IO port electrostatic discharge protection circuit to be connected to the chip power pad or contact through a long line. The line will introduce parasitic resistance. When electrostatic discharge occurs, ampere-level current will flow through the parasitic resistance, thereby introducing additional potential difference in the discharge path, thereby deteriorating the electrostatic discharge protection performance. Usually, the layout needs to have as small a wiring resistance as possible, which brings challenges to the layout wiring and chip area. Summary of the invention

[0004] The present invention provides an electrostatic discharge circuit to solve the parasitic resistance introduced by the long wiring of the layout and improve the electrostatic discharge performance.

[0005] According to one aspect of the present invention, there is provided an electrostatic discharge circuit, comprising:

[0006] A first level protection circuit, the first level protection circuit is connected to the signal pad and is used for human body model protection;

[0007] A second-level protection circuit, the second-level protection circuit is connected to the first-level protection circuit and the signal port, and is used for charging device model protection;

[0008] The first-level protection circuit and the second-level protection circuit are not connected to a power line.

[0009] Optionally, the first level protection circuit includes a diode and a ggNMOS device;

[0010] The cathode of the diode is connected to the signal pad, and the anode of the diode is grounded;

[0011] The gate of the ggNMOS device is connected to the first electrode and grounded, and the second electrode of the ggNMOS device is connected to the signal pad.

[0012] Optionally, the second-level protection circuit includes a second-order RC network circuit and a discharge device;

[0013] The first end of the second-order RC network circuit is connected to the signal pad, the second end and the third end of the second-order RC network circuit are grounded, the fourth end of the second-order RC network circuit is connected to the first end of the discharge device, the second end of the discharge device is grounded, and the first end of the discharge device is connected to the signal port.

[0014] Optionally, the second-order RC network circuit includes a first resistor, a first capacitor, a second resistor and a second capacitor;

[0015] The first end of the first resistor is connected to the signal pad, the second end of the first resistor is connected to the first end of the second resistor, the first end of the first capacitor is connected to the second end of the first resistor, the second end of the first capacitor is grounded, the first end of the second capacitor is connected to the second end of the second resistor and the signal port, and the second end of the second capacitor is grounded.

[0016] Optionally, the sum of the resistances of the first resistor and the second resistor is greater than or equal to 100 ohms.

[0017] Optionally, the discharge device includes a first transistor, a first electrode and a gate of the first transistor are connected to and grounded, and a second electrode of the first transistor is connected to the signal port.

[0018] Optionally, the first transistor includes a parasitic transistor.

[0019] Optionally, a discharge start threshold of the parasitic transistor is smaller than a gate oxide breakdown voltage of the MOS tube of the signal port.

[0020] Optionally, the first transistor includes an NMOS transistor.

[0021] The technical solution of the embodiment of the present invention adopts a first-level protection circuit and a second-level protection circuit through an electrostatic discharge circuit, and neither the first-level protection circuit nor the second-level protection circuit is connected to the power line. The first-level protection circuit is used for human body model protection, and the second-level protection circuit is used for charging device model protection. The cascaded two protection circuits provide multi-level protection, which enhances the circuit's resistance to different types of electrostatic discharge. At the same time, neither the first-level protection circuit nor the second-level protection circuit is connected to the power line, that is, the first-level protection circuit and the second-level protection circuit provided by the embodiment of the present invention are connected to the power port, and the power line is not used, which can simplify the circuit layout, and will not introduce the parasitic resistance caused by the use of longer power lines, which can improve the electrostatic discharge protection performance and improve the reliability of the circuit. The technical solution provided by the embodiment of the present invention can avoid the parasitic resistance introduced by the longer layout lines in the electrostatic discharge circuit, which can improve the electrostatic discharge protection performance, simplify the circuit layout and optimize the chip area.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic diagram of an electrostatic discharge circuit provided according to the relevant technology;

[0025] Figure 2 This is a schematic diagram of the effect of VDD routing on electrostatic discharge performance;

[0026] Figure 3 A schematic diagram of the structure of an electrostatic discharge circuit provided according to an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of an electrostatic discharge circuit provided according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of a discharge current path of an electrostatic discharge circuit of a PS mode signal port according to an embodiment of the present invention;

[0029] Figure 6 Schematic diagram of the discharge current path of the electrostatic discharge circuit of the NS mode signal port according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Figure 1 FIG. 1 is a schematic diagram of an electrostatic discharge circuit provided according to the related art. Figure 1 As shown, the first-level protection circuit 201 of the related art uses a first diode D2 and a second diode D3, the anode of the first diode D2 is grounded, the cathode of the first diode D2 is connected to the signal pad IO PAD2, the anode of the second diode D3 is connected to the signal pad IO PAD2, and the cathode of the second diode D3 is connected to the power supply port VDD, which is used for first-level discharge protection. The second-level protection circuit 202 of the related art includes a third resistor R3, a third diode D4 and a fourth diode D5, and the third resistor R3 is connected between the signal pad IO PAD2 and the signal port IO2 to play a current limiting role. The anode of the third diode D4 is connected to the ground, and the cathode of the third diode D4 is connected to the connection point of the third resistor R3 and the signal port IO2. The cathode of the fourth diode D5 is connected to the power supply port VDD, and the anode of the fourth diode is connected to the connection point of the third resistor R3 and the signal port IO2, which is used for secondary discharge protection. In the related art, the first-level protection circuit 210 and the second-level protection circuit 202 need to be connected to the power port VDD to realize the electrostatic protection function. The power port VDD needs to be connected using power wiring. The power wiring generally has a large width and is easy to introduce parasitic resistance.

[0033] Figure 2 This is a schematic diagram of the impact of VDD routing on electrostatic discharge performance, refer to Figure 2, the ESD discharge current passes from the IO_1 port through the IO port ESD protection circuit, then through the VDD line to the VDD port, and then through the power clamp Power Clamp to another IO port ESD protection circuit, and finally reaches the IO_2 port. The VDD port is connected to the signal pad through a long line, which introduces parasitic resistance. When electrostatic discharge occurs, an ampere-level current flows through the parasitic resistance, thereby introducing an additional potential difference on the discharge path, which affects the electrostatic discharge protection performance. Among them, the power clamp Power Clamp is a circuit used for electrostatic discharge protection on the power line. The main function is to limit the high voltage on the power line to a safe range when electrostatic discharge or transient high voltage occurs, to prevent sensitive devices in the circuit from being damaged.

[0034] Figure 3 The schematic diagram of the structure of an electrostatic discharge circuit provided by an embodiment of the present invention is applicable to protecting input / output ports from electrostatic discharge damage. The circuit can be used in electronic product manufacturing, industrial control systems and integrated circuits. Figure 3 As shown, the electrostatic discharge circuit provided by the embodiment of the present invention includes:

[0035] The first level protection circuit 101 is connected to the signal pad and is used for human body model protection.

[0036] The second level protection circuit 102 is connected to the first level protection circuit 101 and the signal port, and is used for charging device model protection.

[0037] Neither the first-stage protection circuit 101 nor the second-stage protection circuit 102 is connected to a power line.

[0038] Among them, the signal pad is an important component in the integrated circuit for connecting the inside of the chip with the outside world. For example, it can be an input / output pad (IO PAD). Human Body Model Protection (HBM) is a test model for simulating the electrostatic discharge that may be generated when the human body contacts an electronic device. Charged Device Model Protection (CDM) is an electrostatic discharge model that evaluates the discharge phenomenon that occurs during the manufacturing, processing or assembly process of semiconductor devices due to their own charging. The first-level protection circuit 101 is connected to the signal pad for human body model protection. The second-level protection circuit 102 connects the first-level protection circuit 101 and the signal port for charging device model protection.

[0039] The embodiment of the present invention adopts an electrostatic discharge circuit in the form of a first-level protection circuit and a second-level protection circuit, and neither the first-level protection circuit nor the second-level protection circuit is connected to a power line. The first-level protection circuit is used for human body model protection, and the second-level protection circuit is used for charging device model protection. The cascaded two protection circuits provide multi-level protection, which enhances the circuit's resistance to different types of electrostatic discharge. At the same time, neither the first-level protection circuit nor the second-level protection circuit is connected to a power line, that is, the first-level protection circuit and the second-level protection circuit provided by the embodiment of the present invention are connected to the power port, and the power line is not used, which can simplify the circuit layout, and will not introduce the parasitic resistance caused by the use of a longer power line, which can improve the electrostatic discharge protection performance and improve the reliability of the circuit. The technical solution provided by the embodiment of the present invention can avoid the parasitic resistance introduced by the longer layout line in the electrostatic discharge circuit, which can improve the electrostatic discharge protection performance, simplify the circuit layout and optimize the chip area.

[0040] Figure 4 Schematic diagram of an electrostatic discharge circuit provided according to an embodiment of the present invention. Figure 4 In some optional embodiments of the present invention, the first-level protection circuit 101 includes a diode D1 and a ggNMOS device ggM1; the cathode of the diode D1 is connected to the signal pad IO PAD1, and the anode of the diode D1 is grounded; the gate of the ggNMOS device ggM1 is connected to the first electrode and grounded, and the second electrode of the ggNMOS device ggM1 is connected to the signal pad IO PAD1.

[0041] Specifically, the diode D1 is connected between the signal pad IO PAD1 and the ground. When discharge occurs from the ground to the signal pad IOPAD1, the diode D1 is turned on. The drain of the ggNMOS device ggM1 is connected to the signal pad IO PAD1 port, and the gate and source are connected to the ground. When discharge occurs from the signal pad IO PAD1 to the ground, the ggNMOS device ggM1 is turned on, allowing current to pass through, further protecting the circuit. The ggNMOS device ggM1 is an electrostatic discharge device ggNMOS (grounded-gate NMOS) specially designed for electrostatic discharge circuits. Compared with general NMOS, the device increases the distance from the drain to the gate, and adds a self-aligned silicide blocking layer (Self-Aligned Silicide Block, SAB) between the drain and the gate, thereby avoiding the formation of silicide in this area, so that a higher resistance is formed in this area, thereby enhancing the thermal stability and transient large current resistance of the device. Among them, the self-aligned silicide blocking layer is a semiconductor manufacturing process used to form an isolation and protection structure between different material layers. It is mainly used to prevent silicide formation in areas where metal silicide formation is not required.

[0042] refer to Figure 1 and Figure 4 , the embodiment of the present invention uses a diode D1 and a ggNMOS device ggM1 to form a first-level protection circuit 101, which provides a discharge path from the signal pad IO PAD1 to the ground and from the ground to the signal pad IO PAD1 for the human body model discharge. The discharge start threshold voltage of the ggNMOS device ggM1 is greater than the power supply, thereby ensuring that the signal pad IO PAD1 is in a closed state under normal input or output voltage conditions. Compared with the first-level protection circuit 201 of the electrostatic discharge circuit in the related art, the first-level protection circuit 101 of the embodiment of the present invention is composed of a diode D1 and a ggNMOS device ggM1, and is not connected to a power line, thereby avoiding the discharge current from passing through a long line to the signal port, thereby improving the human body model protection performance. Among them, the discharge start threshold usually refers to the trigger voltage, that is, the voltage required for the ggNMOS device ggM1 to change from a high resistance state to a conductive state. The discharge start threshold of the ggNMOS device ggM1 is usually greater than the power supply voltage to ensure that it will not be falsely triggered under normal power supply voltage, and at the same time, it can provide effective protection in electrostatic discharge.

[0043] In some optional embodiments of the present invention, continue to refer to Figure 4 The second-level protection circuit 102 includes a second-order RC network circuit and a discharge device M1; the first end of the second-order RC network circuit is connected to the signal pad IO PAD1, the second end and the third end of the second-order RC network circuit are grounded, the fourth end of the second-order RC network circuit is connected to the first end of the discharge device M1, the second end of the discharge device M1 is grounded, and the first end of the discharge device M1 is connected to the signal port IO1.

[0044] Among them, the second-order RC network circuit contains two resistors and two capacitors, which can be combined in different ways to achieve specific circuit functions. The second-order RC network circuit is widely used in signal processing, filter design, oscillators and control systems. For details, refer to Figure 1 and Figure 4 Compared with the electrostatic discharge circuit in the related art, the second-level protection circuit 102 of the embodiment of the present invention is composed of a second-order RC network circuit and a discharge device M1, and is not connected to a power line, thereby avoiding the discharge current from passing through a long line to the signal port, and improving the protection performance of the charging device model.

[0045] In some optional embodiments of the present invention, Figure 4 As shown, the second-order RC network circuit includes a first resistor R1, a first capacitor C1, a second resistor R2 and a second capacitor C2; the first resistor R1, the first capacitor C1, the second resistor R2, the second capacitor C2 and the discharge device M1 together constitute the second-level protection circuit 102.

[0046] A first end of the first resistor R1 is connected to the signal pad IO PAD1, a second end of the first resistor R1 is connected to a first end of the second resistor R2, a first end of the first capacitor C1 is connected to a second end of the first resistor R1, a second end of the first capacitor C1 is grounded, a first end of the second capacitor C2 is connected to the second end of the second resistor R2 and the signal port IO1, and a second end of the second capacitor C2 is grounded.

[0047] The first resistor R1 and the first capacitor C1, the second resistor R2 and the second capacitor C2 form a second-order RC network, which can further reduce the transient peak voltage of the signal port IO1 when electrostatic discharge occurs, thereby improving the electrostatic discharge performance. The transient peak voltage refers to the maximum voltage value to which the voltage in the circuit rises rapidly due to transient phenomena such as electrostatic discharge, lightning strike, electromagnetic interference or switching operation in a short period of time. This voltage peak value usually exceeds the normal operating voltage of the circuit and may damage the components in the circuit.

[0048] In some optional embodiments of the present invention, the sum of the resistances of the first resistor R1 and the second resistor R2 is greater than or equal to 100 ohms.

[0049] The first resistor R1 and the second resistor R2 are voltage divider resistors in the second-level protection circuit 102, and the sum of the resistances of the first resistor R1 and the second resistor R2 is at least greater than 100 ohms. In order to ensure that the input port can withstand a high voltage shock during electrostatic discharge without damaging the internal circuit when there is no power supply. A larger resistance value helps to limit the instantaneous current, thereby protecting the circuit from damage caused by electrostatic discharge.

[0050] In some optional embodiments of the present invention, the discharge device M1 includes a first transistor, a first electrode and a gate of the first transistor are connected to the ground, and a second electrode of the first transistor is connected to the signal port IO1.

[0051] The first transistor may be an NMOS transistor, the source and gate of the first transistor are connected and grounded, and the drain of the first transistor is connected to the signal port IO1. The second-order RC network circuit and the discharge device M1 constitute the second-level protection circuit 102. When discharge occurs from the signal pad IO PAD1 to the ground, it can be discharged using the discharge device M1, and when discharge occurs from the ground to the signal pad IO PAD1, it can be discharged using the first transistor in a diode connection form.

[0052] The first transistor includes a parasitic transistor, wherein the parasitic transistor refers to an undesigned transistor that is spontaneously formed in an integrated circuit or certain circuits due to the physical properties of semiconductor materials and device structure. Exemplarily, it may be a parasitic NPN transistor.

[0053] In some optional embodiments of the present invention, the discharge start threshold of the parasitic transistor is smaller than the gate oxide breakdown voltage of the MOS tube of the signal port.

[0054] Among them, parasitic transistors may be turned on under certain conditions, resulting in a latch effect. The discharge turn-on threshold refers to the minimum voltage that turns on the parasitic transistor. If the voltage exceeds this minimum voltage, the parasitic transistor will turn on, which may cause a sharp increase in current, thereby causing latching. The gate oxide breakdown voltage of the MOS tube at the signal port refers to the highest voltage at which the gate oxide layer breaks down under the action of the electric field. If the voltage exceeds this value, the gate oxide layer may be damaged, causing the MOS tube to fail to work properly. The discharge turn-on threshold of the parasitic transistor is less than the gate oxide breakdown voltage of the MOS tube at the signal port, preventing the parasitic transistor from turning on under high voltage, thereby avoiding circuit damage. Avoid the activation of parasitic transistors, reduce noise and unnecessary oscillations, and improve signal integrity.

[0055] In some optional embodiments of the present invention, the first transistor includes an NMOS transistor.

[0056] The electrostatic discharge circuit provided by the embodiment of the present invention is used to protect the input / output port from damage caused by electrostatic discharge. Figure 4 As shown, the diode D1 is connected between the signal pad IO PAD1 and the ground. When discharge occurs from the ground to the signal pad IO PAD1, the diode D1 is turned on. The drain of the ggNMOS device ggM1 is connected to the signal pad IO PAD1 port, and the gate and source are connected to the ground. When discharge occurs from the signal pad IO PAD1 to the ground, the ggNMOS device ggM1 is turned on, allowing current to pass through, further protecting the circuit. The diode D1 and the ggNMOS device ggM1 constitute a first-level protection circuit 101 for human body model protection; R1, C1, R2, and C2 constitute a second-order RC network, which can reduce the transient peak voltage of the signal port IO1 when electrostatic discharge occurs, and improve the electrostatic discharge performance. When discharge occurs from the signal pad IO PAD1 to the ground, the discharge device M1 uses a parasitic NPN transistor for discharge, and when discharge occurs from the ground to the signal pad IO PAD1, the discharge device M1 uses a diode-connected NMOS tube for discharge. The second-order RC network circuit and the discharge device M1 constitute the second-level protection circuit 102, which is mainly used to solve the discharge problem of the charging device model.

[0057] Figure 5 Schematic diagram of the discharge current path of the electrostatic discharge circuit of the PS mode signal port according to an embodiment of the present invention. Figure 6The figure is a schematic diagram of the discharge current path of the electrostatic discharge circuit of the NS mode signal port according to an embodiment of the present invention. Among them, the PS mode (Positive to VSS) refers to the situation when the positive charge is discharged directly to the ground. In the present invention, when there is no power line connected, the PS mode refers to the situation when the signal pad is discharged to the ground. The NS mode (Negative to VSS) refers to the situation when the negative charge is discharged directly to the ground. In the present invention, when there is no power line connected, the NS mode refers to the situation when the ground discharges to the signal pad. Figure 5 As shown, discharge occurs from the signal pad IO PAD1 to the ground, the first level protection circuit 101 discharges through the ggNMOS device ggM1, and the discharge current of the second level protection circuit 102 passes through the first resistor R1 and the second resistor R2 and discharges through the discharge device M1. Figure 6 As shown, discharge occurs from the ground to the signal pad IO PAD1, the first level protection circuit 101 discharges through the diode D1, the second level protection circuit 102 discharges through the discharge device M1, and the discharge current passes through the second resistor R2 and the first resistor R1 to reach the signal pad IO PAD1. The technical solution of the present invention does not require the design of additional routing for the power line, which can make the layout more compact and neat, thereby simplifying the wiring process.

[0058] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0059] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An electrostatic discharge circuit, characterized in that: include: A first level protection circuit, the first level protection circuit is connected to the signal pad and is used for human body model protection; A second-level protection circuit, the second-level protection circuit is connected to the first-level protection circuit and the signal port, and is used for charging device model protection; The first-level protection circuit and the second-level protection circuit are not connected to a power line.

2. The circuit according to claim 1, characterized in that The first level protection circuit includes a diode and a ggNMOS device; The cathode of the diode is connected to the signal pad, and the anode of the diode is grounded; The gate of the ggNMOS device is connected to the first electrode and grounded, and the second electrode of the ggNMOS device is connected to the signal pad.

3. The circuit according to claim 1, characterized in that The second level protection circuit includes a second order RC network circuit and a discharge device; The first end of the second-order RC network circuit is connected to the signal pad, the second end and the third end of the second-order RC network circuit are grounded, the fourth end of the second-order RC network circuit is connected to the first end of the discharge device, the second end of the discharge device is grounded, and the first end of the discharge device is connected to the signal port.

4. The circuit according to claim 3, characterized in that The second-order RC network circuit includes a first resistor, a first capacitor, a second resistor and a second capacitor; The first end of the first resistor is connected to the signal pad, the second end of the first resistor is connected to the first end of the second resistor, the first end of the first capacitor is connected to the second end of the first resistor, the second end of the first capacitor is grounded, the first end of the second capacitor is connected to the second end of the second resistor and the signal port, and the second end of the second capacitor is grounded.

5. The circuit according to claim 4, characterized in that The sum of the resistances of the first resistor and the second resistor is greater than or equal to 100 ohms.

6. The circuit according to claim 3, characterized in that The discharge device includes a first transistor, a first electrode and a gate of the first transistor are connected to the ground, and a second electrode of the first transistor is connected to the signal port.

7. The circuit according to claim 6, characterized in that The first transistor includes a parasitic triode.

8. The circuit according to claim 7, characterized in that The discharge start threshold of the parasitic transistor is smaller than the gate oxide breakdown voltage of the MOS tube of the signal port.

9. The circuit according to claim 7, characterized in that The first transistor includes an NMOS transistor.

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