Four-mode integer frequency division circuit and implementation method

Abstract

The invention relates to the technical field of signal processing, in particular to a four-mode integer frequency dividing circuit and an implementation method.The four-mode integer frequency dividing circuit comprises a trigger DFF1, a trigger DFF2, a first logic gate circuit set and a second logic gate circuit set, and the clock input end of the trigger DFF1 and the clock input end of the trigger DFF2 are connected with a frequency-divided clock CLK; a frequency dividing ratio control signal S1 and a frequency dividing ratio control signal S0 are respectively input into the first logic gate circuit group and the second logic gate circuit group, the first logic gate circuit group is used for generating an input signal of the trigger DFF2, and the second logic gate circuit group is used for performing modulus increasing on an output signal of the frequency dividing circuit, so that only two D triggers are used; the first logic gate circuit group and the second logic gate circuit group are matched with two frequency dividing ratio control signals, four-mode integer frequency division with the frequency dividing ratio being 1-2-3-4 selectable is achieved, the overall design is simple, cost is low, and large-scale application and popularization are facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a four-mode integer frequency division circuit, an implementation method and an application thereof. Background Art

[0002] The rapid development of information technology has led to an increasing demand for frequency division technology in the fields of clocks, communication systems, etc. Traditional frequency dividers mostly use single-mode or dual-mode structures, which cannot meet the requirements of complex systems for flexibility and accuracy. Multi-mode frequency dividers can switch between different frequency division modes to meet different frequency division ratio requirements.

[0003] In the clock system of high-precision wireless ranging applications, in order to ensure the accuracy of measurement, it is necessary to transmit measurement signals of different frequencies according to different ranges. Therefore, most systems use single-mode dividers with different division ratios to generate measurement signals of different frequencies. Such a design will increase the complexity of the system and increase the cost.

[0004] In addition, in the prior art, the four-mode frequency divider has made some progress, but there are still some problems. For example, the frequency division ratio of some four-mode frequency dividers can only be 2 to the power of N, which is strongly limited in the frequency division ratio range and is not applicable to many application scenarios; some four-mode frequency dividers require at least 4 control ports, 4 relatively complex master-slave D flip-flops and 10 logic gate circuits to cooperate to achieve, and the overall design is relatively complex and the cost is high, which is not conducive to large-scale promotion and application. Summary of the invention

[0005] In view of the above problems, the present invention provides a four-mode integer frequency division circuit and an implementation method.

[0006] The adopted technical solution is: a four-module integer frequency division circuit, including a trigger DFF1, a trigger DFF2, a first logic gate circuit group and a second logic gate circuit group;

[0007] The clock input terminals of the trigger DFF1 and the trigger DFF2 are connected to the divided clock CLK;

[0008] The inverting output terminal Q2B of the flip-flop DFF2 is connected to the data input terminal D1 of the flip-flop DFF1 and the signal input terminal of the first logic gate circuit group;

[0009] The in-phase output terminal Q1 of the trigger DFF1 is connected to the signal input terminal of the first logic gate circuit group;

[0010] The first logic gate circuit group is used to generate a trigger DFF2 input signal;

[0011] The in-phase output terminal Q2 of the flip-flop DFF2 is signal-connected to the second logic gate circuit group;

[0012] The second logic gate circuit group is used to perform modulus multiplication on the output signal of the frequency division circuit.

[0013] Optionally, the first logic gate circuit group includes a logic OR gate circuit I1, a logic OR gate circuit I2, and a logic AND gate circuit I3, and the two-input logic OR gate circuit I1, the two-input logic OR gate circuit I2, and the two-input logic AND gate circuit I3 all include two signal input terminals;

[0014] The first signal input terminal of the two-input logic OR gate circuit I1 inputs the frequency division ratio control signal S1;

[0015] The in-phase output terminal Q1 of the flip-flop DFF1 is connected to the second signal input terminal of the two-input logic OR gate circuit I1;

[0016] The first signal input terminal of the two-input logic OR gate circuit I2 inputs the frequency division ratio control signal S0;

[0017] The inverting output terminal Q2B of the flip-flop DFF2 is connected to the data input terminal D1 of the flip-flop DFF1 and the second signal input terminal of the two-input logic OR gate circuit I2;

[0018] The first signal input terminal of the two-input logic AND gate circuit I3 is connected to the signal output terminal of the two-input logic OR gate circuit I1, the second signal input terminal of the two-input logic AND gate circuit I3 is connected to the signal output terminal of the two-input logic OR gate circuit I2, and the signal output terminal of the two-input logic AND gate circuit I3 is signal-connected to the data input terminal D2 of the trigger DFF2.

[0019] Optionally, the second logic gate circuit group is used to perform mode multiplication on the output signal of the frequency division circuit, and the second logic gate circuit group includes a three-input logic AND gate circuit I4 and a two-input logic AND gate circuit I5;

[0020] The first signal input terminal of the three-input logic AND gate circuit I4 inputs the frequency division ratio control signal S1, the second signal input terminal of the three-input logic AND gate circuit I4 inputs the frequency division ratio control signal S0, and the third signal input terminal of the three-input logic AND gate circuit I4 inputs the divided clock CLK;

[0021] The first signal input terminal of the two-input logic AND gate circuit I5 is connected to the in-phase output terminal Q2 of the trigger DFF2, the second signal input terminal of the two-input logic AND gate circuit I5 is connected to the signal output terminal of the three-input logic AND gate circuit I4, and the signal output terminal of the two-input logic AND gate circuit I5 serves as the signal output terminal of the frequency division circuit.

[0022] Optionally, it also includes a trigger DFF3, wherein the clock input terminal of the trigger DFF3 is connected to the divided clock CLK, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, the in-phase output terminal Q3 of the trigger DFF3 is connected to the clock input terminal of the trigger DFF1, and a clock signal is output to the trigger DFF1, wherein the clock terminal of the trigger DFF1 is disconnected from the original CLK.

[0023] Optionally, it further includes a trigger DFF3 and a trigger DFF4, wherein the clock input terminal of the trigger DFF4 is connected to the divided clock CLK, the data input terminal D4 of the trigger DFF4 is connected to the inverting output terminal Q4B, the in-phase output terminal Q4 of the trigger DFF4 is connected to the clock input terminal of the trigger DFF3, and a clock signal is output to the trigger DFF3;

[0024] The data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, the inverting output terminal Q3 of the trigger DFF3 is connected to the clock input terminal of the trigger DFF1, and a clock signal is output to the trigger DFF1, wherein the clock terminal of the trigger DFF1 is disconnected from the original CLK.

[0025] Optionally, it further includes N D flip-flops, N is a positive integer greater than 2, and the N D flip-flops are connected in sequence, the clock input terminal of the first D flip-flop located at the signal transmission end is connected to the divided clock CLK, the data input terminal of the first D flip-flop located at the signal transmission end is connected to the inverting output terminal, the in-phase output terminal of the first D flip-flop located at the signal transmission end is connected to the clock input terminal of the second D flip-flop, and a clock signal is output to the second D flip-flop;

[0026] The data input terminal of the second D flip-flop is connected to the inverting output terminal, the non-inverting output terminal of the second D flip-flop is connected to the clock input terminal of the third D flip-flop, and a clock signal is output to the third D flip-flop;

[0027] And so on, until the last D flip-flop, the clock input terminal of the last D flip-flop is connected to the in-phase output terminal signal of the N-1th D flip-flop, the data input terminal of the last D flip-flop is connected to the inverting output terminal, the in-phase output terminal of the last D flip-flop is connected to the clock input terminal of the flip-flop DFF1, and a clock signal is output to the flip-flop DFF1, wherein the clock terminal of the flip-flop DFF1 is disconnected from the original CLK.

[0028] Optionally, it also includes a trigger DFF3, wherein the clock input terminal of the trigger DFF3 is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, and the in-phase output terminal Q3 of the trigger DFF3 serves as the signal output terminal of the frequency division circuit.

[0029] Optionally, it further includes a trigger DFF3 and a trigger DFF4, wherein the clock input terminal of the trigger DFF3 is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, and the in-phase output terminal Q3 of the trigger DFF3 is signal-connected to the clock input terminal of the trigger DFF4;

[0030] The data input terminal D4 of the flip-flop DFF4 is connected to the inverting output terminal Q4B, and the inverting output terminal Q4 of the flip-flop DFF4 serves as the signal output terminal of the frequency dividing circuit.

[0031] Optionally, it further includes N D flip-flops, and N is a positive integer greater than 2, the N D flip-flops are connected in sequence, the clock input terminal of the first D flip-flop at the signal transmission end is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal of the first D flip-flop at the signal transmission end is connected to the inverting output terminal, the in-phase output terminal of the first D flip-flop at the signal transmission end is connected to the clock input terminal of the second D flip-flop, and a clock signal is output to the second D flip-flop;

[0032] The data input terminal of the second D flip-flop is connected to the inverting output terminal, the non-inverting output terminal of the second D flip-flop is connected to the clock input terminal of the third D flip-flop, and a clock signal is output to the third D flip-flop;

[0033] And so on until the last D flip-flop, the clock input terminal of the last D flip-flop is connected to the in-phase output terminal signal of the N-1th D flip-flop, the data input terminal of the last D flip-flop is connected to the inverting output terminal, and the in-phase output terminal of the last D flip-flop serves as the signal output terminal of the frequency division circuit.

[0034] The present application also provides a method for implementing a four-mode integer frequency division, which is implemented based on a four-mode integer frequency division circuit and includes the following steps:

[0035] The data input terminal D1 of the flip-flop DFF1 is connected to the inverting output terminal Q2B of the flip-flop DFF2, so that D1=Q2B is realized;

[0036] D2=(S1+Q1)&(S0+Q2B) is realized through a two-input logic OR gate circuit I1, a two-input logic OR gate circuit I2, and a two-input logic AND gate circuit I3;

[0037] Assume that the initial states of the in-phase output terminal Q2 of the flip-flop DFF2 and the in-phase output terminal Q1 of the flip-flop DFF1 are 00:

[0038] When the frequency division ratio control signal S1=0, the frequency division ratio control signal S0=0, D1=Q2B, D2=Q1&Q2B, under the action of the CLK clock, the state of Q2 Q1 cycles in 00-01-11-00, and the in-phase output terminal Q2 of the trigger DFF2 realizes 3-frequency division;

[0039] When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=1, D1=Q2B and D2=Q1. Under the action of the CLK clock, the states of Q2 and Q1 cycle through 00-01-11-10-00, and the in-phase output terminal Q2 of the flip-flop DFF2 realizes 4-frequency division.

[0040] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=0, D1=Q2B and D2=Q2B. Under the action of the CLK clock, the states of Q2 Q1 cycle from 00-11-00, and the in-phase output terminal Q2 of the trigger DFF2 realizes 2-frequency division.

[0041] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=1, D1=Q2B and D2=1. Under the action of the CLK clock, the states of Q2 and Q1 cycle through 00-11-10-10-10-10. The in-phase output terminal Q2 of the flip-flop DFF2 is finally fixed at a high level, and frequency division is not achieved.

[0042] Then, OUT= Q2 & (S1&S0&CLK) is realized through the three-input logic AND gate circuit I4 and the two-input logic AND gate circuit I5;

[0043] When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=0, OUT= Q2, and the OUT signal achieves 3-frequency division;

[0044] When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=1, OUT= Q2, and the OUT signal achieves 4-frequency division;

[0045] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=0, OUT= Q2, and the OUT signal achieves 2-frequency division;

[0046] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=1, OUT= Q2&CLK. Since Q2=1 at this time, OUT= CLK, and the OUT signal achieves 1 division.

[0047] The present application also provides an application of a four-mode integer frequency division circuit, which is applied to a wireless ranging system.

[0048] The beneficial effects of the present invention include at least one of the following:

[0049] 1. Only two D flip-flops are used, in conjunction with the first logic gate circuit, the second logic gate circuit and the frequency division ratio control signal, to achieve four-mode integer frequency division with optional frequency division ratios of 1-2-3-4. The overall design is relatively simple, low-cost, and conducive to large-scale promotion and use.

[0050] 2. On this basis, by adding N D flip-flops, it can be expanded into a four-mode integer frequency divider circuit with a division ratio of (N+1)*(1-2-3-4) optional. Compared with other multi-mode dividers, it has more flexible division ratio, simple structure, small area, low cost and other effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of a wireless ranging system;

[0052] Figure 2 It is a four-module integer frequency division circuit diagram with a frequency division ratio of 1-2-3-4 selectable;

[0053] Figure 3 It is a waveform diagram of a four-module integer frequency division circuit with a selectable division ratio of 1-2-3-4;

[0054] Figure 4 It is a four-mode integer frequency division circuit diagram with a frequency division ratio of (1+N)*(1-2-3-4) optional;

[0055] Figure 5 A schematic diagram of connecting a trigger DFF3 and a trigger DFF4;

[0056] Figure 6 A schematic diagram of connecting N D flip-flops;

[0057] Figure 7 It is another four-mode integer frequency division circuit diagram with a frequency division ratio of (1+N)*(1-2-3-4) optional;

[0058] Figure 8 A schematic diagram for connecting another type of trigger DFF3 and trigger DFF4;

[0059] Fig. 9 This is another connection diagram of N D flip-flops. DETAILED DESCRIPTION

[0060] The following describes the implementation of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0061] It should be noted that the illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] like Figure 2 As shown, a four-module integer frequency division circuit includes a trigger DFF1, a trigger DFF2, a first logic gate circuit group and a second logic gate circuit group;

[0063] The clock input terminals of the trigger DFF1 and the trigger DFF2 are connected to the divided clock CLK;

[0064] The inverting output terminal Q2B of the flip-flop DFF2 is connected to the data input terminal D1 of the flip-flop DFF1 and the signal input terminal of the first logic gate circuit group;

[0065] The in-phase output terminal Q1 of the trigger DFF1 is connected to the signal input terminal of the first logic gate circuit group;

[0066] The first logic gate circuit group is used to generate a trigger DFF2 input signal;

[0067] The in-phase output terminal Q2 of the flip-flop DFF2 is signal-connected to the second logic gate circuit group;

[0068] The second logic gate circuit group is used to perform modulus multiplication on the output signal of the frequency division circuit.

[0069] The purpose of this design is to use only two D flip-flops, in conjunction with some logic gate circuits, to realize a four-modulus integer frequency division circuit with selectable division ratios of 1-2-3-4. The overall design is relatively simple, low-cost, and conducive to large-scale promotion and use.

[0070] In this embodiment, the first logic gate circuit group includes a logic OR gate circuit I1, a logic OR gate circuit I2, and a logic AND gate circuit I3, and the two-input logic OR gate circuit I1, the two-input logic OR gate circuit I2, and the two-input logic AND gate circuit I3 all include two signal input terminals;

[0071] The first signal input terminal of the two-input logic OR gate circuit I1 inputs the frequency division ratio control signal S1;

[0072] The in-phase output terminal Q1 of the flip-flop DFF1 is connected to the second signal input terminal of the two-input logic OR gate circuit I1;

[0073] The first signal input terminal of the two-input logic OR gate circuit I2 inputs the frequency division ratio control signal S0;

[0074] The inverting output terminal Q2B of the flip-flop DFF2 is connected to the data input terminal D1 of the flip-flop DFF1 and the second signal input terminal of the two-input logic OR gate circuit I2;

[0075] The first signal input terminal of the two-input logic AND gate circuit I3 is connected to the signal output terminal of the two-input logic OR gate circuit I1, the second signal input terminal of the two-input logic AND gate circuit I3 is connected to the signal output terminal of the two-input logic OR gate circuit I2, and the signal output terminal of the two-input logic AND gate circuit I3 is signal-connected to the data input terminal D2 of the trigger DFF2.

[0076] Meanwhile, the second logic gate circuit group is used to divide the frequency of the output signal of the frequency dividing circuit, and the second logic gate circuit group includes a three-input logic AND gate circuit I4 and a two-input logic AND gate circuit I5;

[0077] The first signal input terminal of the three-input logic AND gate circuit I4 inputs the frequency division ratio control signal S1, the second signal input terminal of the three-input logic AND gate circuit I4 inputs the frequency division ratio control signal S0, and the third signal input terminal of the three-input logic AND gate circuit I4 inputs the divided clock CLK;

[0078] The first signal input terminal of the two-input logic AND gate circuit I5 is connected to the in-phase output terminal Q2 of the trigger DFF2, the second signal input terminal of the two-input logic AND gate circuit I5 is connected to the signal output terminal of the three-input logic AND gate circuit I4, and the signal output terminal of the two-input logic AND gate circuit I5 serves as the signal output terminal of the frequency division circuit.

[0079] Based on the above four-mode integer frequency division circuit, this embodiment provides a method for implementing four-mode integer frequency division, including the following steps:

[0080] The data input terminal D1 of the flip-flop DFF1 is connected to the inverting output terminal Q2B of the flip-flop DFF2, so that D1=Q2B is realized;

[0081] D2=(S1+Q1)&(S0+Q2B) is realized through a two-input logic OR gate circuit I1, a two-input logic OR gate circuit I2, and a two-input logic AND gate circuit I3;

[0082] Assume that the initial states of the in-phase output terminal Q2 of the flip-flop DFF2 and the in-phase output terminal Q1 of the flip-flop DFF1 are 00:

[0083] When the frequency division ratio control signal S1=0, the frequency division ratio control signal S0=0, D1=Q2B, D2=Q1&Q2B, under the action of the CLK clock, the state of Q2 Q1 cycles in 00-01-11-00, and the in-phase output terminal Q2 of the trigger DFF2 realizes 3-frequency division;

[0084] When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=1, D1=Q2B and D2=Q1. Under the action of the CLK clock, the states of Q2 and Q1 cycle through 00-01-11-10-00, and the in-phase output terminal Q2 of the flip-flop DFF2 realizes 4-frequency division.

[0085] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=0, D1=Q2B and D2=Q2B. Under the action of the CLK clock, the states of Q2 Q1 cycle from 00-11-00, and the in-phase output terminal Q2 of the trigger DFF2 realizes 2-frequency division.

[0086] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=1, D1=Q2B and D2=1. Under the action of the CLK clock, the states of Q2 and Q1 cycle through 00-11-10-10-10-10. The in-phase output terminal Q2 of the flip-flop DFF2 is finally fixed at a high level, and frequency division is not achieved.

[0087] Then, OUT= Q2 & (S1&S0&CLK) is realized through the three-input logic AND gate circuit I4 and the two-input logic AND gate circuit I5;

[0088] When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=0, OUT= Q2, and the OUT signal achieves 3-frequency division;

[0089] When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=1, OUT= Q2, and the OUT signal achieves 4-frequency division;

[0090] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=0, OUT= Q2, and the OUT signal achieves 2-frequency division;

[0091] When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=1, OUT= Q2&CLK. Since Q2=1 at this time, OUT= CLK, and the OUT signal achieves 1 division.

[0092] The waveform of the above frequency division is as follows Figure 3 shown.

[0093] Based on the original four-mode integer frequency division circuit, such as Figure 4As shown, it also includes a trigger DFF3, the clock input terminal of the trigger DFF3 is connected to the divided clock CLK, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, the in-phase output terminal Q3 of the trigger DFF3 is connected to the clock input terminal of the trigger DFF1, and a clock signal is output to the trigger DFF1. It should be pointed out that at this time, the clock terminal of the trigger DFF1 is disconnected from the original CLK.

[0094] On this basis, it can be further extended to include a trigger DFF3 and a trigger DFF4, wherein the clock input terminal of the trigger DFF4 is connected to the divided clock CLK, the data input terminal D4 of the trigger DFF4 is connected to the inverting output terminal Q4B, the inverting output terminal Q4 of the trigger DFF4 is connected to the clock input terminal of the trigger DFF3, and a clock signal is output to the trigger DFF3;

[0095] The data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, the inverting output terminal Q3 of the trigger DFF3 is connected to the clock input terminal of the trigger DFF1, and the clock signal is output to the trigger DFF1. It should be noted that at this time, the clock terminal of the trigger DFF1 is disconnected from the original CLK, wherein the connection between the trigger DFF3 and the trigger DFF4 is as follows: Figure 5 shown.

[0096] Meanwhile, it can be further extended to include N D flip-flops, N is a positive integer greater than 2, and the N D flip-flops are connected in sequence, the clock input end of the first D flip-flop at the signal transmission end is connected to the divided clock CLK, the data input end of the first D flip-flop at the signal transmission end is connected to the inverting output end, the in-phase output end of the first D flip-flop at the signal transmission end is connected to the clock input end of the second D flip-flop, and a clock signal is output to the second D flip-flop;

[0097] The data input terminal of the second D flip-flop is connected to the inverting output terminal, the non-inverting output terminal of the second D flip-flop is connected to the clock input terminal of the third D flip-flop, and a clock signal is output to the third D flip-flop;

[0098] And so on, until the last D flip-flop, the clock input terminal of the last D flip-flop is connected to the in-phase output terminal signal of the N-1th D flip-flop, the data input terminal of the last D flip-flop is connected to the inverting output terminal, the in-phase output terminal of the last D flip-flop is connected to the clock input terminal of the flip-flop DFF1, and the clock signal is output to the flip-flop DFF1. It should be pointed out that at this time, the clock terminal of the flip-flop DFF1 is disconnected from the original CLK, and the connection method of N D flip-flops is as follows Figure 6As shown, this can be expanded again into a four-module integer frequency division circuit with a selectable division ratio of (1+N)*(1-2-3-4).

[0099] From another perspective, based on the four-mode integer frequency division circuit, such as Figure 7 As shown, it also includes a trigger DFF3, the clock input terminal of the trigger DFF3 is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, and the in-phase output terminal Q3 of the trigger DFF3 serves as the signal output terminal of the frequency division circuit.

[0100] Meanwhile, further development is made on this basis, including a trigger DFF3 and a trigger DFF4, wherein the clock input terminal of the trigger DFF3 is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, and the in-phase output terminal Q3 of the trigger DFF3 is signal-connected to the clock input terminal of the trigger DFF4;

[0101] The data input terminal D4 of the trigger DFF4 is connected to the inverting output terminal Q4B, and the inverting output terminal Q4 of the trigger DFF4 is used as the signal output terminal of the frequency division circuit, wherein the connection between the trigger DFF3 and the trigger DFF4 is as follows: Figure 8 shown.

[0102] Furthermore, it can be further extended to include N D flip-flops, where N is a positive integer greater than 2, and the N D flip-flops are connected in sequence, the clock input terminal of the first D flip-flop at the signal transmission end is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal of the first D flip-flop at the signal transmission end is connected to the inverting output terminal, the in-phase output terminal of the first D flip-flop at the signal transmission end is connected to the clock input terminal of the second D flip-flop, and a clock signal is output to the second D flip-flop;

[0103] The data input terminal of the second D flip-flop is connected to the inverting output terminal, the non-inverting output terminal of the second D flip-flop is connected to the clock input terminal of the third D flip-flop, and a clock signal is output to the third D flip-flop;

[0104] And so on, until the last D flip-flop, the clock input end of the last D flip-flop is connected to the in-phase output end signal of the N-1th D flip-flop, the data input end of the last D flip-flop is connected to the inverting output end, and the in-phase output end of the last D flip-flop is used as the signal output end of the frequency division circuit, wherein the connection mode of N D flip-flops is as follows Fig. 9 As shown, this can be expanded again into a four-module integer frequency division circuit with a selectable division ratio of (1+N)*(1-2-3-4).

[0105] like Figure 1 As shown, in the wireless ranging system, the reference signal is processed by the multi-mode divider to obtain the divided signal, and then the divided signal is converted into a transmission signal through the wireless pulse transmission circuit and the transmitter, and transmitted to the target to be measured; the signal will be reflected by the target to be measured, and then received by the photoelectric receiving module of the system, and then sent to the fragrance comparison module after passing through the signal processing module to perform phase comparison with the above-mentioned divided signal and obtain the delay between the two signals, so as to calculate the measured distance.

[0106] In this system, when the fixed frequency divided signal is measured over a long distance, the phase difference obtained will exceed one cycle, resulting in system measurement errors. This shows that the range of the fixed frequency divided signal is limited. Therefore, for targets at different distances, the divided signals of different frequencies can be obtained by controlling the dividing ratio of the multi-mode divider to expand the range. The four-mode integer frequency division circuit provided in this embodiment can be applied in the above scenarios.

[0107] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A four-mode integer frequency division circuit, characterized in that: It includes a trigger DFF1, a trigger DFF2, a first logic gate circuit group and a second logic gate circuit group; The clock input terminals of the trigger DFF1 and the trigger DFF2 are connected to the divided clock CLK; The inverting output terminal Q2B of the flip-flop DFF2 is connected to the data input terminal D1 of the flip-flop DFF1 and the signal input terminal of the first logic gate circuit group; The in-phase output terminal Q1 of the trigger DFF1 is connected to the signal input terminal of the first logic gate circuit group; The first logic gate circuit group is used to generate a trigger DFF2 input signal; The in-phase output terminal Q2 of the flip-flop DFF2 is signal-connected to the second logic gate circuit group; The second logic gate circuit group is used to perform modulus multiplication on the output signal of the frequency division circuit.

2. A four-mode integer frequency division circuit according to claim 1, characterized in that: The first logic gate circuit group includes a logic OR gate circuit I1, a logic OR gate circuit I2, and a logic AND gate circuit I3, and the two-input logic OR gate circuit I1, the two-input logic OR gate circuit I2, and the two-input logic AND gate circuit I3 all include two signal input terminals; The first signal input terminal of the two-input logic OR gate circuit I1 inputs the frequency division ratio control signal S1; The in-phase output terminal Q1 of the flip-flop DFF1 is connected to the second signal input terminal of the two-input logic OR gate circuit I1; The first signal input terminal of the two-input logic OR gate circuit I2 inputs the frequency division ratio control signal S0; The inverting output terminal Q2B of the flip-flop DFF2 is connected to the data input terminal D1 of the flip-flop DFF1 and the second signal input terminal of the two-input logic OR gate circuit I2; The first signal input terminal of the two-input logic AND gate circuit I3 is connected to the signal output terminal of the two-input logic OR gate circuit I1, the second signal input terminal of the two-input logic AND gate circuit I3 is connected to the signal output terminal of the two-input logic OR gate circuit I2, and the signal output terminal of the two-input logic AND gate circuit I3 is signal-connected to the data input terminal D2 of the trigger DFF2.

3. A four-mode integer frequency division circuit according to claim 2, characterized in that: The second logic gate circuit group is used to perform mode multiplication on the output signal of the frequency division circuit, and the second logic gate circuit group includes a three-input logic AND gate circuit I4 and a two-input logic AND gate circuit I5; The first signal input terminal of the three-input logic AND gate circuit I4 inputs the frequency division ratio control signal S1, the second signal input terminal of the three-input logic AND gate circuit I4 inputs the frequency division ratio control signal S0, and the third signal input terminal of the three-input logic AND gate circuit I4 inputs the divided clock CLK; The first signal input terminal of the two-input logic AND gate circuit I5 is connected to the in-phase output terminal Q2 of the trigger DFF2, the second signal input terminal of the two-input logic AND gate circuit I5 is connected to the signal output terminal of the three-input logic AND gate circuit I4, and the signal output terminal of the two-input logic AND gate circuit I5 serves as the signal output terminal of the frequency division circuit.

4. A four-mode integer frequency division circuit according to any one of claims 1 to 3, characterized in that: It also includes a trigger DFF3, whose clock input terminal is connected to the divided clock CLK, whose data input terminal D3 is connected to the inverting output terminal Q3B, whose in-phase output terminal Q3 is connected to the clock input terminal of the trigger DFF1, and which outputs a clock signal to the trigger DFF1.

5. A four-mode integer frequency division circuit according to any one of claims 1 to 3, characterized in that: It also includes a trigger DFF3 and a trigger DFF4, wherein the clock input terminal of the trigger DFF4 is connected to the divided clock CLK, the data input terminal D4 of the trigger DFF4 is connected to the inverting output terminal Q4B, the inverting output terminal Q4 of the trigger DFF4 is connected to the clock input terminal of the trigger DFF3, and a clock signal is output to the trigger DFF3; The data input terminal D3 of the flip-flop DFF3 is connected to the inverting output terminal Q3B, the inverting output terminal Q3 of the flip-flop DFF3 is connected to the clock input terminal of the flip-flop DFF1, and outputs a clock signal to the flip-flop DFF1.

6. A four-mode integer frequency division circuit according to any one of claims 1 to 3, characterized in that: It also includes N D flip-flops, N is a positive integer greater than 2, and the N D flip-flops are connected in sequence, the clock input terminal of the first D flip-flop located at the signal transmission end is connected to the divided clock CLK, the data input terminal of the first D flip-flop located at the signal transmission end is connected to the inverting output terminal, the in-phase output terminal of the first D flip-flop located at the signal transmission end is connected to the clock input terminal of the second D flip-flop, and the clock signal is output to the second D flip-flop; The data input terminal of the second D flip-flop is connected to the inverting output terminal, the non-inverting output terminal of the second D flip-flop is connected to the clock input terminal of the third D flip-flop, and a clock signal is output to the third D flip-flop; And so on until the last D flip-flop, the clock input terminal of the last D flip-flop is connected to the in-phase output terminal signal of the N-1th D flip-flop, the data input terminal of the last D flip-flop is connected to the inverting output terminal, the in-phase output terminal of the last D flip-flop is connected to the clock input terminal of the flip-flop DFF1, and the clock signal is output to the flip-flop DFF1.

7. The four-mode integer frequency division circuit according to claim 3, characterized in that: It also includes a trigger DFF3, the clock input terminal of the trigger DFF3 is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, and the in-phase output terminal Q3 of the trigger DFF3 serves as the signal output terminal of the frequency division circuit.

8. The four-mode integer frequency division circuit according to claim 3, characterized in that: It also includes a trigger DFF3 and a trigger DFF4, wherein the clock input terminal of the trigger DFF3 is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal D3 of the trigger DFF3 is connected to the inverting output terminal Q3B, and the in-phase output terminal Q3 of the trigger DFF3 is signal-connected to the clock input terminal of the trigger DFF4; The data input terminal D4 of the flip-flop DFF4 is connected to the inverting output terminal Q4B, and the inverting output terminal Q4 of the flip-flop DFF4 serves as the signal output terminal of the frequency dividing circuit.

9. The four-mode integer frequency division circuit according to claim 3, characterized in that: It also includes N D flip-flops, where N is a positive integer greater than 2, and the N D flip-flops are connected in sequence, the clock input terminal of the first D flip-flop at the signal transmission end is connected to the signal output terminal of the two-input logic AND gate circuit I5, the data input terminal of the first D flip-flop at the signal transmission end is connected to the inverting output terminal, the in-phase output terminal of the first D flip-flop at the signal transmission end is connected to the clock input terminal of the second D flip-flop, and a clock signal is output to the second D flip-flop; The data input terminal of the second D flip-flop is connected to the inverting output terminal, the non-inverting output terminal of the second D flip-flop is connected to the clock input terminal of the third D flip-flop, and a clock signal is output to the third D flip-flop; And so on until the last D flip-flop, the clock input terminal of the last D flip-flop is connected to the in-phase output terminal signal of the N-1th D flip-flop, the data input terminal of the last D flip-flop is connected to the inverting output terminal, and the in-phase output terminal of the last D flip-flop serves as the signal output terminal of the frequency division circuit.

10. A method for implementing four-mode integer frequency division, based on the four-mode integer frequency division circuit of claim 3, characterized in that: The following steps are involved: The data input terminal D1 of the flip-flop DFF1 is connected to the inverting output terminal Q2B of the flip-flop DFF2, so that D1=Q2B is realized; D2=(S1+Q1)&(S0+Q2B) is realized through a two-input logic OR gate circuit I1, a two-input logic OR gate circuit I2, and a two-input logic AND gate circuit I3; Assume that the initial states of the in-phase output terminal Q2 of the flip-flop DFF2 and the in-phase output terminal Q1 of the flip-flop DFF1 are 00: When the frequency division ratio control signal S1=0, the frequency division ratio control signal S0=0, D1=Q2B, D2=Q1&Q2B, under the action of the CLK clock, the state of Q2 Q1 cycles in 00-01-11-00, and the in-phase output terminal Q2 of the trigger DFF2 realizes 3-frequency division; When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=1, D1=Q2B and D2=Q1. Under the action of the CLK clock, the states of Q2 and Q1 cycle through 00-01-11-10-00, and the in-phase output terminal Q2 of the flip-flop DFF2 realizes 4-frequency division. When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=0, D1=Q2B and D2=Q2B. Under the action of the CLK clock, the states of Q2 Q1 cycle from 00-11-00, and the in-phase output terminal Q2 of the trigger DFF2 realizes 2-frequency division. When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=1, D1=Q2B and D2=1. Under the action of the CLK clock, the states of Q2 and Q1 cycle through 00-11-10-10-10-10. The in-phase output terminal Q2 of the flip-flop DFF2 is finally fixed at a high level, and frequency division is not achieved. Then, OUT= Q2 & (S1&S0&CLK) is realized through the three-input logic AND gate circuit I4 and the two-input logic AND gate circuit I5; When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=0, OUT= Q2, and the OUT signal achieves 3-frequency division; When the frequency division ratio control signal S1=0 and the frequency division ratio control signal S0=1, OUT= Q2, and the OUT signal achieves 4-frequency division; When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=0, OUT= Q2, and the OUT signal achieves 2-frequency division; When the frequency division ratio control signal S1=1 and the frequency division ratio control signal S0=1, OUT= Q2&CLK. Since Q2=1 at this time, OUT= CLK, and the OUT signal achieves 1 division.

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