Driving assembly of frequency divider and driving method thereof

Abstract

The invention provides a driving assembly of a frequency divider and a driving method thereof. The driving assembly comprises a clock selection module and a frequency division module which are connected in sequence; the clock selection module is used for controlling selection of a frequency division reference clock and carrying out real-time burr-free clock switching and reset synchronization; and the frequency division module is used for generating high-precision frequency division clock output of any one of odd frequency division, even frequency division, decimal frequency division and fractional frequency division under different main frequencies according to off-chip configuration information configuration. According to the high-precision frequency divider, frequency division clock signals with different frequencies can be generated for a plurality of controlled equipment chips at the rear end, the overall structure of the high-precision frequency divider can be greatly simplified, and the integration level and efficiency of a driving assembly are improved. Compared with a traditional scheme, a more complex and higher-precision frequency division function can be realized, and meanwhile, the design and verification difficulty of the driving circuit is lower.

Description

Technical Field

[0001] The invention provides a driving component of a frequency divider and a driving method thereof, belonging to the field of digital integrated circuits. Background Art

[0002] The frequency divider circuit is a circuit used to divide the clock frequency according to a certain frequency division ratio, by reducing the frequency of the input signal to the required target frequency. The frequency divider circuit can provide support for various modules and has many important functions in electronic systems. It is widely used in wireless communications, digital signal processing and other fields, including clock generation, frequency synthesis, signal processing, timing, modulation and demodulation, and data transmission.

[0003] The current mainstream design scheme for the driving circuit of the frequency divider circuit is a top-down design method, that is, first plan the top-level clock frequency division requirements, and then design the front-end and back-end circuits based on the requirements. This scheme needs to first design the frequency division requirements based on the hardware structure of the array drive circuit and the readout circuit of the overall chip, and finally design the control logic to generate the target frequency clock. The design and implementation of a fractional frequency divider may be more complicated than an integer frequency divider. The accuracy of the frequency divider circuit is lower, the flexibility of the adjustable frequency division is low, and the manpower and docking costs of subsequent verification are very high, so more design and testing work is required, resulting in increased costs. Complex designs also lead to higher power consumption and more circuit components. Summary of the invention

[0004] In view of the above problems existing in the prior art, the present invention proposes a driving component of a frequency divider and a driving method thereof, which can greatly simplify the overall structure of the high-precision frequency divider and improve the integration and efficiency of the system.

[0005] The technical solution adopted by the driving assembly of the present invention is as follows:

[0006] A drive component of a frequency divider comprises a clock selection module and a frequency division module connected in sequence; the clock selection module is used to control the selection of a frequency division reference clock and to perform real-time glitch-free clock switching and reset synchronization; the frequency division module is used to generate a high-precision frequency division clock output of any frequency division type among odd frequency division, even frequency division, decimal frequency division and fractional frequency division under different main frequencies according to off-chip configuration information.

[0007] The present invention also provides a driving method of a driving component using the frequency divider, which is used to generate frequency-divided clock signals with different frequencies for a plurality of controlled device chips at the back end.

[0008] Furthermore, the driving method of the driving component of the frequency divider is used to generate fractional frequency division, which specifically includes the following steps:

[0009] S1, reference clock selection: after the clock selection module receives the external configuration information Config_Data, if it only contains an input clock Clock and an off-chip input signal of the reset signal Rst, the clock selection module will synchronize the external reset signal according to the input clock, and then output the synchronization reset signal Rst_n and the output reference clock Clock_ref to the subsequent frequency division module; after the clock selection module receives the type of the controlled device chip and the working mode signal Config_Type and multiple ideal arbitrary frequency reference clocks Clock_n, the frequency division module is configured to select the reference clock Clock_ref based on the signal Config_Type after the combination judgment logic; when the clock switching enable signal Clock_SelectValid is pulled high, the clock selection module realizes real-time glitch-free clock switching according to the type of the controlled device chip and the change of the working mode signal Config_Type;

[0010] S2, perform clock frequency division: after receiving the off-chip configuration information Config_DivRatio, the frequency division module determines the type and frequency division ratio of the frequency division clock through the combinational logic, and configures the corresponding storage unit frequency division fractional value DivRatio_Fra, the fractional frequency division period PeriodNum, the odd frequency division high level count value DivRatio_Int_M_1 and the even frequency division high level count value DivRatio_Int_M_2; the frequency division submodule starts working when the synchronous reset signal Rst_n is at a low level, and the frequency division submodule shares the PeriodCounter counting unit to count according to the odd frequency division period number and the even frequency division period number, and under the control of the odd-even frequency division switching flag signal PeriodFlag, controls the odd frequency division submodule and the even frequency division submodule to realize the DivRatio_Int frequency division of the number of PeriodNum-DivRatio_Fra and the DivRatio_Int+1 frequency division of the number of DivRatio_Fra within the period, thereby realizing the output of the high-precision frequency division clock.

[0011] Compared with the traditional solution, the present invention can realize a more complex and higher precision frequency division function, and the driving circuit design and verification difficulty is lower, and specifically has the following beneficial effects:

[0012] (1) The driving component of the present invention decouples the original on-chip frequency-divided clock generation module and divides it into two modules, including a clock selection module and a frequency-dividing module. Each module is flexibly adjustable and can be combined to realize flexible configuration and switching of any driving clock main frequency of different device chips in different modes, thereby meeting the needs of on-chip driving in multiple devices and multiple modes, and improving the integration and efficiency of the driving component.

[0013] (2) The frequency division module of the present invention has low hardware complexity, and the sub-modules can be repeatedly instantiated in batches. The reusability of the frequency division module shortens the design cycle. By instantiating multiple frequency division modules, based on the off-chip configuration information and the ideal frequency division reference clock, the requirements of flexible configuration and real-time switching of high-precision arbitrary frequency clocks in different modes of different devices can be met without additional individual customized design.

[0014] (3) The driving method of the present invention includes data configuration writing, device type classification, frequency division storage unit configuration and frequency division clock driving configuration. The driving method can flexibly and efficiently configure and generate a high-precision frequency division clock signal with any frequency division rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of a digital control circuit of a drive component of a frequency divider in an embodiment of the present invention;

[0016] Figure 2 is a flow chart of a digital control circuit driving method of a driving component of a frequency divider in an embodiment of the present invention;

[0017] Figure 3 1 is a timing diagram of fractional frequency division driving of the frequency divider in an embodiment of the present invention (taking the division rate of 3.12 as an example). DETAILED DESCRIPTION

[0018] The present invention proposes a drive component of a frequency divider and a drive method thereof. By using the drive component of the present invention, the frequency divider can realize storage unit data configuration of different modes for different controlled device chips according to the type of controlled device and the coding information of the working mode, and can batch provide frequency division clocks with multiple frequency division ratios required by multiple controlled device chips.

[0019] The driving component of this embodiment includes a clock selection module and a frequency division module. The clock selection module is used to control the selection of the frequency division reference clock and perform real-time glitch-free clock switching and reset synchronization, and can select a suitable frequency division reference clock according to the device chip type and working mode; the frequency division module can be used as a universal modulation unit to generate high-precision frequency division clock output of any frequency division type among odd frequency division, even frequency division, decimal frequency division and fractional frequency division under different main frequencies according to the off-chip configuration information, so as to meet the needs of different device chips.

[0020] This embodiment provides a method for driving a frequency divider, the steps of which are shown in the flowchart. Figure 1 shown. Figure 1 In the figure, Config_data is the off-chip configuration information; Clock_ref is the frequency-divided reference clock selected according to the device chip type and functional mode; Rst_n is the synchronous reset signal; Clock_out is the output frequency-divided clock; CountNum is the clock test count value.

[0021] Figure 2 The specific module block diagram of the numerical control circuit of the drive component is shown. Figure 2 In the , Config_data, Config_DivRatio, and Config_Test are off-chip data configuration parameters; Decoder is a decoding logic module; ClockSwitch is a clock switching module; Synchronous is a synchronization module; Clock_ref is an output reference clock; Rst_n is a synchronous reset signal; ODD FD is an odd-number division module; EVEN FD is an even-number division module; LR FD is a small-two division module; Verif_Block is a division clock verification module; Clock_out is an output division clock; CountNum is a clock test module count value; Judge_Logic is a combination judgment logic unit; Data_Processing Unit is a data processing unit; PeriodNum is the value configured in the fractional division period storage unit; DivRatio_Fra is the value configured in the odd division period storage unit in fractional division; DivRatio_Int is the value configured in the division rate rounded down to an integer storage unit; DivRatio_Int_M_1 is the value configured in the odd division high level duration storage unit in fractional division; DivRatio_Int_M_2 is the value configured in the even division high level duration storage unit in fractional division; PeriodFlag is the odd-even division switching flag signal; EvenCounter is the even division counting unit; OddCounter is the odd division counting unit; OddCounter_r is the odd division delay counting unit; SinCounter is the reference clock counting unit; TestCounter is the test module counting unit).

[0022] The clock selection module is adapted to 1 digital input signal and 2 digital output signals, wherein 1 digital input signal is off-chip data configuration information Config_data, and 2 digital output signals are output reference clock Clock_ref and synchronous reset signal Rst_n. The off-chip data configuration information Config_data includes n ideal arbitrary frequency input clocks Clock_n or off-chip input device reset signals Rst, n≥1, or may also include the type of device chip and the working mode signal Config_Type and / or the clock switching enable signal Clock_SelectValid, and the type of device chip and the working mode signal Config_Type include device number information and controlled device working mode information, such as at least one of the programming mode, read-write mode, drive mode and other modes.

[0023] Specifically, the clock selection module includes a decoding module Decorder, a clock switching module ClockSwitch and a synchronization module Synchronous. The decoding module can perform decoding according to the off-chip configuration information Config_Type signal, and select a suitable clock from n ideal arbitrary frequency reference clocks Clock_n through a selector as the output reference clock Clock_ref. The off-chip configuration information can realize real-time configuration, but the output reference clock will not be switched. The clock switching enable signal Clock_SelectValid and the off-chip configuration information Config_Type together control the switching of the output reference clock; when the clock switching enable signal Clock_SelectValid is received as high, the clock switching module performs glitch-free clock switching to avoid glitches and clock Jetters caused by clock switching, and adapts to the various requirements of different device chips for the working main frequency in different mode stages; the synchronization module can synchronize the off-chip reset signal Rst according to the selected output reference clock Clock_ref, thereby avoiding the generation of metastable internal circuits caused by the reset signal.

[0024] The frequency division module is adapted to at least 3 digital input signals and 1 digital output signal, wherein in this embodiment, 4 digital input signals are adapted, namely, the off-chip configuration information Config_DivRatio, the test module configuration information Config_Test, the output reference clock Clock_ref and the synchronous reset signal Rst_n from the clock selection module, and 1 digital output signal is the frequency division clock Clock_out required by the controlled device chip. The off-chip configuration information Config_DivRatio includes the frequency division type, such as odd frequency division, even frequency division, decimal frequency division, fractional frequency division; integer value of the frequency division; decimal value of the frequency division, etc. The test module configuration information Config_Test includes the ideal high-frequency test clock Clock_Test and the test enable signal Clock_Test_Valid. The frequency division clock Clock_out is preferably a one-dimensional array signal, but this does not constitute a limitation.

[0025] Specifically, the frequency division module includes a decoding module, an odd frequency division submodule (ODD FD), an even frequency division submodule (EVEN FD), a small two-frequency division submodule (LR FD) and a frequency division clock test module, wherein the odd frequency division submodule, the even frequency division submodule and the small two-frequency division submodule can be instantiated into k module groups, and k can be customized according to different requirements. If only a single odd frequency division is implemented, only the odd frequency division submodule needs to be instantiated; if it is a universal frequency divider that can meet the frequency division requirements of multiple devices, instantiating the same number is more convenient for the design of the front and back ends, wherein k is the number of frequency division clocks, and k is a positive integer. The frequency division module can be expanded according to the device chip type and function, and each module group in the k module groups can work independently, and at the same time, the generation of frequency division clocks under different division rates can be realized. The decoding module decodes according to the data configuration information Config_DivRatio and outputs the decoded data to the internal submodules to configure and select the data of each submodule, while the submodules that are not selected are in a standby state, and the internal k submodules realize the output of the divided clock with different division rates under the same clock main frequency. Specifically, the decoding module includes a judgment logic unit and a data processing unit, wherein the judgment logic unit decodes according to the off-chip configuration information Config_DivRatio through the internal combinational logic, selects the subsequent k module groups and configures the data of the storage unit DivRatio_Fra and PeriodNum according to the division type and division rate, and the data processing unit is responsible for processing the off-chip configuration information Config_DivRatio and configuring the storage units DivRatio_Int_M_1 and DivRatio_Int_M_2. The odd-numbered frequency-division submodule can be configured to generate an odd-numbered frequency-division clock with a duty cycle of 0.5. The even-numbered frequency-division submodule can be configured to generate an even-numbered frequency-division clock with a duty cycle of 0.5. The small two-division submodule can be configured to generate high-precision fractional frequency division with a division rate less than 2 to meet the requirements for the quality of the frequency division clock. The high-precision fractional frequency division with a division rate greater than 2 is generated by the odd-number division submodule and the even-number division submodule. The frequency division clock test module starts working after receiving the test enable signal Clock_Test_Valid, and uses the test clock Clock_Test to sample and count the output frequency division clock. The count value is stored in the built-in storage unit of the frequency division clock test module, and the output is the clock test count value CountNum, thereby judging the frequency division accuracy of the frequency division clock.

[0026] The specific driving process of the frequency division module is as follows: the judgment logic unit in the decoding module determines the frequency division type and selects the subsequent k module groups based on the off-chip configuration information Config_DivRatio. When the frequency division type of one module group is 2'b10 decimal frequency division, the decimal value of the frequency division rate is decoded as DivRatio_Fra and PeriodNum and input into the frequency division submodule. DivRatio_Fra is the decimal value of the frequency division rate, that is, the number of frequency divisions within the period of DivRatio_Int+1 frequency division, PeriodNum is the decimal frequency division period, and PeriodNum-DivRatio_Fra is the number of frequency divisions within the period of DivRatio_Int frequency division. When the frequency division rate is a single decimal place, PeriodNum is 10; when the frequency division rate is a double decimal place, PeriodNum is 100. The integer value of the frequency division rate is decoded as DivRatio_Int and input into the data processing unit, and calculated using the following formula:

[0027] Odd-number division high level count value

[0028] Even-numbered high-level count value

[0029] The odd-numbered frequency division high-level count value DivRatio_Int_M_1 and the even-numbered frequency division high-level count value DivRatio_Int_M_2 are respectively configured to the odd-numbered frequency division submodule and the even-numbered frequency division submodule, and the submodules start working after the synchronous reset Rst_n is pulled low. When the odd-even frequency division switching flag signal PeriodFlag is high, the built-in counting units OddCounter and OddCounter_r of the odd-numbered frequency division submodule start counting under the triggering of the rising edge and falling edge of the frequency division reference clock Clock_ref, and output a high-level signal. After the count value of the counting unit is greater than DivRatio_Int_M_1, a low-level signal is output. When the count reaches the frequency division number, the built-in counting unit is reset and starts counting again. After the two counting units pass through the logic AND gate, they output the odd-numbered frequency division clock Clk_odd. The even-number frequency division submodule also uses the built-in counting unit EvenCounter to start working when the odd-even frequency division switching flag signal PeriodFlag is low according to the even-number frequency division high-level count value DivRatio_Int_M_2, and outputs the even-number frequency division clock Clk_Even. The two frequency division submodules share the PeriodCounter counting unit to count the frequency division numbers in the odd-number frequency division period and the frequency division numbers in the even-number frequency division period, that is, PeriodNum-DivRatio_Fra and DivRatio_Fra, to control the pulling up or pulling down of the odd-even frequency division switching flag signal PeriodFlag, and use the count values ​​of PeriodFlag and PeriodCounter counting units to control the odd-number frequency division and even-number frequency division submodules to realize DivRatio_Int frequency division and DivRatio_Int+1 frequency division to achieve high-precision fractional frequency division of any frequency division rate.

[0030] When the frequency division type is 2'b11 fractional frequency division, the integer value and decimal value of the fractional frequency division represent the denominator and numerator values ​​respectively. The numerator value of the fractional frequency division is decoded as PeriodNum and input to the post-frequency division submodule, and the denominator value T1 and numerator value T2 of the fractional frequency division are input to the data processing unit.

[0031] DivRatio_Int=T1 / T2

[0032] DivRatio_Fra=T1mod T2

[0033]

[0034] With fractional frequency division, the two frequency division submodules share the PeriodCounter counting unit to count according to the odd and even frequency division cycles, and use the DivRatio_Int frequency division of the PeriodNum-DivRatio_Fra times and the DivRatio_Int+1 frequency division of the DivRatio_Fra times in the cycle to achieve high-precision fractional frequency division. When the division rate is a fractional frequency division between 1 and 2, the frequency division submodule uses the small two-division submodule to achieve high-precision frequency division. The small two-division submodule uses the built-in counting units SinCounter and EvenCounter to count the high and low level durations of the division clock. The signals output by the two counting units pass through the clock switching selection module to avoid the generation of glitches caused by the clock switching selection when the division rate is low, thereby resulting in poor quality of the division clock. The frequency division submodule passes through a first-level data selector to ensure the correctness of the frequency division clock and inputs it into the subsequent frequency division clock test module. When the division ratio is less than 1, the built-in protection logic of the component will directly select the frequency division reference clock Clock_ref as the frequency division clock Clock_out output in the first-level data selector. The frequency division clock test module tests the frequency division clock according to the off-chip configuration information Config_Test. The Config_Test signal includes an ideal high-frequency test clock Clock_Test and a test enable signal Clock_Test_Valid, wherein the ideal high-frequency test clock Clock_Test samples and counts the output frequency division clock when the test enable signal Clock_Test_Valid is high, and the count value is stored in the built-in storage unit of the frequency division clock test module, and the output is the clock test count value CountNum. The accuracy of the frequency division clock is determined off-chip based on the comparison of the high-level duration of Clock_Test_Valid with the output signal CountNum of the clock test module.

[0035] Figure 3The timing diagram of fractional frequency division clock generation with a frequency division rate of 3.12 as an example is shown. The judgment logic unit in the decoding module decodes the fractional value of the frequency division rate into DivRatio_Fra and PeriodNum according to the off-chip configuration information Config_DivRatio, and inputs it into the frequency division subunit. The fractional value of the frequency division rate DivRatio_Fra is 12, and the fractional frequency division period PeriodNum is 100. The integer value of the frequency division rate is decoded as DivRatio_Int and input into the data processing unit, and the odd frequency division high level count value DivRatio_Int_M_1 is calculated to be 1, and the even frequency division high level count value DivRatio_Int_M_2 is 2. The two frequency division submodules share the PeriodCounter counting unit to count the odd frequency division cycle number and the even frequency division cycle number. When the odd-even frequency division switching flag signal PeriodFlag is high, the odd frequency division submodule is controlled to implement the DivRatio_Int(3) frequency division of PeriodNum-DivRatio_Fra(88) times in the cycle. When the odd-even frequency division switching flag signal PeriodFlag is low, the even frequency division submodule is controlled to implement the DivRatio_Int+1(4) frequency division of DivRatio_Fra(12) times in the cycle to achieve high-precision 3.13 frequency division.

[0036] The drive component of the divider provided by the present invention can meet the needs of different devices for flexible configuration and real-time switching of different divided clocks in multiple modes by configuring the division ratio and clock switching selection outside the chip without the need for additional separate customized design, thereby improving the flexibility of the high-precision divider.

Claims

1. A drive assembly for a frequency divider, characterized in that: The driving component includes a clock selection module and a frequency division module connected in sequence; The clock selection module is used to control the selection of the frequency-divided reference clock and to perform real-time glitch-free clock switching and reset synchronization; The frequency division module is used to generate a high-precision frequency division clock output of any frequency division type among odd frequency division, even frequency division, decimal frequency division and fractional frequency division under different main frequencies according to off-chip configuration information.

2. A drive assembly for a frequency divider according to claim 1, characterized in that: The clock selection module adapts to 1 digital input signal and 2 digital output signals, wherein 1 digital input signal is off-chip data configuration information Config_data, and 2 digital output signals are output reference clock Clock_ref and synchronous reset signal Rst_n; the off-chip data configuration information Config_data includes n ideal arbitrary frequency input clocks Clock_n or off-chip input device reset signals Rst, n≥1, or also includes the type of device chip and working mode signal Config_Type and / or clock switching enable signal Clock_SelectValid.

3. A drive assembly for a frequency divider according to claim 2, characterized in that: The clock selection module includes a decoding module, a clock switching module and a synchronization module; The decoding module decodes according to the type of the device chip and the working mode signal Config_Type, and selects a suitable frequency-divided reference clock Clock_ref; The clock switching module performs glitch-free clock switching in real time according to the clock switching enable signal Clock_SelectValid, adapting to various requirements of different device chips for working main frequency in different mode stages; The synchronization module performs synchronization operation on the off-chip reset signal Rst according to the reference clock Clock_ref, thereby avoiding the generation of a metastable state of the internal circuit caused by the reset signal.

4. The driving component of a frequency divider according to claim 1, characterized in that: The frequency division module is adapted to at least 3 digital input signals and 1 digital output signal, wherein the at least 3 digital input signals are respectively the off-chip configuration information Config_DivRatio, the reference clock Clock_ref from the clock selection module and the synchronous reset signal Rst_n; and the 1 digital output signal is the frequency division clock Clock_out required by the controlled device chip.

5. A drive assembly for a frequency divider according to claim 4, characterized in that: The off-chip configuration information Config_DivRatio includes a frequency division type, a frequency division integer value, and a frequency division decimal value.

6. The driving component of a frequency divider according to claim 1, characterized in that: The frequency division module includes a decoding module, an odd frequency division submodule, an even frequency division submodule, a small two-division submodule and a frequency division clock test module; the odd frequency division submodule is used to configure and generate an odd frequency division clock with a duty cycle of 0.5, the even frequency division submodule is used to configure and generate an even frequency division clock with a duty cycle of 0.5, and the small two-division submodule is used to configure and generate a high-precision fractional frequency division with a division ratio less than 2.

7. A drive assembly for a frequency divider according to claim 6, characterized in that: The frequency-divided clock test module tests the frequency-divided clock according to the off-chip configuration signal Config_Test, wherein the signal Config_Test includes an ideal high-frequency test clock Clock_Test and a test enable signal Clock_Test_Valid, wherein the test clock Clock_Test samples and counts the output frequency-divided clock when the test enable signal Clock_Test_Valid is high, and the count value is stored in the built-in storage unit of the frequency-divided clock test module, and the output is the clock test count value CountNum, thereby judging the frequency division accuracy of the frequency-divided clock.

8. The driving component of a frequency divider according to claim 6, characterized in that: The odd-numbered frequency division submodule, the even-numbered frequency division submodule and the smaller-than-two frequency division submodule can be expanded to k, where k is the number of frequency division clocks and is a positive integer; the decoding module decodes according to the data configuration information and outputs the decoded data to each submodule to perform data configuration and selection on the submodule, and the submodule that is not selected is in a standby state, and the k submodules realize frequency division clock outputs with different division rates under the same clock main frequency.

9. A driving method using a driving component of a frequency divider as claimed in claim 1, characterized in that: A driving component comprising the frequency divider as claimed in any one of claims 1 to 8, used for generating frequency-divided clock signals of different frequencies for a plurality of controlled device chips at the back end.

10. The driving method according to claim 9, characterized in that: The driving method generates fractional frequency division, and specifically includes the following steps: S1, reference clock selection: after the clock selection module receives the external configuration information Config_Data, if it only contains an input clock Clock and an off-chip input signal of the reset signal Rst, the clock selection module will synchronize the external reset signal according to the input clock, and then output the synchronization reset signal Rst_n and the output reference clock Clock_ref to the subsequent frequency division module; after the clock selection module receives the type of the controlled device chip and the working mode signal Config_Type and multiple ideal arbitrary frequency reference clocks Clock_n, the frequency division module is configured to select the reference clock Clock_ref based on the signal Config_Type after the combination judgment logic; when the clock switching enable signal Clock_SelectValid is pulled high, the clock selection module realizes real-time glitch-free clock switching according to the type of the controlled device chip and the change of the working mode signal Config_Type; S2, perform clock frequency division: after receiving the off-chip configuration information Config_DivRatio, the frequency division module determines the type and frequency division ratio of the frequency division clock through the combinational logic, and configures the corresponding storage unit frequency division fractional value DivRatio_Fra, the fractional frequency division period PeriodNum, the odd frequency division high level count value DivRatio_Int_M_1 and the even frequency division high level count value DivRatio_Int_M_2; the frequency division submodule starts working when the synchronous reset signal Rst_n is at a low level, and the frequency division submodule shares the PeriodCounter counting unit to count according to the odd frequency division period number and the even frequency division period number, and under the control of the odd-even frequency division switching flag signal PeriodFlag, controls the odd frequency division submodule and the even frequency division submodule to realize the DivRatio_Int frequency division of the number of PeriodNum-DivRatio_Fra and the DivRatio_Int+1 frequency division of the number of DivRatio_Fra within the period, thereby realizing the output of the high-precision frequency division clock.

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