A PTP time-frequency synchronization method for distributed data synchronization acquisition

Abstract

The present invention discloses a PTP time and frequency synchronization method for distributed data synchronous acquisition. The method comprises the following steps: firstly, building a PTP synchronization architecture of a distributed data acquisition system; then generating a hardware timestamp based on a slave hardware clock; finally, based on the PTP synchronization architecture of the distributed data acquisition system, adopting a three-level synchronization mechanism to achieve high-precision time and frequency synchronization between each slave and a host, so that synchronous sampling of each slave is completed under the premise of periodic PTP synchronization between the master and the slave.

Description

Technical Field

[0001] The present invention belongs to the technical field of distributed data acquisition, and more particularly, relates to a PTP time-frequency synchronization method for distributed data synchronous acquisition. Background Art

[0002] Distributed data acquisition systems are a key component of modern measurement and control engineering. They help prevent noise interference caused by long-distance transmission of analog signals from front-end sensors. This technology is widely used in factory automation, smart grids, large wind tunnels, large turbine shafts, long-span bridges, nuclear physics experiments, and telescope arrays.

[0003] In a distributed data acquisition system, distributed data acquisition devices are required to collect multiple correlated signals for joint data processing and analysis. This requires time synchronization of these distributed acquisition devices, assigning time information to sampled data points and ensuring point-to-point synchronization of the collected data. Furthermore, with the rapid advancement of technology, the performance of data acquisition systems is becoming increasingly demanding, requiring not only time synchronization of the distributed data acquisition system but also sampling synchronization (i.e., synchronization of the sampling clock frequency and phase) across each distributed data acquisition device.

[0004] The Precision Time Protocol (PTP) is a high-precision Ethernet-based network time synchronization protocol. With its low cost, high synchronization accuracy, and minimal resource consumption, it has been widely researched and applied in the field of distributed data acquisition. PTP exchanges message data and records timestamps on a master-slave link. The slave receives the four timestamps (t1, t2, t3, and t4) and calculates the average delay of the master-slave link and the clock deviation between the master and slave nodes. A synchronization algorithm then synchronizes the slave's time with the master. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a PTP time-frequency synchronization method for distributed data synchronous acquisition, so as to achieve high-precision time and frequency synchronization between each slave and a master in a distributed data acquisition system.

[0006] To achieve the above object of the invention, the present invention provides a PTP time-frequency synchronization method for distributed data synchronous acquisition, characterized in that it includes the following steps:

[0007] (1) Build a PTP synchronization architecture for distributed data acquisition systems;

[0008] Select a switch that supports PTP hardware synchronization as the PTP synchronization host, and the distributed data acquisition system as the PTP synchronization slave, and directly connect the slave to the switch host via a network cable;

[0009] (2) Generation of hardware clock and hardware timestamp;

[0010] Set each slave to use a voltage-controlled crystal oscillator (VCXO) as the hardware clock source;

[0011] Set the initial value of the timestamp of each slave. The real-time clock module RTC in the slave PTP hardware clock system uses the initial value of the timestamp as the starting point and generates the PTP hardware timestamp T of each slave based on the accumulated time base value of the hardware clock. i , where i represents the slave number;

[0012] (3) The master and slave machines perform periodic PTP synchronization;

[0013] (3.1) Set the cycle number k and initialize k = 1;

[0014] (3.2) Each slave establishes a PTP protocol stack to implement PTP synchronization message exchange, based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k);

[0015] (3.3) Calculate the link delay d during the kth PTP synchronization between the master and slave devices. i (k);

[0016]

[0017] (3.4) Calculate the time deviation θ of the kth PTP synchronization between the master and slave devices. i (k);

[0018] θ i (k) = t 2,i (k)-t 1,i (k)-d i (k)

[0019] (3.5) Determine the time deviation θ i (k) Are they all less than the synchronization completion time deviation threshold θ sync , if θ i (k)<θ sync , then each slave is enabled to start synchronous sampling, and the three-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the master; otherwise, only the three-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the master;

[0020] (3.6) Let k = k + 1, and return to step (3.2) after the next synchronization cycle arrives to continue the next round of PTP synchronization.

[0021] The object of the invention of the present invention is achieved like this:

[0022] The present invention discloses a PTP time-frequency synchronization method for distributed data synchronous acquisition. The method comprises the following steps: firstly, building a PTP synchronization architecture of a distributed data acquisition system; then, generating a hardware timestamp based on a slave hardware clock; finally, based on the PTP synchronization architecture of the distributed data acquisition system, adopting a three-level synchronization mechanism to achieve high-precision time and frequency synchronization between each slave and a master, thereby completing synchronous sampling of each slave under the premise that the master and slave perform periodic PTP synchronization.

[0023] At the same time, the PTP time-frequency synchronization method for distributed data synchronous acquisition of the present invention also has the following beneficial effects:

[0024] (1) Using the PTP hardware synchronization solution, the design timestamps at the MII interface. Compared with PTP software synchronization, timestamps at the application layer reduce the timestamp error from microseconds to nanoseconds, significantly improving synchronization accuracy. Compared with PTP hardware synchronization timestamps at the PHY layer, timestamps at the MII interface do not require a PHY chip that supports PTP hardware synchronization, reducing hardware costs while maintaining the same nanosecond error level.

[0025] (2) A three-level synchronization mechanism is used to achieve fast time and frequency synchronization of the distributed data acquisition system. First, the first-level synchronization directly compensates for the time deviation of the master and slave machines, directly reducing the time synchronization accuracy of the master and slave machines from the second level to the millisecond level. The second-level synchronization uses a PI controller combined with a corrected timestamp to generate a time base, which can quickly reduce the time synchronization accuracy of the master and slave machines from the millisecond level to the hundred nanosecond level within dozens of cycles. The third-level synchronization uses a PI controller combined with a voltage-controlled VCXO crystal oscillator clock source, which can reduce the time synchronization accuracy of the master and slave machines and stabilize it within ±20ns within a few cycles, and complete the frequency synchronization of the master and slave clock sources.

[0026] (3) Sampling synchronization technology realizes the sampling synchronization and sampling data point synchronization of each distributed data acquisition system. Based on the ADC synchronous reset triggered by the 1PPS synchronization signal, it can realize the high-precision synchronous start sampling of each distributed data acquisition system. The clock phase-locked frequency division technology is based on the 1PPS synchronization signal. Compared with the commonly used counting frequency division method, it can achieve nanosecond-level high-precision ADC sampling clock phase synchronization and complete the high-precision sampling synchronization of each distributed data acquisition system. The sampling data point timestamp technology gives each sampling data point a timestamp information to realize the sampling point synchronization of each distributed data acquisition system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of a PTP time-frequency synchronization method for distributed data synchronous acquisition according to the present invention;

[0028] Figure 2This is a diagram of the PTP synchronization architecture of a distributed data acquisition system;

[0029] Figure 3 This is a schematic diagram of the RTC module generating timestamps;

[0030] Figure 4 It is a flowchart for implementing the three-level synchronization mechanism. DETAILED DESCRIPTION

[0031] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0032] Example

[0033] For the convenience of description, the relevant professional terms appearing in the specific implementation methods are first explained:

[0034] PTP (Precision Time Protocol): Precision Time Protocol;

[0035] VCXO (voltage-controlled crystal oscillator): voltage-controlled crystal oscillator;

[0036] AXI GP (Advanced eXtensible Interface General Purpose): General-purpose interface for advanced extensible interfaces;

[0037] RTC (Real Time Clock): Real-time clock;

[0038] PI (Proportional Integral Controller): Proportional Integral Controller;

[0039] DAC (Digital to Analog Converter): digital to analog converter;

[0040] ADC (Analog to Digital Converter): analog-to-digital converter;

[0041] 1PPS (One Pulse Per Second): 1 pulse per second;

[0042] TSU (Time Stamp Unit): time stamp unit;

[0043] PHC (PTP Hardware Clock): PTP hardware clock;

[0044] GMII (Gigabit Media Independent Interface): Gigabit Media Independent Interface;

[0045] ARM: ARM processor;

[0046] MII (Media Independent Interface): media independent interface;

[0047] PHY (Physical Layer): physical layer;

[0048] FPGA (Field Programmable Gate Array): Field Programmable Gate Array;

[0049] Linuxptp: an open source PTP software protocol stack;

[0050] H3C IE4320: H3C IE4320 switch.

[0051] Xilinx ZYNQ: A fully programmable system-on-chip from Xilinx.

[0052] SoC (System on Chip): System on chip;

[0053] Figure 1 The present invention is a PTP time-frequency synchronization principle diagram for distributed data synchronous acquisition.

[0054] In this embodiment, combined with Figure 1 The PTP time-frequency synchronization principle diagram shown in FIG. 1 is a detailed description of a PTP time-frequency synchronization method for distributed data synchronous acquisition according to the present invention, comprising the following steps:

[0055] (1) Build a PTP synchronization architecture for distributed data acquisition systems;

[0056] Select a switch that supports PTP hardware synchronization as the PTP synchronization host, and the distributed data acquisition system as the PTP synchronization slave, and directly connect the slave to the switch host via a network cable;

[0057] In this embodiment, the PTP synchronization architecture of the distributed data acquisition system is as follows: Figure 2As shown, an H3C IE4320 switch is used as the PTP synchronization master, supporting PTP hardware synchronization. Two distributed data acquisition devices are connected to the switch network cable as PTP synchronization slaves. A PC host computer is connected to the switch network cable and is responsible for programmable control of the distributed data acquisition devices and receiving and processing sampled data. In this embodiment, the two slaves achieve time and frequency synchronization with the switch master using PTP time and frequency synchronization technology. Sampling synchronization is achieved between the two slaves based on the hardware clock source of time and frequency synchronization.

[0058] Furthermore, the distributed data acquisition devices (slave devices) use the Xilinx ZYNQ as the master SoC. ZYNQ utilizes an FPGA + ARM architecture, deploying a PTP hardware clock system on the FPGA and a PTP protocol stack and clock servo system on the ARM. Furthermore, the hardware circuitry, including the PHY, VCXO, DAC, and ADC, was designed.

[0059] (2) Generation of hardware clock and hardware timestamp;

[0060] Each slave is configured to use a voltage-controlled crystal oscillator (VCXO) as its hardware clock source. In this embodiment, the hardware clock of each slave uses a 125MHz clock from the RGMII interface of the PHY chip, which is multiplied to 125MHz by a phase-locked loop (PLL) inside the PHY chip using a voltage-controlled crystal oscillator (VCXO) 25MHz clock.

[0061] Set the initial value of the timestamp of each slave. The real-time clock module RTC in the slave PTP hardware clock system uses the initial value of the timestamp as the starting point and generates the PTP hardware timestamp T of each slave based on the accumulated time base value of the hardware clock. i , where i represents the slave number;

[0062] In this embodiment, the timestamp generation is realized by the RTC module of the PTP hardware clock. The RTC module is implemented on the FPGA side and is based on the accumulator principle. It directly compensates the timestamp according to the time adjustment value and accumulates the time base value under the hardware clock to generate a synchronized timestamp. Figure 3 As shown, in the actual operation of FPGA, a 48-bit second register is designed to store the timestamp second information, and a 32-bit nanosecond register is designed to store the maximum 10 9 The timestamp nanosecond information of the value. The resolution of 1 in calculating the adjustment value is equal to 8×10 of the time base value. -9 Nanoseconds are required, so a 32-bit sub-nanosecond clock register is designed to store sub-nanosecond timestamp information. During PTP synchronization, the time adjustment value and time base value used in timestamp generation are both sent by the clock servo system via the AXI_GP interface. At system power-up, the RTC module receives the system time and the 8ns standard time base from the ARM terminal and uses this as a starting point to accumulate and generate the hardware timestamp.

[0063] (3) The master and slave machines perform periodic PTP synchronization;

[0064] (3.1) Set the cycle number k and initialize k = 1;

[0065] (3.2) Each slave establishes a PTP protocol stack to implement PTP synchronization message exchange, based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k);

[0066] In this embodiment, the timestamp information t of the kth PTP synchronization is 1,i (k)-t 4,i (k) is obtained by:

[0067] (3.2.1) When each slave system is initialized, the PTP protocol stack configures the PHC subsystem, enables the hardware timestamp function and selects the network data packets that need to be stamped, enabling the kernel to obtain timestamps when receiving and sending data packets;

[0068] (3.2.2) In this embodiment, the master switch sends a Sync message to the slave device with a period of 1 second to start the PTP synchronization process;

[0069] (3.2.3) The TSU module of the PTP hardware clock system of each slave sets the timestamp of the arrival of the Sync message t 2,i (k), and then timestamp t 2,i (k) Send to Linuxptp;

[0070] (3.2.4) The host continues to send Follow_up messages, carrying the timestamp t of the time when the Sync message was sent. 1,i (k);

[0071] (3.2.5) Each slave receives the Follow_up message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 1,i (k), sent to Linuxptp;

[0072] (3.2.6) Each slave's Linuxptp control sends a Delay_req message and timestamps the time the Delay_req message is sent in the TSU module of the PTP hardware clock system. 3,i (k), and then timestamp t 3,i (k) Send to Linuxptp;

[0073] (3.2.7) The master timestamps the moment it receives the Delay_req message from each slave.4,i (k), carried in the Delay_Resp message and sent to each slave.

[0074] (3.2.8) Each slave receives the Delay_Resp message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 4,i (k), sent to Linuxptp;

[0075] (3.3) Calculate the link delay d during the kth PTP synchronization between the master and slave devices. i (k);

[0076]

[0077] (3.4) Calculate the time deviation θ of the kth PTP synchronization between the master and slave devices. i (k);

[0078] θ i (k) = t 2,i (k)-t 1,i (k)-d i (k)

[0079] (3.5) Determine the time deviation θ i (k) Are they all less than the synchronization completion time deviation threshold θ sync In this embodiment, θ sync is 20ns; if θ i (k)<θ sync , each slave sends a synchronization completion message to the PC host through the network, enabling each slave to start synchronous sampling, and at the same time adopting the three-level synchronization mechanism to achieve high-precision time and frequency synchronization between each slave and the host; otherwise, only the three-level synchronization mechanism is adopted to achieve high-precision time and frequency synchronization between each slave and the host;

[0080] Below we describe the three-level synchronization mechanism in detail, such as Figure 4 As shown, the details are as follows:

[0081] (3.5.1), master-slave first-level synchronization;

[0082] Record the initial time deviation θ obtained by the kernel hardware driver when each slave establishes the first PTP synchronization with the master i (1), converted to binary time adjustment value η t,i , sent to the PTP hardware clock system through the AXI_GP interface; the RTC module of the PTP hardware clock system adjusts the time value η t,i Direct compensation completes a level of synchronization in generating timestamps;

[0083] In this embodiment, the RTC module of the PTP hardware clock system obtains a 32-bit nanosecond time adjustment value and adds it to the nanosecond register to complete nanosecond-level compensation, and adds a 48-bit second time adjustment value to the second register to complete second-level compensation, thereby eliminating the initial time deviation between the master and slave machines, reducing the time deviation to the millisecond level, and completing first-level synchronization.

[0084] (3.5.2) When the master and slave machines synchronize with each other for the kth time, k≥2, and the time deviations θ are determined. i Is (k) greater than the time deviation threshold θ? th In this embodiment, θ is set th is 100ns; if θ i (k)>θ th , then proceed to step (3.5.3) to start the master-slave secondary synchronization; otherwise, proceed to step (3.5.4) to start the master-slave tertiary synchronization;

[0085] (3.5.3), master-slave secondary synchronization;

[0086] Each slave uses the PI controller of the clock servo system according to the time deviation θ i (k) Calculate the adjustment value η i (k);

[0087]

[0088] Among them, K P and K I are the proportional and integral parameters of the PI controller, where the proportional parameter is 0.7 and the integral parameter is 0.3; η 0,i To adjust the initial value and satisfy:

[0089]

[0090] Among them, θ i (2) t 2,i (2) The time deviation and timestamp information of the second PTP synchronization of the master and slave devices respectively;

[0091] Calculate the time base value η generated by the PTP hardware clock timestamp when the master and slave machines synchronize for the kth time p,i (k),

[0092]

[0093] Among them, T base is the period of the host hardware clock;

[0094] Finally, the time base value η is set to p,i(k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the time base value η p,i (k) Accumulating timestamps to correct generated timestamps and complete secondary synchronization;

[0095] In this embodiment, the hardware clock source is the 125MHz clock of the RGMII interface, with an 8ns timebase. Therefore, the timebase is 40 bits wide, consisting of a 32-bit sub-nanosecond timebase and an 8-bit nanosecond timebase. By correcting the timebase generated by the timestamp, the effect of the master-slave clock source frequency deviation on time synchronization is eliminated, reducing the master-slave time synchronization deviation to the hundreds of nanoseconds level, thus achieving secondary synchronization.

[0096] (3.5.4), master-slave three-level synchronization;

[0097] The kernel hardware driver of each slave machine sets the time base value η p,i (k) is fixed to T base ,Right now:

[0098] η p,i (k) = T base

[0099] Then calculate the hardware clock frequency adjustment value η of each slave f,i (k);

[0100]

[0101] The time base value η is set via the AXI_GP interface p,i (k) and frequency adjustment value η f,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the new time base value η p,i (k) accumulates and generates a timestamp; and the frequency synchronization module adjusts the frequency value η f,i (k) Convert the frequency control word of DAC to control DAC to generate corresponding control voltage, voltage-control slave hardware clock source VCXO crystal oscillator, correct the slave hardware clock frequency, and complete three-level synchronization;

[0102] In this embodiment, the RTC module of the PTP hardware clock system generates a timestamp based on the 8ns time base value during three-level synchronization. The frequency synchronization module of the PTP hardware clock system obtains the frequency adjustment value η f,i (k), frequency adjustment value η f,i (k) is the frequency deviation of the slave relative to the master, in ppb. In this embodiment, a 25MHz voltage-controlled crystal oscillator with an absolute pull range of ±50ppm and a control voltage of 0-3.3V is used as the clock source, and a 16-bit DAC is used to generate the voltage-controlled voltage. The frequency resolution of the voltage-controlled VCXO can be calculated to be 1.5ppb, which is consistent with the frequency adjustment value η.f,i (k) with a 1ppb resolution, such as:

[0103]

[0104] The frequency synchronization module adjusts the value η according to the frequency f,i (k) Calculate the frequency control word code and send it to DAC to make the DAC output voltage V co Corresponding VCXO frequency correction value f fix , correct the VCXO output clock frequency so that the slave clock is synchronized with the master clock frequency, completing three-level synchronization. In this embodiment, the VCXO pulling range of ±50ppm corresponds to a 0-3.3V control voltage and also corresponds to a 16-bit DAC bit width. The frequency control word code is calculated as:

[0105]

[0106] V co =1.65+3.3×10 -5 ×f fix

[0107] f fix =-η f,i (k)

[0108] code=2 15 -η f,i (k)×2 16 ×10 -5

[0109] Therefore, the frequency control word code is used to control the DAC to generate the corresponding control voltage, which controls the slave hardware clock source VCXO crystal oscillator, corrects the slave hardware clock frequency, and completes the three-level synchronization.

[0110] In addition, in this embodiment, the process of synchronous sampling of the slave is analyzed, specifically:

[0111] 1) Synchronous reset of each slave;

[0112] After the PC receives the synchronization completion message from all distributed data acquisition systems, it sends a unified ADC reset program control command to each distributed data acquisition system. After receiving the ADC reset command, each distributed data acquisition system uses the rising edge of the next 1PPS synchronization signal as a trigger signal in the sampling synchronization module of the PTP hardware clock system, and simultaneously pulls the ADC reset pin low to complete the ADC reset, allowing multiple distributed data acquisition devices to synchronously start data sampling.

[0113] 2) Clock phase-locked frequency division generates ADC sampling clock;

[0114] The sampling synchronization module in the PTP hardware clock system starts with the rising edge of the 1PPS synchronization signal, triggers and counts on the rising edge of the hardware clock, compares the count value with the frequency division ratio, and outputs an ADC sampling clock of a specific frequency, so that the ADC sampling clock phase and frequency of each slave are synchronized;

[0115] In this embodiment, each slave uses a synchronized 125MHz hardware clock and employs a clock phase-locked frequency division technique to generate phase-synchronized ADC sampling clocks. The ADC sampling clocks have clock edges with identical phases, and the phase deviation of the ADC sampling clocks between slaves is affected by the phase error of the rising edge of the 1PPS synchronization signal and the phase of the 125MHz hardware clock. In this embodiment, the time synchronization deviation of each slave is within ±20ns, while the 125MHz hardware clock period is 8ns. This clock phase-locked frequency division technique can lock the phase deviation of the ADC sampling clocks between slaves within the range of [-28ns, 28ns], achieving sampling synchronization among the slaves.

[0116] 3) Timestamp the sampled data points;

[0117] The sampling synchronization module of the PTP hardware clock system latches the hardware timestamp of the received ADC sampling data point, and stores the timestamp and sampling data point together, so that the data sampled by each slave at the same time has the same timestamp information, thereby completing the alignment and synchronization of the sampling data points of each slave.

[0118] The sampling synchronization module of the PTP hardware clock system implements timestamping of sampled data points. In this embodiment, the sampling synchronization module receives ADC sampled data via the SPI serial bus and, triggered by the rising edge of the DRDY data valid signal, latches the hardware timestamp at that moment, which serves as the timestamp for that sampled data point. Each sampled data point has corresponding timestamp information. Distributed data acquisition systems synchronize sampling points by comparing identical or similar timestamp information, achieving sampling point synchronization across the distributed data acquisition systems.

[0119] (3.6) Let k = k + 1, and return to step (3.2) after the next synchronization cycle arrives to continue the next round of PTP synchronization.

[0120] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. A PTP time-frequency synchronization method for distributed data synchronous acquisition, characterized in that: The following steps are involved: (1) Build a PTP synchronization architecture for distributed data acquisition systems; Select a switch that supports PTP hardware synchronization as the PTP synchronization host, and the distributed data acquisition system as the PTP synchronization slave, and directly connect the slave to the switch host via a network cable; (2) Generation of hardware clock and hardware timestamp; Set each slave to use a voltage-controlled crystal oscillator (VCXO) as the hardware clock source; Set the initial value of the timestamp of each slave. The real-time clock module RTC in the slave PTP hardware clock system uses the initial value of the timestamp as the starting point and generates the PTP hardware timestamp T of each slave based on the accumulated time base value of the hardware clock. i , where i represents the slave number; (3) The master and slave machines perform periodic PTP synchronization; (3.1) Set the cycle number k and initialize k = 1; (3.2) Each slave establishes a PTP protocol stack to implement PTP synchronization message exchange, based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k); (3.3) Calculate the link delay d during the kth PTP synchronization between the master and slave devices. i (k); (3.4) Calculate the time deviation θ of the kth PTP synchronization between the master and slave devices. i (k); θ i (k)=t 2,i (k)-t 1,i (k)-d i (k) (3.5) Determine the time deviation θ i (k) Are they all less than the synchronization completion time deviation threshold θ sync , if θ i (k)<θ sync , each slave sends a synchronization completion message to the PC host through the network, enabling each slave to start synchronous sampling. At the same time, a three-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the host. Otherwise, only a two-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the host. (3.6) After the next synchronization cycle arrives, return to step (3.2) and continue with the next round of PTP synchronization.

2. A PTP time-frequency synchronization method for distributed data synchronous acquisition according to claim 1, characterized in that: The timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k) is obtained by: (2.1) When each slave system is initialized, the PTP protocol stack configures the PHC subsystem, enables the hardware timestamp function and selects the network data packets that need to be stamped, enabling the kernel to obtain timestamps when receiving and sending data packets; (2.2) The host periodically sends a Sync message to the slave based on the PTP protocol to start the PTP synchronization process; (2.3) The TSU module of the PTP hardware clock system of each slave machine timestamps the arrival of the Sync message t 2,i (k), and then timestamp t 2,i (k) Send to Linuxptp; (2.4) The host continues to send Follow_up messages, carrying the timestamp t of the time when the Sync message was sent. 1,i (k); (2.5) Each slave receives the Follow_up message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 1,i (k), sent to Linuxptp; (2.6) The Linuxptp control of each slave sends a Delay_req message and timestamps the time when the Delay_req message is sent in the TSU module of the PTP hardware clock system. 3,i (k), and then timestamp t 3,i (k) Send to Linuxptp; (2.7) The master timestamps the moment it receives the Delay_req message from each slave. 4,i (k), carried in the Delay_Resp message and sent to each slave; (2.8) Each slave receives the Delay_Resp message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 4,i (k), sent to Linuxptp.

3. A PTP time-frequency synchronization method for distributed data synchronous acquisition according to claim 1, characterized in that: The method for achieving high-precision time and frequency synchronization between each slave and the master using the three-level synchronization mechanism in step (3.5) is: (3.5.1), master-slave first-level synchronization; Record the initial time deviation θ obtained by the kernel hardware driver when each slave establishes the first PTP synchronization with the master i (1), converted to binary time adjustment value η t,i , sent to the PTP hardware clock system through the AXI_GP interface; The RTC module of the PTP hardware clock system adjusts the time by the value η t,i Direct compensation completes a level of synchronization in generating timestamps; (3.5.2) When the master and slave devices synchronize for the kth time, k ≥ 2, determine the time deviation θ i Is (k) greater than the time deviation threshold θ? th , if θ i (k)>θ th , then proceed to step (3.5.3) to start the master-slave secondary synchronization; otherwise, proceed to step (3.5.4) to start the master-slave tertiary synchronization; (3.5.3), master-slave secondary synchronization; Each slave uses the PI controller of the clock servo system according to the time deviation θ i (k) Calculate the adjustment value η i (k); Among them, K P and K I are the proportional and integral parameters of the PI controller, η 0,i To adjust the initial value and satisfy: Among them, θ i (2) t 2,i (2) The time deviation and timestamp information of the second PTP synchronization of the master and slave devices respectively; Calculate the time base value η generated by the PTP hardware clock timestamp when the master and slave machines synchronize for the kth time p,i (k), Among them, T base is the period of the host hardware clock; Finally, the time base value η is set to p,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the time base value η p,i (k) Accumulating timestamps to correct generated timestamps and complete secondary synchronization; (3.5.4), master-slave three-level synchronization; The kernel hardware driver of each slave machine sets the time base value η p,i (k) is fixed to T base ,Right now: or p,i (k)=T base Then calculate the hardware clock frequency adjustment value η of each slave f,i (k); The time base value η is set via the AXI_GP interface p,i (k) and frequency adjustment value η f,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the new time base value η p,i (k) accumulates and generates a timestamp; and the frequency synchronization module adjusts the frequency value η f,i (k) is converted into the frequency control word of the DAC, which controls the DAC to generate the corresponding control voltage, which controls the slave hardware clock source VCXO crystal oscillator, corrects the slave hardware clock frequency, and completes the three-level synchronization.

4. A PTP time-frequency synchronization method for distributed data synchronous acquisition according to claim 1, characterized in that: The process of synchronous sampling of each slave is as follows: (4.1) Synchronous reset of each slave; The sampling synchronization module of the PTP hardware clock system uses the rising edge of the 1PPS synchronization signal as a trigger signal to synchronously reset the ADC of each slave, so that each ADC starts data sampling synchronously; (4.2) Phase-locked clock division generates ADC sampling clock; The sampling synchronization module in the PTP hardware clock system starts with the rising edge of the 1PPS synchronization signal, triggers and counts on the rising edge of the hardware clock, compares the count value with the frequency division ratio, and outputs an ADC sampling clock of a specific frequency, so that the ADC sampling clock phase and frequency of each slave are synchronized; (4.3), time stamping of sampled data points; The sampling synchronization module of the PTP hardware clock system latches the hardware timestamp of the received ADC sampling data point, and stores the timestamp and sampling data point together, so that the data sampled by each slave at the same time has the same timestamp information, thereby completing the alignment and synchronization of the sampling data points of each slave.

Images