Board-level fan-out packaging structure and method for preparing ultrathin CIS chip

Abstract

The invention discloses a board-level fan-out packaging structure and method for preparing an ultrathin CIS chip. According to the packaging structure and method, the ultra-thin CIS chip packaging structure is prepared based on the glass support plate through the plate-level fan-out packaging process, the packaging efficiency can be greatly improved, and the processing cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a board-level fan-out packaging structure and method for preparing an ultra-thin CIS chip. Background Art

[0002] Image sensor chip (CMOS Inage Sensor, CIS) is an image sensor based on semiconductor CMOS technology, which began to be widely used in the late 1990s. At present, CIS chips have been widely used in many fields such as mobile phones, cameras, automotive electronics, and security. As mobile consumer electronic products such as mobile phones, computers, and digital cameras have higher and higher requirements for the packaging of high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system integrated electronic products, high-density, multi-type chip system-level packaging products have gradually become the mainstream in the new generation of electronic products. At present, CIS chips are mainly prepared by wafer-level CIS-TSV packaging technology, but CIS-TSV packaging technology has limited requirements for the I / O density on CIS chips. With the increase in the I / O density of CIS chips, the difficulty of packaging CIS chips with high I / O density using CIS-TSV technology will increase significantly, and the packaging cost will also increase significantly.

[0003] Fan Out Panel Level Package (FOPLP) technology is a new type of packaging technology that can package chips on a packaging substrate and perform more I / O wiring outside the boundaries of the chip, thereby increasing the I / O density, reducing the package size, and improving electrical performance. Compared with the traditional Fan Out Wafer Level Package (FOWLP) technology, the difference is that it uses a larger panel instead of a wafer, and there are differences in the materials, equipment, and line width and line spacing of the products used. The emergence of FOPLP technology can effectively achieve a larger overall package, further increase packaging efficiency, reduce packaging costs, and have a broader development prospect. At present, the size of FOPLP samples has gradually developed from the initial 300*300mm to 500*500mm, 600*600mm, and even larger package sizes. Compared with FOWLP technology, FOPLP technology has the advantages of lower cost, flexible design, good electrothermal performance, diverse business models, and a wide range of application fields.

[0004] Glass substrates have smoother surfaces than plastic substrates, and the number of holes opened on glass substrates is much greater than that on organic substrates for the same area. The spacing between through holes on glass substrates can be less than 100 microns, which can directly increase the interconnection density between chips by 10 times. The increase in interconnection density can accommodate more transistors, thereby achieving more complex designs and more efficient use of space. At the same time, glass substrates exhibit better properties than plastic substrates in terms of thermal properties and physical stability. Their higher heat resistance ensures that glass substrates are not prone to warping or deformation at high temperatures. In addition, the unique electrical properties of the glass core (glass substrate through hole) make its dielectric loss lower, allowing clearer signal and power transmission, and the power loss during signal transmission will be significantly reduced, and the overall efficiency of the chip can also be significantly improved.

[0005] Based on the fact that CIS-TSV packaging technology is limited by the I / O density of CIS chips, FOPLP technology can effectively meet the high I / O density chip packaging and its high efficiency, low cost and other characteristics. The glass substrate has excellent properties in thermal properties, physical stability, and low dielectric loss, low power loss, high-definition signal and power transmission during signal transmission. Combining CIS chip packaging technology with FOPLP technology, glass substrate technology, etc., and developing a new CIS chip packaging technology will be one of the popular technologies to meet the high I / O density CIS chip packaging. Summary of the invention

[0006] In order to solve the above technical problems, the purpose of the present invention is to provide a board-level fan-out packaging structure and method for preparing an ultra-thin CIS chip. The packaging structure and method are based on a glass carrier through a board-level fan-out packaging process to prepare an ultra-thin CIS chip packaging structure, which can greatly improve the packaging efficiency and significantly reduce the processing cost.

[0007] According to one aspect of the present invention, there is provided a method for preparing a board-level fan-out packaging structure of an ultra-thin CIS chip, which mainly comprises the following steps:

[0008] S1, forming a first groove structure on a board-level glass carrier;

[0009] S2, forming a second groove structure on the board-level glass carrier;

[0010] S3, forming an adhesive film layer at the groove of the board-level glass carrier;

[0011] S4, pasting the CIS chip into the groove structure of the glass carrier;

[0012] S5, forming a first insulating layer with a conductive through-hole structure;

[0013] S6, forming a conductive through-hole structure on the back side of the CIS chip;

[0014] S7, forming a first metal redistribution layer;

[0015] S8, forming a second insulating layer with a conductive through-hole structure;

[0016] S9, forming a second metal redistribution layer;

[0017] S10, completing the ball planting process;

[0018] The material of the insulating layer in steps S5 and S8 is epoxy resin, silicon oxide insulating material or other insulating materials; in this embodiment, the insulating layer material is photosensitive epoxy resin; the material of the metal redistribution layer in steps S7 and S9 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin; in this embodiment, the insulating layer metal redistribution layer material is copper.

[0019] The present invention provides a method for preparing a board-level fan-out packaging structure of an ultra-thin CIS chip. The method is to form a "step-shaped" groove structure on a board-level glass carrier, paste the CIS chip in the groove structure, and complete subsequent multi-layer metal redistribution layer and multi-layer insulation layer packaging processes to prepare a fan-out ultra-thin CIS chip packaging structure.

[0020] According to another aspect of the present invention, a board-level fan-out packaging structure of an ultra-thin CIS chip prepared according to the above method includes a CIS chip and a glass carrier, a first groove structure is arranged on the board-level glass carrier; a second groove structure is arranged on the board-level glass carrier; an adhesive film layer is arranged at the groove of the board-level glass carrier; the CIS chip is adhered to the groove structure of the glass carrier through the adhesive film layer; a first insulating layer with a conductive through-hole structure is arranged on the back of the CIS chip; a conductive through-hole structure is arranged on the back of the CIS chip, a first metal redistribution layer is arranged on the conductive through-hole structure, and a second insulating layer with a conductive through-hole structure is arranged on the first metal redistribution layer; a second metal redistribution layer is arranged on the second insulating layer; and balls are planted on the second metal redistribution layer.

[0021] Further, a groove structure (203) is formed on the plate-level glass carrier (10) through a glass through hole, and in a TGV process, the groove structures with different depths and areas are formed by controlling the laser induction time, the induction area and the chemical solution etching time;

[0022] The TGV technology is used for the second time on the groove structure to form a stepped groove structure (203). During the second TGV process, the second groove structure is formed by controlling the laser induction time, the induction area and the chemical solution etching time. The two groove structures together form a stepped groove structure.

[0023] Furthermore, an adhesive layer (11) is formed at the "step" of the stepped groove structure; a thinned and cut single CIS chip is pasted downward into the groove structure (203); a first insulating layer (15) is formed on the back of the CIS chip using vacuum lamination technology, and a conductive through-hole structure (206) is formed on PA1, wherein the position of the through-hole structure (206) corresponds to the position of the first insulating layer (15) of the CIS chip.

[0024] Furthermore, a conductive via structure is formed on the CIS chip along the conductive via structure (206) on the first insulating layer (15), and a first metal redistribution layer (16) is formed on the conductive via structure.

[0025] Furthermore, a second insulating layer (17) is formed on the first metal redistribution layer (16), and a conductive via structure (208) is formed on PA2.

[0026] Furthermore, a second metal redistribution layer (18) is formed on the conductive via structure (208); and solder balls are implanted on the second metal redistribution layer (18).

[0027] The beneficial effects of the present invention are mainly the following three points: (1) By using a large-sized glass carrier as a carrier, the board-level packaging technology can be used to carry out related process operations, which can greatly improve production efficiency and reduce packaging costs. (2) The thinned CIS chip is embedded in the glass carrier structure, which can significantly reduce the thickness of CIS packaged electronic products. (3) The CIS chip uses fan-out packaging technology to form a related metal redistribution layer, which can meet the packaging requirements of the increased I / O density on the CIS chip, while reducing the difficulty of the entire packaging process (no need to prepare extremely small line width RDL on a larger packaging area). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of forming a groove structure on a board-level glass carrier using glass through-hole technology.

[0029] Figure 2 For Figure 1 The structure shown is a second use of the TGV technology to form a stepped groove structure; b is a top view of the glass carrier after forming several stepped groove structures.

[0030] Figure 3 For Figure 2 The "steps" of the stepped groove structure shown form an adhesive layer.

[0031] Figure 4 To paste the thinned and cut single CIS chip face down on Figure 3 Schematic diagram of the groove structure shown.

[0032] Figure 5A schematic diagram of forming a first insulating layer (PA1) on the back of a CIS chip using vacuum lamination technology and forming a conductive through-hole structure on PA1.

[0033] Figure 6 For Figure 5 The structure shown is a schematic diagram of forming a conductive through-hole structure on the CIS chip along the conductive through-hole structure on PA1.

[0034] Figure 7 For Figure 6 A first metal redistribution layer (RDL1) is formed on the structure shown.

[0035] Figure 8 For Figure 7 Schematic diagram of a second insulating layer (PA2) being formed on the structure shown and a conductive through-hole structure being formed on PA2.

[0036] Fig. 9 For Figure 8 A second metal redistribution layer (RDL2) is formed on the structure.

[0037] Fig.10 For Fig. 9 Schematic diagram of the ball implantation process completed on the structure shown.

[0038] Fig.11 Schematic diagram of the ultra-thin CIS chip packaging structure based on a glass substrate prepared using panel-level fan-out packaging technology. DETAILED DESCRIPTION

[0039] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0040] (1) A groove structure is formed on a board-level glass carrier through glass via (TGV) technology to obtain Figure 1 The structure shown in FIG. 10 is a glass carrier, 201 is the lower surface of the glass carrier, 202 is the upper surface of the transparent glass carrier, and 203 is a groove structure formed on the glass carrier. In the TGV process, groove structures with different depths and areas are formed by controlling the laser induction time, the induction area, and the chemical solution etching time.

[0041] (2) Figure 1 The structure shown in the figure is then re-used using the TGV technology to form a stepped groove structure, as shown in the figure. Figure 2 a. 203 is a stepped groove structure. In the secondary TGV process, the second groove structure is formed by controlling the laser induction time, the induction area and the chemical solution etching time. The two groove structures together form a stepped groove structure. After forming a plurality of stepped groove structures on the entire glass carrier, the top view of the glass carrier is as shown in FIG. Figure 2 As shown in b.

[0042] (3) Figure 2 The step of the stepped groove structure shown in the figure forms an adhesive layer, and the Figure 3 The structure shown in FIG. 11 is a bonding adhesive layer.

[0043] (4) Paste the thinned and cut single CIS chip face down on Figure 3 In the groove structure shown in FIG. Figure 4 The structure shown in FIG. 12 is a CIS chip, 13 is a CIS chip conductive structure (Al Pad), 14 is a CIS chip photosensitive area, and 204 is a CIS chip backside.

[0044] (5) A first insulating layer (PA1) is formed on the back of the CIS chip by vacuum lamination technology, and a conductive through-hole structure is formed on PA1 to obtain Figure 5 The structure shown in FIG. 15 is PA1, 205 is the upper surface of PA1, and 206 is a conductive through-hole structure formed on PA1. The position of the through-hole structure 206 corresponds to the position of the Al Pad of the CIS chip.

[0045] (6) Figure 5 A conductive through hole structure is formed on the CIS chip along the conductive through hole structure on PA1, and the structure shown in FIG. Figure 6 The structure shown.

[0046] (7) Figure 6 A first metal redistribution layer (RDL1) is formed on the structure shown in FIG. Figure 7 The structure shown in Figure 16 is RDL1.

[0047] (8) Figure 7 A second insulating layer (PA2) is formed on the structure shown in FIG. 1 , and a conductive through-hole structure is formed on PA2 to obtain a structure as shown in FIG. Figure 8 The structure shown in FIG. 17 is PA2, 207 is the upper surface of PA2, and 208 is the conductive through-hole structure formed on PA2.

[0048] (9) Figure 8 A second metal redistribution layer (RDL2) is formed on the structure shown in FIG. Fig. 9 The structure shown in FIG. 18 is RDL2.

[0049] (10) Fig. 9 The ball implantation process is completed on the structure shown in the figure, and the Fig.10 The structure shown in FIG. 19 is a solder ball.

[0050] like Fig.11As shown in the structure, this embodiment uses the board-level fan-out packaging technology to prepare an ultra-thin CIS chip packaging structure based on a glass substrate. The specific layers in the structure are as follows: 10-glass carrier, 11-adhesive layer, 12-CIS chip, 13-CIS chip conductive structure (Al Pad), 14-CIS chip photosensitive area, 15-first insulating layer, 16-first metal redistribution layer, 17-second insulating layer, 18-second metal redistribution layer, 19-conductive structure (solder ball).

[0051] It is worth noting that: in the description of the present invention, the meaning of "multiple" is two or more than two, unless otherwise clearly and specifically defined. In the present invention, unless otherwise clearly stipulated and defined, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; the circuits described in the present invention are all commonly used circuits in the art, and other related components are all existing commonly used components. For ordinary technicians in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0052] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and scope of the elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

Claims

1. A method for preparing a board-level fan-out package of an ultra-thin CIS chip, characterized in that: The steps include: S1, forming a first groove structure on a board-level glass carrier; S2, forming a second groove structure on the board-level glass carrier; S3, forming an adhesive film layer at the groove of the board-level glass carrier; S4, pasting the CIS chip into the groove structure of the glass carrier; S5, forming a first insulating layer with a conductive through-hole structure; S6, forming a conductive through-hole structure on the back side of the CIS chip; S7, forming a first metal redistribution layer; S8, forming a second insulating layer with a conductive through-hole structure; S9, forming a second metal redistribution layer; S10, completing the ball planting process.

2. The method according to claim 1, characterized in that: The material of the insulating layer in steps S5 and S8 is epoxy resin or silicon oxide insulating material.

3. The method according to claim 1, characterized in that: The material of the metal redistribution layer in steps S7 and S9 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin.

4. The method according to claim 1, characterized in that: A fan-out ultra-thin CIS chip packaging structure is prepared by forming a "step-shaped" groove structure on a board-level glass carrier, pasting and placing a CIS chip in the groove structure, and completing subsequent multi-layer metal redistribution layer and multi-layer insulation layer packaging processes.

5. The board-level fan-out packaging structure of the ultra-thin CIS chip prepared by the method according to claim 1, characterized in that: The invention comprises a CIS chip (12) and a level glass carrier (10), wherein a first groove structure (203) is arranged on the board-level glass carrier (10); a second groove structure is arranged on the board-level glass carrier; an adhesive film layer is arranged at the groove of the board-level glass carrier; the CIS chip is adhered in the groove structure of the glass carrier via the adhesive film layer; a first insulating layer with a conductive through-hole structure is arranged on the back of the CIS chip; a conductive through-hole structure is arranged on the back of the CIS chip, a first metal redistribution layer is arranged on the conductive through-hole structure, and a second insulating layer with a conductive through-hole structure is arranged on the first metal redistribution layer; a second metal redistribution layer is arranged on the second insulating layer; and balls are planted on the second metal redistribution layer.

6. The board-level fan-out packaging structure of the ultra-thin CIS chip according to claim 5, characterized in that: A groove structure (203) is formed on a plate-level glass carrier (10) through a glass through hole, and in a TGV process, the groove structures with different depths and areas are formed by controlling the laser induction time, the induction area and the chemical solution etching time; The TGV technology is used for the second time on the groove structure to form a stepped groove structure (203). During the second TGV process, the second groove structure is formed by controlling the laser induction time, the induction area and the chemical solution etching time. The two groove structures together form a stepped groove structure.

7. The board-level fan-out packaging structure of the ultra-thin CIS chip according to claim 6, characterized in that: An adhesive layer (11) is formed at the "step" of the stepped groove structure; a thinned and cut single CIS chip is adhered downwardly in the groove structure (203); a first insulating layer (15) is formed on the back of the CIS chip using a vacuum lamination technique, and a conductive through-hole structure (206) is formed on PA1, wherein the position of the through-hole structure (206) corresponds to the position of the first insulating layer (15) of the CIS chip.

8. The board-level fan-out packaging structure of the ultra-thin CIS chip according to claim 7, characterized in that: A conductive through-hole structure is formed on the CIS chip along the conductive through-hole structure (206) on the first insulating layer (15), and a first metal redistribution layer (16) is formed on the conductive through-hole structure.

9. The board-level fan-out packaging structure of the ultra-thin CIS chip according to claim 8, characterized in that: A second insulating layer (17) is formed on the first metal redistribution layer (16), and a conductive via structure (208) is formed on PA2.

10. The board-level fan-out packaging structure of the ultra-thin CIS chip according to claim 9, characterized in that: A second metal redistribution layer (18) is formed on the conductive through-hole structure (208); and solder balls are implanted on the second metal redistribution layer (18).

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