Light-emitting diode and light-emitting diode preparation method
By designing step structures and isolation trenches in light-emitting diodes, and using SiO2 coating layers and distributed Bragg mirror reflection layers, the problem of improving the brightness of light-emitting diodes in the existing technology is solved, achieving significant brightness improvement and reflectivity enhancement. .
Patent Information
- Application Number
- CN202411247756.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2025-01-24
AI Technical Summary
Existing light emitting diodes have challenges in improving brightness, especially how to effectively improve the overall reflectivity of the chip.
By introducing a step structure and isolation trench into the light-emitting diode, and covering it with a SiO2 coating layer and a distributed Bragg mirror reflection layer, a planar structure reflection layer is formed to improve the overall reflectivity of the chip.
The brightness of the light -emitting diodes is significantly improved, and the overall reflection rate of the chip is increased through the reflex layer of the plane structure, thereby enhancing the reflection and output efficiency of light.
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Figure CN119364955A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for preparing the light-emitting diode. Background Art
[0002] Light Emitting Diode (LED) is a semiconductor device that can emit light. It has the advantages of energy saving, high brightness, high durability, long life and light weight. It has been widely used in two major fields: backlight display and direct display.
[0003] The related technology provides a light emitting diode, the structure of which includes an epitaxial structure, an electrode structure, a reflective layer, and the like.
[0004] Among the above-mentioned light-emitting diodes, how to improve the brightness of the light-emitting diodes is a major focus of current research. Summary of the invention
[0005] The embodiments of the present disclosure provide a light emitting diode and a method for manufacturing a light emitting diode, which can significantly improve the overall reflectivity of the chip, thereby improving the brightness of the light emitting diode. The technical solution is as follows:
[0006] In one aspect, a light emitting diode is provided, the light emitting diode comprising: an epitaxial structure, an electrode structure, a coating layer and a reflective layer;
[0007] The epitaxial structure is a step structure; the epitaxial structure is also provided with an isolation groove; the current blocking layer is located on the epitaxial structure; the electrode structure is connected to the epitaxial structure; the coating layer covers the isolation groove, the step structure and the electrode structure, and the surface of the coating layer is a plane; the reflective layer is located on the surface of the coating layer.
[0008] Optionally, the coating layer is a SiO2 coating layer.
[0009] Optionally, the coating layer is formed by spin coating a dielectric material and then baking it.
[0010] Optionally, the light emitting diode further comprises a substrate, a current blocking layer and a transparent conductive layer; the epitaxial structure is located on the substrate, the current blocking layer is located on the epitaxial structure; the transparent conductive layer covers the current blocking layer;
[0011] The electrode structure comprises a first electrode and a second electrode, the first electrode is located on the transparent conductive layer, and the second electrode is located on a step surface of the step structure;
[0012] The upper surface of the coating layer covers the top of the first electrode, and the surface of the coating layer is parallel to the surface of the substrate.
[0013] Optionally, the distance between the surface of the coating layer and the surface of the electrode structure is 0-1 μm.
[0014] In another aspect, a method for preparing a light emitting diode comprises:
[0015] fabricating epitaxial structures;
[0016] Performing a patterning process on the epitaxial structure to form a step structure and an isolation groove;
[0017] manufacturing an electrode structure, wherein the electrode structure is connected to the epitaxial structure;
[0018] Manufacturing a coating layer, wherein the coating layer covers the isolation groove, the step structure and the electrode structure, and the surface of the coating layer is a plane;
[0019] A reflective layer is formed on the coating layer.
[0020] Optionally, the manufacturing of the coating layer comprises:
[0021] Using a spin-coated dielectric material to coat the surfaces of the isolation groove, the step structure, and the electrode structure;
[0022] The coated film layer is baked at high temperature to form a SiO2 dielectric layer.
[0023] Optionally, the high-temperature baking of the coated film layer comprises:
[0024] The coated film layer is baked at a baking temperature of 200 to 400° C. for a baking time of 0.5 to 3 hours.
[0025] Optionally, the manufacturing of the epitaxial structure includes:
[0026] Fabricating the epitaxial structure on a substrate;
[0027] Before manufacturing the electrode structure, the method further comprises:
[0028] forming a current blocking layer on the epitaxial structure;
[0029] forming a transparent conductive layer on the current blocking layer;
[0030] The electrode structure comprises a first electrode and a second electrode, the first electrode is located on the transparent conductive layer, and the second electrode is located on a step surface of the step structure;
[0031] The upper surface of the coating layer covers the top of the first electrode, and the surface of the coating layer is parallel to the surface of the substrate.
[0032] Optionally, the distance between the surface of the coating layer and the surface of the electrode structure is 0-1 μm.
[0033] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0034] In the disclosed embodiment, the coating layer covers the isolation groove, the step structure and the electrode structure, and the surface of the coating layer is planar. The reflective layer formed on the coating layer is also a planar structure. The reflective layer with a planar structure can significantly improve the overall reflectivity of the chip, thereby improving the brightness of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0036] Figure 1 It is a structural schematic diagram of a light emitting diode provided by the related technology;
[0037] Figure 2 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;
[0038] Figure 3 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;
[0039] Figure 4 is a flow chart of another method for preparing a light emitting diode provided by an embodiment of the present disclosure;
[0040] Figure 5 It is a schematic diagram of the reflectivity of the reflective layer in the light-emitting diode provided by the related art;
[0041] Figure 6 It is a schematic diagram of the reflectivity of the reflective layer in the light-emitting diode provided in the embodiment of the present disclosure.
[0042] The reference numerals are as follows:
[0043] 10: epitaxial structure; 20: electrode structure;
[0044] 101: substrate; 102: first semiconductor layer; 103: active layer; 104: second semiconductor layer; 105: current blocking layer; 106: transparent conductive layer; 107: first electrode; 108: second electrode; 109: coating layer; 110: reflective layer; 111: isolation groove; 112: step structure; 201: position 1; 202: position 2; 203: position 3. DETAILED DESCRIPTION
[0045] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0046] Figure 1 It is a schematic diagram of the structure of a light emitting diode provided by the related technology. Figure 1 The light emitting diode includes: a substrate 101 , an epitaxial structure 10 , a current blocking layer 105 , a transparent conductive layer 106 , an electrode structure 20 and a reflective layer 110 .
[0047] The epitaxial structure 10 is located on the substrate 101, and the epitaxial structure 10 has a step structure 112. The epitaxial structure 10 is also provided with an isolation groove (ISO) 111; the current blocking layer 105 is located on the epitaxial structure 10; the transparent conductive layer 106 covers the current blocking layer 105; the electrode structure 20 is connected to the epitaxial structure 10; the reflective layer 110 covers the isolation groove 111, the epitaxial structure 10, the transparent conductive layer 106 and the electrode structure 20.
[0048] Exemplarily, the epitaxial structure 10 includes a first semiconductor layer 102 , an active layer 103 and a second semiconductor layer 104 . The first semiconductor layer 102 , the active layer 103 and the second semiconductor layer 104 are sequentially stacked on the substrate 101 , and the step surface of the step structure 112 is located in the first semiconductor layer 102 .
[0049] Exemplarily, the electrode structure 20 includes a first electrode 107 and a second electrode 108 . The first electrode 107 is located on the transparent conductive layer 106 , and the second electrode 108 is located on a step surface of the step structure 112 .
[0050] In the related art, the reflective layer 110 covers the isolation groove 111, the epitaxial structure 10, the transparent conductive layer 106 and the electrode structure 20. The surface of the reflective layer 110 is uneven, and the reflectivity will be greatly reduced.
[0051] Figure 2 is a schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 2 The light emitting diode includes: an epitaxial structure 10 , an electrode structure 20 , a coating layer 109 and a reflective layer 110 .
[0052] The epitaxial structure 10 is a step structure 112; the epitaxial structure 10 is also provided with an isolation groove (ISO) 111; the electrode structure 20 is connected to the epitaxial structure 10; the coating layer 109 covers the isolation groove 111, the step structure 112 and the electrode structure 20, and the surface of the coating layer 109 is a plane; the reflective layer 110 is located on the surface of the coating layer 109.
[0053] like Figure 2As shown, since the reflective layer 110 is disposed on the coating layer 109 with a flat surface, the reflective layer 110 itself is a flat film layer.
[0054] In the embodiment of the present disclosure, the coating layer 109 covers the isolation groove 111, the epitaxial structure 10, the transparent conductive layer 106 and the electrode structure 20, and the surface of the coating layer 109 is planar. The reflective layer 110 formed on the coating layer 109 is also a planar structure. The reflective layer with a planar structure can significantly improve the overall reflectivity of the chip, thereby improving the brightness of the light-emitting diode.
[0055] In the disclosed embodiment, the light emitting diode further includes a substrate 101 , a current blocking layer 105 and a transparent conductive layer 106 ; the epitaxial structure 10 is located on the substrate 101 , the current blocking layer 105 is located on the epitaxial structure 10 ; and the transparent conductive layer 106 covers the current blocking layer 105 .
[0056] In the embodiment of the present disclosure, the substrate 101 may be a sapphire substrate.
[0057] In the embodiment of the present disclosure, the epitaxial structure 10 includes a first semiconductor layer 102 , an active layer 103 and a second semiconductor layer 104 .
[0058] The first semiconductor layer 102, the active layer 103, and the second semiconductor layer 104 are sequentially stacked on the substrate 101. The first semiconductor layer 102, the active layer 103, and the second semiconductor layer 104 are provided with a step structure 112 extending to the first semiconductor 102, that is, the step surface is located in the first semiconductor layer 102. The first semiconductor layer 102, the active layer 103, and the second semiconductor layer 104 are also provided with an isolation groove 111 extending to the surface of the substrate 101. The current blocking layer 105 is located on the surface of the second semiconductor layer 104.
[0059] In the embodiment of the present disclosure, the first semiconductor layer 102 may be an N-type semiconductor layer, and the second semiconductor layer 104 may be a P-type semiconductor layer.
[0060] In the embodiment of the present disclosure, the active layer 103 may be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.
[0061] For example, the first semiconductor layer 102 may be an N-type GaN layer, and the second semiconductor layer 104 may be a P-type GaN layer.
[0062] In other embodiments, the first semiconductor layer 102 may be a P-type semiconductor layer, and the second semiconductor layer 104 may be an N-type semiconductor layer.
[0063] In the embodiment of the present disclosure, the current blocking layer 105 may be an AlGaN or SiO 2 layer.
[0064] Exemplarily, the current blocking layer 105 is an AlGaN current blocking layer.
[0065] In the embodiment of the present disclosure, the transparent conductive layer 106 may be an indium tin oxide (ITO) layer. ITO has good transparency and conductivity and can conduct current to form an electrical connection while allowing light to pass through.
[0066] In the embodiment of the present disclosure, the reflective layer 110 may be a distributed Bragg reflector (DBR) layer.
[0067] Exemplarily, the DBR layer may include a plurality of periodically alternately stacked Ti3O5 layers and SiO2 layers.
[0068] In the embodiment of the present disclosure, the electrode structure 20 includes a first electrode 107 and a second electrode 108 . The first electrode 107 is located on the transparent conductive layer 106 , and the second electrode 108 is located on a step surface of the step structure 112 .
[0069] In other examples, the electrode structure 20 may include electrode pads in addition to electrodes.
[0070] In the embodiment of the present disclosure, the first electrode 107 and the second electrode 108 may be AuGe / Au electrodes or AuBe / Au electrodes.
[0071] Exemplarily, the first electrode is an AuBe / Au electrode, and the second electrode is an AuGe / Au electrode.
[0072] In the embodiment of the present disclosure, the coating layer 109 may be a SiO 2 coating layer.
[0073] In this implementation, the SiO2 coating layer has high density, no pinholes, excellent three-dimensional conformality, good coverage, and can significantly improve the flatness of the chip surface.
[0074] The SiO2 coating layer is formed by spin-coating a dielectric material (Spin-On Dielectrics, SOD) and baking it.
[0075] In this implementation, the spin coating process can ensure that the coating layer covers the isolation groove, the epitaxial structure, the transparent conductive layer and the electrode structure at the same time, thereby forming a coating layer with a smooth surface, preparing for the subsequent formation of a smooth reflective layer.
[0076] In the disclosed embodiment, the upper surface of the coating layer 109 can cover the top of the first electrode 107, and the surface of the coating layer 109 is parallel to the surface of the substrate 101, so as to completely cover the isolation groove, epitaxial structure, transparent conductive layer and electrode structure.
[0077] In this implementation, by designing the surface of the coating layer to be parallel to the substrate, the light emitted by the active layer can be better reflected by the reflective layer located on the coating layer, thereby improving the light extraction efficiency.
[0078] Exemplarily, the distance between the surface of the coating layer 109 and the surface of the electrode structure 20 (the surface of the first electrode 107 ) is 0 to 1 μm.
[0079] In this implementation, the coating layer with the above thickness can cover the isolation groove, the epitaxial structure, the transparent conductive layer and the electrode structure at the same time to form a flat surface.
[0080] It is worth noting that the electrode can pass through the reflective layer 110 and the coating layer 109, and the structure of the passing part is not shown in the figure.
[0081] It is worth noting that in the embodiments of the present disclosure, structures may be selectively increased or decreased based on the structure of the above-mentioned light emitting diode, and the present disclosure does not impose any limitation on this.
[0082] Figure 3 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 3 The method steps include:
[0083] S11. Fabricating an epitaxial structure.
[0084] In the embodiment of the present disclosure, the substrate may be a sapphire substrate.
[0085] S12, performing graphic processing on the epitaxial structure to form a step structure and an isolation groove.
[0086] In the embodiment of the present disclosure, the epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer.
[0087] The first semiconductor layer, the active layer and the second semiconductor layer are stacked on the substrate in sequence. The first semiconductor layer, the active layer and the second semiconductor layer are provided with a step structure extending to the first semiconductor, that is, the step surface is located in the first semiconductor layer. The first semiconductor layer, the active layer and the second semiconductor layer are also provided with an isolation groove extending to the surface of the substrate.
[0088] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type semiconductor layer, and the second semiconductor layer may be a P-type semiconductor layer.
[0089] In the embodiment of the present disclosure, the active layer may be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.
[0090] For example, the first semiconductor layer may be an N-type GaN layer, and the second semiconductor layer may be a P-type GaN layer.
[0091] In other embodiments, the first semiconductor layer may be a P-type semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer.
[0092] S13, manufacturing an electrode structure, and connecting the electrode structure to the epitaxial structure.
[0093] In the embodiment of the present disclosure, the electrode structure includes a first electrode and a second electrode, the first electrode is located on the transparent conductive layer, and the second electrode is located on the step surface of the step structure.
[0094] In other examples, the electrode structure may include an electrode pad in addition to the electrode.
[0095] In the embodiment of the present disclosure, the first electrode and the second electrode may be AuGe / Au electrodes or AuBe / Au electrodes.
[0096] Exemplarily, the first electrode is an AuBe / Au electrode, and the second electrode is an AuGe / Au electrode.
[0097] S14, manufacturing a coating layer, wherein the coating layer covers the isolation groove, the step structure and the electrode structure, and the surface of the coating layer is flat.
[0098] In the embodiment of the present disclosure, the coating layer may be a SiO2 coating layer.
[0099] S15. Making a reflective layer on the coating layer.
[0100] In the embodiment of the present disclosure, the reflective layer may be a DBR layer.
[0101] Exemplarily, the DBR layer may include a plurality of periodically alternately stacked Ti3O5 layers and SiO2 layers.
[0102] In the disclosed embodiment, the coating layer covers the isolation groove, the step structure and the electrode structure, and the surface of the coating layer is planar. The reflective layer formed on the coating layer is also a planar structure. The reflective layer with a planar structure can significantly improve the overall reflectivity of the chip, thereby improving the brightness of the light-emitting diode.
[0103] Figure 4 is a flow chart of another method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 4 The method steps include:
[0104] S21. Forming a first semiconductor layer, an active layer, and a second semiconductor layer in sequence on a substrate, wherein the first semiconductor layer, the active layer, and the second semiconductor layer constitute an epitaxial structure.
[0105] The substrate may be a sapphire substrate.
[0106] In one example, step S21 includes:
[0107] The first step is to make the first semiconductor layer.
[0108] In the embodiment of the present disclosure, the first semiconductor layer is an N-type GaN layer.
[0109] The second step is to make the active layer.
[0110] In the embodiment of the present disclosure, the active layer is a multi-quantum well layer.
[0111] The third step is to make the second semiconductor layer.
[0112] In the embodiment of the present disclosure, the second semiconductor layer is a P-type GaN layer.
[0113] In the embodiment of the present disclosure, the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked on the substrate.
[0114] In the disclosed embodiment, VeecoK465i or C4or RB MOCVD (Metal Organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition (MOCVD)) equipment or AIXTRON metal organic compound chemical vapor deposition equipment can be used to achieve the growth of the above semiconductor layer. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as a carrier gas, high-purity NH3 is used as an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) are used as gallium sources, trimethyl indium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethylaluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl) magnesium (CP2Mg) is used as a P-type dopant.
[0115] It is worth noting that other equipment may also be used to manufacture the semiconductor layer, and the present disclosure does not impose any limitation on this.
[0116] S22, performing graphic processing on the epitaxial structure to form a step structure and an isolation groove.
[0117] In the disclosed embodiment, the first semiconductor layer, the active layer and the second semiconductor layer are in a step structure extending to the first semiconductor, that is, the step surface is located in the first semiconductor layer. The first semiconductor layer, the active layer and the second semiconductor layer are also provided with an isolation groove, and the bottom of the isolation groove is located in the substrate.
[0118] Exemplarily, step S22 may include:
[0119] A patterned mask layer is formed on the surface of the second semiconductor layer; under the protection of the mask layer, the epitaxial structure is etched to form a step extending to the first semiconductor layer and an isolation groove extending to the substrate.
[0120] S23. Fabricate a current blocking layer on the epitaxial structure.
[0121] In the embodiment of the present disclosure, the current blocking layer may be an AlGaN or SiO2 layer.
[0122] Exemplarily, the current blocking layer is an AlGaN current blocking layer.
[0123] Exemplarily, step S23 may include:
[0124] An electron beam evaporation device is used to evaporate a current blocking layer on the surface of the second semiconductor layer of the epitaxial structure.
[0125] S24. Making a transparent conductive layer on the current blocking layer.
[0126] In the embodiment of the present disclosure, the transparent conductive layer may be an ITO layer. ITO has excellent transparency and conductivity. It allows light to pass through while also conducting current to form an electrical connection.
[0127] Exemplarily, step S24 may include:
[0128] Depositing an ITO film; and patterning the ITO film to obtain an ITO conductive layer.
[0129] The ITO film may be formed by evaporation. Patterning the ITO film may include: spin coating photoresist; forming a mask pattern by exposure and development; and wet etching the ITO film under the protection of the mask pattern.
[0130] S25. Fabricate an electrode structure.
[0131] Exemplarily, step S25 may include:
[0132] A first electrode is fabricated on the step surface of the step structure, and a second electrode is fabricated on the transparent conductive layer.
[0133] The first electrode and the second electrode can be manufactured by a deposition process.
[0134] In the embodiment of the present disclosure, the first electrode and the second electrode may be AuGe / Au electrodes or AuBe / Au electrodes.
[0135] Exemplarily, the first electrode is an AuBe / Au electrode, and the second electrode is an AuGe / Au electrode.
[0136] S26, making a coating layer, wherein the coating layer covers the isolation groove, the epitaxial structure, the transparent conductive layer and the electrode structure.
[0137] In the embodiment of the present disclosure, step S26 may include:
[0138] In the first step, SOD is used to coat the surfaces of the isolation grooves, epitaxial structures, transparent conductive layers and electrode structures.
[0139] Exemplarily, the coating process is as follows: SOD glue (SiO2) is coated on the light emitting diode chip with the electrode structure fabricated thereon by spin coating.
[0140] In the second step, the coated film layer is baked at high temperature to form a SiO2 dielectric layer.
[0141] In this implementation, the spin coating process can ensure that the coating layer covers the isolation groove, the epitaxial structure, the transparent conductive layer and the electrode structure at the same time, thereby forming a coating layer with a smooth surface, preparing for the subsequent formation of a smooth reflective layer.
[0142] In the disclosed embodiment, the upper surface of the coating layer may cover the top of the first electrode, and the surface of the coating layer is parallel to the surface of the substrate, thereby completely covering the isolation groove, the epitaxial structure, the transparent conductive layer and the electrode structure.
[0143] In this implementation, by designing the surface of the coating layer to be parallel to the substrate, the light emitted by the active layer can be better reflected by the reflective layer located on the coating layer, thereby improving the light extraction efficiency.
[0144] For example, after SOD coating, the distance between the surface of SOD and the surface of the electrode structure is about 2 μm. After heating and baking at high temperature and evaporation of the solvent, the thickness is reduced by 1 to 2 μm, and the distance between the surface of the formed coating layer and the surface of the electrode structure is 0 to 1 μm, for example, 0 μm, 0.5 μm or 1 μm.
[0145] In this implementation, the coating layer with the above thickness can cover the isolation groove, the epitaxial structure, the transparent conductive layer and the electrode structure at the same time to form a flat surface.
[0146] In the embodiment of the present disclosure, the step of high-temperature baking the coated film layer includes:
[0147] The coated film layer is baked at a baking temperature of 200 to 400° C. for a baking time of 0.5 to 3 hours.
[0148] Exemplarily, the baking temperature is 300° C. and the baking time is 2 h.
[0149] In this implementation, high temperature baking is used to polymerize and cross-link the adhesive material, and a SiO2 film layer is formed after the solvent evaporates.
[0150] S27. Making a reflective layer on the coating layer.
[0151] In the embodiment of the present disclosure, the reflective layer is a distributed Bragg reflector DBR layer.
[0152] For example, the DBR layer may include a plurality of periodically alternately stacked Ti3O5 layers and SiO2 layers, wherein the reflective layer may be manufactured by an evaporation process.
[0153] In the embodiment of the present disclosure, the reflective layer covers the coating layer, and a flat reflective layer is formed on the coating layer.
[0154] In the disclosed embodiment, after DBR front side evaporation, the DBR film layer on the entire chip surface is completely flat, and there is no slope position that causes the DBR reflectivity to decrease, thereby improving the overall reflectivity of the DBR inside the chip.
[0155] Figure 5 It is a schematic diagram of the reflectivity of the reflective layer in the light-emitting diode provided by the related technology. Figure 6 Schematic diagram of the reflectivity of the reflective layer in the light emitting diode provided by the embodiment of the present disclosure. Figure 5 and Figure 6 , the horizontal axis is the incident angle; the vertical axis is the reflectivity. Figure 5 It can be seen that the solution provided by the related art LED has a low reflectivity when the incident angle is the same at different positions. Figure 6 It can be seen that the reflectivity of the light-emitting diode provided in the embodiment of the present disclosure at various positions and angles is significantly enhanced compared with the related art, and the reflection uniformity is better.
[0156] Among them, position 1, position 2 and position 3 correspond to Figure 1 and Figure 2 Reference numerals 201, 202 and 203 in FIG.
[0157] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A light emitting diode, characterized in that: The light-emitting diode comprises: an epitaxial structure (10), an electrode structure (20), a coating layer (109) and a reflective layer (110); The epitaxial structure (10) is in the form of a step structure (112); the epitaxial structure (10) is also provided with an isolation groove (111); the electrode structure (20) is connected to the epitaxial structure (10); the coating layer (109) covers the isolation groove (111), the step structure (112) and the electrode structure (20), and the surface of the coating layer (109) is a plane; and the reflective layer (110) is located on the surface of the coating layer (109).
2. The light emitting diode according to claim 1, characterized in that: The coating layer (109) is a SiO2 coating layer.
3. The light emitting diode according to claim 1, characterized in that: The coating layer (109) is formed by spin coating a dielectric material and then baking it.
4. The light emitting diode according to claim 1, characterized in that: The light-emitting diode further comprises a substrate (101), a current blocking layer (105) and a transparent conductive layer (106); the epitaxial structure (10) is located on the substrate (101), the current blocking layer (105) is located on the epitaxial structure (10); and the transparent conductive layer (106) covers the current blocking layer (105); The electrode structure (20) comprises a first electrode (107) and a second electrode (108), wherein the first electrode (107) is located on the transparent conductive layer (106), and the second electrode (108) is located on a step surface of the step structure (112); The upper surface of the coating layer (109) covers the top of the first electrode (107), and the surface of the coating layer (109) is parallel to the surface of the substrate (101).
5. The light emitting diode according to any one of claims 1 to 4, characterized in that: The distance between the surface of the coating layer (109) and the surface of the electrode structure (20) is 0 to 1 μm.
6. A method for preparing a light emitting diode, characterized in that: The method comprises: fabricating epitaxial structures; Performing a patterning process on the epitaxial structure to form a step structure and an isolation groove; manufacturing an electrode structure, wherein the electrode structure is connected to the epitaxial structure; Manufacturing a coating layer, wherein the coating layer covers the isolation groove, the step structure and the electrode structure, and the surface of the coating layer is a plane; A reflective layer is formed on the coating layer.
7. The method for preparing a light emitting diode according to claim 6, characterized in that: The method of making the coating layer comprises: Using a spin-coated dielectric material to coat the surfaces of the isolation groove, the step structure, and the electrode structure; The coated film layer is baked at high temperature to form a SiO2 dielectric layer.
8. The method for preparing a light emitting diode according to claim 7, characterized in that: The high temperature baking of the coated film layer comprises: The coated film layer is baked at a baking temperature of 200 to 400° C. for a baking time of 0.5 to 3 hours.
9. The method for preparing a light emitting diode according to any one of claims 6 to 8, characterized in that: The method of manufacturing the epitaxial structure comprises: Fabricating the epitaxial structure on a substrate; Before manufacturing the electrode structure, the method further comprises: forming a current blocking layer on the epitaxial structure; forming a transparent conductive layer on the current blocking layer; The electrode structure comprises a first electrode and a second electrode, the first electrode is located on the transparent conductive layer, and the second electrode is located on a step surface of the step structure; The upper surface of the coating layer covers the top of the first electrode, and the surface of the coating layer is parallel to the surface of the substrate.
10. The method for preparing a light emitting diode according to any one of claims 6 to 8, characterized in that: The distance between the surface of the coating layer and the surface of the electrode structure is 0-1 μm.