Synchronous phasor calculation method and system based on digital phase-locked loop

Abstract

The invention discloses a synchronous phasor calculation method and system based on a digital phase-locked loop, and relates to the technical field of synchronous phasor calculation, and the method comprises the steps: carrying out the sampling after the physical low-pass filtering of a three-phase signal of a power system, and obtaining the original A, B and C three-phase data; key parameters of the digital phase-locked loop are designed; performing positive and negative sequence Park transformation on the original ABC three-phase data to obtain dq-axis components; performing decoupling calculation on the dq-axis component, and updating the intermediate variable; the intermediate variable is used for filtering, PI adjustment and final output of phase, frequency and amplitude signals, and the intermediate variable is stored for decoupling calculation of the next time sequence. Compared with a Fourier algorithm generally adopted by a current measurement and control device, the method is suitable for various power system working conditions, better calculation real-time performance and smaller calculation amount are achieved while the calculation precision is met, and the amplitude, the phase and the frequency can be obtained through calculation at the same time without depending on other methods.

Description

Technical Field

[0001] The present invention relates to the technical field of synchronous phasor calculation, and in particular to a synchronous phasor calculation method and system based on a digital phase-locked loop. Background Art

[0002] Nowadays, electricity is the main energy source for social life and production. As the main carrier of electricity, the power system converts primary energy in nature into electrical energy through power generation devices, and then transmits electrical energy to various users through transmission, substation and distribution. In order to ensure the safe and reliable development of social economy, the normal operation of the power system is crucial. When there is a fault in the electrical equipment of the power system, such as transformers, transmission lines, etc., or in the system, the relay protection device must be able to cut off the faulty equipment from the power system according to the established parameters to avoid the expansion of the fault and even cause a large-scale power outage. According to the classification of action principles, such as overcurrent protection, differential protection and other relay protection functions, reclosing and synchronization detection and other conventional operations of the power system have high requirements for the calculation accuracy and real-time performance of the power system phase, frequency and amplitude (hereinafter referred to as the power system phasor).

[0003] The current calculation methods of phase, frequency and amplitude of power systems can be divided into two categories: one is designed for protection function, and the other is designed for measurement and control function. Among them, the power system phasor calculation methods designed for protection function mainly include zero-crossing algorithm or 90-degree phase angle difference algorithm in combination with Fourier transform. In order to meet the requirements of rapid relay protection, the above algorithms exchange accuracy, scope of application and high sampling requirements for the improvement of calculation speed. For example, the zero-crossing algorithm calculates once per cycle (about 20ms), and its real-time performance is worse than that of algorithms such as Fourier algorithm that can calculate each sampling point, and it cannot calculate the amplitude, and still needs to rely on other algorithms; the Fourier algorithm requires complete sampling of the cycle, otherwise it is easy to cause spectrum leakage when the frequency offset is large; the 90-degree phase angle difference algorithm is used to calculate the frequency, but it depends on the calculation accuracy of the phase and amplitude. The phase and amplitude are usually calculated by the Fourier algorithm, so it also has high requirements for complete sampling of the cycle. In addition, due to the narrow calculation time window, the above algorithms are not suitable for complex applications such as waveform distortion, large frequency deviation, frequency slope and low-frequency oscillation, and the accuracy is low. The synchronous phasor calculation method of the power system designed for measurement and control functions adopts the Fourier decomposition algorithm. Although it can be applied to a variety of applications, the time window required for calculation is long and the real-time performance is poor.

[0004] As social and economic development progresses, the power system's requirements for measurement and control functions will inevitably increase gradually, and the existing calculation methods may be unable to meet the demand. Summary of the invention

[0005] In view of the above-mentioned problems, the present invention is proposed.

[0006] Therefore, the problem to be solved by the present invention is: how to solve the problem that the current electric power system synchronous phasor calculation method requires a relatively long time window and has poor real-time performance.

[0007] To solve the above technical problems, the present invention provides the following technical solutions: a synchronous phasor calculation method based on a digital phase-locked loop, comprising: sampling the three-phase signal of the power system after physical low-pass filtering to obtain original ABC three-phase data; designing key parameters of the digital phase-locked loop; performing positive and negative sequence Park transformation on the original ABC three-phase data respectively to obtain dq axis components; performing decoupling calculation on the dq axis components to update intermediate variables; the intermediate variables are used for filtering, PI adjustment and ultimately outputting phase, frequency and amplitude signals, and storing the intermediate variables for the next time series decoupling calculation.

[0008] As a preferred solution of the synchronous phasor calculation method based on a digital phase-locked loop described in the present invention, the key parameters of the digital phase-locked loop include the proportional coefficient, integral coefficient and low-pass filter cutoff frequency of the phase-locked loop controller, which are designed according to classical control theory.

[0009] As a preferred solution of the synchronous phasor calculation method based on a digital phase-locked loop described in the present invention, the sampling after low-pass filtering includes collecting the three-phase voltage and current signals of the power system outgoing line interval after physical low-pass filtering to obtain the original ABC three-phase data.

[0010] As a preferred solution of the synchronous phasor calculation method based on a digital phase-locked loop described in the present invention, wherein: the positive and negative sequence Park transformation includes performing positive and negative sequence Park transformation on the three-phase voltage and the three-phase current respectively, and obtaining the positive sequence d-axis voltage component u after the three-phase voltage is transformed by the positive and negative sequence Park transformation d +1 , positive sequence q-axis voltage component u q +1 , negative sequence d-axis voltage component u d -1 , negative sequence q-axis voltage component u q -1 The dq axis components of the three-phase current are transformed by the positive and negative sequence Park to obtain the positive sequence d axis current component i d +1 , positive sequence q-axis current component i q +1 , negative sequence d-axis current component i d -1 , negative sequence q-axis current component i q -1 The dq-axis components of .

[0011] As a preferred solution of the synchronous phasor calculation method based on a digital phase-locked loop described in the present invention, the decoupling calculation includes:d +1 、u q +1 、u d -1 and u q -1 , combined with the phase angle calculated in the previous time series and the result of the low-pass filtering of the intermediate variable in the previous time series and Calculate the intermediate variable ud* +1 、uq* +1 ,ud* -1 and uq* -1 , expressed as:

[0012]

[0013] in, is the intermediate variable of the positive sequence d-axis voltage component, is the intermediate variable of the positive sequence q-axis voltage component, is the intermediate variable of the negative-sequence d-axis voltage component, is the intermediate variable of the negative sequence q-axis voltage component, θ' is the phase angle of the previous time sequence, It is the calculation result of the intermediate variable of the previous time series after low-pass filtering.

[0014] As a preferred solution of the synchronous phasor calculation method based on a digital phase-locked loop described in the present invention, wherein: the final output phase, frequency and amplitude signal includes the intermediate variable u d * +1 、u q * +1 、u d * -1 、u q * -1 After filtering and PI adjustment, the angular frequency w is expressed as:

[0015] w=2π*f

[0016] Where w is the angular frequency and f is the frequency. After integrating the angular frequency w, the output phase θ and amplitude signal amp are expressed as:

[0017]

[0018] Among them, amp is the amplitude signal, is the positive sequence direct axis component, is the positive sequence quadrature axis component.

[0019] As a preferred solution of the synchronous phasor calculation method based on a digital phase-locked loop described in the present invention, the decoupling calculation for the next timing includes storing intermediate variables for the next timing decoupling calculation, and restarting the calculation from sampling after low-pass filtering.

[0020] Another object of the present invention is to provide a system of a synchronous phasor calculation method based on a digital phase-locked loop, which can solve a synchronous phasor calculation problem based on a digital phase-locked loop by constructing a synchronous phasor calculation system.

[0021] To solve the above technical problems, the present invention provides the following technical solutions: a synchronous phasor calculation system based on a digital phase-locked loop, comprising a key parameter design module, a data acquisition module, a positive and negative sequence Park transformation module, a decoupling calculation module and an output module; the key parameter design module is used to design the key parameters of the digital phase-locked loop; the data acquisition module is used to sample the three-phase signal of the power system after physical low-pass filtering to obtain the original ABC three-phase data; the positive and negative sequence Park transformation module is used to perform positive and negative sequence Park transformation on the original ABC three-phase data respectively to obtain dq axis components; the decoupling calculation module is used to perform decoupling calculation on the dq axis components and update intermediate variables; the output module is used to filter the intermediate variables, PI adjust and finally output phase, frequency and amplitude signals, store the intermediate variables for the next time series decoupling calculation.

[0022] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the above-mentioned method for calculating synchronous phasors based on a digital phase-locked loop are implemented.

[0023] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a synchronous phasor calculation method based on a digital phase-locked loop as described above.

[0024] The beneficial effects of the present invention are as follows: compared with the Fourier algorithm commonly used in current measurement and control devices, the synchronous phasor calculation method based on a digital phase-locked loop provided by the present invention is suitable for various power system operating conditions, meets the calculation accuracy, and also has better calculation real-time performance and smaller calculation amount. Moreover, the method of the present invention can simultaneously calculate the amplitude, phase and frequency without relying on other methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0026] Figure 1 A flowchart of a synchronous phasor calculation method based on a digital phase-locked loop is provided for the first embodiment of the present invention.

[0027] Figure 2 A block diagram of a phase-locked loop structure in a decoupled dual synchronous coordinate system of a synchronous phasor calculation method based on a digital phase-locked loop provided in the first embodiment of the present invention.

[0028] Figure 3 A structural diagram of a synchronous phasor calculation system based on a digital phase-locked loop is provided for the second embodiment of the present invention.

[0029] Figure 4 A comparison diagram between the calculated value of the present invention and the reference value when the frequency offset of a synchronous phasor calculation method based on a digital phase-locked loop provided in the third embodiment of the present invention is large.

[0030] Figure 5 A comparison diagram between the calculated value of the present invention and the reference value during frequency modulation of a synchronous phasor calculation method based on a digital phase-locked loop provided in the third embodiment of the present invention.

[0031] Figure 6 A distorted three-phase signal diagram of a synchronous phasor calculation method based on a digital phase-locked loop provided in the third embodiment of the present invention.

[0032] Figure 7 A diagram of calculated values ​​and reference values ​​of a synchronous phasor calculation method based on a digital phase-locked loop provided in a third embodiment of the present invention when waveform distortion is severe. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0035] Example 1, reference Figure 1 and Figure 2, which is the first embodiment of the present invention, and provides a synchronous phasor calculation method based on a digital phase-locked loop, including: designing key parameters of a digital phase-locked loop; sampling the three-phase signal of the power system after physical low-pass filtering to obtain original ABC three-phase data; performing positive and negative sequence Park transformation on the original ABC three-phase data respectively to obtain dq axis components; performing decoupling calculation on the dq axis components to update intermediate variables; the intermediate variables are used for filtering, PI adjustment and ultimately outputting phase, frequency and amplitude signals, and storing the intermediate variables for the next time series decoupling calculation.

[0036] S1. Design key parameters of digital phase-locked loop.

[0037] Including the phase-locked loop controller proportional coefficient k p , integration coefficient k i and the low-pass filter cutoff frequency ω c , can be designed according to classical control theory. p =2.22, k i =246.7,ω c =250.

[0038] S2, sampling after low-pass filtering.

[0039] The three-phase voltage and current signals of the power system outgoing line interval are collected after physical low-pass filtering to obtain the original ABC three-phase data.

[0040] S3, the original ABC three-phase data are respectively subjected to positive and negative sequence Park transformation to obtain dq axis components.

[0041] The original ABC three-phase data are transformed into positive and negative sequence Parks to obtain the dq axis components. The three-phase voltage and three-phase current are transformed into Parks (corresponding to Figure 2 abc / dq+ and abc / dq-), the three-phase voltage is transformed by positive and negative sequence Park to obtain the positive sequence d-axis voltage component u d +1 , positive sequence q-axis voltage component u q +1 , negative sequence d-axis voltage component u d -1 , negative sequence q-axis voltage component u q -1 The dq axis components of the three-phase current are transformed by the positive and negative sequence Park to obtain the positive sequence d axis current component i d +1 , positive sequence q-axis current component i q +1 , negative sequence d-axis current component i d -1 , negative sequence q-axis current component i q -1The dq-axis components of . Figure 2 The following steps are all based on voltage as an example.

[0042] S4, dq axis components are decoupled and calculated, and intermediate variables are updated.

[0043] The dq axis components are decoupled and calculated to update the intermediate variables. The u obtained in step S3 d +1 、u q +1 、u d -1 and u q -1 , and then combine the phase angle θ calculated in the previous step and the calculation result of the intermediate variable of the previous cycle after low-pass filtering, and calculate the intermediate variable u through formula (1) (2) d * +1 、u q * +1 、u d * -1 and u q * -1 , expressed as:

[0044]

[0045] in, is the intermediate variable of the positive sequence d-axis voltage component, is the intermediate variable of the positive sequence q-axis voltage component, is the intermediate variable of the negative-sequence d-axis voltage component, is the intermediate variable of the negative sequence q-axis voltage component, θ' is the phase angle of the previous time sequence, It is the calculation result of the intermediate variable of the previous time series after low-pass filtering.

[0046] By the attached Figure 2 middle u q * +1 , after PI adjustment, the angular frequency w is obtained, and the angular frequency w is then integrated over time to obtain the phase angle θ, that is, Figure 2 The symbol of the elongated s in the figure is explained in another way: the superscript "^" in the figure indicates an estimated value, that is, the value calculated by this method after collecting three-phase voltage and current data. The reference value means the actual value. The ideal goal is that the estimated value is completely equal to the actual value, but there is often an error between the two. For example, the actual voltage frequency of the current system = 50.002Hz, but the value calculated by the method may be 50.00199Hz.

[0047] S5. Intermediate variables are used for filtering, PI adjustment and final output of phase, frequency and amplitude signals. Intermediate variables are stored for the next time series decoupling calculation.

[0048] Intermediate variable u d * +1 、u q * +1 、u d * -1 、u q * -1 After filtering and PI adjustment, the angular frequency w is expressed as:

[0049] w=2π*f

[0050] Where w is the angular frequency and f is the frequency;

[0051] The output phase θ after the angular frequency w is integrated is the angular frequency multiplied by time, that is, the integral of the angular frequency over time, expressed as:

[0052] θ=w*t

[0053] The amplitude signal amp is expressed as:

[0054]

[0055] Among them, amp is the amplitude signal, is the positive sequence direct axis component, It is the positive sequence quadrature axis component and is used for relay protection function.

[0056] The intermediate variables are stored for the next time series decoupling calculation, and then the process goes to step S2.

[0057] abc / dq + and abc / dq - Respectively represent abc coordinate system to dq + and dq - The coordinate system is transformed, and LPF is a low-pass filter. By extracting the positive sequence component of the voltage, its q-axis component This can accurately output the amplitude, phase angle and frequency of the positive sequence component and the negative sequence component. Signal, Elimination The second harmonic component caused by the negative sequence voltage component is reduced, thereby suppressing the influence of three-phase voltage unbalance.

[0058] The present invention applies the digital phase-locked loop method to the field of synchronous phasor calculation in power systems to obtain better real-time calculation and smaller calculation amount. The method of the present invention can simultaneously calculate the amplitude, phase and frequency without relying on other methods.

[0059] Example 2, reference Figure 3, which is the second embodiment of the present invention, is different from the previous embodiment in that it provides a synchronous phasor calculation system based on a digital phase-locked loop, including: a key parameter design module 100, a data acquisition module 200, a positive and negative sequence Park transformation module 300, a decoupling calculation module 400 and an output module 500.

[0060] The key parameter design module 100 is used to design key parameters of a digital phase-locked loop.

[0061] The data acquisition module 200 is used for sampling the three-phase signal of the power system after physical low-pass filtering to obtain the original ABC three-phase data.

[0062] The positive- and negative-sequence Park transformation module 300 is used to perform positive- and negative-sequence Park transformation on the original ABC three-phase data respectively to obtain dq axis components.

[0063] The decoupling calculation module 400 is used to perform decoupling calculations on dq axis components and update intermediate variables.

[0064] The output module 500 is used for filtering, PI adjustment and finally outputting phase, frequency and amplitude signals of intermediate variables, and storing the intermediate variables for the next time series decoupling calculation.

[0065] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0066] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0067] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0068] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0069] Example 3, reference Figures 4 to 7 , which is the third embodiment of the present invention, and is different from the previous two embodiments in that: it is used to verify and illustrate the technical effects adopted in the present invention, so as to verify the real effects of this method.

[0070] After analysis, the method of the present invention only needs to calculate 39 multiplications and divisions, 27 additions and subtractions, and several sine and cosine table lookups per sampling sequence to obtain the phase, frequency, and amplitude of the new sampling sequence synchronous phasor, and the amount of calculation is relatively small. Since the algorithm includes a PI control link, the overall tracking real-time performance of the algorithm is good and the controllability is excellent.

[0071] like Figures 4 to 7 As shown in the figure, the comparison between the calculated value and the reference value of the calculation method of the present invention is shown when the frequency offset is large (45Hz), the amplitude step, and the waveform distortion is serious (high harmonic content). Due to the limited space, only the above three types of common faults in the power system are listed. The actual effects of the present invention under other conditions such as frequency ramp, phase step and amplitude modulation are no longer listed one by one, but the method of the present invention is also effective under these conditions. The horizontal axis in the figure is the number of half cycles, which is Figure 4 , Figure 6 and Figure 7 It can be seen that the method described in the present invention has a small overall calculation amount and can achieve high calculation accuracy under various working conditions. Figure 5 It can be seen that when a sudden change in the amplitude parameter occurs, the output amplitude of the method of the present invention can be tracked in about one cycle (20ms), which is much less than the 70ms required by the specification (such as Q / CSG1203052-2018 Southern Power Grid Phasor Measurement Unit (PMU) Technical Specification 6.8.9 Step Response), and the output frequency can be tracked in about 4 cycles (80ms), which is much less than the 280ms required by the specification, and the output phase is less affected.

[0072] Some calculations are basic / general calculation methods, such as low-pass filtering, park transformation and PI controller, so detailed formulas are not given. The calculated values ​​are close to the reference values, so Figure 4 , Figure 7 Visually similar to a line, it can be seen from Figure 5 See the difference between the two. The reference value is the true value. Figure 4 , 5, and 7 are some simulated voltage and current data, which illustrate the effectiveness of this method by comparing the real values ​​with the calculated values.

[0073] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A synchronous phasor calculation method based on a digital phase-locked loop, characterized in that: include, Design key parameters of digital phase-locked loop; The three-phase signal of the power system is sampled after physical low-pass filtering to obtain the original ABC three-phase data; The original ABC three-phase data are subjected to positive and negative sequence Park transformation respectively to obtain the dq axis components; The dq axis components are decoupled and calculated, and the intermediate variables are updated; The intermediate variables are used for filtering, PI adjustment and final output of phase, frequency and amplitude signals. The intermediate variables are stored for the next time series decoupling calculation.

2. A synchronous phasor calculation method based on a digital phase-locked loop as claimed in claim 1, characterized in that: The key parameters of the digital phase-locked loop include a phase-locked loop controller proportional coefficient, an integral coefficient and a low-pass filter cut-off frequency, and are designed according to classical control theory.

3. A synchronous phasor calculation method based on a digital phase-locked loop as claimed in claim 2, characterized in that: The post-low-pass filtering sampling includes collecting three-phase voltage and current signals of the power system outgoing line interval after physical low-pass filtering to obtain original ABC three-phase data.

4. A synchronous phasor calculation method based on a digital phase-locked loop as claimed in claim 3, characterized in that: The positive and negative sequence Park transformation includes performing positive and negative sequence Park transformation on the three-phase voltage and the three-phase current respectively. After the positive and negative sequence Park transformation, the three-phase voltage obtains the positive sequence d-axis voltage component u d +1 , positive sequence q-axis voltage component u q +1 , negative sequence d-axis voltage component u d -1 , negative sequence q-axis voltage component u q -1 The dq axis components of the three-phase current are transformed by the positive and negative sequence Park to obtain the positive sequence d axis current component i d +1 , positive sequence q-axis current component i q +1 , negative sequence d-axis current component i d -1 , negative sequence q-axis current component i q -1 The dq-axis components of .

5. A synchronous phasor calculation method based on a digital phase-locked loop as claimed in claim 4, characterized in that: The decoupling calculation includes obtaining u d +1 、u q +1 、u d -1 and u q -1 , combined with the phase angle calculated in the previous time series and the result of low-pass filtering of the intermediate variable in the previous time series and Calculate the intermediate variable ud* +1 、uq* +1 ,ud* -1 and uq* -1 , expressed as, in, is the intermediate variable of the positive sequence d-axis voltage component, is the intermediate variable of the positive sequence q-axis voltage component, is the intermediate variable of the negative-sequence d-axis voltage component, is the intermediate variable of the negative sequence q-axis voltage component, θ' is the phase angle of the previous time sequence, It is the calculation result of the intermediate variable of the previous time series after low-pass filtering.

6. A synchronous phasor calculation method based on a digital phase-locked loop as claimed in claim 5, characterized in that: The final output phase, frequency and amplitude signals include the intermediate variable u d * +1 、u q * +1 、u d * -1 、u q * -1 After filtering and PI adjustment, the angular frequency w is expressed as: w=2π*f Where w is the angular frequency and f is the frequency; After integrating the angular frequency w, the output phase θ and amplitude signal amp are expressed as: Among them, amp is the amplitude signal, is the positive sequence direct axis component, is the positive sequence quadrature axis component.

7. A synchronous phasor calculation method based on a digital phase-locked loop as claimed in claim 6, characterized in that: The providing for the next time series decoupling calculation includes storing the intermediate variables for the next time series decoupling calculation, and restarting the calculation from the sampling after the low-pass filtering.

8. A system using a synchronous phasor calculation method based on a digital phase-locked loop as claimed in any one of claims 1 to 7, characterized in that: It comprises a key parameter design module (100), a data acquisition module (200), a positive and negative sequence Park transformation module (300), a decoupling calculation module (400) and an output module (500); The key parameter design module (100) is used to design key parameters of a digital phase-locked loop; The data acquisition module (200) is used for sampling after physical low-pass filtering of the three-phase signal of the power system to obtain original ABC three-phase data; The positive and negative sequence Park transformation module (300) is used to perform positive and negative sequence Park transformation on the original ABC three-phase data respectively to obtain dq axis components; The decoupling calculation module (400) is used to perform decoupling calculation on dq axis components and update intermediate variables; The output module (500) is used for filtering and PI regulation of intermediate variables and finally outputting phase, frequency and amplitude signals, and storing intermediate variables for the next time series decoupling calculation.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of a synchronous phasor calculation method based on a digital phase-locked loop according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of a synchronous phasor calculation method based on a digital phase-locked loop according to any one of claims 1 to 7 are implemented.

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