Quantum computing chips based on vertical micromirrors, on-chip systems, and their simulator correction methods

Abstract

The application discloses a quantum computing chip based on a vertical micro-lens, a system on a chip and a simulator correction method thereof, a vertical micro-lens structure with roughness less than 5nm can be formed by smoothing the sidewall of a deep etching vertical structure, which can greatly reduce the loss of light irradiation on the sidewall interface of a silicon-based optical device, a quantum computing chip is developed on a silicon wafer, another optical computing chip structure other than macroscopic space optics and silicon-based optoelectronics is realized, and the process is fully compatible with advanced packaging processes, so that photoelectric wafer-level system integration of sensing, storage and calculation can be realized. For the system on a chip of the integrated quantum computing chip, the integrated circuit chip (and the optical sensing chip), the crosstalk, loss and delay of the TSV transmission signal are reduced through the vertical micro-lens technology, and the indirect measurement of the sidewall roughness is realized through the Fabry-Perot interference, and then the ideal system on a chip simulator is corrected, so that the simulation result of the simulator is closer to the actual measurement result of the system on a chip.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic technology, and particularly relates to a quantum computing chip based on a vertical micromirror, a system-on-a-chip, and a method for correcting its simulator. Background Technology

[0002] In 2003, O'Brien et al. first realized a quantum controlled NOT gate based on space optics. By realizing a two-qubit quantum state based on polarization and path, they used optical components such as polarizing beam splitters and semi-transparent beam splitters to realize a CNOT logic gate for a single photon of the two-qubit quantum state. However, macroscopic space optics usually occupy a large area, which is not convenient for large-scale applications. In 2007, Politi et al. realized an integrated quantum logic gate based on silicon-based optoelectronics. However, the manufacturing process of silicon photonic devices is usually difficult, and silicon waveguides have poor long-distance transmission capabilities.

[0003] As integrated circuit manufacturing processes enter the sub-10 nanometer range, Moore's Law is gradually slowing down and eventually becoming obsolete. Advanced packaging technologies, such as 2.5D / 3D packaging and wafer-level packaging, have become effective technical routes to further improve the performance of integrated circuit systems in the post-Moore's Law era. Through advanced packaging technologies, multi-chip systems can achieve high-density, high-bandwidth, low-latency, and low-power wafer-level heterogeneous integrated systems. Quantum computing chips have improved the computing efficiency of optoelectronic integrated on-chip systems and promoted the development of optoelectronic integration technology. However, with the expansion of system scale, system design and manufacturing also face new challenges: at the design level, wafer-level systems are large in scale and complex in function, requiring the development of domain-specific wafer-level system simulators to achieve optimal configuration of resource scheduling, data exchange, etc., to achieve efficient operation of the on-chip system; at the manufacturing level, the silicon wafer interposer in the wafer-level system is a carrier board that manufactures a whole wafer into a fully functional electrical / optical interconnect, and its quality directly determines the degree of crosstalk, loss, delay, and reliability between on-chip system chips. One of the most critical influencing factors is the sidewall roughness of the through silicon vias (TSVs) on silicon wafer interposers. TSVs manufactured using Bosch's deep etching technology inevitably exhibit scalloped defects on the sidewalls, severely impacting signal quality and reliability. Since atomic force microscopy (AFM) typically measures the roughness of planar thin films, it is difficult to directly measure the roughness of the vertical sidewalls of TSVs. Therefore, there is an urgent need to develop a method to indirectly measure the TSV sidewall roughness of silicon wafer interposers, and to use this method to construct electrical and mechanical models to correct for signal crosstalk, loss, and delay in an ideal on-chip system simulator. Summary of the Invention

[0004] To address the problems existing in the prior art, this application provides a quantum computing chip based on a vertical micromirror, a system-on-a-chip, and a method for correcting its simulator.

[0005] According to a first aspect of the embodiments of this application, a quantum computing chip is provided, the quantum computing chip including a plurality of quantum gates, the quantum gates being manufactured through the following process:

[0006] Deeply etch vertical structures onto single-crystal silicon wafers;

[0007] The vertical structure is sidewall smoothed to form a vertical micromirror. Sidewall smoothing methods include, but are not limited to, high-temperature annealing, low-flow dry etching, reducing the alternation cycle of etching and protection processes, low-concentration wet chemical etching, and gas cluster ion beam etching.

[0008] One or more of the following are deposited on the sidewall surface of a vertical micromirror: an antireflective coating, an anti-reflective coating, a filter coating, a polarizing coating, and a beam-splitting coating, using an optical vacuum coating machine, physical vapor deposition, chemical vapor deposition, or atomic layer deposition:

[0009] Using a two-photon 3D printer, submicron structures are printed on the sidewalls of a vertical micromirror to form one or more of the following: spherical lens, aperture, grating, polarizer, half-wave plate, superlens, and optical waveguide.

[0010] Furthermore, the low-flow dry etching specifically refers to:

[0011] The vertical structure is post-etched using one or more of the following: sulfur hexafluoride, argon plasma, oxygen plasma, and xenon difluoride, with a gas flow rate of less than 30 sccm.

[0012] Furthermore, the low-concentration wet chemical corrosion specifically refers to:

[0013] The sidewalls of the vertical structure were etched using a solution of less than 5 wt.% potassium hydroxide or tetramethylammonium hydroxide, 10 wt.% to 30 wt.% isopropanol, and deionized water.

[0014] According to a second aspect of the embodiments of this application, a quantum computing chip is provided, the quantum computing chip including a plurality of quantum gates, the quantum gates being manufactured through the following process:

[0015] Photosensitive resin-based vertical micromirrors were fabricated on the upper surface of a substrate using a two-photon 3D printing method.

[0016] One or more of the following: antireflective coating, filter coating, polarizing coating, and beam-splitting coating are grown on the surface of a vertical micromirror;

[0017] Using a two-photon 3D printer, submicron structures are printed on the sidewalls of a vertical micromirror to form one or more of the following: spherical lens, aperture, grating, polarizer, half-wave plate, superlens, and optical waveguide.

[0018] Furthermore, for the quantum computing chip described in the first and second aspects, the quantum gate further includes a waveplate, which is manufactured through the following process:

[0019] Depositing a metal seed layer on a single-crystal silicon wafer;

[0020] A submicron-sized photosensitive resin-based electroplated mask layer was printed on the sidewall of a vertical micromirror using a two-photon 3D printer.

[0021] Photoresist is sprayed onto the upper surface of a single-crystal silicon wafer using a spray coating method, and the area with the photosensitive resin-based electroplated mask layer is exposed and developed.

[0022] A submicron metal structure layer is grown by electroplating in the area of ​​the seed layer that has been exposed and developed but is not covered by an electroplating mask layer with a photosensitive resin base.

[0023] The photosensitive resin-based electroplated mask layer, photoresist, and seed layer are removed to obtain a metal structure waveplate on the sidewall of the vertical micromirror.

[0024] According to a third aspect of the embodiments of this application, a system-on-a-chip is provided, including a quantum computing chip and an integrated circuit chip as described in the first or second aspect, wherein the quantum computing chip and the integrated circuit chip are coupled by optical fiber or by photonic wire bonding through a polymer waveguide manufactured by two-photon 3D printing, thereby achieving optoelectronic co-packaging.

[0025] Furthermore, it also includes a sensing chip, in which the vertical structure is sidewall smoothed by methods such as high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, gas cluster ion beam etching, or reducing the alternation cycle of etching and protection processes.

[0026] Furthermore, the sensing chip is a triaxial photoelectric dual-readout accelerometer chip. The triaxial photoelectric dual-readout accelerometer chip includes a mass block, a spring beam, comb teeth, an upper cover plate, a lower cover plate, and a second end face. The second end face and the sidewall of the comb teeth form an FP cavity to realize optical readout in the XY direction. Electrical readout in the XY direction is realized through a parallel plate capacitor formed by the comb teeth. The mass block, the upper cover plate, and the lower cover plate form an FP cavity to realize optical readout in the Z direction. Electrical readout in the Z-axis direction is realized through a parallel plate capacitor formed by the mass block, the upper cover plate, and the lower cover plate.

[0027] Furthermore, the sensing chip is a photoelectric dual-readout gyroscope, which includes an optical fiber array, a mass block, a second end face, and comb teeth. Under the action of angular acceleration, the mass block drives the comb teeth to twist. Each optical fiber in the optical fiber array forms an FP cavity with the second end face and the comb teeth to realize optical readout. Electrical readout is realized through a parallel plate capacitor composed of the comb teeth.

[0028] According to a fourth aspect of the embodiments of this application, a method for correcting an on-chip system simulator is provided, comprising:

[0029] Deeply etch through-silicon vias onto the silicon wafer adapter board;

[0030] The sidewalls of the through-silicon via are smoothed using any one of the following methods: high-temperature annealing, low-flow dry etching, reducing the alternation cycle of etching and protection processes, or low-concentration wet chemical etching.

[0031] A single-mode fiber is coupled into the sidewall of the smoothed silicon via. A laser in the communication band is used as the light source, and the light source, power meter and single-mode fiber are connected through a circulator to obtain the FP interference spectrum. The correspondence between the FP interference spectrum and the sidewall roughness of the silicon via is established, and a simulation model of the silicon wafer adapter board considering process deviation is established based on the correspondence.

[0032] The simulation model of the silicon wafer adapter is modified based on silicon wafer adapters with different sidewall roughness.

[0033] The on-chip system simulator in an ideal state is modified based on the modified silicon wafer adapter simulation model, wherein the on-chip system simulator is used to simulate the on-chip system described in the third aspect.

[0034] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0035] First, the present invention uses methods such as high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle of etching and protection processes, and gas cluster ion beam etching to smooth the sidewalls of deeply etched vertical structures, which can form vertical micromirror structures with a roughness of less than 5 nm, and can significantly reduce the loss of light irradiation on the sidewall interface of silicon-based optical devices.

[0036] Secondly, the vertical micromirror technology developed in this invention achieves transparent silicon-based vertical sidewalls for communication bands. Combined with an optical vacuum coating machine, antireflective coatings, anti-reflective coatings, filters, polarizing films, and beam splitters can be fabricated on these silicon-based vertical sidewalls. Furthermore, by combining this technology with submicron two-photon 3D printing, key optical components such as mirrors, cylindrical lenses, spherical lenses, collimators, apertures, gratings, beam splitters, polarizers, half-wave plates, superlenses, and optical waveguides can be fabricated on the silicon-based vertical sidewalls. This allows for the integration of macroscopic spatial optical devices onto silicon wafers, reducing system size and increasing integration compared to traditional macroscopic spatial optical systems. Compared to silicon-based optoelectronics, the process is not only simpler, but also results in lower light transmission loss in air compared to silicon waveguides.

[0037] Third, this invention develops a quantum computing chip on a silicon wafer based on vertical micromirror technology, realizing an alternative optical computing chip structure beyond macroscopic spatial optics and silicon-based optoelectronics. Moreover, the process is fully compatible with advanced packaging technology, enabling optoelectronic wafer-level system integration of sensing, storage, and computing.

[0038] Fourth, for on-chip systems integrating quantum computing chips, integrated circuit chips (and optical sensing chips), this invention reduces crosstalk, loss and delay of TSV transmission signals through vertical micromirror technology, and achieves indirect measurement of sidewall roughness through Fabry-Perot interferometry, thereby correcting the ideal on-chip system simulator so that its simulation results are closer to the real measurement results of the on-chip system.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0041] Figure 1 The diagram shows the collimating lens and beam splitter based on the vertical micromirror of the present invention. (a)-(b) are schematic diagrams of the principle of collimating incident light by manufacturing a vertical spherical lens on a silicon substrate and the sidewall of a silicon vertical micromirror using two-photon 3D printing technology. (c)-(d) are schematic diagrams of the beam splitter based on the vertical micromirror technology.

[0042] Figure 2 The diagram shows the schematic of a two-bit quantum logic gate and photographs of a beam splitter and a quantum gate chip based on vertical micromirror technology. (a) is the schematic of the two-bit quantum logic gate, and (b)-(c) are photographs of the beam splitter and the CNOT quantum gate chip based on vertical micromirror technology, respectively.

[0043] Figure 3The diagram shows the manufacturing process flow chart of CNOT quantum gates, where (a)-(f) are wafer cross-sectional views of each process.

[0044] Figure 4 The diagram shows the effect of the sidewall smoothing technology of the present invention, where (a) is an electron microscope image of the sidewall cross section before smoothing, and (b) is an electron microscope image of the sidewall cross section after smoothing.

[0045] Figure 5 The diagram shows the process flow for manufacturing three-dimensional optical chips using two-photon 3D printing technology.

[0046] Figure 6 The diagram shows a cross-sectional view of the fabrication process of waveplates on the sidewall of a silicon-based vertical micromirror.

[0047] Figure 7 The diagram shows a schematic of the on-chip system, where (a) and (b) are schematic diagrams of the on-chip system under two optoelectronic co-packaging architectures.

[0048] Figure 8 The diagram shows a schematic of the manufacturing process of a sensor chip based on a vertical micromirror. (a)-(b) are top views and cross-sectional views of the FP pressure sensor chip, (c)-(d) are top views and cross-sectional views of the triaxial photoelectric dual readout accelerometer sensor chip, and (e)-(f) are schematic diagrams of the principle of measuring angular acceleration using a photoelectric dual readout gyroscope.

[0049] Figure 9 The diagram shows the on-chip system simulator correction method of the present invention, wherein (a) is a flowchart of the on-chip system simulator correction method, and (b) is the FP interferogram measured after sidewall smoothing.

[0050] Figure 10 The diagram shows the key technical logic of quantum computing chips, on-chip systems, and on-chip system simulator correction methods.

[0051] Figure 11 The diagram shown is a key technical logic diagram for the hardware manufacturing of the optoelectronic integrated on-chip system of the present invention.

[0052] Reference numerals: 1. Single-crystal silicon wafer; 2. Vertical micromirror; 3. Antireflective coating; 4. Anti-reflective coating; 5. Spherical collimating lens; 6. Half-wave plate; 7. Integrated circuit chip; 8. Redistribution layer; 9. TSV; 10. Pad; 11. Power control chip; 12. Circuit board; 13. First optical fiber; 14. Beam splitter; 15. Inclined mirror; 16. First end face; 17. Pressure-sensitive diaphragm; 18. Substrate; 19. FP cavity; 20. Second optical fiber; 21. Spring beam; 22. Mass block; 23. Comb teeth; 24. Second end face; 25. Top cover plate; 26. Bottom cover plate; 27. Fiber array; 28. Seed layer; 29. ​​Electroplated mask layer; 30. Photoresist; 31. Electroplated grown metal structure layer; 32. Metal structure waveplate; 33. Laser; 34. Polymer waveguide. Detailed Implementation

[0053] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0054] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0055] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0056] Example 1

[0057] This application provides a quantum computing chip. The manufacturing process of the quantum computing chip is described below using the manufacturing process of CNOT quantum gate as an example. However, the application scenarios of this invention are not limited to the example given, and can also be applied to other quantum gates, sensors, and other scenarios.

[0058] Macroscopic geometric optics and silicon-based optoelectronics are two commonly used techniques for realizing optical quantum gates. However, the former is bulky and difficult to apply on a large scale, while the latter is difficult to manufacture. The vertical micromirror technology and integration method described in this invention, compared to macroscopic spatial optics methods which use three-dimensional microelectromechanical systems (MEMS) fabrication technology to manufacture micrometer-sized and nanometer-precision optical devices on silicon wafers, miniaturizes macroscopic optical systems to chip-level dimensions and has the advantage of high integration. Compared to silicon-based optoelectronics methods, the propagation of light in this invention does not rely on silicon waveguides but propagates in the air, resulting in lower transmission loss.

[0059] Beam splitters are crucial components in CNOT gates. According to Fresnel's equations, different reflectance and transmittance ratios can be obtained by adjusting the angle between the incident light and the mirror, resulting in half-beam splitters and third-beam splitters. The beam splitters can be fabricated using vertical single-crystal silicon thin films etched with vertical micromirror technology, or using high-precision 3D printing of photosensitive resins, such as two-photon 3D printing technology. Taking two-photon 3D printing as an example, this additive manufacturing technology utilizes femtosecond lasers and two-photon polymerization reactions for nanoscale precision processing; also known as two-photon grayscale lithography, it can fabricate nanoscale precision optical three-dimensional structures on silicon-based vertical micromirror sidewalls and silicon substrates, such as vertical beam splitters, vertical spherical lenses, vertical polarizers, vertical half-wave plates, vertical metasurface lenses, 45° angled mirrors, gratings, and apertures. To reduce the absorption loss of reflected light by vertical mirrors, antireflective films or metal films can be deposited on the surface of the mirror using a combination of methods such as physical vapor deposition (PVD), thermal evaporation, optical vacuum coating machine, and atomic layer deposition (ALD).

[0060] Since the light emitted from an optical fiber is typically divergent and can be considered a point source, it needs to be collimated by a vertical spherical convex lens to form parallel light before being coupled into the aforementioned beam splitter. The vertical spherical convex lens can be achieved by adjusting the etching and passivation cycle of a deep etching process, or it can be implemented using high-precision 3D printing of photosensitive resin. Figure 1 Figures (a)-(b) show the principle of collimating incident light by fabricating a vertical spherical lens on the sidewall of a silicon-based vertical micromirror using two-photon 3D printing technology on a silicon-based substrate. Since the silicon-based vertical micromirror also reflects incident light, causing losses, antireflection films can be deposited on the surface of the silicon-based vertical micromirror using a combination of methods such as optical vacuum coating machines, ALD, and chemical vapor deposition (CVD) to reduce these losses. Figure 1 Figures (c)-(d) show the schematic diagrams of a beam splitter based on vertical micromirror technology. Figure 2 Figure (a) shows the schematic diagram of a two-bit quantum logic gate. Figure 2 Images (b)-(c) in the image are of a beam splitter and a CNOT quantum gate chip based on vertical micromirror technology, respectively.

[0061] Taking CNOT quantum gates as an example, such as Figure 3 As shown, the manufacturing process of a quantum computing chip includes the following steps:

[0062] S11: Deeply etch a vertical structure onto a single-crystal silicon wafer;

[0063] Specifically, for CNOT quantum gates, on a single-crystal silicon wafer 1 ( Figure 3 The upper surface of (a) is etched with a depth greater than 100 micrometers, a verticality better than 90°±0.3°, and an initial sidewall roughness better than 50 nanometers by a deep etching process.

[0064] S12: Smooth the sidewalls of the vertical structure, including but not limited to high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle of etching and protection processes, gas cluster ion beam etching, etc.

[0065] As an embodiment of the present invention, it is preferable to use a solution of less than 5 wt.% low-concentration potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), 10 wt.% to 30 wt.% isopropanol, and deionized water to etch the above-mentioned deep-etched silicon vias, which can yield a vertical micromirror 2 with a sidewall roughness of less than 5 nm. Figure 3 (b)). As another embodiment of the invention, it is preferred to use one or more of the following—sulfur hexafluoride (SF6), argon plasma, oxygen plasma, and xenon difluoride (XeF2)—in one or more steps to perform post-etching on the vertical structure, wherein the gas flow rate should generally be less than 30 sccm. Figure 4 (a) and Figure 4 (b) in the figure is an experimental example of how to effectively smooth the sidewalls of a vertical structure. Figure 4 (a) is an electron microscope image of the sidewall profile before smoothing, with a roughness of about 50 nm, where defects can be observed; Figure 4 (b) is an electron microscope image of the sidewall profile after smoothing by a low-flow dry etching method with a gas flow rate of 15 sccm. The roughness is better than 1 nm and there are no obvious defects. Therefore, it can significantly reduce the loss of light irradiating the sidewall interface of silicon-based optical devices.

[0066] S13: Using optical vacuum coating machines, physical vapor deposition, chemical vapor deposition or atomic layer deposition methods, deposit antireflective coatings, anti-reflective coatings, filter coatings, polarizing coatings or beam-splitting coatings on the sidewall surface of vertical micromirrors;

[0067] In this embodiment, an antireflection film 3 is deposited on the sidewall surface of a portion of the vertical micromirrors using an optical vacuum coating machine. The optical vacuum coating machine allows for real-time monitoring of the optical properties during thin film growth and offers the advantage of high film quality. Atomic layer deposition, on the other hand, offers advantages such as low film growth temperature and good shape retention. In practice, the optical thin film deposition method should be selected based on the structural characteristics and requirements of the optical device. Figure 3 (c) in the middle.

[0068] S14: Using two-photon 3D printing technology, submicron structures are printed on the sidewalls of vertical micromirrors to form spherical lenses, apertures, gratings, polarizers, half-wave plates, superlenses, and optical waveguides.

[0069] Two-photon 3D printing, also known as two-photon lithography or grayscale lithography, uses a near-infrared femtosecond pulsed laser as a light source. Initiator or photosensitizer molecules simultaneously absorb two photons, transitioning from the ground state to an excited state, thereby triggering a polymerization reaction at any focused location, solidifying the liquid resin. Compared to conventional 3D printing technologies, two-photon 3D printing offers higher resolution, enabling the printing of sub-micron 3D optical structures. Compared to conventional lithography techniques such as contact lithography and laser direct writing, two-photon 3D printing can expose and solidify liquid photosensitive resin in three-dimensional space, meeting the need to print three-dimensional optical devices on the sidewalls of silicon vertical structures.

[0070] In this embodiment, based on the structure of the CNOT quantum gate, an anti-reflection film 4 is grown on the sidewall surface of the vertical micromirror to form a reflector. Figure 3 In (d) of the example, a spherical collimating lens 5 is printed on the sidewall surface of a vertical micromirror on which an antireflection coating 3 is partially grown using a two-photon 3D printer. Figure 3 In (e) of the example, a half-wave plate 6 is fabricated using two-photon 3D printing on the sidewall surface of a vertical micromirror on which an antireflection coating 3 is partially grown. Figure 3 (f) in the middle.

[0071] Example 2

[0072] It is important to note that the advantage of using silicon-based beam splitters lies in the ability to fabricate silicon-based vertical micromirror sidewalls with fixed relative positions and angles in a single photolithography and etching process based on microelectronics technology. However, this does not mean that the invention is only applicable to silicon-based device structures and communication bands. The invention is also applicable to scenarios where three-dimensional optical components, such as beam splitters and lenses, are directly manufactured on horizontal substrates using two-photon 3D printing technology. Compared to silicon-based vertical micromirror technology, its advantages lie in its flexible application and wider applicable bands; its disadvantage is that the three-dimensional optical components are manufactured discretely, resulting in lower efficiency. In practical applications, silicon-based vertical micromirror technology and two-photon 3D printing micromirror technology can be combined to meet the needs of different scenarios.

[0073] Figure 5 The diagram shows the process flow for directly manufacturing quantum computing chips using two-photon 3D printing technology. Taking CNOT quantum gates as an example, the manufacturing process includes the following steps:

[0074] S21: Prepare the substrate. The substrate material includes, but is not limited to, silicon, quartz glass, ITO glass, ceramics, organic substrates, etc. In this embodiment, a single-crystal silicon wafer 1 ( Figure 5 The manufacturing steps are explained using (a) as an example.

[0075] S22: A photosensitive resin-based vertical micromirror (which may include a vertically oriented spherical micromirror, a planar lens, or a combination of both) is fabricated on the upper surface of a single-crystal silicon substrate wafer 1 using a two-photon 3D printing method, wherein the spherical collimating lens 5 is used to collimate the incident light. Figure 5 (b) in the middle.

[0076] S23: An antireflective coating 3 is grown on the surfaces of the spherical collimating lens 5 and the planar lens. The preferred growth method for the antireflective coating is ALD or inductively coupled plasma chemical vapor deposition (ICPCVD), because ALD and IPCVD have lower growth temperatures and better shape retention, which can avoid damage to the photosensitive resin-based vertical micromirrors caused by high temperatures during antireflective coating growth. Figure 5 (c) in the middle.

[0077] S24: An anti-reflective coating 4 is grown on the surface of a vertical micromirror to form a reflective mirror. Figure 5 In (d) of the above, the preferred growth method is ALD or ICPCVD.

[0078] S25: A half-wave plate 6 (e) in the figure is fabricated by two-photon 3D printing on the sidewall surface of a vertical micromirror on which an antireflection film 3 is partially grown.

[0079] Example 3

[0080] Because the vertical micromirror technology of this invention achieves transparent silicon-based vertical sidewalls in the communication band, it possesses the capability to function as optical elements in the communication band. Combined with two-photon 3D printing technology, in addition to printing optical elements such as spherical mirrors, it is also possible to fabricate submicron structures of optical elements such as apertures, gratings, polarizers, half-wave plates, superlenses, and optical waveguides on the sidewalls, thereby forming horizontally cascaded optical chips. The sidewall fabrication steps of a wave plate are described here as an example. Figure 6 The diagram shows a cross-sectional view of the fabrication process of waveplates on the sidewall of a silicon-based vertical micromirror.

[0081] S31: On a single-crystal silicon wafer 1 ( Figure 6The upper surface of (a) was etched with a depth greater than 100 micrometers and a verticality better than 90°±0.3° using a deep etching process, and the sidewalls were smoothed to obtain a vertical micromirror 2. Figure 8 (b) in the middle.

[0082] S32: Deposited metal seed layer 28 ( Figure 6 (c) in the middle.

[0083] S33: Using two-photon 3D printing, a submicron-sized photosensitive resin-based electroplated mask layer 29 is printed on the sidewall of the vertical micromirror 2. Figure 6 (d) in the middle.

[0084] S34: First, photoresist 30 is sprayed onto the upper surface of the single-crystal silicon wafer 1 using a spray coating method. Then, the area with the photosensitive resin-based electroplated mask layer 29 is exposed and developed. Figure 6 (e) in the middle.

[0085] S35: Electroplating is performed on the areas of the seed layer 28 that have been exposed and developed but are not covered by the photosensitive resin-based electroplating mask layer 29 to grow a submicron metal structure layer 31. The other areas of the seed layer 28 that are covered by the photosensitive resin-based electroplating mask layer 29 and the photoresist 30 will not be electroplated with the metal structure layer 31. Figure 6 (f) in the middle.

[0086] S36: Remove the photosensitive resin-based electroplated mask layer 29, photoresist 30, and seed layer 28 to obtain the metal structure waveplate 32 on the sidewall of the vertical micromirror 2. Figure 6 (g) in the middle, and can be combined with other optical elements on vertical micromirrors to form a complex optical chip in the horizontal direction.

[0087] Example 4

[0088] Because the vertical micromirror technology of this invention achieves transparent silicon-based vertical sidewalls in the communication band, it enables the use of optical elements in the communication band. Optical elements can be manufactured in a single deep etching process, forming a series optical path within the wafer plane. Based on this, combined with optical vacuum coating technology, antireflective coatings, anti-reflective coatings, filters, polarizing films, and beam splitters can be fabricated on the silicon-based vertical sidewalls, meeting the functional requirements of different optical elements for thin films. Furthermore, by combining it with submicron 3D printing technology, major optical components such as mirrors, cylindrical lenses, spherical lenses, collimators, apertures, gratings, beam splitters, polarizers, half-wave plates, superlenses, and optical waveguides can be fabricated on the silicon-based vertical sidewalls, allowing the integration of macroscopic spatial optical devices onto silicon wafers.

[0089] Therefore, vertical micromirrors use single-crystal silicon wafers as optical element platforms and employ deep etching, sidewall smoothing, optical vacuum coating, and submicron 3D printing technologies in microelectromechanical systems (MEMS) 3D manufacturing processes to fabricate optical elements with different functions on the silicon wafer plane. They also form a complete optical path in the horizontal direction to realize functions such as computing, sensing, and storage, and are compatible with electrical system processes, thus constituting a wafer-level optoelectronic heterogeneous integrated system.

[0090] Therefore, this application also provides a system-on-a-chip, which includes at least the quantum computing chip and integrated circuit chip provided in Embodiment 1. Figure 7 As shown in (a), the integrated circuit chip 7 forms on-chip electrical interconnects through the redistribution layer 8, and achieves electrical interconnection between the upper and lower layers of the chip through the TSV 9, which has a depth greater than the height of the vertical micromirror. It is then assembled and connected to the circuit board 12 with the power control chip 11 via pads 10. Photons are emitted from the first optical fiber 13 and become parallel light after passing through the spherical collimating lens 5. Then, they are split into two beams by the inclined beam splitter 14 based on two-photon 3D printing. One beam is incident horizontally into the upper quantum computing chip; the other beam shines downwards onto the inclined reflector 15, which is manufactured based on two-photon 3D printing and has an anti-reflection coating deposited on its surface. The reflected beam becomes horizontal light and is then incident into the lower quantum computing chip. The upper and lower quantum computing chips can operate independently. The calculation results are converted into electrical signals after passing through a single-photon detector, enabling collaborative operation with the integrated circuit chip 7.

[0091] Figure 7 Image (b) shows another embodiment of the Co-Packaged Optics (CPO) on-chip system of the present invention. Compared to Figure 7 The image (a) shows an optoelectronic co-packaging architecture in which the laser source is placed outside the on-chip system and coupled into the system by the first optical fiber 13. Figure 7 The architecture shown in (b) integrates the laser 33 directly onto the on-chip system and uses two-photon 3D printing to fabricate a polymer waveguide 34 for photonic wire bonding (PWB), realizing direct optical interconnection between the laser and the optical device interface on the on-chip system.

[0092] In specific implementations, the on-chip system may further include, for example: Figure 8 The sensor chip shown is manufactured in the same way as in Example 1 or Example 2.

[0093] Figure 8 (a)- Figure 8Figure (b) shows a top view and a cross-sectional view of the FP pressure sensor chip. The first end face 16 and the pressure-sensitive diaphragm 17 of the FP pressure sensor are implemented using the vertical deep etching technique and sidewall smoothing technique described in Example 1. The first end face 16 and the pressure-sensitive diaphragm 17 are vacuum-bonded to the substrate 18 to form a vacuum FP cavity 19. The end face of the second optical fiber 20 is coupled to the first end face 16 of the FP pressure sensor and cured by adhesive dispensing. When the external pressure changes, the pressure-sensitive diaphragm 17 deforms, causing a change in the cavity length of the FP cavity 19. Therefore, the corresponding pressure value can be obtained by detecting the change in the FP cavity length.

[0094] Figure 8 (c)- Figure 8 Figure (d) shows a top view and a cross-sectional view of the triaxial photoelectric dual-readout accelerometer chip. The triaxial photoelectric dual-readout accelerometer chip includes a mass block 22, a spring beam 21, comb teeth 23, an upper cover plate 25, a lower cover plate 26, and a second end face 24. The spring beam 21 is used to keep the mass block 22 suspended between the upper cover plate 25 and the lower cover plate 26. Electrical readout in the XY direction is achieved by a parallel plate capacitor formed by the comb teeth 23, and electrical readout in the Z-axis direction is achieved by a parallel plate capacitor formed by the mass block 22, the upper cover plate 25, and the lower cover plate 26. Since the manufacturing of the accelerometer chip uses both the vertical deep etching technique and the sidewall smoothing technique described in Example 1, the sidewalls of the second end face 24 and the comb teeth 23 form FP cavities. When subjected to acceleration in the XY direction, the cavity length of the FP cavity changes. Simultaneously, the mass block 22, the upper cover plate 25, and the lower cover plate 26 also form FP cavities, and when subjected to acceleration in the Z direction, the cavity length of the FP cavity changes. Therefore, the corresponding acceleration value can be obtained by detecting the change in the FP cavity length.

[0095] If a single optical fiber is replaced with an optical fiber array, a photoelectric dual-readout gyroscope can be fabricated to perform photoelectric dual-readout measurements of angular acceleration. For optical measurement methods... Figure 8 Figures (e)-(f) illustrate the principle of measuring angular acceleration using fiber array 27. Figure 8 As shown in (e), when there is no external angular acceleration, each fiber in the fiber array 27, together with the second end face 24 and the comb teeth 23, constitutes an FP cavity sensor, and the FP cavity length is the spacing H0. Figure 8As shown in (f), when there is a small angular acceleration ω from the outside, the comb array twists under the influence of the mass block 22. The cavity length of the FP cavity formed by each fiber in the fiber array 27, the second end face 24, and the comb 23 changes to H1, H2, H3... respectively due to the twisting of the comb angle. Generally, H1 > H2 > H3... By detecting the FP cavity lengths H1, H2, H3..., a fitted straight line L1 can be obtained. Then, the angle θ between the straight line L2 parallel to the straight line L1 and the straight line L3 containing the second end face 24 can be calculated. By differentiating the angle θ, the corresponding angular acceleration ω can be calculated.

[0096] In electrical measurement methods, when there is an external angular acceleration ω2, the comb array twists under the influence of the mass block 22. This causes changes in the spacing and plate area of ​​the parallel plate capacitor formed by the comb teeth 23, resulting in a change in capacitance. Therefore, the angular acceleration ω2 can be measured by measuring the capacitance of the parallel plate capacitor formed by the comb teeth 23.

[0097] In the aforementioned photoelectric dual-readout measurement method, the optical measurement method has advantages such as high precision, high sensitivity, and strong anti-interference capability; while the electrical measurement method has advantages such as large measurement range, small packaging size, and low cost. The two methods can work independently or in conjunction.

[0098] Example 5

[0099] In wafer-level VLSI design, software-defined methods for optimizing physical topology, logical topology, and node architecture performance can establish domain-specific on-chip system simulators. Using these simulators to optimize on-chip system data exchange mechanisms, obstacle avoidance algorithms, and resource scheduling enables the construction of multi-type, multi-layered, flexible, and reliable logical topologies, improving the switching throughput of on-chip interconnect networks in domain-specific scenarios and reducing hop count and switching latency. However, these simulators are typically based on ideal silicon wafer interposers. In reality, silicon wafer interposers manufactured using microelectronic processes often have certain process defects, inevitably introducing parasitic parameters and latency issues. This results in a mismatch between the design results obtained from the silicon on-chip system simulator and the test results of the actual system. Therefore, it is urgent to optimize the manufacturing process of silicon wafer interposers in on-chip systems and extract key electrical parameters from silicon wafer interposers manufactured using actual processes, thereby correcting the on-chip system simulator.

[0100] The TSV (Transmission Vias) of a silicon wafer interposer is typically obtained by etching deep holes and filling them with copper pillars on a silicon wafer substrate using Bosch's process. An ideal TSV should have smooth sidewalls, uniform metal filling, and a depth typically exceeding tens of micrometers, serving as the electrical interconnect channel between the bottom power supply unit module and the top integrated circuit chip. However, in actual etching, because the Bosch process uses isotropic etching of silicon with fluorine-based active groups followed by sidewall passivation, alternating etching and protection processes, scalloping defects are formed on the etched edge surfaces, such as… Figure 4 Image (a) shows a scanning electron microscope (SEM) image of a scalloped defect on the sidewall of a deeply etched through-silicon via. Scalloped tips are typically areas of concentrated thermal stress and electric field distribution, which can easily lead to a decrease in the reliability of electrical interconnects, as well as crosstalk, signal loss, and delay.

[0101] Figure 9 The flowchart shown is a process for correcting the on-chip system simulator of the present invention. Figure 9 As shown, the method includes:

[0102] S41: Deeply etch through-silicon vias onto the silicon wafer adapter.

[0103] S42: The sidewalls of the aforementioned through-silicon vias (TSVs) are smoothed using methods including, but not limited to, high-temperature annealing, low-flow dry etching, reducing the alternation cycle between etching and protection processes, and low-concentration wet chemical etching. As an embodiment of the present invention, it is preferable to use a solution of less than 5 wt.% low-concentration potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), 10 wt.% to 30 wt.% isopropanol, and deionized water to etch the aforementioned deep-etched TSVs, which can yield TSVs with a sidewall roughness of less than 5 nm. Figure 4 (b) shows a scanning electron microscope image after the sidewalls have been smoothed. The scallop-shaped defects have been almost completely removed, which can greatly improve the signal quality. Also, since there is no light scattering or loss problem after the removal of the scallop-shaped defects, it has the ability to be used as an optical element in the communication band.

[0104] S43: A single-mode fiber is coupled into the smoothed sidewall of the via-silicon aperture (TSA) using an optical fiber. A laser in the communication band is used as the light source, and the light source, power meter, and single-mode fiber are connected through a circulator to obtain the FP interference spectrum. With a fixed cavity length in the FP cavity, if the sidewall roughness is high, the interference effect is weak due to scattering and loss of light caused by the scalloped defects; conversely, if the sidewall roughness is low, there is no scattering or loss of light, and the interference effect is strong. Figure 9 (b) in the diagram can establish the correspondence between the FP interferometric spectrum and the sidewall roughness of the through-silicon via. Furthermore, based on the FP interferometric measurement results, a simulation model of the silicon wafer adapter board considering process deviations can be established.

[0105] S44: Actual testing of TSV silicon wafer adapters with different sidewall roughness was conducted to extract electrical parameters and to verify and correct the above silicon wafer adapter simulation model.

[0106] S45: Based on the silicon interposer simulation model considering process deviations mentioned above, the losses, parasitic parameters, stress reliability, etc. of the ideal on-chip system simulator are corrected.

[0107] In summary, as Figure 10 and Figure 11 As shown, this application proposes vertical deep etching technology and sidewall smoothing technology, and combines them with two-photon 3D printing technology and optical vacuum coating technology to prepare quantum computing chips. These chips are then combined with integrated circuit chips and sensor chips to form an optoelectronic integrated on-chip system. Based on the vertical deep etching technology and sidewall smoothing technology, the simulator of the on-chip system is modified. The on-chip system simulator can further optimize the software of the on-chip system.

[0108] The above provides a detailed description of the on-chip system simulator correction method and quantum computing chip based on vertical micromirrors provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A quantum computing chip, comprising: The quantum computing chip comprises a plurality of quantum gates, and the quantum gates are manufactured by the following process: Deeply etching a vertical structure on a single crystal silicon wafer; Performing side wall smoothing on the vertical structure to form a vertical micro-mirror, and the side wall smoothing method comprises but is not limited to high-temperature annealing, low-flow dry etching, reducing the alternating period of etching and protection process, low-concentration wet chemical etching, and gas cluster ion beam etching; Depositing one or more of a reflection-increasing film, a transparent film, a light filtering film, a polarizing film, and a light splitting film on the side wall surface of the vertical micro-mirror by using an optical vacuum coating machine, physical vapor deposition, chemical vapor deposition, or atomic layer deposition; Printing sub-micron structures on the side wall of the vertical micro-mirror by using a two-photon 3D printer to form one or more of a spherical lens, a diaphragm, a grating, a polarizer, a half-wave plate, a superlens, and an optical waveguide.

2. The quantum computing chip of claim 1, wherein, The low-flow dry etching specifically comprises: Performing post-etching on the vertical structure by using one or more of sulfur hexafluoride, argon plasma, oxygen plasma, and xenon difluoride with a low flow rate of less than 30 sccm.

3. The quantum computing chip of claim 1, wherein, The low-concentration wet chemical etching specifically comprises: Etching the side wall of the vertical structure by using a solution of less than 5 wt.% of potassium hydroxide or tetramethylammonium hydroxide, 10 wt.% to 30 wt.% of isopropyl alcohol, and deionized water.

4. A quantum computing chip, comprising: The quantum computing chip comprises a plurality of quantum gates, and the quantum gates are manufactured by the following process: Manufacturing a vertical micro-mirror based on photosensitive resin on the upper surface of a substrate by using a two-photon 3D printing method; Growth of one or more of a transparent film, a light filtering film, a polarizing film, and a light splitting film on the surface of the vertical micro-mirror; Printing sub-micron structures on the side wall of the vertical micro-mirror by using a two-photon 3D printer to form one or more of a spherical lens, a diaphragm, a grating, a polarizer, a half-wave plate, a superlens, and an optical waveguide.

5. The quantum computing chip of claim 1 or 4, wherein, The quantum gate further comprises a wave plate, and the wave plate is manufactured by the following process: Depositing a seed layer of metal on a single crystal silicon wafer; Printing a sub-micron-sized electroplating mask layer based on photosensitive resin on the side wall of the vertical micro-mirror by using a two-photon 3D printer; Spraying photoresist on the upper surface of the single crystal silicon wafer by using a glue spraying method, and exposing and developing the area with the electroplating mask layer based on photosensitive resin; Electroplating and growing a sub-micron metal structure layer on the area of the seed layer that is exposed and developed and is not shielded by the electroplating mask layer based on photosensitive resin; Removing the electroplating mask layer based on photosensitive resin, the photoresist, and the seed layer to obtain a metal structure wave plate on the side wall of the vertical micro-mirror.

6. An on-chip system, characterized by comprising: The quantum computing chip and the integrated circuit chip are optically coupled or are photonically wire-bonded by manufacturing a polymer waveguide through two-photon 3D printing, thereby realizing optoelectronic co-packaging.

7. The on-wafer system of claim 6, wherein, The sensing chip further comprises a vertical structure that is subjected to side wall smoothing by high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, gas cluster ion beam etching, or a method of reducing the alternating period of etching and protection process.

8. The on-wafer system of claim 7, wherein, The sensing chip is a triaxial photoelectric double-readout acceleration sensing chip, which comprises a mass block, a spring beam, a comb tooth, an upper cover plate, a lower cover plate and a second end face.

9. The on-wafer system of claim 7, wherein, The sensing chip is a photoelectric double-readout gyroscope, which comprises a fiber array, a mass block, a second end face and a comb tooth.

10. A method of modifying an on-chip system emulator, the method comprising: It comprises: Deep etching of a through silicon via on a silicon wafer adapter plate; Based on any one of high-temperature annealing, low-flow dry etching, reducing the etching and protection process alternation period, low-concentration wet chemical etching, the side wall of the through silicon via is smoothed; A single-mode optical fiber is coupled into the side wall of the through silicon via after the side wall is smoothed, a laser in a communication band is used as a light source, and the light source, a power meter and the single-mode optical fiber are connected through a circulator to obtain an FP interference spectrum, a corresponding relationship between the FP interference spectrum and the roughness of the side wall of the through silicon via is established, and a silicon wafer adapter plate simulation model considering process deviation is established based on the corresponding relationship; Based on silicon wafer adapter plates with different side wall roughnesses, the silicon wafer adapter plate simulation model is corrected; According to the corrected silicon wafer adapter plate simulation model, a system-on-chip simulator in an ideal state is corrected, wherein the system-on-chip simulator is used to simulate the system-on-chip in any one of claims 6-9.

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