Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device, and aims to solve the problem that an active layer is easy to corrode when a metal oxide thin film transistor is prepared by adopting a back channel etching process in the prior art. The array substrate comprises: a substrate; the pixel electrode is located on one side of the substrate and comprises a plurality of sub-pixel electrode parts distributed in the first direction and the second direction, and each sub-pixel electrode part comprises a plurality of first slits; part of the outer edge of at least part of the sub-pixel electrode parts is an opening, and the first direction intersects with the second direction.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] In liquid crystal displays, there is a vertical alignment (VA) mode, in which the long axes of liquid crystal molecules are arranged vertically relative to the surface of the display panel when no power is applied. Compared with other liquid crystal displays, VA mode liquid crystal displays usually have high contrast ratio (CR) and wide viewing angle.

[0003] However, the current VA mode display panels have problems of coarse dark lines and low transmittance. Summary of the invention

[0004] The present invention provides an array substrate, a display panel and a display device to solve the problem that an active layer is easily corroded when a metal oxide thin film transistor is prepared by a back channel etching process in the prior art.

[0005] An embodiment of the present invention provides an array substrate, including:

[0006] substrate;

[0007] The pixel electrode is located on one side of the substrate, and includes a plurality of sub-pixel electrode portions distributed along a first direction and a second direction, wherein the sub-pixel electrode portions include a plurality of first slits; at least a portion of the outer edges of the sub-pixel electrode portions are open, and the first direction intersects with the second direction.

[0008] In a possible implementation manner, there is a gap between at least some adjacent sub-pixel electrode portions.

[0009] In a possible implementation manner, the array substrate further includes: a plurality of gate lines extending along the first direction;

[0010] The pixel electrode comprises: two pixel electrode groups located at different sides of the gate line, namely a first pixel electrode group and a second pixel electrode group; the pixel electrode group comprises a plurality of sub-pixel electrode portions;

[0011] In the same pixel electrode, the opening positions of the two pixel electrode groups in the second direction are the same.

[0012] In a possible implementation, the pixel electrode group includes a first sub-pixel electrode group extending along the second direction and sequentially distributed along the first direction, and a second sub-pixel electrode group;

[0013] The first sub-pixel electrode group includes: a first sub-pixel electrode portion and a second sub-pixel electrode portion sequentially distributed along the second direction; the second sub-pixel electrode group includes: a third sub-pixel electrode portion and a fourth sub-pixel electrode portion sequentially distributed along the second direction;

[0014] An extension direction of the first slit of the first sub-pixel electrode portion is the same as an extension direction of the first slit of the fourth sub-pixel electrode portion; an extension direction of the first slit of the second sub-pixel electrode portion is the same as an extension direction of the first slit of the third sub-pixel electrode portion.

[0015] In a possible implementation manner, in the same pixel electrode group, the first slits of each sub-pixel electrode portion form a plurality of U-shaped patterns that are surrounded in sequence.

[0016] In a possible implementation manner, in the first pixel electrode group, an outer edge of the first sub-pixel electrode portion away from the second sub-pixel electrode portion, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, and an outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion are all openings;

[0017] In the second pixel electrode group, the outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, the outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion, and the outer edge of the fourth sub-pixel electrode portion away from the third sub-pixel electrode portion are all openings.

[0018] In a possible implementation manner, in the first pixel electrode group, an outer edge of the first sub-pixel electrode portion away from the third sub-pixel electrode portion, an outer edge of the third sub-pixel electrode portion away from the fourth sub-pixel electrode portion, and an outer edge of the fourth sub-pixel electrode portion away from the second sub-pixel electrode portion are all openings;

[0019] In the second pixel electrode group, the outer edge of the first sub-pixel electrode portion away from the third sub-pixel electrode portion, the outer edge of the second sub-pixel electrode portion away from the first sub-pixel electrode portion, and the outer edge of the fourth sub-pixel electrode portion away from the second sub-pixel electrode portion are all openings.

[0020] In a possible implementation, in the first pixel electrode group, an outer edge of the first sub-pixel electrode portion close to the second sub-pixel electrode portion, an outer edge of the second sub-pixel electrode portion close to the first sub-pixel electrode portion, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, an outer edge of the third sub-pixel electrode portion away from the first pixel electrode portion, an outer edge of the third sub-pixel electrode portion close to the fourth sub-pixel electrode portion, and an outer edge of the fourth sub-pixel electrode portion close to the third sub-pixel electrode portion are all openings;

[0021] In the second pixel electrode group, the outer edge of the first sub-pixel electrode portion close to the second sub-pixel electrode portion, the outer edge of the second sub-pixel electrode portion close to the first sub-pixel electrode portion, the outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, the outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion, the outer edge of the third sub-pixel electrode portion close to the fourth sub-pixel electrode portion, and the outer edge of the fourth sub-pixel electrode portion close to the third sub-pixel electrode portion are all openings.

[0022] In a possible implementation manner, the first slit in the first sub-pixel electrode portion and the first slit in the second sub-pixel electrode portion are an integrally connected structure;

[0023] The first slit in the third sub-pixel electrode portion is integrally connected with the first slit in the fourth sub-pixel electrode portion.

[0024] In a possible implementation manner, in the first pixel electrode group, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion and an outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion are both openings;

[0025] In the second pixel electrode group, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion and an outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion are both openings;

[0026] In the first pixel electrode group and the second pixel electrode group, a second slit is provided between the first sub-pixel electrode portion and the third sub-pixel electrode portion, and a third slit is provided between the second sub-pixel electrode portion and the fourth sub-pixel electrode portion.

[0027] In a possible implementation, in the first pixel electrode group and the second pixel electrode group, a fourth slit is provided between the first sub-pixel electrode portion and the second sub-pixel electrode portion, and a fifth slit is provided between the third sub-pixel electrode portion and the fourth sub-pixel electrode portion.

[0028] In a possible implementation manner, in the first pixel electrode group, an outer edge of the first sub-pixel electrode portion on a side close to the second sub-pixel electrode portion is an opening.

[0029] In a possible implementation manner, the second slit and the third slit are an integrally connected structure; the fourth slit and the fifth slit are an integrally connected structure.

[0030] In a possible implementation, the array substrate includes: a plurality of data lines extending along the second direction, a plurality of first signal lines, a first common electrode group extending along the first direction, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor; wherein the first common electrode group includes: a first common wiring and a second common wiring located on both sides of the gate line;

[0031] The control electrode of the first transistor is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first pixel electrode group;

[0032] The control electrode of the second transistor is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the second pixel electrode group;

[0033] The control electrode of the third transistor is electrically connected to the gate line, the first electrode is electrically connected to the second electrode of the second transistor, and the second electrode is electrically connected to the first signal line.

[0034] In a possible implementation manner, the array substrate further includes: a first electrode of a transistor electrically connected to the data line, a first electrode block, a second electrode block, a first common electrode portion connected to the first common wiring, and a second common electrode portion connected to the second common wiring;

[0035] The orthographic projections of the first electrode block and the second electrode block on the substrate are respectively located on different sides of the orthographic projection of the gate line on the substrate; the first electrode block comprises: a first electrode body, and a first electrode extension portion extending from the first electrode body toward one side of the gate line; the second electrode block comprises: a second electrode body, and a second electrode extension portion extending from the second electrode body toward one side of the gate line;

[0036] The orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the gate line on the substrate have an overlapping area, forming the first electrode of the first transistor and the first electrode of the second transistor;

[0037] The orthographic projection of the first electrode extension on the substrate and the orthographic projection of the gate line on the substrate have an overlapping area, forming a second electrode of the first transistor;

[0038] The orthographic projection of the second electrode extension on the substrate and the orthographic projection of the gate line on the substrate have an overlapping area, forming a second electrode of the second transistor;

[0039] The orthographic projection of the first electrode body on the substrate has an overlapping area with the orthographic projection of the first common electrode portion on the substrate, forming the first capacitor;

[0040] The orthographic projection of the second electrode body on the substrate has an overlapping area with the orthographic projection of the second common electrode portion on the substrate, thereby forming the second capacitor.

[0041] An embodiment of the present invention further provides a display panel, comprising the array substrate provided in the embodiment of the present invention, and further comprising an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0042] An embodiment of the present invention further provides a display device, comprising the display panel provided by the embodiment of the present invention.

[0043] The beneficial effects of the embodiments of the present invention are as follows: the pixel electrode of the array substrate of the embodiments of the present invention includes a plurality of sub-pixel electrode portions distributed along the first direction and the second direction, and the sub-pixel electrode portions include a plurality of first slits; at least part of the outer edges of some of the sub-pixel electrode portions are openings, that is, at least part of the outer edges of some of the sub-pixel electrode portions are openings, and part of the outer edges are closed. By differentially designing the outer edges of the sub-pixel electrode portions, the transmittance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1A One of the schematic diagrams of an array substrate provided by an embodiment of the present invention;

[0045] Figure 1B for Figure 1A Schematic diagram of a single film layer of the pixel electrode layer;

[0046] Figure 1C for Figure 1B Unnumbered schematic diagrams;

[0047] Figure 2A A second schematic diagram of an array substrate provided in an embodiment of the present invention;

[0048] Figure 2B for Figure 2A Schematic diagram of a single film layer of the pixel electrode layer;

[0049] Figure 2C for Figure 2B Unnumbered schematic diagrams;

[0050] Figure 3A A third schematic diagram of an array substrate provided in an embodiment of the present invention;

[0051] Figure 3B for Figure 3A Schematic diagram of a single film layer of the pixel electrode layer;

[0052] Figure 3C for Figure 3B Unnumbered schematic diagrams;

[0053] Figure 4A A fourth schematic diagram of an array substrate provided in an embodiment of the present invention;

[0054] Figure 4B for Figure 4A Schematic diagram of a single film layer of the pixel electrode layer;

[0055] Figure 4C for Figure 4B Unnumbered schematic diagrams;

[0056] Figure 5A A fifth schematic diagram of an array substrate provided in an embodiment of the present invention;

[0057] Figure 5B for Figure 5A Schematic diagram of a single film layer of the pixel electrode layer;

[0058] Figure 5C for Figure 5B Unnumbered schematic diagrams;

[0059] Fig. 6A A sixth schematic diagram of an array substrate provided in an embodiment of the present invention;

[0060] Figure 6B for Fig. 6A Schematic diagram of a single film layer of the pixel electrode layer;

[0061] Figure 6C for Figure 6B Unnumbered schematic diagrams;

[0062] Fig. 7A A seventh schematic diagram of an array substrate provided in an embodiment of the present invention;

[0063] Figure 7B Can be Fig. 7A Schematic diagram of a single film layer where the middle grid line 3 is located;

[0064] Figure 7C Can be Fig. 7A Schematic diagram of a single film layer of the active layer 8;

[0065] Fig.7D Can be Fig. 7A Schematic diagram of a single film layer of a pixel electrode;

[0066] Fig. 7E Can be Fig. 7A Schematic diagram of the via hole;

[0067] Figure 7F Can be Fig. 7A Schematic diagram of a single film layer of the data line layer;

[0068] Figure 8 A schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0069] Fig. 9 A schematic diagram of dark pixel patterns provided by an embodiment of the present invention;

[0070] Fig.10 A schematic diagram of transmittance corresponding to different embodiments provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0072] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0073] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0074] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0075] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0076] In order to achieve a wide viewing angle, in a VA mode display panel, a pixel has sub-regions or domains with different liquid crystal molecule orientation directions. Different domains have different liquid crystal orientations, and it is necessary to provide the liquid crystal molecules with pre-tilt angles in various predetermined directions.

[0077] See also Figure 1A-Figure 1C , Figure 2A-2C , Figure 3A-3C , Figure 4A-4C and Figure 5A-5C As shown, Figure 1B for Figure 1A Schematic diagram of a single film layer of a pixel electrode. Figure 1C for Figure 1B Unnumbered schematic diagram, Figure 2B for Figure 2A Schematic diagram of a single film layer of a pixel electrode. Figure 2C for Figure 2B Unnumbered schematic diagram, Figure 3B for Figure 3A Schematic diagram of a single film layer of a pixel electrode. Figure 3C for Figure 3B Unnumbered schematic diagram, Figure 4B for Figure 4A Schematic diagram of a single film layer of a pixel electrode. Figure 4C for Figure 4B Unnumbered schematic diagram, Figure 5B for Figure 5A Schematic diagram of a single film layer of a pixel electrode. Figure 5C for Figure 5B In the schematic diagram without adding reference numerals, an embodiment of the present invention provides an array substrate, including:

[0078] Substrate 1;

[0079] The pixel electrode 2 is located on one side of the substrate 1, and includes a plurality of sub-pixel electrode portions P distributed along the first direction X and the second direction Y, and the sub-pixel electrode portion P includes a plurality of first slits S1; at least a portion of the outer edges of some of the sub-pixel electrode portions P are open, and the first direction X intersects with the second direction Y. Specifically, the first direction X and the second direction Y may be perpendicular to each other. Specifically, at least a portion of the outer edges of some of the sub-pixel electrode portions P are open, and the remaining outer edges of the sub-pixel electrode portions P with the open outer edges may be closed; specifically, the outer edges of some of the sub-pixel electrode portions P may be open, or the outer edges of all of the sub-pixel electrode portions P may be open.

[0080] In an embodiment of the present invention, the pixel electrode 2 of the array substrate includes a plurality of sub-pixel electrode portions P distributed along a first direction X and a second direction Y, and the sub-pixel electrode portions P include a plurality of first slits S1; at least a portion of the outer edges of some of the sub-pixel electrode portions P are openings, that is, at least a portion of the outer edges of some of the sub-pixel electrode portions P are openings, and a portion of the outer edges are closed. By differentially designing the outer edges of the sub-pixel electrode portions P, the width of the peripheral dark lines can be improved, thereby achieving an improvement in transmittance.

[0081] It should be noted that when each sub-pixel electrode portion has a plurality of branch electrodes and a first slit located between adjacent branches, the outer edge of the sub-pixel electrode portion being open can be understood as the ends of the branch electrodes being not connected to each other, the ends of the first slits being not connected to each other, and the outer edge of the sub-pixel electrode portion being closed can be understood as the ends of the branch electrodes being connected to each other. Figure 1B As shown, the left edge of the second sub-pixel electrode portion P2 in the second pixel electrode group PZ2 is open, and in the second sub-pixel electrode portion P2, the ends of each dark-filled strip-shaped branch electrode toward the left edge are not connected to each other; the lower side edge of the second sub-pixel electrode portion P2 in the second pixel electrode group PZ2 is closed, and in the second sub-pixel electrode portion P2, the ends of each dark-filled strip-shaped branch electrode toward the lower side edge are connected to each other.

[0082] In one possible implementation, see Figure 1A-Figure 1C , Figure 2A-2C , Figure 3A-3C , Figure 4A-4C and Figure 5A-5C As shown, the array substrate also includes: a plurality of gate lines 3 extending along a first direction X; the pixel electrode 2 includes: two pixel electrode groups PZ located on different sides of the gate line 3, namely a first pixel electrode group PZ1 and a second pixel electrode group PZ2; the pixel electrode group PZ includes a plurality of sub-pixel electrode portions P.

[0083] For details, see Figure 1A-Figure 1C , Figure 2A-2C , Figure 3A-3C , Figure 4A-4C and Figure 5A-5C As shown, the pixel electrode group PZ includes a first sub-pixel electrode group PZ11 extending along the second direction Y and distributed in sequence along the first direction X, and a second sub-pixel electrode group PZ12; the first sub-pixel electrode group PZ11 includes: a first sub-pixel electrode portion P1 and a second sub-pixel electrode portion P2 distributed in sequence along the second direction Y; the second sub-pixel electrode group PZ12 includes: a third sub-pixel electrode portion P3 and a fourth sub-pixel electrode portion P4 distributed in sequence along the second direction Y.

[0084] In one possible implementation, see Figure 1A-Figure 1C , Figure 2A-2C , Figure 3A-3C , Figure 4A-4C and Figure 5A-5C As shown, in the same pixel electrode 2, the opening positions of the two pixel electrode groups PZ in the second direction Y are the same. Figure 1B as well as Figure 1C As shown, in the second sub-pixel electrode portions of the first pixel electrode group PZ1 and the second pixel electrode group PZ2, openings are set at the left edge of the second sub-pixel electrode portion P2 and the right edge of the third sub-pixel electrode portion P3.

[0085] In one possible implementation, see Figure 1A-Figure 1C , Figure 2A-2C , Figure 3A-3C , Figure 4A-4C and Figure 5A-5C As shown, the extension direction of the first slit S1 of the first sub-pixel electrode portion P1 is the same as the extension direction of the first slit S1 of the fourth sub-pixel electrode portion P4; the extension direction of the first slit S1 of the second sub-pixel electrode portion P2 is the same as the extension direction of the first slit S1 of the third sub-pixel electrode portion P3. Specifically, the angles formed by the extension directions of the first slit S1 of the first sub-pixel electrode portion P1 and the first slit S1 of the fourth sub-pixel electrode portion P4 and the first direction X may both be 45°; the angles formed by the extension directions of the first slit S1 of the second sub-pixel electrode portion P2 and the first slit S1 of the third sub-pixel electrode portion P3 and the first direction X may both be -45°. Specifically, in the same pixel electrode group PZ, the first slits S1 of each sub-pixel electrode portion P form a plurality of U-shaped patterns that are surrounded in sequence.

[0086] In the embodiment of the present invention, the pixel electrode 2 includes: two pixel electrode groups PZ, the pixel electrode group PZ includes: a first sub-pixel electrode group PZ11, and a second sub-pixel electrode group PZ12; the first sub-pixel electrode group PZ11 includes: a first sub-pixel electrode portion P1 and a second sub-pixel electrode portion P2 sequentially distributed along the second direction Y; the second sub-pixel electrode group PZ12 includes: a third sub-pixel electrode portion P3 and a fourth sub-pixel electrode portion P4 sequentially distributed along the second direction Y, and in the same pixel electrode group PZ, the first narrow portion of each sub-pixel electrode portion P The slit S1 forms a plurality of U-shaped patterns surrounded in sequence, that is, different sub-pixel electrode portions have different first slit S1 directions, providing pre-tilt angles in different predetermined directions for the liquid crystal molecules in the areas where different sub-pixel electrode portions are located. Different first slit S1 directions will produce different electric fields, and different electric fields can better control the orientation of the liquid crystal molecules, reduce disordered liquid crystal molecules, and further refine the dark lines. That is, the pixel electrode design structure provided in the embodiment of the present invention can better control the orientation of the liquid crystal molecules, reduce disordered liquid crystal molecules, and refine the dark lines, thereby improving the transmittance.

[0087] In one possible implementation, see Figure 4A-4C and Figure 5A-5C As shown, there is a gap between at least some adjacent sub-pixel electrode portions P. Specifically, for example, Figure 4B and Figure 4C In the embodiment, there is a gap between the first sub-pixel electrode portion P1 and the third sub-pixel electrode portion P3; and there is a gap between the second sub-pixel electrode portion P2 and the fourth sub-pixel electrode portion P4.

[0088] In one possible implementation, see Figure 1B-Figure 1CAs shown, in the first pixel electrode group PZ11, the outer edge of the first sub-pixel electrode portion P1 away from the second sub-pixel electrode portion P2 (that is, the upper edge of the first sub-pixel electrode portion P1), the outer edge of the second sub-pixel electrode portion P2 away from the fourth sub-pixel electrode portion P4 (that is, the left edge of the second sub-pixel electrode portion P2), and the outer edge of the third sub-pixel electrode portion P3 away from the first sub-pixel electrode portion P1 (that is, the right edge of the third sub-pixel electrode portion P3) are all open, and in the first pixel electrode group PZ11, the remaining outer edges can be closed. Opening; in the second pixel electrode group PZ12, the outer edge of the second sub-pixel electrode portion P2 away from the fourth sub-pixel electrode portion P4 (that is, the left edge of the second sub-pixel electrode portion P2), the outer edge of the third sub-pixel electrode portion P3 away from the first sub-pixel electrode portion P1 (that is, the right edge of the third sub-pixel electrode portion P3), and the outer edge of the fourth sub-pixel electrode portion P4 away from the third sub-pixel electrode portion P2 (that is, the lower edge of the fourth sub-pixel electrode portion P4) are all openings. In the second pixel electrode group PZ12, the remaining outer edges can be closed. Combined Fig. 9 As shown, it is a dark pattern corresponding to a conventional pixel electrode. In the embodiment of the present invention, the transmittance of the display panel is improved by making a closed design at the position corresponding to the dark pattern around the pixel electrode and making an open design at the non-dark pattern position.

[0089] In one possible implementation, see Figure 2B-2C As shown, in the first pixel electrode group PZ11, the first sub-pixel electrode portion P1 is away from the outer edge of the third sub-pixel electrode portion P3 (that is, the left edge of the first sub-pixel electrode portion P1), the third sub-pixel electrode portion P3 is away from the outer edge of the fourth sub-pixel electrode portion P4 (that is, the upper edge of the third sub-pixel electrode portion P3), and the fourth sub-pixel electrode portion P4 is away from the outer edge of the second sub-pixel electrode portion P2 (that is, the upper edge of the fourth sub-pixel electrode portion P3). 4) are all open, and in the first pixel electrode group PZ11, the remaining outer edges can be closed; in the second pixel electrode group PZ12, the outer edge of the first sub-pixel electrode part P1 away from the third sub-pixel electrode part P3 (that is, the left edge of the first sub-pixel electrode part P1), the outer edge of the second sub-pixel electrode part P2 away from the first sub-pixel electrode part P1 (that is, the lower edge of the second sub-pixel electrode part P2), and the outer edge of the fourth sub-pixel electrode part P4 away from the second sub-pixel electrode part P2 (that is, the right edge of the fourth sub-pixel electrode part P4) are all open, and in the second pixel electrode group PZ12, the remaining outer edges can be closed. In the embodiment of the present invention, the transmittance of the display panel is improved by designing the pixel electrode and the position corresponding to the dark lines around it as an opening, and the position without dark lines as a closed design.

[0090] In one possible implementation, see Figure 3B-Figure 3CAs shown, in the first pixel electrode group PZ12, the outer edge of the first sub-pixel electrode portion P1 close to the second sub-pixel electrode portion P2 (that is, the lower edge of the first sub-pixel electrode portion P1), the outer edge of the second sub-pixel electrode portion P2 close to the first sub-pixel electrode portion P1 (that is, the upper edge of the second sub-pixel electrode portion P2), the outer edge of the second sub-pixel electrode portion P2 away from the fourth sub-pixel electrode portion P4 (that is, the left edge of the second sub-pixel electrode portion P2), the outer edge of the third sub-pixel electrode portion P3 away from the first sub-pixel electrode portion P1 (that is, the right edge of the third sub-pixel electrode portion P3), the outer edge of the third sub-pixel electrode portion P3 close to the fourth sub-pixel electrode portion P4 (that is, the lower edge of the third sub-pixel electrode portion P3), and the outer edge of the fourth sub-pixel electrode portion P4 close to the third sub-pixel electrode portion P3 (that is, the upper edge of the fourth sub-pixel electrode portion P3) are all openings, and in the first pixel electrode group PZ11, the remaining outer edges can be closed. Opening; in the second pixel electrode group PZ12, the outer edge of the first sub-pixel electrode portion P1 close to the second sub-pixel electrode portion P2 (that is, the lower edge of the first sub-pixel electrode portion P1), the outer edge of the second sub-pixel electrode portion P2 close to the first sub-pixel electrode portion P1 (that is, the upper edge of the second sub-pixel electrode portion P2), the outer edge of the second sub-pixel electrode portion P2 away from the fourth sub-pixel electrode portion P4 (that is, the left edge of the second sub-pixel electrode portion P2), the outer edge of the third sub-pixel electrode portion P3 away from the first sub-pixel electrode portion P1 (that is, the right edge of the third sub-pixel electrode portion P3), the outer edge of the third sub-pixel electrode portion P3 close to the fourth sub-pixel electrode portion P4 (that is, the upper edge of the third sub-pixel electrode portion P3), and the outer edge of the fourth sub-pixel electrode portion P4 close to the third sub-pixel electrode portion P3 (that is, the upper edge of the fourth sub-pixel electrode portion P4) are all openings, and in the second pixel electrode group PZ12, the remaining outer edges can be closed. In the embodiment of the present invention, the transmittance of the display panel is improved by designing openings at the positions corresponding to the non-dark lines around the pixel electrode and disconnecting the positions corresponding to the central horizontal dark lines.

[0091] In one possible implementation, see Figure 3B-Figure 3C As shown, the first slit S1 in the first sub-pixel electrode portion P1 is connected to the first slit S2 in the second sub-pixel electrode portion P2 as an integral structure; the first slit S1 in the third sub-pixel electrode portion P3 is connected to the first slit S1 in the fourth sub-pixel electrode portion P4 as an integral structure.

[0092] In one possible implementation, see Figure 4B-4CAs shown, in the first pixel electrode group PZ11, the outer edge of the second sub-pixel electrode portion P2 away from the fourth sub-pixel electrode portion P4 (that is, the left edge of the second sub-pixel electrode portion P2) and the outer edge of the third sub-pixel electrode portion P3 away from the first sub-pixel electrode portion P1 (that is, the right edge of the third sub-pixel electrode portion P3) are both open, and in the first pixel electrode group PZ11, the remaining outer edges can be closed; in the second pixel electrode group PZ12, the outer edge of the second sub-pixel electrode portion P2 away from the fourth sub-pixel electrode portion P4 (that is, the right edge of the third sub-pixel electrode portion P3) are both open. The left edge of the second sub-pixel electrode portion P2 and the outer edge of the third sub-pixel electrode portion P3 away from the first sub-pixel electrode portion P1 (i.e., the right edge of the third sub-pixel electrode portion P3) are both open, and in the second pixel electrode group PZ12, the remaining outer edges can be closed; and in the first pixel electrode group PZ11 and the second pixel electrode group PZ12, there is a second slit S2 between the first sub-pixel electrode portion P1 and the third sub-pixel electrode portion P3, and there is a third slit S3 between the second sub-pixel electrode portion P2 and the fourth sub-pixel electrode portion P4. In the embodiment of the present invention, the transmittance of the display panel is improved by designing the opening of the portion corresponding to the non-dark lines around the pixel electrode and disconnecting the portion corresponding to the central vertical dark lines.

[0093] In one possible implementation, see Figure 5B-Figure 5C As shown, in the first pixel electrode group PZ11 and the second pixel electrode group PZ12, there is a fourth slit S4 between the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2, and there is a fifth slit S5 between the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4. In the embodiment of the present invention, the transmittance of the display panel is improved by designing openings at the positions corresponding to the non-dark lines around the pixel electrode and disconnecting the positions corresponding to the horizontal and vertical dark lines at the center.

[0094] In one possible implementation, see Figure 5B-Figure 5C As shown, in the first pixel electrode group PZ11, the outer edge of the first sub-pixel electrode portion P1 close to the second sub-pixel electrode portion P2 is an opening. In the embodiment of the present invention, there is a second slit S2 between the first sub-pixel electrode portion P1 and the third sub-pixel electrode portion P3, a third slit S3 between the second sub-pixel electrode portion P2 and the fourth sub-pixel electrode portion P4, a fourth slit S4 between the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2, a fifth slit S5 between the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4, and the outer edge of the first sub-pixel electrode portion P1 close to the second sub-pixel electrode portion P2 is an opening, which can optimize the starting point of the dark lines, thereby improving the horizontal dark lines at the center of the pixel.

[0095] In one possible implementation, see Figure 4B-4C and Figure 5B-Figure 5C As shown, the second slit S2 and the third slit S3 are an integrally connected structure; the fourth slit S4 and the fifth slit S5 are an integrally connected structure.

[0096] In one possible implementation, see Fig. 6A Figure 4C As shown, the outer edges of the first sub-pixel electrode portion P1 , the second sub-pixel electrode portion P2 , the third sub-pixel electrode portion P3 , and the fourth sub-pixel electrode portion P4 may be closed to improve transmittance.

[0097] Specifically, by testing the transmittance of each structure provided in the embodiment of the present invention, the transmittance improvement level of the optimized embodiment is shown in detail. Fig.10 As shown by Fig.10 It can be seen that Figure 3A , Figure 4A and Figure 5A The corresponding array substrate structure has a better effect on improving transmittance.

[0098] See also Figure 1A-Figure 1C , Figure 2A-2C , Figure 3A-3C , Figure 4A-4C , Figure 5A-5C , Figure 6A-6C , Figure 7A-7F and Figure 8As shown, the array substrate may include a plurality of pixel circuits, at least one pixel circuit includes: a plurality of data lines extending along the second direction Y, a plurality of first signal lines 5, a first common electrode group 6 extending along the first direction X, a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1 and a second capacitor C2; wherein the first common electrode group 6 includes: a first common wiring 61 and a second common wiring 62 located on both sides of the gate line 3; the control electrode of the first transistor T1 is electrically connected to the gate line 3, the first electrode is electrically connected to the data line 4, and the second electrode is electrically connected to the first pixel electrode group PZ1; the control electrode of the second transistor T2 is electrically connected to the gate line 3, the first electrode is electrically connected to the data line 4, and the second electrode is electrically connected to the second pixel electrode group PZ2; the control electrode of the third transistor T3 is electrically connected to the gate line 3, the first electrode is electrically connected to the second electrode of the second transistor T2, and the second electrode is electrically connected to the first signal line 5. Specifically, the first signal line 5 may be a discharge signal line. Specifically, the array substrate further includes a first liquid crystal capacitor Cpx1 and a second liquid crystal capacitor Cpx2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first pixel electrode group PZ1 and the common electrode, and the second liquid crystal capacitor Cpx2 can be formed by the second pixel electrode group PZ2 and the common electrode. In the embodiment of the present invention, the first pixel electrode group PZ1 can be electrically connected to the gate line 3 and the data line 4 through the first transistor T1, and the second pixel electrode group PZ2 can be electrically connected to the gate line 3 and the data line 4 through the second transistor T2, wherein the second capacitor C2 is also electrically connected to the third transistor T3, and the second electrode of the third transistor T3 is electrically connected to the first signal line 5, and the capacitance stored in the second capacitor C2 can be released to the first signal line 5 through the third transistor T3, thereby making the brightness of the second pixel electrode group PZ2 lower than the brightness of the first pixel electrode group PZ1, so as to achieve different light and dark pixels in the same pixel electrode 2, and realize the display effect of 8 domains.

[0099] See also Figure 1A-Figure 1C , Figure 2A-2C , Figure 3A-3C , Figure 4A-4C , Figure 5A-5C , Figure 6A-6C , Figure 7A-7F and Figure 8 As shown, Figure 7B Can be Fig. 7A Schematic diagram of a single film layer where the middle grid line 3 is located. Figure 7C Can be Fig. 7A Schematic diagram of a single film layer of the active layer 8, Fig.7D Can be Fig. 7A Schematic diagram of a single film layer of a pixel electrode. Fig. 7E Can be Fig. 7A Schematic diagram of via hole, Figure 7F Can be Fig. 7ASchematic diagram of a single film layer of the data line layer, the array substrate also includes: a transistor first electrode 41 electrically connected to the data line 4, a first electrode block 42, a second electrode block 43, a first common electrode portion 63 connected to the first common wiring 61, and a second common electrode portion 64 connected to the second common wiring 62; the orthographic projections of the first electrode block 42 and the second electrode block 43 on the substrate 1 are respectively located on different sides of the orthographic projection of the gate line 3 on the substrate 1; the first electrode block 42 includes: a first electrode body 421, and a first electrode extension portion 422 extending from the first electrode body 421 toward one side of the gate line 3; the second electrode block 43 includes: a second electrode body 431, and a second electrode extension portion 432 extending from the second electrode body 431 toward one side of the gate line 3; the transistor first electrode 41 The orthographic projection of the substrate 1 and the orthographic projection of the gate line 3 on the substrate 1 have an overlapping area, forming the first electrode of the first transistor T1 and the first electrode of the second transistor T2; the orthographic projection of the first electrode extension portion 422 on the substrate 1 and the orthographic projection of the gate line 3 on the substrate 1 have an overlapping area, forming the second electrode of the first transistor T2; the orthographic projection of the second electrode extension portion 432 on the substrate 1 and the orthographic projection of the gate line 3 on the substrate have an overlapping area, forming the second electrode of the second transistor T2; the orthographic projection of the first electrode body 421 on the substrate 1 and the orthographic projection of the first common electrode portion 63 on the substrate 1 have an overlapping area, forming the first capacitor C1; the orthographic projection of the second electrode body 431 on the substrate 1 and the orthographic projection of the second common electrode portion 64 on the substrate 1 have an overlapping area, forming the second capacitor C2.

[0100] Specifically, the first pixel electrode group PZ1 may be electrically connected to the first electrode body 421 through the first via hole K1 , and the second pixel electrode group PZ2 may be electrically connected to the second electrode body 431 through the second via hole K2 .

[0101] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, including the array substrate provided in the embodiment of the present invention, and also including an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0102] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including a display panel provided by an embodiment of the present invention. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be repeated.

[0103] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0104] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0105] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that: include: substrate; The pixel electrode is located on one side of the substrate, and includes a plurality of sub-pixel electrode portions distributed along a first direction and a second direction, wherein the sub-pixel electrode portions include a plurality of first slits; at least a portion of the outer edges of the sub-pixel electrode portions are open, and the first direction intersects with the second direction.

2. The array substrate according to claim 1, characterized in that: At least some of the adjacent sub-pixel electrode portions have gaps therebetween.

3. The array substrate according to claim 1 or 2, characterized in that: The array substrate further comprises: a plurality of gate lines extending along the first direction; The pixel electrode comprises: two pixel electrode groups located at different sides of the gate line, namely a first pixel electrode group and a second pixel electrode group; the pixel electrode group comprises a plurality of sub-pixel electrode portions; In the same pixel electrode, the opening positions of the two pixel electrode groups in the second direction are the same.

4. The array substrate according to claim 3, characterized in that: The pixel electrode group includes a first sub-pixel electrode group extending along the second direction and sequentially distributed along the first direction, and a second sub-pixel electrode group; The first sub-pixel electrode group includes: a first sub-pixel electrode portion and a second sub-pixel electrode portion sequentially distributed along the second direction; the second sub-pixel electrode group includes: a third sub-pixel electrode portion and a fourth sub-pixel electrode portion sequentially distributed along the second direction; An extension direction of the first slit of the first sub-pixel electrode portion is the same as an extension direction of the first slit of the fourth sub-pixel electrode portion; an extension direction of the first slit of the second sub-pixel electrode portion is the same as an extension direction of the first slit of the third sub-pixel electrode portion.

5. The array substrate according to claim 4, characterized in that: In the same pixel electrode group, the first slits of each sub-pixel electrode portion form a plurality of U-shaped patterns that are surrounded in sequence.

6. The array substrate according to claim 4, characterized in that: In the first pixel electrode group, an outer edge of the first sub-pixel electrode portion away from the second sub-pixel electrode portion, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, and an outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion are all openings; In the second pixel electrode group, the outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, the outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion, and the outer edge of the fourth sub-pixel electrode portion away from the third sub-pixel electrode portion are all openings.

7. The array substrate according to claim 4, characterized in that: In the first pixel electrode group, an outer edge of the first sub-pixel electrode portion away from the third sub-pixel electrode portion, an outer edge of the third sub-pixel electrode portion away from the fourth sub-pixel electrode portion, and an outer edge of the fourth sub-pixel electrode portion away from the second sub-pixel electrode portion are all openings; In the second pixel electrode group, the outer edge of the first sub-pixel electrode portion away from the third sub-pixel electrode portion, the outer edge of the second sub-pixel electrode portion away from the first sub-pixel electrode portion, and the outer edge of the fourth sub-pixel electrode portion away from the second sub-pixel electrode portion are all openings.

8. The array substrate according to claim 4, characterized in that: In the first pixel electrode group, an outer edge of the first sub-pixel electrode portion close to the second sub-pixel electrode portion, an outer edge of the second sub-pixel electrode portion close to the first sub-pixel electrode portion, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, an outer edge of the third sub-pixel electrode portion away from the first pixel electrode portion, an outer edge of the third sub-pixel electrode portion close to the fourth sub-pixel electrode portion, and an outer edge of the fourth sub-pixel electrode portion close to the third pixel electrode portion are all openings; In the second pixel electrode group, the outer edge of the first sub-pixel electrode portion close to the second sub-pixel electrode portion, the outer edge of the second sub-pixel electrode portion close to the first sub-pixel electrode portion, the outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion, the outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion, the outer edge of the third sub-pixel electrode portion close to the fourth sub-pixel electrode portion, and the outer edge of the fourth sub-pixel electrode portion close to the third sub-pixel electrode portion are all openings.

9. The array substrate according to claim 8, characterized in that: The first slit in the first sub-pixel electrode portion is connected to the first slit in the second sub-pixel electrode portion in an integrated structure; The first slit in the third sub-pixel electrode portion is connected to the first slit in the fourth sub-pixel electrode portion in an integrated structure.

10. The array substrate according to claim 4, characterized in that: In the first pixel electrode group, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion and an outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion are both openings; In the second pixel electrode group, an outer edge of the second sub-pixel electrode portion away from the fourth sub-pixel electrode portion and an outer edge of the third sub-pixel electrode portion away from the first sub-pixel electrode portion are both openings; In the first pixel electrode group and the second pixel electrode group, a second slit is provided between the first sub-pixel electrode portion and the third sub-pixel electrode portion, and a third slit is provided between the second sub-pixel electrode portion and the fourth sub-pixel electrode portion.

11. The array substrate according to claim 10, characterized in that: In the first pixel electrode group and the second pixel electrode group, a fourth slit is provided between the first sub-pixel electrode portion and the second sub-pixel electrode portion, and a fifth slit is provided between the third sub-pixel electrode portion and the fourth sub-pixel electrode portion.

12. The array substrate according to claim 11, characterized in that: In the first pixel electrode group, an outer edge of the first sub-pixel electrode portion on a side close to the second sub-pixel electrode portion is an opening.

13. The array substrate according to claim 11, characterized in that: The second slit and the third slit are an integrally connected structure; the fourth slit and the fifth slit are an integrally connected structure.

14. The array substrate according to claim 3, characterized in that: The array substrate comprises: a plurality of data lines extending along the second direction, a plurality of first signal lines, a first common electrode group extending along the first direction, a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor; wherein the first common electrode group comprises: a first common wiring and a second common wiring located on both sides of the gate line; The control electrode of the first transistor is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first pixel electrode group; The control electrode of the second transistor is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the second pixel electrode group; The control electrode of the third transistor is electrically connected to the gate line, the first electrode is electrically connected to the second electrode of the second transistor, and the second electrode is electrically connected to the first signal line.

15. The array substrate according to claim 14, characterized in that: The array substrate further comprises: a first electrode of a transistor electrically connected to the data line, a first electrode block, a second electrode block, a first common electrode portion connected to the first common wiring, and a second common electrode portion connected to the second common wiring; The orthographic projections of the first electrode block and the second electrode block on the substrate are respectively located on different sides of the orthographic projection of the gate line on the substrate; the first electrode block comprises: a first electrode body, and a first electrode extension portion extending from the first electrode body toward one side of the gate line; the second electrode block comprises: a second electrode body, and a second electrode extension portion extending from the second electrode body toward one side of the gate line; The orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the gate line on the substrate have an overlapping area, forming the first electrode of the first transistor and the first electrode of the second transistor; The orthographic projection of the first electrode extension on the substrate and the orthographic projection of the gate line on the substrate have an overlapping area, forming a second electrode of the first transistor; The orthographic projection of the second electrode extension on the substrate and the orthographic projection of the gate line on the substrate have an overlapping area, forming a second electrode of the second transistor; The orthographic projection of the first electrode body on the substrate has an overlapping area with the orthographic projection of the first common electrode portion on the substrate, forming the first capacitor; The orthographic projection of the second electrode body on the substrate has an overlapping area with the orthographic projection of the second common electrode portion on the substrate, thereby forming the second capacitor.

16. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 15, and further comprises an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

17. A display device, characterized in that: Comprising the display panel as claimed in claim 16.

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