Operation method of memory and memory

Abstract

The invention provides an operation method of a memory and the memory. The operation method comprises the following steps: circularly executing a first type of read-write operation on a selected memory unit in a plurality of memory units; obtaining a first cycle index of the first type of read-write operation; judging the first cycle index; if the first cycle number is greater than or equal to the first threshold value, circularly executing a second type of read-write operation on the selected storage unit; the voltage of the second type of read-write operation and the voltage of the first type of read-write operation correspond to each other and are opposite in direction. According to the operation method of the memory and the memory system provided by the invention, the failure risk caused by accumulative migration of the elements after multiple cyclic operations can be reduced, and the cycle life of the memory is prolonged.

Description

Technical Field

[0001] The present application relates to the field of storage, and in particular to a storage operation method and a storage. Background Art

[0002] The rapid development of artificial intelligence has put forward higher requirements for comprehensive computing performance, and has put forward high requirements for dynamic random access memory (DRAM) and non-volatile storage. At present, academia and industry are developing a variety of emerging non-volatile storage technologies to solve the performance bottleneck of the current von Neumann computing architecture, such as 3D XPT technology based on phase change storage, magnetic storage technology, resistive memristive storage technology, and ferroelectric storage technology, as well as the latest chalcogenide-based Selector Only Memory (SOM, also known as Self-Selecting Memory, SSM or Single chalcoenide Xpoint Memory, SXM) technology. Compared with 3DXPoint memory, SOM has the advantages of simple structure, high miniaturization (down to ~10nm), fast SET / RESET speed (~30ns), good cycle life, vertical stacking, and no write crosstalk caused by thermal effects. It is a very promising non-volatile memory with obvious advantages in the fields of Computer Express Link (CXL) and High Bandwidth Memory (HBM).

[0003] The read and write modes of SOM devices require the use of SET and RESET pulses in opposite directions to operate the cell in order to obtain SET and RESET states with different threshold transition voltages. The main working mechanism of SOM is the migration of internal elements under pulse voltage: after SET, the elements migrate to reduce the threshold transition voltage (Vt), and after RESET, the elements migrate in the opposite direction to increase Vt; therefore, a specific read voltage can be selected to distinguish the two states. Although the RESET and SET operations are in opposite directions, due to the different pulse intensities, there will still be asymmetric migration of elements: as reported by Hynix, SET operation is prone to cause element segregation, while RESET operation can partially migrate elements back to the initial state. It is inevitable that there will be some residue in element migration, so after multiple cycles, element migration will still occur, and serious element aggregation or loss will occur inside, causing failure problems and affecting the cycle life of the device. Summary of the invention

[0004] The purpose of the present application is to provide a memory operation method and a memory, so as to reduce the risk of failure caused by element migration and improve the cycle life of the memory.

[0005] In a first aspect, the present application provides a method for operating a memory, the memory comprising a plurality of memory cells, the operating method comprising: cyclically performing a first type of read and write operation on a selected memory cell among the plurality of memory cells; obtaining a first number of cycles of the first type of read and write operation; determining the first number of cycles; if the first number of cycles is greater than or equal to a first threshold, cyclically performing a second type of read and write operation on the selected memory cell; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction.

[0006] In some embodiments of the present application, the operating method further includes: if the first cycle number is less than a first threshold, continuing to perform the first type of read and write operations on the selected storage unit.

[0007] In some embodiments of the present application, the operating method further includes: obtaining a second cycle number of the second type of read and write operation; determining the second cycle number; if the second cycle number is greater than or equal to a second threshold, cyclically performing the first type of read and write operation on the selected storage unit.

[0008] In some embodiments of the present application, the operating method also includes: obtaining the 2N+1th cycle number of the first type of read and write operation again; the 2N+1th cycle number is the sum of the number of times the first type of read and write operation is continuously performed again after the second type of read and write operation corresponding to the 2Nth cycle number is completed; determining the 2N+1th cycle number; if the 2N+1th cycle number is greater than or equal to the 2N+1th threshold, cyclically performing the second type of read and write operation on the selected storage unit; wherein N is an integer greater than or equal to 1.

[0009] In some embodiments of the present application, the range of the first threshold, the second threshold and the 2N+1th threshold are all 1E3 to 1E6.

[0010] In some embodiments of the present application, the 2N+1th threshold is less than or equal to the 2Nth threshold, and the 2Nth threshold is less than or equal to the 2N-1th threshold; wherein the 2Nth threshold is the threshold corresponding to the 2Nth number of cycles, and the 2N-1th threshold is the threshold corresponding to the 2N-1th number of cycles.

[0011] In some embodiments of the present application, the read and write operations corresponding to the 2N+1th cycle number are exactly the same as the cycle operations corresponding to the first cycle number; or the voltage of the read and write operations corresponding to the 2N+1th cycle number is greater than the voltage of the cycle operations corresponding to the first cycle number; or the pulse width of the read and write operations corresponding to the 2N+1th cycle number is greater than the pulse width of the cycle operations corresponding to the first cycle number.

[0012] In some embodiments of the present application, the read and write operations corresponding to the 2Nth number of cycles are exactly the same as the read and write operations corresponding to the first number of cycles except for the direction; or the voltage of the read and write operations corresponding to the 2Nth number of cycles is greater than the voltage of the cycle operations corresponding to the first number of cycles; or the pulse width of the read and write operations corresponding to the 2Nth number of cycles is greater than the pulse width of the cycle operations corresponding to the first number of cycles.

[0013] In some embodiments of the present application, the voltage or pulse width of the read and write operations corresponding to each cycle of the read and write operations corresponding to the first number of cycles is the same; or the voltage or pulse width of the read and write operations corresponding to each cycle of the read and write operations corresponding to the first number of cycles is different.

[0014] The present application also provides a memory, the memory comprising a memory cell array; the memory cell array comprising a plurality of memory cells; and an operation circuit coupled to the memory cell array; wherein the operation circuit is configured to perform: cyclically performing a first type of read and write operation on a selected memory cell among a plurality of memory cells; obtaining a first number of cycles of the read and write operation; determining the first number of cycles; if the first number of cycles is greater than or equal to a first threshold, cyclically performing a second type of read and write operation on the selected memory cell; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction.

[0015] The memory operation method and memory system provided by the present application obtain the first cycle number of the first type of read and write operation; after the first cycle number is greater than or equal to the first threshold, the second type of write operation is cyclically performed on the selected storage unit; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction. In this way, when performing the second type of read and write operation, the operation direction is reversed, which can cause the elements to migrate in the opposite direction, prevent and repair the aggregation or loss of elements caused by multiple cycles of the first type of read and write operation, thereby reducing the risk of failure caused by element migration and improving the cycle life of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0017] Figure 1 An exemplary module diagram of a memory system provided for some embodiments of the present application.

[0018] Figure 2 Some embodiments of the present application provide Figure 1 An exemplary block diagram of a memory card of a memory system is shown.

[0019] Figure 3An exemplary module diagram of an exemplary solid-state drive with a memory system provided for some embodiments of the present application.

[0020] Figure 4 An exemplary three-dimensional schematic diagram of a memory cell array in a SOM device provided in some embodiments of the present application.

[0021] Figure 5 Schematic diagram of two pulse directions of a SOM device provided in some embodiments of the present application.

[0022] Figure 6 This is a diagram of element distribution within a selected storage cell after performing SET and RESET operations in a SOM device provided in some embodiments of the present application.

[0023] Figure 7 The resistance and cycle number distribution diagram of the PCM device after performing the set operation SET and the reset operation RESET and after performing the operation direction flipping provided in some embodiments of the present application.

[0024] Figure 8 A flowchart of a method for operating a memory provided in some embodiments of the present application.

[0025] Fig. 9 for Figure 8 A schematic diagram of the direction of bias voltages for a first type of read / write operation and a second type of read / write operation performing one flip is shown.

[0026] Fig.10 A flowchart of a memory operation method provided for some other embodiments of the present application.

[0027] Fig.11 for Fig.10 A schematic diagram of a specific flow chart of operations S4 and S5 in a memory operation method is provided.

[0028] Fig.12 for Fig.10 The diagram shows the direction of voltage during the read and write operations that were flipped twice.

[0029] Fig.13 for Fig.11 The diagram shows the direction of voltage during the read and write operations that were flipped three times. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of this application.

[0031] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0032] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. "At least one of A, B and C" has the same meaning as "at least one of A, B or C", and both include the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0033] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0034] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more conditions or values ​​may, in practice, be based on additional conditions or beyond values.

[0035] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0036] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0037] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0038] This application aims to solve the technical problem that the element aggregation or missing phenomenon caused by multiple write operation cycles leads to memory failure and affects the cycle life of the memory.

[0039] By obtaining the first cycle number of the first type of read and write operation; after the first cycle number is greater than or equal to the first threshold, cyclically performing the second type of write operation on the selected storage unit; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction. In this way, when performing the second type of read and write operation, the operation direction is reversed, which can cause the elements to migrate in the opposite direction, prevent and repair the element aggregation or loss caused by multiple cycles of the first type of read and write operation, thereby reducing the risk of failure caused by element migration and improving the cycle life of the memory.

[0040] See also Figures 1 to 5 Some embodiments of the present application provide a memory system, and the memory system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0041] The memory system 100 includes a memory 104 and an operating circuit. The memory 104 includes a memory cell array. The memory cell array includes a plurality of memory cells. The operating circuit is coupled to the memory cell array.

[0042] Wherein, the operation circuit is configured to perform the following operations: cyclically perform a first type of read and write operation on a selected storage cell among a plurality of storage cells; obtain a first cycle number of the first type of read and write operation; determine the first cycle number; if the first cycle number is greater than or equal to a first threshold, cyclically perform a second type of read and write operation on the selected storage cell; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction.

[0043] In some embodiments of the present application, the operation circuit is further configured to perform the following operation: if the first cycle number is less than the first threshold, continue to perform the first type of read and write operations on the selected memory cell.

[0044] In some embodiments of the present application, the operating circuit is further configured to perform the following operations: obtain a second cycle number of a second type of read and write operation; determine the second cycle number; if the second cycle number is greater than or equal to a second threshold, cyclically perform the first type of read and write operation on the selected storage unit.

[0045] In some embodiments of the present application, the operation circuit is further configured to perform the following operations: obtaining the 2N+1th cycle number of the first type of read and write operation again; the 2N+1th cycle number is the sum of the number of times the first type of read and write operation is continuously performed again after the second type of read and write operation corresponding to the 2Nth cycle number is completed; determining the 2N+1th cycle number; if the 2N+1th cycle number is greater than or equal to the 2N+1th threshold, cyclically performing the second type of read and write operation on the selected storage unit; wherein N is an integer greater than or equal to 1.

[0046] In some embodiments of the present application, the memory system 100 also includes a controller 106, which is coupled to the memory 104 and configured to control the memory 104. The controller 106 includes a register 1061, and the register 1061 is configured to record the number of write operations performed on the selected storage unit (corresponding to the same address) and the system set threshold.

[0047] Combine the following Figures 1 to 5 , the structure of the memory system 100 is described in detail.

[0048] like Figure 1 As shown in , the memory system 100 may include a host 108, one or more memories 104, and a controller 106. The host 108 includes a processor, which may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to the memory 104 or obtain data from the memory 104.

[0049] According to some embodiments, the controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the controller 106 is designed to operate in a low duty cycle environment, such as a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multimedia Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0050] The controller 106 may be configured to control the operation of the memory 104, such as read, erase, and program operations. The controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 106 is also configured to process error correction code (ECC) regarding data read from or written to the memory 104. The controller 106 may also perform any other suitable functions, such as formatting the memory 104. The controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the controller 106 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0051] The controller 106 and one or more memories 104 may be integrated into various types of storage devices. Figure 2 In one example shown in FIG. 1 , the controller 106 and the single memory 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 3 In another example shown in , the controller 106 and the plurality of memories 104 can be integrated into the SSD 206. The SSD 206 can also include a processor that connects the SSD 206 to a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0052] The memory 104 may include a magnetic hard disk, a random access memory (RAM), a read-only memory (ROM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric RAM (FeRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), a flash memory, a phase change memory (PCM), a selector only memory (SOM), and others. The memory may be volatile or non-volatile. A non-volatile memory cell can maintain its stored logic state for a long time in the absence of an external power supply. A volatile memory cell loses its stored state over time after power is lost, and usually needs to be refreshed periodically by an external power supply.

[0053] For ease of understanding, the memory in the embodiments of the present application is described by taking a selector only memory (SOM) as an example.

[0054] Please continue reading Figure 1 , each memory 104 may include a memory cell array 1041 and a peripheral circuit 1042 , which may be integrated on the same or different dies, which allows a wider bus and a higher operating speed.

[0055] The peripheral circuit 1042 may include any suitable digital, analog and / or mixed signal circuits for facilitating the operation of the memory. For example, the peripheral circuit may include control logic, data buffers, decoders (also referred to as decoders), drivers, and read / write circuits. When the control logic receives a read / write operation command and address data, under the action of the control logic, the decoder may apply the corresponding voltage generated by the driver to the corresponding word line (WordLine, WL) and bit line (Bit Line, BL) based on the decoded address to implement the data read operation or write operation, and perform data interaction with the outside through the data buffer. Exemplarily, after receiving the read operation or write operation command and address data, the control logic may determine the selected word line and the selected bit line corresponding to the selected storage cell in a plurality of storage cells under the action of the decoder. Exemplarily, the storage cell may be controlled by a row decoder and a column decoder. Specifically: the row decoder may receive a row address from the controller and activate the appropriate word line based on the received row address. The column decoder may receive a column address from the controller and activate the appropriate bit line, and may activate the storage cell at the intersection of the word line and the bit line.

[0056] The memory cell array 1041 may include at least one memory array block, each memory array block may include a plurality of memory cell layers stacked along the Z-axis direction, and each memory cell layer may include a plurality of memory cells. Each memory cell may include a first electrode, a selection memory, and a second electrode stacked along the Z-axis direction, wherein each row of memory cells is connected to an address line (such as a word line), and each column of memory cells is connected to an address line (such as a bit line). It should be understood that a memory cell may be located at the intersection of two address lines, and this intersection may be referred to as the address of the memory cell; other memory cells connected to a common conductor may be referred to as unselected memory cells.

[0057] Exemplary, reference Figure 3 and Figure 5 , the memory cell array 1041 includes a first memory cell layer located between the first type address line 301 and the second type address line 303, and a second memory cell layer located between the second type address line 303 and the third type address line 305, the first memory cell layer includes a plurality of first memory cells 302, the second memory cell layer includes a plurality of second memory cells 304, the first memory cell 302 includes a first electrode 3021, a selection memory 3023, and a second electrode 3025, and the second memory cell 304 includes a first electrode 3041, a selection memory 3043, and a second electrode 3045. In some embodiments, the first type address line is perpendicular to the second type address line, and the first type address line is parallel to the third type address line. Exemplarily, the first type address line and the third type address line are word lines WL, and the second type address line is a bit line BL. It should be understood that the word line WL and the bit line BL can be interchanged.

[0058] In some embodiments, the memory is selected to have both storage and switching functions, that is, the material of the memory is selected to be a dual-function material (DFM). Exemplarily, the material of the memory may include any appropriate bidirectional threshold switch (OTS) material, which may include chalcogenide alloys, such as germanium (Ge), arsenic (As) and selenium (Se) and compounds thereof; the first electrode and the second electrode may be the same material or different materials, and the materials of the first electrode and the second electrode include but are not limited to copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and compounds thereof, conductive doped semiconductors, etc.

[0059] In some embodiments, when a memory, such as a SOM device, performs a write operation, each memory cell can be programmed to store two storage states represented by logic "1" (low resistance state, SET state) and logic "0" (high resistance state, RESET state). A forward pulse is applied to the selected memory cell to cause the elements in the OTS material to achieve forward migration or forward polarization. This process is called a SET process, or a SET operation. A reverse pulse (or negative pulse) is applied to the selected memory cell to cause the elements in the OTS material to achieve reverse migration or reverse polarization. This process is called a RESET process, or a RESET operation. In other devices, more than two states can be stored, which will not be described in detail here.

[0060] In some embodiments, during the read operation, the SOM device can apply a pulse voltage between the SET and RESET state threshold transition voltages, i.e., a read voltage V Read , to measure the resistance values ​​of the two states of the OTS material in the memory cell to obtain data. It should be understood that the storage state of the SOM device will generally not be changed if the read voltage is read a small number of times.

[0061] It should be noted that the OTS material as the storage medium in the storage unit makes the two storage states have a large threshold voltage difference; the difference is about 1V. For example, the threshold voltage V th1 The RESET state threshold voltage V th2 The voltage difference between the two (i.e., the memory window, MW) is about 1.2V, such as MW ~ 1.2V. In this way, the read voltage V Read Can be located at V th1 and V th2 Between, used to distinguish the two storage states of the storage unit.

[0062] It should be noted that, in the write operation, the direction of the current (pulse) during the SET process can be positive or negative, and the direction of the current (pulse) during the RESET process can be positive or negative, but the directions of the current (pulse) during the SET process and the RESET process are opposite. Figure 5 , during the SET process, the current (pulse) flows from the word line (305) to the bit line (303), which is a positive pulse ①, and during the RESET process, the current (pulse) flows from the bit line BL to the word line WL, which is a negative pulse ②. It can also be understood that the current direction of the same memory cell is different when performing different write operations. In addition, during the read operation, the direction of the current applied to the selected memory cell can be positive or negative; but it should be understood that the direction of the read current remains unchanged during multiple read operations. In other words, the direction of the current (pulse) when performing a read operation may be the same as or opposite to the direction of the current (pulse) when performing a write operation.

[0063] See also Figure 6 , Figure 6 (a) is the element distribution diagram of the selected storage cell after the set operation SET is performed in the SOM device. Figure 6 (b) is a diagram showing the element distribution in the selected memory cell after the reset operation RESET is performed. Figure 6 (a) When the set operation SET is performed on the selected storage unit, the z element migrates from the bottom Bot. to the top Top, and the x and y elements migrate from the top Top to the bottom Bot. Figure 6 (b) After the reset operation RESET is performed on the selected storage cell, the elements migrate in the opposite direction, and the three element components at the top Top and bottom Bot. are more evenly distributed. Although the bias voltage directions of the RESET operation and the SET operation are opposite, there will still be asymmetric migration of elements due to the different pulse intensities. The SET operation is prone to cause element aggregation, while the RESET operation can partially migrate the elements back to the initial state. There will inevitably be some residue in the element migration, so after multiple cycles, element migration will still occur, and serious aggregation or loss of elements will occur inside, affecting the cycle performance of the device.

[0064] See also Figure 7 , Figure 7 (a) is the resistance and cycle number distribution diagram of the PCM device after performing the set operation SET and the reset operation RESET. Figure 7 (b) is the distribution diagram of the resistance and cycle number of the PCM device after the operation direction is reversed. Figure 7 (a) During operation of a memory device (e.g., PCM device), element migration causes the selected memory cell to be written to ~10 5When a fault occurs, the device cannot be restored to high impedance state by RESET operation. Figure 7 (b), through multiple times (for example: 2.4*10 2 ) Applying a reverse bias voltage can restore the operating window of a failed device, such as Figure 7 (b) The data in the dashed box. It can be seen that by reversing the operation direction of the selected memory cell (applying a reverse bias voltage), the elements can be reversely migrated to avoid element aggregation / missing, thereby reducing the risk of failure caused by element migration.

[0065] Based on this, the operation method of the memory provided in the present application is further described in detail below by taking the SOM device as an example.

[0066] See also Figure 8 and Fig. 9 , the present application also provides a memory operation method, including:

[0067] Operation S1, cyclically performing a first type of read and write operation on a selected memory cell among a plurality of memory cells;

[0068] Operation S2, obtaining a first cycle number of a first type of read / write operation;

[0069] Operation S3, determining the first cycle number; if the first cycle number is greater than or equal to the first threshold, cyclically performing a second type of read and write operation on the selected memory cell; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction.

[0070] In some embodiments of the present application, if the first cycle number is less than the first threshold, the first type of read and write operations are continued to be performed on the selected memory cell.

[0071] In some embodiments of the present application, the first threshold ranges from 1E3 to 1E6.

[0072] In some embodiments of the present application, a first type of read / write operation includes a first set operation SET1, a first reset operation RESET1 and a first read / write operation READ1; a second type of read / write operation includes a second set operation SET2, a second reset operation RESET2 and a second read / write operation READ2; the bias voltages of the first set operation SET1 and the first reset operation RESET1 are in opposite directions; the bias voltages of the second set operation SET2 and the first set operation SET1 are in opposite directions; the bias voltages of the second reset operation RESET2 and the first reset operation RESET1 are in opposite directions; the bias voltages of the read operation READ in the first type of read / write operation are in the same direction as the bias voltages of the first set operation SET1; and the bias voltages of the read operation READ in the second type of read / write operation are in the same direction as the bias voltages of the second set operation SET2.

[0073] In other embodiments, the first type of read / write operations may not include the read / write operation READ, and the second type of read / write operations may not include the read / write operation READ.

[0074] Operation S1 includes: applying a first set pulse and a first reset pulse to a selected memory cell, respectively, to perform a first type of read and write operation on the selected memory cell among a plurality of memory cells.

[0075] In some embodiments of the present application, operation S1 further includes: applying a read pulse after the first set pulse and the first reset pulse, respectively.

[0076] The first set pulse is applied to the selected memory cell to perform a first set operation SET1; the first reset pulse is applied to the selected memory cell to perform a first reset operation RESET1; and the read pulse is applied to the selected memory cell to perform a read operation READ. The pulse direction of the first set pulse is opposite to the pulse direction of the first reset pulse. The pulse direction is the same as the direction of the bias voltage. The pulse direction of the read pulse in the first type of read and write operation is the same as the pulse direction of the first set pulse.

[0077] In some embodiments of the present application, the first cycle number of the read-write operation in operation S2 may be the write number of the first set operation SET1, the sum of the write number of the first set operation SET1 and the first reset operation RESET1, or the read number of the read operation READ.

[0078] In some embodiments of the present application, "cyclically performing a second type of read and write operation on a selected memory cell" in operation S3 includes: applying a second set pulse and a second reset pulse to the selected memory cell, respectively, to cyclically perform a second type of read and write operation on the selected memory cell among a plurality of memory cells.

[0079] In some embodiments of the present application, "cyclically performing the second type of read and write operations on the selected memory cell" in operation S3 further includes: applying a read pulse after the second set pulse and the second reset pulse, respectively.

[0080] The second set pulse is applied to the selected memory cell to perform a second set operation SET2; the second reset pulse is applied to the selected memory cell to perform a second reset operation RESET2. The read pulse is applied to the selected memory cell to perform a read operation READ. The direction of the second set pulse is opposite to the direction of the second reset pulse and opposite to the direction of the first set pulse. The pulse direction of the read pulse in the second type of read and write operation is the same as the pulse direction of the second set pulse.

[0081] Of course, the operation method provided in the present application is not limited to operation S1 to operation S3 (operation S3 is equivalent to flipping the bias voltage direction of the read and write operation once), and may also include other operations to perform multiple bias voltage flips. The number of bias voltage flips of the write operation can be set according to actual conditions.

[0082] See also Fig.10 and Fig.12 In some embodiments of the present application, the operation method further includes:

[0083] Operation S4, obtaining a second cycle number of the second type of read / write operation; and

[0084] Operation S5, determining the second cycle number, if the second cycle number is greater than or equal to the second threshold, cyclically performing the first type of read and write operations on the selected memory cell.

[0085] In operation S5, the bias voltage direction of the read and write operations is reversed twice.

[0086] In some embodiments of the present application, the second threshold value ranges from 1E3 to 1E6.

[0087] In some embodiments of the present application, as the number of writes to the selected storage unit increases, the selected storage unit will have a certain amount of wear, and the second threshold may be less than or equal to the first threshold. Of course, if the number of writes to the selected storage unit is not enough to cause the selected storage unit to wear, the second threshold may also be greater than the first threshold.

[0088] See also Figures 11 to 13 In some embodiments of the present application, the operation method further includes:

[0089] Operation S6, obtaining the 2N+1th cycle number of the first type of read / write operation again; the 2N+1th cycle number is the sum of the number of times the first type of read / write operation is continuously executed again after the second type of read / write operation corresponding to the 2Nth cycle number is completed.

[0090] Operation S7, determining the 2N+1th cycle number; if the 2N+1th cycle number is greater than or equal to the 2N+1th threshold, cyclically performing the second type of read and write operations on the selected storage unit; wherein N is an integer greater than or equal to 1.

[0091] In operation S6, the direction of the bias voltage for the read and write operations is reversed 2N+1 times.

[0092] Correspondingly, for the case of flipping 2N times, reference can be made to operations S2 and S3, which will not be described in detail here.

[0093] In some embodiments of the present application, the range of the 2N+1th threshold is 1E3 to 1E6.

[0094] In some embodiments of the present application, as the number of writes to the selected storage unit increases, the selected storage unit will have a certain amount of wear, and the 2N+1th threshold may be less than or equal to the first threshold. Of course, if the number of writes to the selected storage unit is not enough to cause the selected storage unit to wear out, the 2N+1th threshold may also be greater than the first threshold.

[0095] In some embodiments of the present application, the 2N+1th threshold is less than or equal to the 2Nth threshold, and the 2Nth threshold is less than or equal to the 2N-1th threshold; wherein the 2Nth threshold is the threshold at which the voltage of the read operation corresponding to the 2Nth cycle number is reversed, and the 2N-1th threshold is the threshold at which the voltage of the read operation corresponding to the 2N-1th cycle number is reversed.

[0096] In some embodiments of the present application, the read and write operations corresponding to the 2N+1th cycle number are exactly the same as the cycle operations corresponding to the first cycle number; or the voltage of the read and write operations corresponding to the 2N+1th cycle number is greater than or less than the voltage of the cycle operations corresponding to the first cycle number; or the pulse width of the read and write operations corresponding to the 2N+1th cycle number is greater than or less than the pulse width of the cycle operations corresponding to the first cycle number.

[0097] In some embodiments of the present application, the read and write operations corresponding to the 2Nth number of cycles are exactly the same as the read and write operations corresponding to the first number of cycles except for the direction; or the voltage of the read and write operations corresponding to the 2Nth number of cycles is greater than or less than the voltage of the cycle operation corresponding to the first number of cycles; or the pulse width of the read and write operations corresponding to the 2Nth number of cycles is greater than or less than the pulse width of the cycle operation corresponding to the first number of cycles.

[0098] In some embodiments of the present application, the voltage or pulse width of the read and write operations corresponding to each cycle of the read and write operations corresponding to the first number of cycles is the same; or the voltage or pulse width of the read and write operations corresponding to each cycle of the read and write operations corresponding to the first number of cycles is different.

[0099] In some embodiments of the present application, the pulse height of the first pulse, the second pulse, the third pulse, or the fourth pulse is 4V to 6V, and the pulse width is 10ns to 500ns.

[0100] In some embodiments of the present application, the pulse height of the read pulse is 4.5V-5.5V, and the pulse width is less than 100ns.

[0101] The operations S1, S2, S3, S4, S5, S6 and S7 are all performed by an operation circuit, and the operation circuit receives instructions issued by a processor.

[0102] The memory operation method and memory system provided by the present application obtain the first cycle number of the first type of read and write operation; after the first cycle number is greater than or equal to the first threshold, the second type of write operation is cyclically performed on the selected storage unit; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction. In this way, when performing the second type of read and write operation, the operation direction is reversed, which can cause the elements to migrate in the opposite direction, prevent and repair the aggregation or loss of elements caused by multiple cycles of the first type of read and write operation, thereby reducing the risk of failure caused by element migration and improving the cycle life of the memory.

[0103] In addition, the memory operation method and memory system provided in the present application can perform multiple flips of the operation direction as needed, which can further improve element aggregation or loss.

[0104] In addition, the memory operation method and memory system provided by the present application can prevent element aggregation or loss by reversing the execution operation direction of the selected memory cell of the device before failure (for example, setting the threshold value to 1E3-1E6).

[0105] In addition, in the memory operation method provided in the present application, the direction of the bias voltage of the RESET operation is opposite to the direction of the bias voltage of the SET operation, which provides the conditions for performing write operations with two opposite bias voltages with the system set threshold as the dividing line.

[0106] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for operating a memory, wherein the memory comprises a plurality of storage units, characterized in that: The operation method comprises: cyclically performing a first type of read and write operations on selected memory cells among the plurality of memory cells; Obtaining a first cycle number of the first type of read and write operations; Determining the first cycle number; If the first cycle number is greater than or equal to a first threshold, a second type of read and write operation is cyclically performed on the selected memory cell; the voltage of the second type of read and write operation corresponds to the voltage of the first type of read and write operation and is opposite in direction.

2. The operating method according to claim 1, characterized in that: Also includes: If the first cycle number is less than a first threshold, the first type of read and write operations are continued to be performed on the selected memory cell.

3. The operating method according to claim 1, characterized in that: The operation method also includes: Obtaining a second cycle number of the second type of read and write operations; Determining the second cycle number; If the second cycle number is greater than or equal to a second threshold, the first type of read and write operations are cyclically performed on the selected memory cell.

4. The operating method according to claim 3, characterized in that: The operation method also includes: Obtaining the 2N+1th cycle number of the first type of read and write operation again; the 2N+1th cycle number is the sum of the number of times the first type of read and write operation is continuously executed again after the second type of read and write operation corresponding to the 2Nth cycle number is completed; Determining the 2N+1th cycle number; If the 2N+1th cycle number is greater than or equal to the 2N+1th threshold, cyclically performing the second type of read and write operations on the selected memory cell; Wherein, N is an integer greater than or equal to 1.

5. The operating method according to claim 4, characterized in that: The first threshold, the second threshold and the 2N+1th threshold are all in the range of 1E3 to 1E6.

6. The operating method according to claim 4, characterized in that: The 2N+1th threshold is less than or equal to the 2Nth threshold, and the 2Nth threshold is less than or equal to the 2N-1th threshold; Among them, the 2Nth threshold is the threshold corresponding to the 2Nth cycle number, and the 2N-1th threshold is the threshold corresponding to the 2N-1th cycle number.

7. The operating method according to claim 4, characterized in that: The read and write operations corresponding to the 2N+1th number of cycles are exactly the same as the cycle operations corresponding to the first number of cycles; or The voltage of the read / write operation corresponding to the 2N+1th number of cycles is greater than the voltage of the cycle operation corresponding to the first number of cycles; or The pulse width of the read and write operation corresponding to the 2N+1th cycle number is greater than the pulse width of the cycle operation corresponding to the first cycle number.

8. The operating method according to claim 4, characterized in that: The read and write operations corresponding to the 2Nth number of cycles are exactly the same as the read and write operations corresponding to the first number of cycles except for the direction; or The voltage of the read / write operation corresponding to the 2Nth number of cycles is greater than the voltage of the cycle operation corresponding to the first number of cycles; or The pulse width of the read and write operation corresponding to the 2Nth number of cycles is greater than the pulse width of the cycle operation corresponding to the first number of cycles.

9. The operating method according to any one of claims 1 to 8, characterized in that: The voltage or pulse width of the read / write operation corresponding to each cycle of the read / write operation corresponding to the first number of cycles is the same; or The voltage or pulse width of the read / write operation corresponding to each cycle of the read / write operation corresponding to the first number of cycles is different.

10. A memory, characterized in that: comprising a memory cell array; the memory cell array comprising a plurality of memory cells; and an operating circuit coupled to the memory cell array; The operating circuit is configured to execute the operating method according to any one of claims 1 to 9.

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