Signal processing device

Abstract

The invention discloses a signal processing device. The signal processing device provided by the embodiment of the invention comprises a random access memory, wherein the random access memory is used for storing data; the computing unit is connected with the random access memory so as to acquire the storage data, and the computing unit is used for computing the storage data; and the control unit is connected with the random access memory so as to control the reading and writing of the random access memory. According to the signal processing device provided by the embodiment of the invention, the chip area is saved, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a signal processing device. Background Art

[0002] In the fields of AM radio and NFC, for On-Off Keying (OOK) signals with non-100% amplitude modulation, the performance of coherent demodulation is better than other methods such as envelope detection. In a typical coherent demodulation architecture, the analog RF front-end circuit is responsible for mixing, amplifying, filtering, and analog-to-digital conversion of the antenna signal, and then providing the digital circuit IQ with two orthogonal multi-bit sampling depth and high sampling rate baseband signals; the digital circuit restores the original baseband signal based on these two signals, and further decodes the communication content according to the communication protocol.

[0003] In the existing coherent demodulation method, when the digital circuit performs signal processing, it is necessary to perform signal processing on the numerical sequence to achieve operations such as filtering, summing, and averaging. The digital circuit usually stores these numerical sequences in a shift register structure. This storage circuit is mature and simple, but when the numerical sequence to be stored is very long or the bit width of the numerical value is large, the circuit area consumed by the storage becomes very considerable, which has a large cost burden.

[0004] Therefore, it is hoped that there will be a new signal processing device that can overcome the above problems. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a signal processing device, in particular a signal processing device based on a random access memory, so as to save chip area and reduce production costs.

[0006] According to one aspect of the present invention, there is provided a signal processing device, comprising:

[0007] A random access memory, wherein the random access memory is used for storing data;

[0008] a computing unit connected to the random access memory to obtain the stored data and perform calculations on the stored data; and

[0009] A control unit is connected to the random access memory to control the reading and writing of the random access memory.

[0010] Optionally, the control unit provides a first control signal to control the reading and writing of the random access memory; the control unit provides a second control signal to control the data path of the computing unit;

[0011] The first control signal includes at least one selected from a read enable signal, a write enable signal, a read address code, and a write address code.

[0012] Optionally, the computing unit includes:

[0013] A first computing subunit, the first computing subunit being configured to perform a first type of operation; and

[0014] a second computing subunit, the second computing subunit being configured to perform a second type of operation;

[0015] The signal processing device further comprises:

[0016] An operation multiplexer, wherein the operation multiplexer is connected to the first calculation subunit and the second calculation subunit respectively to output the operation result of the currently operating first calculation subunit or second calculation subunit.

[0017] Optionally, the control unit comprises:

[0018] Control state machine; and

[0019] An address generator, the address generator is used to generate a read address code and / or a write address code;

[0020] The control unit configures the working mode and / or working parameters according to requirements to adjust the length of the numerical sequence involved in the calculation and / or adjust the accuracy of the numerical sequence involved in the calculation and / or select an effective calculation subunit and / or select an effective storage subunit in the random access memory.

[0021] Optionally, the calculation unit calculates a numerical sequence sliding over time;

[0022] The signal processing device receives an updated value;

[0023] The control unit sends a read enable to the random access memory, and the read address is the address of the value at the end of the value sequence to be calculated in the random access memory;

[0024] The random access memory reads out the value at the end of the sliding window of the value sequence to be calculated and transmits it to the selected calculation subunit configured in the calculation unit;

[0025] The calculation subunit receives the updated value; the calculation subunit performs calculations based on the updated value and the value at the end of the sliding window sequence.

[0026] Optionally, the calculation of the calculation unit includes at least one selected from sum calculation, difference calculation, convolution calculation and average calculation.

[0027] Optionally, in a first calculation cycle, the calculation subunit calculates to obtain a first calculation result; the calculation subunit temporarily stores the first calculation result;

[0028] In a second calculation cycle, the calculation subunit performs calculations according to the updated value, the value at the end of the sliding window sequence and the first calculation result to obtain a second calculation result;

[0029] The calculation subunit updates the temporarily stored first calculation result to the second calculation result;

[0030] The control unit sends a write enable to the random access memory, wherein the write address of the write enable is the same as the read address; the update value covers the value at the end of the sequence sliding window,

[0031] Wherein, when the address pointer in the control unit reaches the window width value, the address pointer is reset to zero;

[0032] When the address pointer in the control unit does not reach the window width value, the address pointer is incremented by one.

[0033] Optionally, the signal processing device further comprises a data input terminal, a result output terminal and a data multiplexer;

[0034] The data multiplexer is connected to the data input terminal and the result output terminal respectively to obtain data from the data input terminal or the result output terminal, and stores the data from the data input terminal or the result output terminal as the storage data in the random access memory;

[0035] The calculation unit acquires the stored data and performs operations on the stored data to obtain result data; the operation unit is also connected to the result output terminal to provide the result data to the result output terminal.

[0036] Optionally, the signal processing device further includes:

[0037] A configuration unit is connected to the control unit and is used to provide configuration parameters for configuring the control unit.

[0038] Optionally, the signal processing device further includes:

[0039] A signal receiving end, wherein the signal receiving end receives a signal to be processed;

[0040] The calculation unit is connected to the signal receiving end to perform calculation processing on the signal to be processed.

[0041] The signal processing device provided by the embodiment of the present invention uses a random access memory to store data during the signal processing process, thereby saving chip area and reducing production costs.

[0042] Furthermore, the computing unit includes a plurality of computing sub-units; different computing sub-units perform different types of operations; and can implement a variety of operations conveniently, efficiently, and accurately.

[0043] Furthermore, for the calculation operation of the sliding numerical sequence, the result of this calculation operation can be substituted into the next calculation, so that the next calculation does not need to use the values ​​of the entire numerical sequence, but only uses the increments and decrements in the numerical sequence, which reduces the amount of data required for the calculation and improves the calculation efficiency.

[0044] Furthermore, the signal processing device can perform coherent demodulation on an on-off keying signal that is not 100% amplitude modulated, with good demodulation effect and low hardware requirements.

[0045] The signal processing device for which protection is sought in the present application utilizes the temporal locality of data and adopts a random access memory to replace registers in the circuit, thereby improving data storage density, saving chip area, and reducing production costs; this calculation method tightly coupled with the random access memory can be used for certain specific sliding numerical sequence calculation operations, such as correlators and filters in baseband signal processing, and can also be used in application fields with large storage requirements but small read and write bandwidths. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0047] Figure 1 It shows a schematic diagram of the structure of a signal processing device according to the first embodiment of the present invention;

[0048] Figure 2 It shows a schematic diagram of the structure of a signal processing device according to Embodiment 2 of the present invention;

[0049] Figure 3 A schematic diagram showing the structure of a computing unit according to a third embodiment of the present invention is shown;

[0050] Figure 4 It shows a processing flow chart of a signal processing device according to a fourth embodiment of the present invention;

[0051] Figure 5 It shows a processing flow chart of a signal processing device according to a fifth embodiment of the present invention;

[0052] Figure 6 A processing flow chart of a signal processing device according to a sixth embodiment of the present invention is shown. DETAILED DESCRIPTION

[0053] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0054] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. Many specific details of the present invention, such as the structure, materials, dimensions, processing technology and techniques of the components are described below to provide a clearer understanding of the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0055] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0056] Figure 1 FIG. 2 shows a schematic diagram of the structure of a signal processing device according to Embodiment 1 of the present invention. Figure 1 As shown, the signal processing device according to the first embodiment of the present invention includes a random processor 100, a calculation unit 200 and a control unit 300.

[0057] Specifically, the random access memory 100 is used to store data. The random access memory (Random Access Memory, RAM for short) allows random access to data, that is, any location in the memory can be directly accessed. This means that data at any specified location can be quickly read or written without sequentially accessing other data in the memory. The random access memory 100 can be an on-chip random access memory of an integrated circuit, which can be a static random access memory (SRAM), a phase change memory (PRAM), a ferromagnetic random access memory (FRAM), or a resistive random access memory (RRAM).

[0058] The calculation unit 200 is connected to the random access memory 100 to obtain the storage data stored in the random access memory 100 and perform calculations on the storage data.

[0059] The control unit 300 is connected to the random access memory 100 to control the reading and writing of the random access memory 100 .

[0060] Optionally, the signal processing device further includes a configuration unit (not shown in the figure). The configuration unit is connected to the control unit 300 and is used to provide configuration parameters for configuring the control unit 300.

[0061] Optionally, the control unit 300 provides read enable, write enable, and address encoding required for read and write for the random access memory 100. The control unit 300 includes at least one address generator and a control state machine. The control unit 300 can be configured into different working modes and working parameters as required to adjust the length or precision of the numerical sequence involved in the calculation, select the effective calculation subunit, select the effective storage subunit in the random access memory 100, etc.

[0062] Optionally, the signal processing device further includes a signal receiving end (not shown in the figure). The signal receiving end receives the signal to be processed; the calculation unit 200 is connected to the signal receiving end to perform operation processing on the signal to be processed, and the operation processing includes at least one selected from summation calculation, difference calculation, convolution calculation and average calculation. In a specific embodiment, the signal receiving end receives an on-off keying signal of non-100% amplitude modulation. The random access memory 100, the calculation unit 200 and the control unit 300 are connected to the signal receiving end to coherently demodulate the on-off keying signal of non-100% amplitude modulation. Coherent demodulation is a communication technology that is applicable to the demodulation of all linear modulated signals. The core of coherent demodulation is that the receiving end can recover a coherent carrier that is strictly synchronized with the modulated carrier. This demodulation method uses a multiplier to multiply a reference signal that is coherent with the carrier frequency (same frequency and same phase) with the carrier frequency, thereby realizing signal demodulation. Coherent demodulation relies on known phase information, which makes it generally superior to incoherent demodulation methods in terms of anti-interference. Coherent demodulation can provide higher demodulation accuracy and better signal recovery effect, and is particularly suitable for application scenarios that have high requirements on signal quality, such as high-speed data transmission and precision communication systems.

[0063] In an optional embodiment of the present invention, the control unit 300 provides a first control signal to control the reading and writing of the random access memory 100. The control unit 300 provides a second control signal to control the data path of the computing unit 200. The first control signal includes at least one selected from a read enable signal, a write enable signal, a read address code, and a write address code. The second control signal is used to control the gating.

[0064] In an optional embodiment of the present invention, the computing unit 200 includes a first computing subunit and a second computing subunit. The signal processing device also includes an operation multiplexer. The first computing subunit is used to perform a first type of operation. The second computing subunit is used to perform a second type of operation. The first type of operation / the second type of operation can be a summation calculation, a difference calculation, a convolution calculation of a numerical sequence and another fixed numerical sequence, an average calculation of a numerical sequence, etc. The operation multiplexer is connected to the first computing subunit and the second computing subunit respectively to output the operation result of the first computing subunit or the second computing subunit currently working.

[0065] Optionally, the random access memory 100 may have only one storage subunit, and the first computing subunit and the second computing subunit may share this storage subunit. The random access memory 100 may also have multiple storage subunits, providing data storage for multiple computing subunits (respectively).

[0066] In an optional embodiment of the present invention, the calculation unit 200 calculates a numerical sequence. A numerical sequence is an ordered set consisting of a series of numbers, which are arranged according to certain rules. The numerical sequence can be finite or infinite. Each number in the numerical sequence is called an item of the sequence, which can be represented by a1, a2, a3, ...,. The types of numerical sequences are very diverse, and can be arithmetic progressions, geometric progressions, Fibonacci sequences, and random sequences. A sliding numerical sequence generally refers to a technique used in time series analysis, called a sliding window. This technique divides time series data into multiple windows of fixed size, which can be overlapping or non-overlapping. The time series data in each window is used to generate a feature vector, which represents the state or characteristics of the window. Optionally, the processed signal is a numerical sequence, and the total length of the numerical sequence is not limited during the entire processing process, but the window length of the numerical sequence involved in the processing in each cycle is limited, and this window can slide over time in the entire sequence. Optionally, in the first calculation cycle, the calculation unit 200 calculates and obtains a first numerical sequence. Then, a value is added to the beginning of the first numerical sequence and the value at the end is removed to obtain a second numerical sequence. In a second calculation cycle, the calculation unit 200 operates on the second numerical sequence. The length of the first numerical sequence is the same as the length of the second numerical sequence.

[0067] In an optional embodiment of the present invention, the signal processing device further includes a data input terminal, a result output terminal and a data multiplexer. The data multiplexer is connected to the data input terminal and the result output terminal respectively to obtain data from the data input terminal or the result output terminal, and stores the data from the data input terminal or the result output terminal as storage data in the random access memory 100. The computing unit 200 acquires the storage data and performs operations on the storage data to obtain result data. The computing unit 200 is also connected to the result output terminal to provide the result data to the result output terminal.

[0068] Figure 2 FIG. 2 shows a schematic diagram of the structure of a signal processing device according to Embodiment 2 of the present invention. Figure 2 As shown, the signal processing device according to the second embodiment of the present invention includes a random access memory 100, a calculation unit 200, a control unit 300, a data input terminal (port) 104, a result output terminal (port) 105 and a data multiplexer 106.

[0069] The control unit 300 provides read and write control for the random access memory 100 and provides data path control for the computing unit 200. This control can generate read enable, write enable, and address encoding required for read and write. The random access memory 100 provides storage space for the data input port 104 and provides data to be calculated for the computing unit 200.

[0070] Figure 3 FIG. 4 shows a schematic diagram of the structure of a computing unit according to Embodiment 3 of the present invention. Figure 3 As shown, the computing unit according to the third embodiment of the present invention may include multiple computing subunits (a first computing subunit 201, a second computing subunit 202, a third computing subunit 203, and a fourth computing subunit, etc.). Each computing subunit performs a computing operation, and different computing subunits may perform different computing operations. When there are multiple computing subunits, the output of the currently working computing subunit will be selected by the operation multiplexer (output multiplexer) 206 as the final output result and output from the output port 205 to the result output terminal 105. The data required for the operation of each computing subunit (input value (group)) is input, for example, from the input port 204. The computing operation object performed by the computing subunit is a numerical sequence that slides over time, that is, in each computing cycle, after the computing operation is completed, the old value at the end of the sequence will be removed, and a new value will be added to the beginning of the sequence, so as to ensure that the sequence length remains unchanged for a specific configuration. The computing subunit can store the intermediate value of each calculation process internally for use in the next calculation.

[0071] In an optional embodiment of the present invention, in combination with Figure 2 and Figure 3As shown, a data multiplexer 106 can be added to the data input terminal 104 of the random access memory 100 as needed. The data multiplexer 106 selects one path from the data input terminal 104 and the result output terminal to store in the random access memory 100 according to the scheduling of the control unit 300. In this way, the signal processing device of the present application can be combined into a multi-level computing system, that is, the data input terminal 104 is sent to a computing sub-unit in the computing unit 200 after passing through the random access memory 100. After calculation, the data of the result output terminal 105 is written back to the random access memory 100 through the data multiplexer 106, and the data is taken out again at an appropriate time and sent to another computing sub-unit in the computing unit 200 for another computing operation, and then output to the result output terminal 105 to give the final calculation result (for example, the coherent demodulation result).

[0072] In an optional embodiment of the present invention, in the simplest case where the data multiplexer 106 is not used and the system is used as a single-stage computing system with only one computing subunit and only one random access memory 100 (storage subunit), the operating principle of the signal processing device described in the present application is as follows:

[0073] After configuring the parameters such as sequence length and calculation function to the control unit 300, the signal processing device is started, and the following operations are performed in each data processing cycle:

[0074] The data input terminal 104 updates a new value and inputs it into the signal processing device.

[0075] The control unit 300 sends a read enable to the random access memory 100, and the read address is the address of the value at the end of the numerical sequence to be calculated in the random access memory 100; the random access memory 100 reads the value at the end of the sliding window of the numerical sequence to be calculated and transmits it to the selected calculation subunit configured in the calculation unit 200; the new value currently input by the data input terminal 104 is also transmitted to the aforementioned calculation subunit at the same time.

[0076] The calculation subunit performs a certain calculation based on the latest input value, the value at the end of the sliding window sequence, and the result of the last calculation temporarily stored in the calculation subunit, and obtains a new calculation result, which is finally output to the result output terminal 105 via the output multiplexer 206 and the output port 205. The calculation performed by the calculation (sub) unit includes at least one selected from sum calculation, difference calculation, convolution calculation, and average calculation.

[0077] The calculation subunit updates the calculation result temporarily stored inside; at the same time, the control unit 300 sends a write enable to the random access memory 100, and the write address is the same as the read address in step 1. At this time, the new value will overwrite the old value at the end of the previous sequence sliding window; if the address pointer in the control unit 300 reaches the window width value n, the address pointer returns to 0, otherwise it increases by 1, so that the original address will be used as the start of the sequence, and the new address after +1 (or after returning to 0) will be used as the end of the sequence.

[0078] The signal processing device based on random access memory according to the embodiment of the present invention can realize certain specific calculation operations of numerical sequence at a lower cost by using random access memory with higher storage density to replace the shift register.

[0079] Compared with the prior art, the advantages and novelty of the present invention are: for the calculation operation of certain specific sliding numerical sequences, the result of this calculation operation can be substituted into the next calculation, so that the next calculation does not need to use the values ​​of the entire numerical sequence, but only uses the increments and decrements in the numerical sequence. Based on this feature, the access bandwidth requirement of the numerical sequence is significantly reduced, so that the data can be stored in a random access memory. In integrated circuit design, the storage density of a random access memory array is several times that of a register. When a numerical sequence with a longer sequence or a larger bit width needs to be stored, the circuit scale that can be saved is considerable. This cost advantage makes the products using this technology more competitive in the market.

[0080] The solution of the present application is further described below in conjunction with some specific embodiments.

[0081] Figure 4 FIG. 4 shows a processing flow chart of a signal processing device according to Embodiment 4 of the present invention. Figures 2 to 4 As shown, the signal processing device according to the fourth embodiment of the present invention is used to calculate the sum of a numerical sequence with a length of n.

[0082] Specifically, suppose that each value of an infinite length numerical sequence A is sequentially input into the signal processing device from the data input terminal 104, and the value input into the signal processing device at a certain moment is A. i , this device will calculate A in real time i-n＋1 ~A i The sum of these n values. Let the address pointer in the current control unit 300 be x. The calculation subunit temporarily stores the n values ​​calculated last time (A i-n ~A i-1 ) and M i-1 The most recently received A is stored in the random access memory 100. i-n ~A i-1 There are n values ​​in total, and the head address of the sequence is x-1, and the tail address of the sequence is x.

[0083] In one processing cycle of the device, the control unit 300 causes the random access memory 100 to read the value A of the address x. i-n The calculation subunit for summation performs the following operation M i =M i-1 -A i-n +A i , and obtain the sum of the new sequence; M i Temporarily store in the calculation subunit to replace M i-1 The control unit 300 writes new data A to the address x of the random access memory 100. i Overwrite old data A i-n ; The address pointer in the control unit 300 is incremented by 1. If the address exceeds n, the address pointer returns to 0.

[0084] When the following initial conditions are met, the above "address pointer is x, the value temporarily stored in the calculation subunit is A i-n ~A i-1 and M i-1 , and the random access memory 100 stores the most recently received A i-n ~A i-1 There are n values ​​in total, and the head address of the sequence is x-1, and the tail address of the sequence is x". This premise is established: the initial value of the address pointer in the control unit 300 is 0, and the initial value in the random access memory 100 is all 0, and the sum temporarily stored in the calculation subunit is 0.

[0085] The data processed in the above embodiment has the characteristics of infinite sequence, finite window and time sliding. The control unit 300 generates read and write enable and address generation, and there is a data flow relationship between the storage subunit and the calculation subunit, and the calculation subunit temporarily stores the sum of data M i , and is used for calculation in the next cycle.

[0086] Figure 5 FIG. 5 shows a processing flow chart of a signal processing device according to Embodiment 5 of the present invention. Figure 2 , Figure 3 and Figure 5 As shown, the signal processing device according to the fifth embodiment of the present invention is used to calculate a convolution operation between a numerical sequence with a length of n and a fixed binary sequence B (1, -1, 1, -1, 1, -1, ...) with a length of n, wherein B 2j = -1, B 2j＋1 =1.

[0087] Specifically, suppose that each value of an infinite length numerical sequence A is sequentially input into the signal processing device from the data input terminal 104, and the value input into the device at a certain moment is A. i , this device will calculate A in real timei-n＋1 ~A i Convolution with sequence B R = ∑ B i A i . Let the address pointer in the current control unit 300 be x. The calculation subunit temporarily stores the odd items of the A sequence and M left over from the previous calculation. odd With even terms and M even The most recently received A is stored in the random access memory 100. i-n ~A i-1 There are n values ​​in total, and the head address of the sequence is x-1, and the tail address of the sequence is x. In one processing cycle of the device, the control unit 300 causes the random access memory 100 to read the value A at the address x. i-n ; The computing subunit for convolution calculation performs the following operation and replaces the old value with the new value and temporarily stores it, M odd =M even -A i-n +A i , M even =M odd The calculation result of the calculation subunit is M odd -M even , output to the result output terminal 105. The control unit 300 writes new data A to the x address of the random access memory 100 i Overwrite old data A i-n ; The address pointer in the control unit 300 is incremented by 1. If the address exceeds n, the address pointer returns to 0.

[0088] When the following initial conditions are met, the above "address pointer is x, the value temporarily stored in the calculation subunit is the numerical sequence A i-n ~A i-1 The odd terms and M odd With even terms and M even , and the random access memory 100 stores the most recently received A i-n ~A i-1 There are n values ​​in total, and the head address of the sequence is x-1, and the tail address of the sequence is x". This premise is established: the initial value of the address pointer in the control unit 300 is 0, and the initial value in the random access memory 100 is all 0, and the two sums temporarily stored in the calculation subunit (M odd , M even ) are all 0.

[0089] It should be pointed out that in the above embodiment, the fixed binary sequence B involved in the convolution calculation is not limited to (1, -1, 1, -1, 1, -1, ...); some values ​​in the sequence may not be binary, such as (2, -1, 1, -1, ..., 1, -1, 1, -2); this can be achieved by simply making corresponding modifications to the calculation formula of the calculation subunit.

[0090] The data processed in the above embodiment has the characteristics of infinite sequence, finite window and time sliding. The control unit 300 generates read and write enable and address generation, and there is a data flow relationship between the storage subunit and the calculation subunit, and the calculation subunit temporarily stores M odd , M even , and is used for calculation in the next cycle.

[0091] Figure 6 FIG. 1 shows a processing flow chart of a signal processing device according to Embodiment 6 of the present invention. Figure 2 , Figure 3 and Figure 6 As shown, the signal processing device according to the sixth embodiment of the present invention is used to calculate a numerical sequence A with a length of n and a fixed binary sequence B with a length of n to perform a convolution operation and then perform a sliding average of the calculation results with a length of m.

[0092] Specifically, the signal processing device according to this embodiment is a multi-level computing system. Assume that the fixed binary sequence B is the same as that in the fifth embodiment. Assume that each value of an infinite length numerical sequence A is sequentially input to the signal processing device from the data input terminal 104, and the value input to the device at a certain moment is A. i .

[0093] Suppose the address pointer for calculating the convolution in the current control unit 300 is x, and the address pointer for calculating the sliding average is y. The calculation subunit temporarily stores the odd items of the A sequence and M left over from the previous calculation. odd With even terms and M even The other calculation subunit temporarily stores the sum of the m values ​​calculated last time, M i-1 The random access memory 100 includes two storage subunits, one of which stores the most recently received A. i-n ~A i-1 There are n values ​​in total, and the head address of the sequence is x-1, and the tail address of the sequence is x; another storage subunit of the random access memory 100 stores the most recently calculated R i-m ~R i-1 There are m convolution calculation results in total, and the head address of the sequence is y-1, and the tail address of the sequence is y.

[0094] In one processing cycle of the device, the control unit 300 causes the random access memory 100 to read the value A of the address x. i-n ; The computing subunit for convolution operation performs the following operation and replaces the old value with the new value and temporarily stores it, M odd = M even -A i-n +A i , M even = M odd ; The calculation result is Ri = M odd -M even , after passing through the output multiplexer 206 and the output port 205, the result is output to the result output terminal 105. The control unit 300 writes data A to the x address of the random access memory 100 i The control unit 300 causes the random access memory 100 to read the value R of the y address. i-m The calculation subunit for the sliding average calculation operation performs the following operation and temporarily stores the new value instead of the old value, M i = M i +R i -R i-m , the calculation subunit outputs the calculation result as M i / m; the control unit 300 writes data R to the random access memory 100y address i ; The x address pointer in the control unit 300 is incremented by 1. If the address exceeds n, the address pointer is reset to 0; the y address pointer in the control unit 300 is incremented by 1. If the address exceeds m, the address pointer is reset to 0.

[0095] The above calculation needs to meet the initial conditions: the initial values ​​of all address pointers in the control unit 300 are 0, and the initial values ​​in the random access memory 100 are all 0, and all the values ​​temporarily stored in the two calculation sub-units are 0.

[0096] It should be pointed out that in the above embodiment, the present device implements a two-level computing system, but the present device can implement a computing system with more levels. In the present embodiment, the present device implements a serial multi-level computing system, but the present device can also implement a parallel computing system, for example, by enabling two computing sub-units to simultaneously calculate the sliding average of two input sequences. The data processed in the above embodiment has the characteristics of infinite sequence, finite window, and time sliding. The control unit 300 generates read and write enable and address generation. In this embodiment, two storage sub-units and two computing sub-units are used, and the two have a data flow relationship, and the two computing sub-units in the above embodiment respectively temporarily store M. odd 、M even and M i , are used for calculation in the next cycle. The calculation result of the convolution will be written back to the calculation subunit, and the multiplexer will perform data selection and transmit it to the random access memory 100, and the result is used to calculate the mean.

[0097] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0098] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A signal processing device, comprising: A random access memory, wherein the random access memory is used for storing data; A calculation unit, the calculation unit is connected to the random access memory to obtain the stored data and perform calculations on the stored data; as well as A control unit is connected to the random access memory to control the reading and writing of the random access memory.

2. The signal processing device according to claim 1, wherein: The control unit provides a first control signal to control the reading and writing of the random access memory; the control unit provides a second control signal to control the data path of the computing unit; The first control signal includes at least one selected from a read enable signal, a write enable signal, a read address code, and a write address code.

3. The signal processing device according to claim 1, wherein: The computing unit comprises: A first computing subunit, the first computing subunit being configured to perform a first type of operation; and a second computing subunit, the second computing subunit being configured to perform a second type of operation; The signal processing device further comprises: an operation multiplexer, the operation multiplexer being connected to the first calculation subunit and the second calculation subunit respectively to output the operation result of the first calculation subunit or the second calculation subunit currently operating, Wherein, the first computing subunit and the second computing subunit share a storage subunit of the random access memory; or The data of the first computing subunit and the second computing subunit are respectively stored in different storage subunits in the random access memory.

4. The signal processing device according to claim 1, wherein: The control unit comprises: Control state machine; and An address generator, the address generator is used to generate a read address code and / or a write address code; The control unit configures the working mode and / or working parameters according to requirements to adjust the length of the numerical sequence involved in the calculation and / or adjust the accuracy of the numerical sequence involved in the calculation and / or select an effective calculation subunit and / or select an effective storage subunit in the random access memory.

5. The signal processing device according to claim 1, wherein: The calculation unit calculates the numerical sequence sliding over time; The signal processing device receives an updated value; The control unit sends a read enable to the random access memory, and the read address is the address of the value at the end of the value sequence to be calculated in the random access memory; The random access memory reads out the value at the end of the sliding window of the value sequence to be calculated and transmits it to the selected calculation subunit configured in the calculation unit; The calculation subunit receives the updated value; the calculation subunit performs calculations based on the updated value and the value at the end of the sliding window sequence.

6. The signal processing device according to claim 5, wherein: The calculation of the calculation unit includes at least one selected from sum calculation, difference calculation, convolution calculation and average calculation.

7. The signal processing device according to claim 5, wherein: In a first calculation cycle, the calculation subunit calculates and obtains a first calculation result; the calculation subunit temporarily stores the first calculation result; In a second calculation cycle, the calculation subunit performs calculations according to the updated value, the value at the end of the sliding window sequence and the first calculation result to obtain a second calculation result; The calculation subunit updates the temporarily stored first calculation result to the second calculation result; The control unit sends a write enable to the random access memory, wherein the write address of the write enable is the same as the read address; the update value covers the value at the end of the sequence sliding window, Wherein, when the address pointer in the control unit reaches the window width value, the address pointer is reset to zero; When the address pointer in the control unit does not reach the window width value, the address pointer is incremented by one.

8. The signal processing device according to claim 1, wherein: The signal processing device also includes a data input terminal, a result output terminal and a data multiplexer; The data multiplexer is connected to the data input terminal and the result output terminal respectively to obtain data from the data input terminal or the result output terminal, and stores the data from the data input terminal or the result output terminal as the storage data in the random access memory; The calculation unit acquires the stored data and performs operations on the stored data to obtain result data; the operation unit is also connected to the result output terminal to provide the result data to the result output terminal.

9. The signal processing device according to claim 1, wherein: The signal processing device further comprises: A configuration unit is connected to the control unit and is used to provide configuration parameters for configuring the control unit.

10. The signal processing device according to claim 1, wherein: The signal processing device further comprises: A signal receiving end, wherein the signal receiving end receives a signal to be processed; The calculation unit is connected to the signal receiving end to perform calculation processing on the signal to be processed.

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