A server, computer system and multi-node management method

Abstract

The embodiment of the present application provides a server, a computer system and a multi-node management method, wherein the server includes: a processor node and a connection node, the processor node includes: multiple processors and a first controller, the connection node includes: multiple cable groups; the connection node is used to connect a reference device, and provide multiple processors with multiple data links for data transmission with the reference device through multiple cable groups; the first controller is used to establish a correspondence between the multiple data links and the multiple cable groups; in the process of data transmission between the multiple processors and the reference device, according to the correspondence and the fault status of each data link in the multiple data links, the target cable group with fault is detected from the multiple cable groups. Through the present application, the problem of low efficiency in locating the cable group with fault is solved, thereby achieving the effect of improving the efficiency of locating the cable group with fault.

Description

Technical Field

[0001] The embodiments of the present application relate to the server field, and specifically, to a server, a computer system, and a multi-node management method. Background Art

[0002] In the related art, during the use or installation of the cable group in the server, faults such as improper installation and breakage of high-speed Seders cables may occur. Taking the cable group in the server including the Cable Tray as an example, due to the intricate cables inside the Cable Tray, there are several thousand differential pairs in a single cabinet, and as the number of GPUs in the cabinet increases, the number of GPUs in a single cabinet will increase dramatically, and the number of differential pairs in a single cabinet will increase exponentially, which will lead to a great increase in the number of cables inside the Cable Tray, and the complexity of the Cable Tray will also increase greatly, accompanied by a great increase in the cost of the Cable Tray, which brings great challenges to the maintenance, fault location and detection of the Cable Tray.

[0003] For example, when it is necessary to find specific cable faults (such as breakage) or poor signal quality, traditional manual troubleshooting methods may find it difficult to quickly locate the fault and are prone to errors, resulting in a longer maintenance cycle for the cable group in the server and lower operation and maintenance efficiency, affecting the operation and maintenance efficiency and stability of the server.

[0004] In the related art, no effective solution has been proposed to address the problem of low efficiency in locating a faulty cable group. Summary of the invention

[0005] The embodiments of the present application provide a server, a computer system, and a multi-node management method to at least solve the problem of low efficiency in locating a faulty cable group in the related art.

[0006] According to one embodiment of the present application, a server is provided, comprising: a processor node and a connection node, the processor node comprising: a plurality of processors and a first controller, the connection node comprising: a plurality of cable groups; the connection node is used to connect to a reference device, and provide the plurality of processors with a plurality of data links for data transmission with the reference device through the plurality of cable groups; the first controller is used to establish a correspondence between the plurality of data links and the plurality of cable groups; during data transmission between the plurality of processors and the reference device, a target cable group with a fault is detected from the plurality of cable groups according to the correspondence and the fault status of each data link in the plurality of data links.

[0007] In an exemplary embodiment, the processor node includes: a first storage device, the first storage device is used to store a first firmware of the first controller, the first firmware includes a correspondence between the multiple groups of data links and the multiple cable groups, the first storage device is connected to the first controller; the first controller is used to read the correspondence from the first storage device when a fault state is detected in a first candidate data link to indicate a faulty first data link, and detect the faulty target cable group from the multiple cable groups based on the correspondence and the first data link, wherein each processor among the multiple processors is used to transmit data to the reference device through a corresponding data link in the first candidate data link.

[0008] In an exemplary embodiment, the processor node includes: a plurality of acquisition devices and a target processor, the plurality of acquisition devices being connected to the target processor, and the target processor being connected to the first controller; the plurality of acquisition devices being used to be connected one-to-one with the plurality of cable groups and to acquire actual link parameters of each data link in the plurality of data links, wherein the actual link parameters are used to indicate the quality of data transmission between each processor in the plurality of processors and the reference device through the corresponding data link in the plurality of data links; the plurality of processors being used to be connected one-to-one with first candidate acquisition devices corresponding to the first candidate data link in the plurality of acquisition devices when there is no fault state in the first candidate data link in the plurality of data links for indicating a faulty data link, and to extract the link parameters of each data link in the first candidate data link acquired by the first candidate acquisition device to obtain a first group of link parameters, and to transmit the extracted first group of link parameters to the target processor.

[0009] In an exemplary embodiment, the target processor is used to receive the first set of link parameters extracted and transmitted by the multiple processors, and detect the fault status of each data link in the first candidate data link based on the first set of link parameters to obtain a first set of fault status, and transmit the detected first set of fault information to the first controller, wherein each link parameter in the first set of link parameters is used to indicate the quality of data transmission performed by each processor in the multiple processors to the reference device through the corresponding data link in the first candidate data link, and the first set of fault information includes the first set of fault statuses having a corresponding relationship and the link identifier of each data link in the first candidate data link.

[0010] In an exemplary embodiment, the processor node includes: a first conversion device and a second conversion device, the target processor includes a first processor and a second processor, the first processor and the second processor are both connected to the first controller, the first conversion device is connected to the first processor, the second conversion device is connected to the second processor, the first conversion device is connected to a first group of processors corresponding to the multiple processors, the second conversion device is connected to a second group of processors corresponding to the multiple processors, the second group of processors is processors other than the first group of processors in the multiple processors, the first group of processors is connected to a first group of acquisition devices corresponding to the multiple acquisition devices, the second group of processors is connected to a second group of acquisition devices corresponding to the multiple acquisition devices, the second group of acquisition devices is acquisition devices other than the first group of acquisition devices in the multiple acquisition devices; the first processor is used to receive, through the first conversion device, a second group of link parameters corresponding to the first group of data links in the first candidate data links extracted by the first group of processors; and detect each data link in the first group of data links according to the second group of link parameters. The first controller is used to detect the fault state of each data link in the second group of data links, obtain the second group of fault states, and transmit the second group of fault information to the first controller, wherein each processor in the first group of processors is used to transmit data to the reference device through the corresponding data link in the first group of data links, and the second group of fault information includes the second group of fault states and the link identifiers of the first group of data links with a corresponding relationship; the second processor is used to extract the third group of link parameters of the second group of data links corresponding to the first candidate data links extracted by the second group of processors through the second conversion device; and according to the third group of link parameters, detect the fault state of each data link in the second group of data links, obtain the third group of fault states, and transmit the third group of fault information to the first controller, wherein the second group of processors is used to transmit data to the reference device through the second group of data links, and the third group of fault information includes the third group of fault states and the link identifiers of the second group of data links with a corresponding relationship; wherein the first group of fault states includes the second group of fault states and the third group of fault states, and the first group of link parameters includes the second group of link parameters and the third group of link parameters.

[0011] In an exemplary embodiment, the first processor is used to detect the relationship between each link parameter in the second group of link parameters and the corresponding link parameter threshold, and when it is detected that there is a first reference link parameter in the second group of link parameters that is less than a first link parameter threshold and the difference between the first link parameter threshold and the first link parameter threshold is greater than or equal to a first difference threshold, the failure state of the first reference data link corresponding to the first reference link parameter in the first group of data links is determined as indicating that the first reference data link has failed, and the first link parameter threshold is the link parameter of the first reference data link when the first reference data link has not failed; the second processor is used to detect the relationship between each link parameter in the third group of link parameters and the corresponding second link parameter threshold, and when it is detected that there is a second reference link parameter in the third group of link parameters that is less than the second link parameter threshold and the difference between the second link parameter threshold and the second link parameter threshold is greater than or equal to the second difference threshold, the failure state of the second reference data link corresponding to the second reference link parameter in the second group of data links is determined as indicating that the second reference data link has failed, and the second link parameter threshold is the link parameter of the second reference data link when the second reference data link has not failed; the first data link includes the first reference data link and the second reference data link.

[0012] In an exemplary embodiment, the first controller is used to connect to a reference acquisition device corresponding to a reference processor among the multiple acquisition devices when a fault state is detected in the first candidate data link to indicate a faulty reference data link, wherein the first controller is used to extract reference link parameters of the reference data link corresponding to the reference processor in the first candidate data link acquired by the connected reference acquisition device, and the reference processor is a processor corresponding to the reference data link among the multiple processors.

[0013] In an exemplary embodiment, the processor node includes: a plurality of gating devices, the plurality of gating devices are connected to the plurality of acquisition devices in a one-to-one correspondence, the plurality of gating devices are connected to the plurality of processors in a one-to-one correspondence, and the plurality of gating devices are all connected to the first controller; the first controller is used to send a high-level first control signal to an alternative gating device corresponding to the alternative data link among the plurality of gating devices when a fault state is detected in the first candidate data link to indicate an alternative data link that has not failed, wherein when the first controller sends the high-level first control signal to the alternative gating device, an alternative processor among the plurality of processors is connected to the alternative gating device and the corresponding alternative acquisition device among the plurality of acquisition devices.

[0014] In an exemplary embodiment, the first controller is used to send a low-level first control signal to a reference gating device corresponding to the reference processor among the multiple gating devices when a fault state is detected in the first candidate data link to indicate the reference data link that has failed, wherein when the first controller sends the low-level first control signal to the reference gating device, the first controller extracts the reference link parameters collected by the reference acquisition device through the reference gating device.

[0015] In an exemplary embodiment, each of the plurality of gating devices comprises a first pin, a second pin, a signal input terminal and a data extraction terminal, the first pin being connected to a corresponding processor among the plurality of processors, the second pin being connected to the first controller, the signal input terminal being connected to the first controller, and the data extraction terminal being connected to a corresponding acquisition device among the plurality of acquisition devices; when the first controller sends the first control signal of a low level to the signal input terminal, the second pin is connected to the data extraction terminal; when the first controller sends the first control signal of a high level to the signal input terminal, the first pin is connected to the data extraction terminal.

[0016] In an exemplary embodiment, the processor node includes: a plurality of first connectors and a plurality of acquisition devices, the plurality of first connectors being connected to the plurality of acquisition devices in a one-to-one correspondence, and the plurality of first connectors being connected to the plurality of cable groups in a one-to-one correspondence; the first controller is used to extract a first data link identifier of the first data link from first fault information corresponding to the first data link when a first data link having a fault state indicating a fault is detected in a first candidate data link, obtain a first target connector identifier corresponding to the first data link identifier from data link identifiers and first connector identifiers having a corresponding relationship, obtain a target cable group identifier corresponding to the first target connector identifier from first connector identifiers and cable group identifiers having a corresponding relationship, and determine the cable group corresponding to the target cable group identifier as the target cable group, wherein the first fault information includes the fault state of the first data link and the first data link identifier of the first data link, and the corresponding relationship includes a corresponding relationship between the data link identifier and the connector identifier, and a corresponding relationship between the connector identifier and the cable group identifier.

[0017] In an exemplary embodiment, the reference device includes: a data switch, the data switch includes a second controller, the second controller is connected to the multiple cable groups; the second controller is used to establish a correspondence between the multiple groups of data links and the multiple cable groups; during data transmission between the multiple processors and the reference device, a faulty reference cable group is detected from the multiple cable groups based on the correspondence and the fault status of each data link in the multiple groups of data links.

[0018] In an exemplary embodiment, the data switch includes: a second storage device, the second storage device is used to store a second firmware of the second controller, the second firmware includes a correspondence between the multiple groups of data links and the multiple cable groups, and the second storage device is connected to the second controller; the second controller is used to read the correspondence from the second storage device when a fault state is detected in a second candidate data link to indicate a faulty second data link, and detect the faulty reference cable group from the multiple cable groups based on the correspondence and the second data link, wherein the data switch is used to transmit data to a corresponding processor among the multiple processors through each data link in the second candidate data link, and the second candidate data link is a data link in the multiple groups of data links other than the first candidate data link.

[0019] In an exemplary embodiment, the data switch includes: a switching device and a plurality of second connectors, the switching device is connected to the second controller, the plurality of second connectors are connected to the switching device, the plurality of second connectors are connected to the plurality of cable groups in a one-to-one correspondence, and the plurality of cable groups are connected to the plurality of acquisition devices in a one-to-one correspondence;

[0020] The second controller is used to send an acquisition instruction to the switching device during data transmission between the multiple processors and the reference device, and extract the second link parameter of the second candidate data link collected by the second candidate acquisition device corresponding to the second candidate data link among the multiple acquisition devices collected by the switching device in response to the acquisition instruction, and detect the fault state of the second candidate data link according to the second link parameter, wherein the acquisition instruction is used to request the collection of the second link parameter, and the switching device is used to execute the acquisition instruction.

[0021] In an exemplary embodiment, the second controller is used to detect the relationship between each link parameter in the extracted second link parameters and the corresponding link parameter threshold, and when it is detected that there is a third reference link parameter in the second link parameters that is less than a third link parameter threshold and the difference between the third reference link parameter and the third link parameter threshold is greater than or equal to a third difference threshold, the fault state of the third reference data link is determined as indicating that the third reference data link has failed, wherein the third reference data link is the data link corresponding to the third reference link parameter in the second candidate data link, and the third link parameter threshold is the link parameter of the third reference data link when the third reference data link has not failed.

[0022] In an exemplary embodiment, the second controller is used to obtain the second target connector identifier corresponding to the second data link identifier from the data link identifier and the second connector identifier having a corresponding relationship, and obtain the reference cable group identifier corresponding to the second target connector identifier from the second connector identifier and the cable group identifier having a corresponding relationship, when detecting that a fault state exists in the second candidate data link for indicating a faulty second data link, and determine the cable group corresponding to the reference cable group identifier as the reference cable group, wherein the corresponding relationship includes the corresponding relationship between the data link identifier and the connector identifier, and the corresponding relationship between the connector identifier and the cable group identifier.

[0023] In an exemplary embodiment, the reference device includes: a data switch, the data switch includes: a second controller, the first controller is connected to a management switch, and the second controller is connected to the management switch; the first controller is used to transmit first fault information of the target cable group to the management switch; the second controller is used to transmit second fault information of the reference cable group to the management switch; the management switch is used to transmit the second fault information to the first controller, and transmit the first fault information to the second controller.

[0024] In an exemplary embodiment, the processor node includes: a first interface, the first controller is connected to the first interface, the management switch includes multiple management interfaces, and the first interface is connected to a corresponding first management interface among the multiple management interfaces; the first controller is used to transmit the first fault information to the first management interface through the first interface, and receive the second fault information transmitted by the management switch through the first management interface through the first interface.

[0025] In an exemplary embodiment, the data switch includes: a second interface, the second controller is connected to the second interface, and the second interface is connected to a corresponding second management interface among the multiple management interfaces; the second controller is used to transmit the second fault information to the second management interface through the second interface, and receive the first fault information transmitted by the management switch through the second management interface through the second interface.

[0026] In an exemplary embodiment, the first controller is used to determine the target cable group and the reference cable group as the cable group with faults; and the second controller is used to determine the target cable group and the reference cable group as the cable group with faults.

[0027] According to another embodiment of the present application, a computer system is also provided, including: a management switch, multiple power supply devices and multiple servers, a first group of servers among the multiple servers and the management switch are connected to a first group of power supply devices among the multiple power supply devices, a second group of servers is connected to a second group of power supply devices, the first group of power supply devices is used to power the first group of servers and the management switch, the second group of power supply devices is used to power the second group of servers, the second group of servers is servers other than the first group of servers among the multiple servers, and the second group of power supply devices is power supply devices other than the first group of power supply devices among the multiple power supply devices.

[0028] According to another embodiment of the present application, a multi-node management method is also provided, wherein a server comprises: a plurality of processor nodes and a plurality of connection nodes, each of the processor nodes comprises: a plurality of processors and a first controller, each of the connection nodes comprises: a plurality of cable groups, the connection nodes are used to connect to a reference device, the connection nodes provide the plurality of processors with a plurality of data links for data transmission with the reference device through the plurality of cable groups, the method is applied to the first controller, the method comprises: establishing a correspondence between the plurality of data links and the plurality of cable groups; during data transmission between the plurality of processors and the reference device, detecting a target cable group with a fault from the plurality of cable groups according to the correspondence and the fault status of each data link in the plurality of data links.

[0029] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0030] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0031] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0032] Through this application, since the controller in the server can establish a correspondence between multiple groups of data links and multiple cable groups, during the data transmission process, according to the fault status and correspondence of the monitoring data link, the faulty cable group can be timely identified and located, avoiding the problem of slow positioning of the faulty cable group in the server, time-consuming and error-prone due to manual inspection of each cable one by one in the case of high-density cable interconnection. Therefore, the problem of low efficiency in locating the faulty cable group is solved, and the effect of improving the efficiency of locating the faulty cable group is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of connection between multiple processors and a reference device in an optional server according to an embodiment of the present application;

[0034] Figure 2 is an optional network management topology diagram of processor nodes and reference device nodes according to an embodiment of the present application;

[0035] Figure 3 is an architectural diagram of an optional fault location of a cable group of a server according to an embodiment of the present application;

[0036] Figure 4 This is a schematic diagram of an optional process flow when a server is started normally according to an embodiment of the present application;

[0037] Figure 5 is a flow chart of locating a faulty cable group when a cable group fails according to an embodiment of the present application;

[0038] Figure 6 It is a hardware structure block diagram of a server device of a multi-node management method according to an embodiment of the present application;

[0039] Figure 7 is a flowchart of a multi-node management method according to an embodiment of the present application;

[0040] Figure 8 It is a structural block diagram of a multi-node management device according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0043] First, the terms involved in the embodiments of the present application are explained as follows:

[0044] CPU: Central Processing Unit, central processing unit;

[0045] GPU: Graphics Processing Unit, image processing unit;

[0046] PCIE: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus;

[0047] UPI: Ultra Path Interconnect;

[0048] FW: firmware, the underlying software written in the erasable memory. After the chip is powered on, FW is run to initialize the chip and its peripherals.

[0049] BMC: Baseboard Management Controller, baseboard management controller;

[0050] BIOS: Basic Input / Output System, basic input / output system;

[0051] Serders: Serialization / Deserialization, serial-to-parallel converter;

[0052] Cable Tray: Cable tray.

[0053] In this embodiment, a server is provided, including: a processor node and a connection node, the processor node including: multiple processors and a first controller, the connection node including: multiple cable groups; the connection node is used to connect to a reference device, and provide the multiple processors with multiple groups of data links for data transmission with the reference device through the multiple cable groups; the first controller is used to establish a correspondence between the multiple groups of data links and the multiple cable groups; during the process of data transmission between the multiple processors and the reference device, according to the correspondence and the fault status of each data link in the multiple groups of data links, a faulty target cable group is detected from the multiple cable groups.

[0054] Optionally, in this embodiment, Figure 1 is a schematic diagram of a connection between multiple processors and a reference device in an optional server according to an embodiment of the present application, such as Figure 1 As shown, the server may include but is not limited to a processor node and a connection node, the processor node may include but is not limited to n processors and a first controller, the connection node may include but is not limited to n cable groups, and the reference device may include but is not limited to n reference devices. Multiple processors may be connected to corresponding reference devices in the n reference devices through the cable group in the connection node for data transmission. For example, each of the n processors may be connected to a corresponding connection node in the n connection nodes, and each of the n connection nodes may be connected to a reference device. It should be noted that the number of reference devices may be one or more, and the number of reference devices and the number of connection nodes may be the same or different, but are not limited to the same.

[0055] Optionally, in this embodiment, each of the multiple processors may be, but is not limited to, used for data transmission with a reference device via a data link. For example, each of the multiple processors may be, but is not limited to, include a GPU processor or other processors, and this application does not impose any restrictions on this.

[0056] Optionally, in this embodiment, the first controller can be but is not limited to being used to establish a correspondence between multiple groups of data links and multiple cable groups; during data transmission between multiple processors and a reference device, based on the correspondence and the fault status of each data link in the multiple groups of data links, a faulty target cable group is detected from multiple cable groups. For example, the first controller can be but is not limited to including a BMC controller or other controllers, and the present application does not impose any restrictions on this.

[0057] Optionally, in this embodiment, each processor among the multiple processors may, but is not limited to, transmit data with a reference device via a data link. For example, each processor among the multiple processors may, but is not limited to, transmit data to a reference device via a data link, or, the reference device may, but is not limited to, transmit data to a corresponding processor among the multiple processors via a corresponding data link in the data link. As an optional example, the reference device may, but is not limited to, include a service switch, a router, and the like.

[0058] Optionally, in this embodiment, each group of data links in the multiple groups of data links may, but is not limited to, have a corresponding cable group in the multiple cable groups. It can be understood that a group of data links has a corresponding cable group. As an optional example, a cable group may, but is not limited to, include two cables, and the two cables are used to provide data links in two transmission directions, for example, cable group 1 includes cable 1 and cable 2, wherein cable 1 provides a data link for the processor to transmit data to the reference device, and cable 2 provides a data link for the reference device to transmit data to the processor.

[0059] Optionally, in this embodiment, the connection node may be, but is not limited to, used to connect to a reference device, and provide multiple sets of data links for multiple processors to transmit data with the reference device through multiple cable groups. For example, the multiple cable groups may be, but are not limited to, cable groups in a cable tray, and the cable groups in the cable tray may be, but are not limited to, cable groups including connectors connected to the processor node side and connectors connected to the reference device side. The cable tray may be, but is not limited to, including multiple cable groups, each cable group may be, but is not limited to, used to connect a connector on the processor node side and a connector on the reference device side, and each cable group may be, but is not limited to, including two cables, wherein one cable may be, but is not limited to, used to transmit data in each of the multiple processors to the reference device, and the other cable may be, but is not limited to, used to transmit data in the reference device to each of the multiple processors.

[0060] Optionally, in this embodiment, the fault status of the data link can be, but is not limited to, used to indicate that the data link has failed or that the data link has not failed. For example, when the fault status of the data link is used to indicate that the data link has failed, the data link may transmit data at a low rate, or the data link may be unable to transmit data, etc.

[0061] Optionally, in this embodiment, during data transmission between multiple processors and a reference device, after detecting a faulty target cable group from multiple cable groups based on the corresponding relationship and the fault status of each data link in the multiple groups of data links, the faulty target cable group can be quickly replaced or maintained, but is not limited to. For example, the multiple cable groups included in the connection node can be designed to be pluggable, but is not limited to. When a faulty target cable group is detected, the faulty cable group can be directly replaced, thereby improving the efficiency of replacing the faulty cable group.

[0062] Through the above server, since the controller in the server can establish a correspondence between multiple groups of data links and multiple cable groups, during the data transmission process, according to the fault status and correspondence of the monitoring data link, the faulty cable group can be timely identified and located, avoiding the problem of slow positioning of the faulty cable group in the server, time-consuming and error-prone due to manual inspection of each cable one by one in the case of high-density cable interconnection. Therefore, the problem of low efficiency in locating the faulty cable group is solved, and the effect of improving the efficiency of locating the faulty cable group is achieved.

[0063] In an exemplary embodiment, the processor node includes: a first storage device, the first storage device is used to store a first firmware of the first controller, the first firmware includes a correspondence between the multiple groups of data links and the multiple cable groups, the first storage device is connected to the first controller; the first controller is used to read the correspondence from the first storage device when a fault state is detected in a first candidate data link to indicate a faulty first data link, and detect the faulty target cable group from the multiple cable groups based on the correspondence and the first data link, wherein each processor among the multiple processors is used to transmit data to the reference device through a corresponding data link in the first candidate data link.

[0064] Optionally, in this embodiment, the first candidate data link may be, but is not limited to, used to transmit data in the reference device to each processor of the plurality of processors.

[0065] Optionally, in this embodiment, the first storage device may include but is not limited to a storage device for storing the first firmware of the first controller. For example, the first storage device may include but is not limited to a flash memory, or a solid-state drive, etc. For example, the first storage device may include but is not limited to SPI Nor Flash (Serial Peripheral Interface NorFlash, serial peripheral interface non-volatile memory).

[0066] Optionally, in this embodiment, the first firmware may include but is not limited to a program solidified in the first storage device, and the first firmware may include but is not limited to storing the correspondence between multiple groups of data links and multiple cable groups. For example, the first firmware may include but is not limited to the FW in the first storage device.

[0067] Optionally, in this embodiment, the first controller may also, but is not limited to, read the correspondence between the multiple groups of data links and the multiple cable groups stored in the first firmware during the initialization phase of the first controller.

[0068] Optionally, in this embodiment, when the correspondence between multiple groups of data links and multiple cable groups changes, a first adjustment instruction can be sent to the first firmware, but is not limited to adjusting the correspondence between the multiple groups of data links and the multiple cable groups stored in the first firmware to an updated correspondence, wherein the first adjustment instruction is used to adjust the correspondence between the multiple groups of data links and the multiple cable groups stored in the first firmware to an updated correspondence, and the updated correspondence includes the correspondence between the updated group data link and the updated cable groups, the updated group data link is the same as or different from the multiple groups of data links, and the updated cable groups are the same as or different from the multiple cable groups.

[0069] In an exemplary embodiment, the processor node includes: a plurality of acquisition devices and a target processor, the plurality of acquisition devices being connected to the target processor, and the target processor being connected to the first controller; the plurality of acquisition devices being used to be connected one-to-one with the plurality of cable groups and to acquire actual link parameters of each data link in the plurality of data links, wherein the actual link parameters are used to indicate the quality of data transmission between each processor in the plurality of processors and the reference device through the corresponding data link in the plurality of data links; the plurality of processors being used to be connected one-to-one with first candidate acquisition devices corresponding to the first candidate data link in the plurality of acquisition devices when there is no fault state in the first candidate data link in the plurality of data links for indicating a faulty data link, and to extract the link parameters of each data link in the first candidate data link acquired by the first candidate acquisition device to obtain a first group of link parameters, and to transmit the extracted first group of link parameters to the target processor.

[0070] Optionally, in this embodiment, the acquisition device may be but is not limited to being connected to the cable group in a one-to-one correspondence, and collect actual link parameters in the data link. For example, the acquisition device may be but is not limited to including a PHY Retimer (Physical Layer Retimer) chip.

[0071] For example, taking the example that the acquisition device includes a PHY Retimer chip, each PHYRetimer chip among the multiple PHY Retimer chips can, but is not limited to, acquire actual link parameters of a data link used to transmit data in each of the multiple processors to a reference device, and acquire actual link parameters of a data link used to transmit data in the reference device to each of the multiple processors.

[0072] Optionally, in this embodiment, the target processor may be, but is not limited to, used to receive the first set of link parameters extracted from transmissions of multiple processors, the first set of link parameters including link parameters of a data link used by the processor to transmit data to a reference transmission device. For example, the target processor may be, but is not limited to, a CPU, an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device), or other processors, and this application does not impose any restrictions on this.

[0073] Optionally, in this embodiment, it can be, but not limited to, assumed that multiple processors are connected to multiple acquisition devices in a one-to-one correspondence, and it can be, but not limited to, taking multiple processors including multiple GPUs, acquisition devices including PHY Retimer chips, target processors including CPUs, and reference devices including service switches as an example. In the initialization phase of the PHY Retimer chip, each GPU in the multiple GPUs is respectively connected to each PHY Retimer chip in the multiple PHY Retimer chips, and each GPU in the multiple GPUs can, but not limited to, communicate with each PHY Retimer chip in the multiple PHY Retimer chips through a management bus (e.g., MDIO bus) to configure parameters of the PHY Retimer chip, such as setting the transmission rate of data transmission, adjusting the signal level, etc.; in the data transmission phase, as long as the data link detected by the CPU is not faulty, each GPU in the multiple GPUs will continue to maintain connection with each PHY Retimer chip in the multiple PHY Retimer chips to ensure that data can be transmitted to the service switch normally.

[0074] Optionally, in this embodiment, the link parameters may be, but are not limited to, used to indicate the quality of data transmission between each processor among the multiple processors and a reference device through a corresponding data link in the multiple groups of data links. The link parameters may be, but are not limited to, parameters reflecting the quality of data transmission, for example, SI (Signal Integrity) parameters. SI parameters may be, but are not limited to, amplitude-frequency parameters, pulse response parameters, and step response parameters.

[0075] Optionally, in this embodiment, when it is detected that there is an actual link parameter in the actual link parameters that is greater than or equal to the actual link parameter threshold and the difference between the actual link parameter threshold and the actual link parameter difference threshold is less than the actual link parameter difference threshold, the quality of data transmission between each of the multiple processors and the reference device through the corresponding data link in the multiple data links can be determined as normal, but is not limited to; when it is detected that there is an actual link parameter in the actual link parameters that is less than the actual link parameter threshold and the difference between the actual link parameter threshold and the actual link parameter difference threshold is greater than or equal to the actual link parameter difference threshold, the quality of data transmission between each of the multiple processors and the reference device through the corresponding data link in the multiple data links can be determined as abnormal, wherein the actual link parameter threshold and the actual link parameter difference threshold can be determined by, but is not limited to, statistical analysis of historical data or field testing, or other methods that can be used to determine the actual link parameter threshold and the actual link parameter difference threshold, and the present application does not impose any restrictions on this.

[0076] In an exemplary embodiment, the target processor is used to receive the first set of link parameters extracted and transmitted by the multiple processors, and detect the fault status of each data link in the first candidate data link based on the first set of link parameters to obtain a first set of fault status, and transmit the detected first set of fault information to the first controller, wherein each link parameter in the first set of link parameters is used to indicate the quality of data transmission performed by each processor in the multiple processors to the reference device through the corresponding data link in the first candidate data link, and the first set of fault information includes the first set of fault statuses having a corresponding relationship and the link identifier of each data link in the first candidate data link.

[0077] Optionally, in this embodiment, each data link may, but is not limited to, have a one-to-one corresponding link identifier, and the link identifier may, but is not limited to, be used to identify and locate the data link. For example, the link identifier may, but is not limited to, include the number of the data link, the address of the data link, etc.

[0078] Optionally, in this embodiment, each link parameter in the first set of link parameters may be, but is not limited to, used to indicate the quality of data transmission performed by each processor among the multiple processors to a reference device through a corresponding data link in the first candidate data link, wherein each link parameter in the first set of link parameters and the data link for data transmission to the reference device may be, but is not limited to, one-to-one corresponding, for example, one data link corresponds to one link parameter.

[0079] In an exemplary embodiment, the processor node includes: a first conversion device and a second conversion device, the target processor includes a first processor and a second processor, the first processor and the second processor are both connected to the first controller, the first conversion device is connected to the first processor, the second conversion device is connected to the second processor, the first conversion device is connected to a first group of processors corresponding to the multiple processors, the second conversion device is connected to a second group of processors corresponding to the multiple processors, the second group of processors is processors other than the first group of processors in the multiple processors, the first group of processors is connected to a first group of acquisition devices corresponding to the multiple acquisition devices, the second group of processors is connected to a second group of acquisition devices corresponding to the multiple acquisition devices, the second group of acquisition devices is acquisition devices other than the first group of acquisition devices in the multiple acquisition devices; the first processor is used to receive, through the first conversion device, a second group of link parameters corresponding to the first group of data links in the first candidate data links extracted by the first group of processors; and detect each data link in the first group of data links according to the second group of link parameters. The first controller is used to detect the fault state of each data link in the second group of data links, obtain the second group of fault states, and transmit the second group of fault information to the first controller, wherein each processor in the first group of processors is used to transmit data to the reference device through the corresponding data link in the first group of data links, and the second group of fault information includes the second group of fault states and the link identifiers of the first group of data links with a corresponding relationship; the second processor is used to extract the third group of link parameters of the second group of data links corresponding to the first candidate data links extracted by the second group of processors through the second conversion device; and according to the third group of link parameters, detect the fault state of each data link in the second group of data links, obtain the third group of fault states, and transmit the third group of fault information to the first controller, wherein the second group of processors is used to transmit data to the reference device through the second group of data links, and the third group of fault information includes the third group of fault states and the link identifiers of the second group of data links with a corresponding relationship; wherein the first group of fault states includes the second group of fault states and the third group of fault states, and the first group of link parameters includes the second group of link parameters and the third group of link parameters.

[0080] Optionally, in this embodiment, each data link may, but is not limited to, have a one-to-one corresponding fault state, and may, but is not limited to, detect the fault state corresponding to the data link based on the link parameters collected in real time by the acquisition device. It can be understood that the fault state corresponding to the data link may change or remain unchanged, for example, data link 1 recovers from a fault to normal data transmission, or data link 1 is always normal.

[0081] Optionally, in this embodiment, the second group of fault states may include, but is not limited to, a fault state for indicating that a data link has failed and a fault state for indicating that a data link has not failed.

[0082] Optionally, in this embodiment, the number of processors in the first group of processors and the second group of processors may be, but is not limited to, the same or different. For example, the number of processors in the first group of processors and the second group of processors is both 4, or the number of processors in the first group of processors is 3 and the number of processors in the second group of processors is 5.

[0083] Optionally, in this embodiment, the first conversion device may be, but is not limited to, used to connect the first processor and a corresponding first group of processors among the plurality of processors; the second conversion device may be, but is not limited to, used to connect the second processor and a corresponding second group of processors among the plurality of processors. For example, the conversion device may include, but is not limited to, a PCIE Switch chip.

[0084] In an exemplary embodiment, the first processor is used to detect the relationship between each link parameter in the second group of link parameters and the corresponding link parameter threshold, and when it is detected that there is a first reference link parameter in the second group of link parameters that is less than a first link parameter threshold and the difference between the first link parameter threshold and the first link parameter threshold is greater than or equal to a first difference threshold, the failure state of the first reference data link corresponding to the first reference link parameter in the first group of data links is determined as indicating that the first reference data link has failed, and the first link parameter threshold is the link parameter of the first reference data link when the first reference data link has not failed; the second processor is used to detect the relationship between each link parameter in the third group of link parameters and the corresponding second link parameter threshold, and when it is detected that there is a second reference link parameter in the third group of link parameters that is less than the second link parameter threshold and the difference between the second link parameter threshold and the second link parameter threshold is greater than or equal to the second difference threshold, the failure state of the second reference data link corresponding to the second reference link parameter in the second group of data links is determined as indicating that the second reference data link has failed, and the second link parameter threshold is the link parameter of the second reference data link when the second reference data link has not failed; the first data link includes the first reference data link and the second reference data link.

[0085] Optionally, in this embodiment, the first link parameter threshold and the second link parameter threshold may be, but are not limited to, the same or different.

[0086] Optionally, in this embodiment, when determining that the fault state of the data link is used for the case of a fault, during the process of each of the multiple processors transmitting data (or signal) to the reference device through the corresponding data link, abnormalities such as reduced signal quality or signal interruption may occur.

[0087] In an exemplary embodiment, the first controller is used to connect to a reference acquisition device corresponding to a reference processor among the multiple acquisition devices when a fault state is detected in the first candidate data link to indicate a faulty reference data link, wherein the first controller is used to extract reference link parameters of the reference data link corresponding to the reference processor in the first candidate data link acquired by the connected reference acquisition device, and the reference processor is a processor corresponding to the reference data link among the multiple processors.

[0088] Optionally, in this embodiment, it can be but not limited to taking the first controller including the BMC, the acquisition device including the PHYRetimer chip, and the reference processor including the GPU as an example. When the BMC detects that a reference data link has a fault, the BMC is connected to the PHY Retimer chip corresponding to the GPU corresponding to the reference data link with the fault among multiple GPUs.

[0089] Optionally, in this embodiment, the reference data link may include but is not limited to one or more data links in the first candidate data link, and the reference acquisition device may include but is not limited to one or more acquisition devices corresponding to the reference data link in multiple acquisition devices.

[0090] In an exemplary embodiment, the processor node includes: a plurality of gating devices, the plurality of gating devices are connected to the plurality of acquisition devices in a one-to-one correspondence, the plurality of gating devices are connected to the plurality of processors in a one-to-one correspondence, and the plurality of gating devices are all connected to the first controller; the first controller is used to send a high-level first control signal to an alternative gating device corresponding to the alternative data link among the plurality of gating devices when a fault state is detected in the first candidate data link to indicate an alternative data link that has not failed, wherein when the first controller sends the high-level first control signal to the alternative gating device, an alternative processor among the plurality of processors is connected to the alternative gating device and the corresponding alternative acquisition device among the plurality of acquisition devices.

[0091] Optionally, in this embodiment, the alternative data link may include but is not limited to one data link or multiple data links in the first candidate data link, or all data links in the first candidate data link. When the alternative data link includes multiple data links in the first candidate data link, the first controller may send high-level first control signals to the alternative gating devices corresponding to the alternative data links in batches, so as to realize batch control of the alternative gating devices and improve the control efficiency of the gating devices.

[0092] Optionally, in this embodiment, the high level can be but is not limited to being used to indicate a logic level. For example, the high level can be but is not limited to being used to indicate that the voltage is greater than or equal to a first voltage threshold. The high level can be but is not limited to being represented by a corresponding identifier. For example, the high level can be but is not limited to being represented by identifier 1.

[0093] In an exemplary embodiment, the first controller is used to send a low-level first control signal to a reference gating device corresponding to the reference processor among the multiple gating devices when a fault state is detected in the first candidate data link to indicate the reference data link that has failed, wherein when the first controller sends the low-level first control signal to the reference gating device, the first controller extracts the reference link parameters collected by the reference acquisition device through the reference gating device.

[0094] Optionally, in this embodiment, the reference data link may include but is not limited to one or more data links in the first candidate data link. When the reference data link includes multiple data links in the first candidate data link, the first controller may send low-level first control signals to the reference gating device in batches, but is not limited to, to achieve batch control of the reference gating device and improve the control efficiency of the gating device.

[0095] Optionally, in this embodiment, the low level can be but is not limited to being used to indicate a logic level. For example, the low level can be but is not limited to being used to indicate that the voltage is less than a second voltage threshold. The low level can be but is not limited to being represented by a corresponding identifier. For example, the low level can be but is not limited to being represented by an identifier 0.

[0096] In an exemplary embodiment, each of the plurality of gating devices comprises a first pin, a second pin, a signal input terminal and a data extraction terminal, the first pin being connected to a corresponding processor among the plurality of processors, the second pin being connected to the first controller, the signal input terminal being connected to the first controller, and the data extraction terminal being connected to a corresponding acquisition device among the plurality of acquisition devices; when the first controller sends the first control signal of a low level to the signal input terminal, the second pin is connected to the data extraction terminal; when the first controller sends the first control signal of a high level to the signal input terminal, the first pin is connected to the data extraction terminal.

[0097] Optionally, in this embodiment, when the first controller switches from sending a low-level first control signal to the signal input terminal to sending a high-level first control signal to the signal input terminal, the connection between the second pin and the data extraction terminal is switched to being connected to the first pin; when the first controller switches from sending a high-level first control signal to the signal input terminal to sending a low-level first control signal to the signal input terminal, the connection between the first pin and the data extraction terminal is switched to being connected to the second pin.

[0098] In an exemplary embodiment, the processor node includes: a plurality of first connectors and a plurality of acquisition devices, the plurality of first connectors being connected to the plurality of acquisition devices in a one-to-one correspondence, and the plurality of first connectors being connected to the plurality of cable groups in a one-to-one correspondence; the first controller is used to extract a first data link identifier of the first data link from first fault information corresponding to the first data link when a first data link having a fault state indicating a fault is detected in a first candidate data link, obtain a first target connector identifier corresponding to the first data link identifier from data link identifiers and first connector identifiers having a corresponding relationship, obtain a target cable group identifier corresponding to the first target connector identifier from first connector identifiers and cable group identifiers having a corresponding relationship, and determine the cable group corresponding to the target cable group identifier as the target cable group, wherein the first fault information includes the fault state of the first data link and the first data link identifier of the first data link, and the corresponding relationship includes a corresponding relationship between the data link identifier and the connector identifier, and a corresponding relationship between the connector identifier and the cable group identifier.

[0099] Optionally, in this embodiment, the first fault information may include, but is not limited to, fault information detected by the first processor and transmitted to the first controller, and fault information detected by the second processor and transmitted to the first controller.

[0100] Optionally, in this embodiment, the connector identifier may be but is not limited to being used to identify and locate the connector. For example, the connector identifier may be but is not limited to including the connector number, the connector address, or the connector ID, etc.; the cable group identifier may be but is not limited to being used to identify and locate the cable group. For example, the cable group identifier may be but is not limited to including the cable group number, the cable group address, or the cable group ID, etc.

[0101] In an exemplary embodiment, the reference device includes: a data switch, the data switch includes a second controller, the second controller is connected to the multiple cable groups; the second controller is used to establish a correspondence between the multiple groups of data links and the multiple cable groups; during data transmission between the multiple processors and the reference device, a faulty reference cable group is detected from the multiple cable groups based on the correspondence and the fault status of each data link in the multiple groups of data links.

[0102] Optionally, in this embodiment, the data switch may include, but is not limited to, a service switch or other switches that can be used for data transmission, and this application does not impose any limitation on this.

[0103] Optionally, in this embodiment, a second controller may be deployed in the reference device but is not limited to being deployed. For example, the second controller may be but is not limited to including a controller such as a BMC. The second controller may be but is not limited to being used to establish a correspondence between multiple groups of data links and multiple cable groups. During data transmission between multiple processors and the reference device, a faulty reference cable group is detected from multiple cable groups based on the correspondence and the fault status of each data link in the multiple groups of data links. For example, the second controller may be but is not limited to including a BMC controller or other controllers, and the present application does not impose any restrictions on this.

[0104] Optionally, in this embodiment, during data transmission between multiple processors and a reference device, after detecting a faulty reference cable group from multiple cable groups based on the corresponding relationship and the fault status of each data link in the multiple groups of data links, the faulty reference cable group can be quickly replaced or maintained, but is not limited to.

[0105] In an exemplary embodiment, the data switch includes: a second storage device, the second storage device is used to store a second firmware of the second controller, the second firmware includes a correspondence between the multiple groups of data links and the multiple cable groups, and the second storage device is connected to the second controller; the second controller is used to read the correspondence from the second storage device when a fault state is detected in a second candidate data link to indicate a faulty second data link, and detect the faulty reference cable group from the multiple cable groups based on the correspondence and the second data link, wherein the data switch is used to transmit data to a corresponding processor among the multiple processors through each data link in the second candidate data link, and the second candidate data link is a data link in the multiple groups of data links other than the first candidate data link.

[0106] Optionally, in this embodiment, the reference device may, but is not limited to, transmit data to a corresponding processor among the multiple processors through each data link in the second candidate data link.

[0107] Optionally, in this embodiment, the second storage device may include but is not limited to a storage device storing the second firmware of the second controller. For example, the second storage device may include but is not limited to a flash memory, or a solid state drive, etc. For example, the second storage device may include but is not limited to SPI Nor Flash.

[0108] Optionally, in this embodiment, the second firmware may include but is not limited to a program solidified in the second storage device, and the second firmware may include but is not limited to storing the correspondence between multiple groups of data links and multiple cable groups. For example, the second firmware may include but is not limited to the FW in the first storage device.

[0109] Optionally, in this embodiment, the second controller may also, but is not limited to, read the correspondence between the multiple groups of data links and the multiple cable groups stored in the first firmware during the initialization phase of the second controller.

[0110] Optionally, in this embodiment, when the correspondence between multiple groups of data links and multiple cable groups changes, a second adjustment instruction can be sent to the second firmware, but is not limited to adjusting the correspondence between the multiple groups of data links and the multiple cable groups stored in the second firmware to an updated correspondence, wherein the second adjustment instruction is used to adjust the correspondence between the multiple groups of data links and the multiple cable groups stored in the second firmware to an updated correspondence, and the updated correspondence includes the correspondence between the updated group data link and the updated cable groups, the updated group data link is the same as or different from the multiple groups of data links, and the updated cable groups are the same as or different from the multiple cable groups.

[0111] In an exemplary embodiment, the data switch includes: a switching device and a plurality of second connectors, the switching device is connected to the second controller, the plurality of second connectors are connected to the switching device, the plurality of second connectors are connected to the plurality of cable groups in a one-to-one correspondence, and the plurality of cable groups are connected to the plurality of acquisition devices in a one-to-one correspondence;

[0112] The second controller is used to send an acquisition instruction to the switching device during data transmission between the multiple processors and the reference device, and extract the second link parameter of the second candidate data link collected by the second candidate acquisition device corresponding to the second candidate data link among the multiple acquisition devices collected by the switching device in response to the acquisition instruction, and detect the fault state of the second candidate data link according to the second link parameter, wherein the acquisition instruction is used to request the collection of the second link parameter, and the switching device is used to execute the acquisition instruction.

[0113] Optionally, in this embodiment, the switching device may be but is not limited to being deployed in a data switch, and the switching device may be but is not limited to being used to execute acquisition instructions. For example, the switching device may include but is not limited to an Ethernet switching chip.

[0114] Optionally, in this embodiment, multiple processors in a processor node can, but are not limited to, realize data transmission through connected switching devices. For example, when processor 1 in a processor node wishes to transmit data to processor 2 in the processor node, processor 1 sends data 1 to the connected switching device, and the switching device then transmits the received data 1 to processor 2, thereby realizing data transmission between processor 1 and processor 2.

[0115] In an exemplary embodiment, the second controller is used to detect the relationship between each link parameter in the extracted second link parameters and the corresponding link parameter threshold, and when it is detected that there is a third reference link parameter in the second link parameters that is less than a third link parameter threshold and the difference between the third reference link parameter and the third link parameter threshold is greater than or equal to a third difference threshold, the fault state of the third reference data link is determined as indicating that the third reference data link has failed, wherein the third reference data link is the data link corresponding to the third reference link parameter in the second candidate data link, and the third link parameter threshold is the link parameter of the third reference data link when the third reference data link has not failed.

[0116] Optionally, in this embodiment, each link parameter in the second link parameters may be, but is not limited to, greater than a corresponding link parameter threshold, or less than a corresponding link parameter threshold, or equal to a corresponding link parameter threshold.

[0117] In an exemplary embodiment, the second controller is used to obtain the second target connector identifier corresponding to the second data link identifier from the data link identifier and the second connector identifier having a corresponding relationship, and obtain the reference cable group identifier corresponding to the second target connector identifier from the second connector identifier and the cable group identifier having a corresponding relationship, when detecting that a fault state exists in the second candidate data link for indicating a faulty second data link, and determine the cable group corresponding to the reference cable group identifier as the reference cable group, wherein the corresponding relationship includes the corresponding relationship between the data link identifier and the connector identifier, and the corresponding relationship between the connector identifier and the cable group identifier.

[0118] Optionally, in this embodiment, the reference cable group may be, but is not limited to, the same as or different from the target cable group. For example, the cable groups corresponding to the reference cable group and the target cable group are both cable group 1, or the cable group corresponding to the reference cable group is cable group 1, and the cable group corresponding to the target cable group is cable group 2.

[0119] Optionally, in this embodiment, the second data link may, but is not limited to, correspond to the same cable group as the first data link, or correspond to a different cable group. For example, the second data link and the first data link both correspond to cable group 1, or the second data link corresponds to cable group 1, and the first data link corresponds to cable group 3. It can be understood that the second data link and the first data link are data links provided by the same cable group, or the second data link and the first data link are data links provided by different cable groups.

[0120] In an exemplary embodiment, the reference device includes: a data switch, the data switch includes: a second controller, the first controller is connected to a management switch, and the second controller is connected to the management switch; the first controller is used to transmit first fault information of the target cable group to the management switch; the second controller is used to transmit second fault information of the reference cable group to the management switch; the management switch is used to transmit the second fault information to the first controller, and transmit the first fault information to the second controller.

[0121] Optionally, in this embodiment, the first fault information in the first controller and the second fault information in the second controller may be interacted with each other through, but not limited to, a management switch.

[0122] Optionally, in this embodiment, after the second fault information is transmitted to the first controller and the first fault information is transmitted to the second controller, the first fault information and the second fault information can be displayed on the web (World Wide Web) interface of the first controller, but is not limited to, to improve the efficiency of operation and maintenance personnel in viewing all fault information.

[0123] Optionally, in this embodiment, after the second fault information is transmitted to the first controller and the first fault information is transmitted to the second controller, the second fault information and the first fault information may be displayed on a web interface of the second controller, but is not limited to.

[0124] In an exemplary embodiment, the processor node includes: a first interface, the first controller is connected to the first interface, the management switch includes multiple management interfaces, and the first interface is connected to a corresponding first management interface among the multiple management interfaces; the first controller is used to transmit the first fault information to the first management interface through the first interface, and receive the second fault information transmitted by the management switch through the first management interface through the first interface.

[0125] Optionally, in this embodiment, one of the multiple processors in the processor node may be connected to, but is not limited to, a management interface, and the management interface may include, but is not limited to, a GE interface in a management switch.

[0126] In an exemplary embodiment, the data switch includes: a second interface, the second controller is connected to the second interface, and the second interface is connected to a corresponding second management interface among the multiple management interfaces; the second controller is used to transmit the second fault information to the second management interface through the second interface, and receive the first fault information transmitted by the management switch through the second management interface through the second interface.

[0127] Optionally, in this embodiment, one data switch may be, but is not limited to, connected to one management interface, and the management interface may be, but is not limited to, include a GE (Gigabit Ethernet) interface in the management switch.

[0128] In an exemplary embodiment, the first controller is used to determine the target cable group and the reference cable group as the cable group with faults; and the second controller is used to determine the target cable group and the reference cable group as the cable group with faults.

[0129] Optionally, in this embodiment, the first controller may, but is not limited to, determine the target cable group and the reference cable group as faulty cable groups in combination with the first fault information and the second fault information received from the management switch; the second controller may, but is not limited to, determine the target cable group and the reference cable group as faulty cable groups in combination with the second fault information and the first fault information received from the management switch.

[0130] Through the embodiments of the present application, it is possible to determine the cable group fault by combining the first fault information and the second fault information. Even in a complex server architecture, the faulty cable group can be accurately located and identified, ensuring the rapid repair of the faulty cable group and improving the operation and maintenance efficiency of the cable group in the server.

[0131] In this embodiment, a computer system is also provided, including: a management switch, multiple power supply devices and multiple servers, a first group of servers among the multiple servers and the management switch are connected to a first group of power supply devices among the multiple power supply devices, a second group of servers is connected to a second group of power supply devices, the first group of power supply devices is used to power the first group of servers and the management switch, the second group of power supply devices is used to power the second group of servers, the second group of servers is servers among the multiple servers except the first group of servers, and the second group of power supply devices is power supply devices among the multiple power supply devices except the first group of power supply devices.

[0132] Optionally, in this embodiment, the power supply device may be, but is not limited to, used to supply power to the management switch, multiple processor nodes, and multiple reference devices. For example, the power supply device may be, but is not limited to, include a Power Shelf.

[0133] In order to better understand the application scenarios and workflows of the server in the embodiments of the present application, the application scenarios and workflows of the server in the embodiments of the present application are explained and illustrated below in combination with optional embodiments, which may be applicable to but not limited to the embodiments of the present application.

[0134] It can be but is not limited to the example that the power supply device includes a Power Shelf, the processor node includes a GPU BOX node, each of the multiple processors includes a GPU, the first storage device includes SPI Nor Flash1, the first firmware includes a FW for storing the first controller, the second storage device includes SPI Nor Flash 3, the second firmware includes a FW for storing the second controller, the first controller includes BMC0, the second controller includes BMC1, the first processor includes CPU0, the second processor includes CPU1, the acquisition device includes a PHY Retimer chip, the conversion device includes a PCIE Switch chip, the selection device includes a Mux chip, the connector includes a 112Gbps high-speed connector, the switching device includes an Ethernet switching chip, and the cable group includes a cable group in a Cable Tray.

[0135] Figure 2 is an optional network management topology diagram of processor nodes and reference device nodes according to an embodiment of the present application, such as Figure 2 As shown, the AI ​​Rack server may include, but is not limited to, 2 Power Shelf nodes, n GPU BOX nodes, n switch nodes, and 1 management switch. The management switch includes multiple GE ports (equivalent to multiple management interfaces). Each GPU BOX node and switch node has a GE port (equivalent to the first interface and the second interface) connected to a corresponding GE port among the multiple GE ports on the management switch for communication.

[0136] Figure 3 is an architecture diagram of an optional fault location of a cable group of a server according to an embodiment of the present application, such as Figure 3 As shown, it can be but not limited to Figure 2 The explanation and description are given by taking any processor node and a connected data switch as an example.

[0137] like Figure 3As shown, on the GPU BOX node, 8 GPUs including GPU0 to GPU7 are designed on the GPU BOX node (equivalent to the multiple processors included in the processor node), GPU0 to GPU3 are equivalent to the first group of processors, GPU4 to GPU7 are equivalent to the second group of processors, 8 PHY Retimer0 to PHY Retimer7 chips with a rate of 112Gbps (Gigabits per second), 8 Mux0 to Mux7 chips, and 1 BMC chip (for example, BMC0, equivalent to the first controller), 2 PCIE Switch chips (equivalent to the first conversion device and the second conversion device), 2 CPU chips (equivalent to the first processor and the second processor), and a SPI Nor Flash chip mounted under the BMC chip (equivalent to the first storage device, for example, SPI Nor Flash 1 mounted under BMC 0) are also designed.

[0138] The high-speed link design is as follows: CPU0 (equivalent to the first processor) and CPU1 (equivalent to the second processor) respectively output PCIE x16 high-speed links to connect to two PCIE Switch chips. At the same time, CPU0 and CPU1 are interconnected through UPI high-speed links. PCIE Switch0 chip is connected to GPU0 to GPU3 through 4 downstream PCIE x16 high-speed links. PCIE Switch1 chip is connected to GPU4 to GPU7 through 4 downstream PCIE x16 high-speed links. GPU0 to GPU7 respectively output x16 112Gbps Seders and connect to PHY Retimer0 to PHY Retimer7 chips. PHY Retimer0 to PHY Retimer7 chips (equivalent to multiple acquisition devices) respectively output x16 112Gbps Serders and connect to 112Gbps high-speed connectors. The 112Gbps high-speed connector is then connected to the Cable Tray. The cable in the Cable Tray carries 112Gbps Serders and is connected to the Ethernet switching chip (equivalent to the switching device) of the switch node. SPI Nor Flash 0 is mounted under CPU0, and SPI Nor Flash 0 may store, but is not limited to, an operating system of CPU0 and a firmware of CPU0.

[0139] The low-speed management link of the GPU BOX node is designed as follows: the BMC0 chip and the GPU0 module each have an MDIO link connected to the Mux0 chip, and the Select0 signal (equivalent to the first control signal) of the Mux0 chip is connected to the BMC0 chip. The BMC sends the Select0 signal to control whether the MDIO (Management Data Input / Output) of the output end (equivalent to the data extraction end) of the Mux0 chip comes from BMC0 or GPU0. When the Select0 signal (equivalent to the first control signal) is at a low level, the 1 pin (equivalent to the second pin) on the Mux0 chip is connected to the output end of the Mux0 chip, and the MDIO of the output end of the Mux0 chip comes from BMC0; when the Select0 signal is at a high level, the 0 pin (equivalent to the first pin) on the Mux0 chip is connected to the output end of the Mux0 chip, and the MDIO of the output end of the Mux0 chip comes from GPU0. The output MDIO link of Mux0 is connected to the PHY Retimer0 chip, and the link status of the PHY Retimer0 chip and the Ethernet switch chip of the opposite service switch node is obtained and managed; similarly, the MDIO output of BMC0 is also connected to the Mux1 to Mux7 chips, and the MDIO link output of GPU1 to GPU7 is also connected to the Mux1 to Mux7 chips. BMC0 controls whether the output MDIO signal of the Mux0 to Mux7 chips comes from BMC0 or from GPU0 to GPU7 by sending the Select[7:0] signal; CPU0 hangs SPI Nor Flash0 through the SPI chain to store BIOS FW, BMC0 hangs SPI Nor Flash1 through the SPI link to store BMC0's FW, and BMC0 connects the GE port of the management switch node through the RGMII (Reduced Gigabit Media Independent Interface) link output GE port.

[0140] On the service switch node, an Ethernet switch chip, an ARM CPU chip, a BMC chip (equivalent to the second controller, for example, BMC1), and an SPI Nor Flash chip mounted under the BMC chip (equivalent to the second storage device, for example, SPI Nor Flash 3 mounted under BMC1) are designed. The ARM (Advanced RISC (Reduced Instruction Set Computing) Machines) CPU is connected to the Ethernet switch chip through a high-speed link of PCIE x2. The ARM CPU hangs the SPI Nor Flash 2 chip through the SPI link to store the FW and OS (Operating System) of the ARM CPU. The BMC1 hangs the SPI Nor Flash 3 chip through the SPI link to store the FW of BMC1. At the same time, BMC1 is connected to the Ethernet switch chip through the MDIO link to obtain the link status information between the Ethernet switch chip and the PHY Retimer chip of the GPU BOX node. BMC1 is connected to the GE port of the management switch node through the RGMII link GE port. At the same time, the 112Gbps serders from PHY Retimer0 to PHYRetimer7 of the GPU BOX node are connected to the 112Gbps high-speed connector on the board, and the high-speed connector is connected to the Cable Tray, which is then connected to the Ethernet switching chip on the service switch. At this point, the 112Gbps serders from GPU BOX0 to GPU BOXn nodes to the service switch node 0 and the service switch node n are interconnected through the Cable Tray.

[0141] Through the above embodiments, a general architecture design for Cable Tray fault location of an AI Rack (Artificial Intelligence Rack) server (equivalent to a server) mentioned in the embodiments of the present application is provided. Based on the implementation scheme of this server, the problem of Cable Tray fault location and maintenance difficulties on the mainstream AI Rack servers in the industry can be solved. This solution architecture design is simple, flexible and low-cost. It only requires a set of system board designs combined with the interconnection scheme of each node inside the AI ​​Rack and the BMC code design. It can effectively solve the challenges and difficulties encountered in the current Cable Tray fault location, greatly simplify the system design, greatly improve the system reliability, shorten the Cable Tray maintenance time, reduce the maintenance cost, and solve the existing problems of the AI ​​Rack server in the industry. At the same time, the architecture has strong versatility and can be transplanted to the Cable Tray fault location of switches and router cabinets, so it has a high market value.

[0142] Figure 4 is a schematic diagram of an optional process flow when a server is started normally according to an embodiment of the present application, such as Figure 4 As shown in the figure, the process of normal server startup is as follows:

[0143] Step 1: After the system is powered on, first check whether the n GPU BOX nodes and n service switch nodes of the system have been powered on. If they have not been powered on, the system has a hardware failure and needs to be repaired. After the repair is completed, power it on again.

[0144] Step 2: After power-on, CPU0 loads BIOS FW from SPI Nor Flash0, and BMC0 and BMC1 load FW from SPI Nor Flash1 / 3 respectively. BMC0's FW contains the correspondence between the lane number of the entire system (equivalent to the data link identifier) ​​and the wafe (chip group, equivalent to the cable group) in the cable tray, and BMC1's FW contains the correspondence between the lane number of the entire system (equivalent to the link identifier) ​​and the wafe in the cable tray. ARMCPU loads FW from SPI Nor Flash2, CPU0, CPU1, BMC0, BMC1, and ARM CPU complete the startup. At this time, CPU0 and CPU1 of the GPU BOX node establish PCIE connections with PCIE Switch0 and Switch1 respectively, and PCIE Switch0 and PCIE Switch1 establish PCIE connections with GPU0 to GPU7 respectively, completing the identification action of CPU0 and 1 to 8 GPUs; at the same time, the service switch node ARM CPU completes the configuration of the Ethernet switch chip through the PCIE x2 high-speed link, including the configuration register, the working mode of the Ethernet switch chip, etc.

[0145] Step 3: BMC0 of the GPU BOX node sends Select[7:0] to Mux7 to Mux0 chips, controlling the output MDIO data of the Mux chips to come from GPU7 to GPU0. Next, GPU0 to GPU7 of the GPU BOX node complete the startup and configure PHY Retimer0 to PHY Retimer7 through the MDIO bus, including configuring the rate, working mode, etc.

[0146] Step 4: PHY Retimer0 to PHY Retimer7 of the GPU BOX node send signals to the Ethernet switching chip of the service switch node through the x16 112Gbps Serders link to establish a connection. The Ethernet switching chip of the service switch node sends signals to the PHYRetimer0 to PHY Retimer7 chips of the GPU BOX node through the x16 112Gbps Serders link to establish a connection.

[0147] Step 5: At this point, PHY Retimer0 to PHY Retimer7 of the GPU BOX node have established a connection with the Ethernet switching chip of the service switch node.

[0148] Step 6: If the connection is established successfully, it works normally. If the connection fails, the bandwidth of the connection is less than x16 or a Link Down fault occurs, and the Cable Tray hardware fault needs to be located.

[0149] Through the above steps, after the GPU BOX node and service switch node of the entire cabinet AI Rack (equivalent to the server) are powered on, the PHY Retimer chip and the Ethernet switch chip are connected to each other through 112Gbps Serders.

[0150] Figure 5 is a flow chart of locating a faulty cable group when a cable group fails according to an embodiment of the present application, such as Figure 5 As shown in the figure, when a cable group fails, the process of locating the cable group is as follows:

[0151] Step 1: After the Cable Tray link fails, the GPU BOX node BMC0 sends a Select[7:0] signal to control the MDIO link output from the Mux7 to the Mux0 chip from BMC0 (equivalent to sending the first control signal of a low level).

[0152] Step 2: Next, BMC0 sends a command to PHY Retimer0 to PHY Retimer7 chips through the MDIO link to obtain the 112Gbps Serdes signal quality sent by the Ethernet switch chip on the service switch node to the PHY Retimer chip. At the same time, BMC1 on the service switch node sends a command to the Ethernet switch chip through the MDIO link to obtain the 112Gbps Serdes signal quality sent by PHY Retimer0 to PHY Retimer7 chips on the GPU BOX node to the Ethernet switch chip. Since the PHY Retimer chip can detect the signal quality sent by the Ethernet switch chip and the link up / down (link establishment / disconnection) status, the Ethernet switch chip can also detect the signal quality sent by the PHY Retimer chip and the link up / down status.

[0153] Step 3: PHY Retimer0 to PHY Retimer7 chips transfer the lane number of the failed connection to BMC0 through the MDIO link. At the same time, the Ethernet switch chip transfers the lane number of the failed connection with PHY Retimer0 to PHY Retimer7 chips through the MDIO link to BMC1. Next, BMC0 sends the lane number data of the failed connection detected by PHY Retimer0 to PHY Retimer7 chips to the management switch through the GE port, and finally to the BMC1 of the service switch node. At the same time, BMC0 can also obtain the reason for the failed connection from PHY Retimer0 to 7 chips. The specific reasons are: poor SI signal quality and cable breakage. At the same time, BMC1 sends the lane number data of the failed connection detected by the service switch node to the management switch through the GE port, and finally to the BMC0 of the GPUBOX node. At this time, BMC0 of the GPU Box node and BMC1 of the service switch node have obtained the Lane number of the failed connection and the reason for the failure.

[0154] Step 4: BMC0 compares the failed lane number with its internal mapping table (equivalent to the correspondence between multiple data links and multiple cable groups), and prints out on the BMC0 web page which wafe of which lane of which connector in the Cable Tray needs to be replaced. At the same time, BMC1 compares the failed lane number with its internal mapping table, and prints out on the BMC1 web page which wafe of which lane of which connector in the Cable Tray needs to be replaced.

[0155] Step 6: According to the fault information printed on the web pages of BMC0 and BMC1, find out which service switch node to which GPU BOX node, which connector, and which WAFE (chip set) the cable corresponding to is faulty, and quickly replace and maintain it.

[0156] Step 7: End.

[0157] Through the above embodiments, Cable Tray is currently the industry's most advanced solution for GPU interconnection on AI Rack servers. Its disadvantages are high price, high complexity, high maintenance cost, and difficulty in fault location. The technical solution proposed in this application can effectively solve the challenges and difficulties encountered in the current Cable Tray fault location, greatly simplify the system design, shorten the AI ​​RACK maintenance time, reduce maintenance costs, and greatly improve system reliability.

[0158] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 6 1 is a hardware structure block diagram of a server device of a multi-node management method in an embodiment of the present application. Figure 6 As shown, the server device may include one or more ( Figure 6 Only one is shown in the figure) a processor 602 (the processor 602 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 604 for storing data, wherein the above-mentioned server device may also include a transmission device 606 and an input and output device 608 for communication functions. It can be understood by those skilled in the art that Figure 6 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 6 More or fewer components as shown, or with Figure 6 Different configurations are shown.

[0159] The memory 604 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the multi-node management method in the embodiment of the present application. The processor 602 executes various functional applications and data processing by running the computer program stored in the memory 604, that is, the above method is implemented. The memory 604 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 604 may further include a memory remotely arranged relative to the processor 602, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0160] The transmission device 606 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 606 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 606 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0161] In this embodiment, a multi-node management method is provided. Figure 7 is a flowchart of a multi-node management method according to an embodiment of the present application, such as Figure 7As shown, the server includes: a plurality of processor nodes and a plurality of connection nodes, each of the processor nodes includes: a plurality of processors and a first controller, each of the connection nodes includes: a plurality of cable groups, the connection nodes are used to connect to a reference device, and the connection nodes provide the plurality of processors with a plurality of data links for data transmission with the reference device through the plurality of cable groups, the method is applied to the first controller, and the process includes the following steps:

[0162] Step S702, establishing a correspondence between the plurality of data links and the plurality of cable groups;

[0163] Step S704 , during data transmission between the multiple processors and the reference device, detecting a target cable group with a fault from the multiple cable groups according to the corresponding relationship and the fault status of each data link in the multiple data link groups.

[0164] In the technical solution provided in the above step S702, each data link can be clearly identified, such as a data link ID (Identification) during the hardware design stage, but is not limited to, and each cable group can be clearly identified, such as a cable group ID.

[0165] Optionally, in this embodiment, the correspondence between each data link and the cable group can be recorded but is not limited to forming a data link-cable group mapping relationship table, and the mapping relationship between the data link identifier and the cable group identifier can be recorded in detail in the data link-cable group mapping relationship table but is not limited to.

[0166] Optionally, in this embodiment, when the system configuration changes or the cable group is replaced, the correspondence between the data link and the cable group can be adjusted in time to ensure the accuracy of the correspondence.

[0167] In the technical solution provided in the above step S704, after detecting a target cable group with a fault from multiple cable groups, the target cable group with a fault may be maintained or replaced, but is not limited to the above.

[0168] Through the above steps, the fault status of the data link is continuously monitored during the data transmission process, and the faulty cable group is quickly located through the corresponding relationship, so that anomalies in data transmission can be responded to in time, and the service interruption time caused by the cable group failure is reduced, thereby improving the stability of server operation.

[0169] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0170] In this embodiment, a multi-node management device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0171] Figure 8 is a structural block diagram of a multi-node management device according to an embodiment of the present application, such as Figure 8 As shown, the server includes: a plurality of processor nodes and a plurality of connection nodes, each of the processor nodes includes: a plurality of processors and a first controller, each of the connection nodes includes: a plurality of cable groups, the connection nodes are used to connect to a reference device, and the connection nodes provide the plurality of processors with a plurality of data links for data transmission with the reference device through the plurality of cable groups, and the device is applied to the first controller, and the device includes:

[0172] Establishing module 802, establishing a correspondence between the plurality of data links and the plurality of cable groups;

[0173] The detection module 804 detects a target cable group with a fault from the multiple cable groups according to the corresponding relationship and the fault status of each data link in the multiple groups of data links during data transmission between the multiple processors and the reference device.

[0174] Through the above-mentioned device, the fault status of the data link is continuously monitored during the data transmission process, and the faulty cable group is quickly located through the corresponding relationship, which can respond to abnormalities in data transmission in a timely manner, reduce the service interruption time caused by cable group failure, and thus improve the stability of server operation.

[0175] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0176] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0177] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0178] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0179] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0180] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0181] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0182] An embodiment of the present application also provides a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0183] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0184] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0185] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A server, characterized in that: include: A processor node and a connection node, the processor node comprising: a plurality of processors, a plurality of first connectors and a first controller, the connection node comprising: a plurality of cable groups; The connection node is used to connect to a reference device and provide the multiple processors with multiple groups of data links for data transmission with the reference device through the multiple cable groups; The plurality of first connectors are connected to the plurality of cable groups in a one-to-one correspondence; The first controller is used to establish a correspondence between the multiple groups of data links and the multiple cable groups, wherein the correspondence includes a correspondence between a data link identifier and a connector identifier, and a correspondence between the connector identifier and a cable group identifier; during data transmission between the multiple processors and the reference device, a target cable group with a fault is detected from the multiple cable groups according to the correspondence and a fault state of each data link in the multiple groups of data links; The first controller is further used for, when a fault state is detected in the first candidate data link to indicate a faulty first data link, extracting the first data link identifier of the first data link from the first fault information corresponding to the first data link, obtaining the first target connector identifier corresponding to the first data link identifier from the data link identifier and the first connector identifier having a corresponding relationship, obtaining the target cable group identifier corresponding to the first target connector identifier from the first connector identifier and the cable group identifier having a corresponding relationship, and determining the cable group corresponding to the target cable group identifier as the target cable group, wherein the first fault information includes the fault state of the first data link and the first data link identifier of the first data link.

2. The server according to claim 1, characterized in that: The processor node includes: a first storage device, the first storage device is used to store a first firmware of the first controller, the first firmware includes a correspondence between the multiple groups of data links and the multiple cable groups, the first storage device is connected to the first controller; The first controller is used to read the corresponding relationship from the first storage device when a fault state is detected in the first candidate data link to indicate a faulty first data link, and detect the faulty target cable group from the multiple cable groups based on the corresponding relationship and the first data link, wherein each of the multiple processors is used to transmit data to the reference device through a corresponding data link in the first candidate data link.

3. The server according to claim 2, characterized in that: The processor node includes: a plurality of acquisition devices and a target processor, the plurality of acquisition devices are connected to the target processor, and the target processor is connected to the first controller; The multiple acquisition devices are used to be connected to the multiple cable groups in a one-to-one correspondence, and to acquire actual link parameters of each data link in the multiple data link groups, wherein the actual link parameters are used to indicate the quality of data transmission between each processor in the multiple processors and the reference device through the corresponding data link in the multiple data link groups; The multiple processors are used to connect one-to-one with the first candidate acquisition devices corresponding to the first candidate data link in the multiple acquisition devices when there is no fault state in the first candidate data link in the multiple groups of data links to indicate a faulty data link, and extract the link parameters of each data link in the first candidate data link collected by the first candidate acquisition device to obtain a first group of link parameters, and transmit the extracted first group of link parameters to the target processor.

4. The server according to claim 3, characterized in that: The target processor is used to receive the first group of link parameters extracted and transmitted by the multiple processors, and detect the fault status of each data link in the first candidate data link based on the first group of link parameters to obtain a first group of fault status, and transmit the detected first group of fault information to the first controller, wherein each link parameter in the first group of link parameters is used to indicate the quality of data transmission performed by each processor in the multiple processors to the reference device through the corresponding data link in the first candidate data link, and the first group of fault information includes the first group of fault statuses having a corresponding relationship and the link identifier of each data link in the first candidate data link.

5. The server according to claim 4, characterized in that: The processor node includes: a first conversion device and a second conversion device, the target processor includes a first processor and a second processor, the first processor and the second processor are both connected to the first controller, the first conversion device is connected to the first processor, the second conversion device is connected to the second processor, the first conversion device is connected to a first group of processors corresponding to the plurality of processors, the second conversion device is connected to a second group of processors corresponding to the plurality of processors, the second group of processors is the processors other than the first group of processors in the plurality of processors, the first group of processors is connected to a first group of acquisition devices corresponding to the plurality of acquisition devices, the second group of processors is connected to a second group of acquisition devices corresponding to the plurality of acquisition devices, and the second group of acquisition devices is the acquisition devices other than the first group of acquisition devices in the plurality of acquisition devices; The first processor is used to receive, through the first conversion device, a second group of link parameters of the first group of data links corresponding to the first candidate data links extracted by the first group of processors; and detect the fault status of each data link in the first group of data links according to the second group of link parameters, obtain a second group of fault status, and transmit the second group of fault information to the first controller, wherein each processor in the first group of processors is used to transmit data to the reference device through a corresponding data link in the first group of data links, and the second group of fault information includes the second group of fault status and the link identifier of the first group of data links having a corresponding relationship; The second processor is used to extract, through the second conversion device, a third group of link parameters of the second group of data links corresponding to the first candidate data links extracted by the second group of processors; and detect the fault status of each data link in the second group of data links according to the third group of link parameters, obtain a third group of fault status, and transmit the third group of fault information to the first controller, wherein the second group of processors is used to transmit data to the reference device through the second group of data links, and the third group of fault information includes the third group of fault status and the link identifier of the second group of data links having a corresponding relationship; The first group of fault states includes the second group of fault states and the third group of fault states, and the first group of link parameters includes the second group of link parameters and the third group of link parameters.

6. The server according to claim 5, characterized in that: the first processor being configured to detect a relationship between each link parameter in the second group of link parameters and a corresponding link parameter threshold, and, when detecting that there is a first reference link parameter in the second group of link parameters that is less than a first link parameter threshold and whose difference with the first link parameter threshold is greater than or equal to a first difference threshold, determine a failure state of a first reference data link corresponding to the first reference link parameter in the first group of data links as indicating that the first reference data link has failed, wherein the first link parameter threshold is a link parameter of the first reference data link when the first reference data link has not failed; the second processor is configured to detect a relationship between each link parameter in the third group of link parameters and a corresponding second link parameter threshold, and when detecting that there is a second reference link parameter in the third group of link parameters that is less than the second link parameter threshold and whose difference with the second link parameter threshold is greater than or equal to a second difference threshold, determine a fault state of a second reference data link corresponding to the second reference link parameter in the second group of data links as indicating that the second reference data link has failed, the second link parameter threshold being a link parameter of the second reference data link when the second reference data link has not failed; The first data link includes the first reference data link and the second reference data link.

7. The server according to claim 3, characterized in that: The first controller is used to connect to a reference acquisition device corresponding to a reference processor among the multiple acquisition devices when a fault state is detected in the first candidate data link to indicate a faulty reference data link, wherein the first controller is used to extract reference link parameters of the reference data link corresponding to the reference processor in the first candidate data link acquired by the connected reference acquisition device, and the reference processor is a processor corresponding to the reference data link among the multiple processors.

8. The server according to claim 7, characterized in that: The processor node comprises: a plurality of gating devices, the plurality of gating devices are connected to the plurality of acquisition devices in a one-to-one correspondence, the plurality of gating devices are connected to the plurality of processors in a one-to-one correspondence, and the plurality of gating devices are all connected to the first controller; The first controller is used to send a high-level first control signal to an alternative gating device corresponding to the alternative data link among the multiple gating devices when a fault state is detected in the first candidate data link to indicate an alternative data link that has not failed, wherein when the first controller sends the high-level first control signal to the alternative gating device, an alternative processor among the multiple processors is connected to the alternative gating device and a corresponding alternative acquisition device among the multiple acquisition devices.

9. The server according to claim 8, characterized in that: The first controller is used to send a low-level first control signal to a reference gating device corresponding to the reference processor among the multiple gating devices when a fault state is detected in the first candidate data link to indicate the reference data link that has failed, wherein when the first controller sends the low-level first control signal to the reference gating device, the first controller extracts the reference link parameters collected by the reference acquisition device through the reference gating device.

10. The server according to claim 8, characterized in that: Each of the plurality of gating devices comprises a first pin, a second pin, a signal input terminal and a data extraction terminal, the first pin is connected to a corresponding processor among the plurality of processors, the second pin is connected to the first controller, the signal input terminal is connected to the first controller, and the data extraction terminal is connected to a corresponding acquisition device among the plurality of acquisition devices; When the first controller sends the first control signal of a low level to the signal input terminal, the second pin is connected to the data extraction terminal; When the first controller sends the first control signal of a high level to the signal input terminal, the first pin is connected to the data extraction terminal.

11. The server according to claim 2, characterized in that: The processor node further includes: a plurality of acquisition devices, and the plurality of first connectors are connected to the plurality of acquisition devices in a one-to-one correspondence.

12. The server according to claim 1, characterized in that: The reference device includes: a data switch, the data switch includes a second controller, and the second controller is connected to the plurality of cable groups; The second controller is used to establish a correspondence between the multiple groups of data links and the multiple cable groups; during the process of data transmission between the multiple processors and the reference device, based on the correspondence and the fault status of each data link in the multiple groups of data links, a faulty reference cable group is detected from the multiple cable groups.

13. The server according to claim 12, characterized in that: The data switch comprises: a second storage device, the second storage device is used to store a second firmware of the second controller, the second firmware includes a correspondence between the multiple groups of data links and the multiple cable groups, and the second storage device is connected to the second controller; The second controller is used to read the corresponding relationship from the second storage device when a fault state is detected in the second candidate data link to indicate a faulty second data link, and detect the faulty reference cable group from the multiple cable groups based on the corresponding relationship and the second data link, wherein the data switch is used to transmit data to a corresponding processor among the multiple processors through each data link in the second candidate data link, and the second candidate data link is a data link in the multiple groups of data links except the first candidate data link.

14. The server according to claim 13, characterized in that: The data switch comprises: a switching device and a plurality of second connectors, the switching device is connected to the second controller, the plurality of second connectors are connected to the switching device, the plurality of second connectors are connected to the plurality of cable groups in a one-to-one correspondence, and the plurality of cable groups are connected to the plurality of acquisition devices in a one-to-one correspondence; The second controller is used to send an acquisition instruction to the switching device during data transmission between the multiple processors and the reference device, and extract the second link parameter of the second candidate data link collected by the second candidate acquisition device corresponding to the second candidate data link among the multiple acquisition devices collected by the switching device in response to the acquisition instruction, and detect the fault state of the second candidate data link according to the second link parameter, wherein the acquisition instruction is used to request the collection of the second link parameter, and the switching device is used to execute the acquisition instruction.

15. The server according to claim 14, characterized in that: The second controller is used to detect the relationship between each link parameter in the extracted second link parameters and the corresponding link parameter threshold, and when it is detected that there is a third reference link parameter in the second link parameters that is less than a third link parameter threshold and the difference between the third reference link parameter and the third link parameter threshold is greater than or equal to a third difference threshold, determine the fault state of the third reference data link as indicating that the third reference data link has failed, wherein the third reference data link is a data link corresponding to the third reference link parameter in the second candidate data link, and the third link parameter threshold is a link parameter of the third reference data link when the third reference data link has not failed.

16. The server according to claim 15, characterized in that The second controller is used to obtain the second target connector identifier corresponding to the second data link identifier from the data link identifier and the second connector identifier having a corresponding relationship, and obtain the reference cable group identifier corresponding to the second target connector identifier from the second connector identifier and the cable group identifier having a corresponding relationship, when detecting that a fault state exists in the second candidate data link for indicating a faulty second data link, and determine the cable group corresponding to the reference cable group identifier as the reference cable group, wherein the corresponding relationship includes the corresponding relationship between the data link identifier and the connector identifier, and the corresponding relationship between the connector identifier and the cable group identifier.

17. The server according to claim 1, characterized in that: The reference device comprises: a data switch, the data switch comprises: a second controller, the first controller is connected to a management switch, and the second controller is connected to the management switch; The first controller is used to transmit the first fault information of the target cable group to the management switch; The second controller is used to transmit second fault information of the reference cable group to the management switch; The management switch is used to transmit the second fault information to the first controller, and transmit the first fault information to the second controller.

18. The server according to claim 17, characterized in that: The processor node comprises: a first interface, the first controller is connected to the first interface, the management switch comprises a plurality of management interfaces, the first interface is connected to a corresponding first management interface among the plurality of management interfaces; The first controller is configured to transmit the first fault information to the first management interface through the first interface, and receive, through the first interface, the second fault information transmitted by the management switch through the first management interface.

19. The server according to claim 18, characterized in that The data switch comprises: a second interface, the second controller is connected to the second interface, and the second interface is connected to a corresponding second management interface among the multiple management interfaces; The second controller is configured to transmit the second fault information to the second management interface through the second interface, and receive the first fault information transmitted by the management switch through the second management interface through the second interface.

20. The server according to claim 19, characterized in that The first controller is configured to determine the target cable group and the reference cable group as failed cable groups; The second controller is configured to determine the target cable group and the reference cable group as faulty cable groups.

21. A computer system, characterized in that: include: A management switch, multiple power supplies and multiple servers as described in any one of claims 1 to 20, a first group of servers among the multiple servers and the management switch are connected to a first group of power supplies among the multiple power supplies, a second group of servers is connected to a second group of power supplies, the first group of power supplies is used to power the first group of servers and the management switch, the second group of power supplies is used to power the second group of servers, the second group of servers is servers other than the first group of servers among the multiple servers, and the second group of power supplies is power supplies other than the first group of power supplies among the multiple power supplies.

22. A multi-node management method, characterized in that: The server includes: a plurality of processor nodes and a plurality of connection nodes, each of the processor nodes includes: a plurality of processors, a plurality of first connectors and a first controller, each of the connection nodes includes: a plurality of cable groups, the plurality of first connectors are connected to the plurality of cable groups in a one-to-one correspondence, the connection nodes are used to connect to a reference device, the connection nodes provide the plurality of processors with a plurality of data links for data transmission with the reference device through the plurality of cable groups, the method is applied to the first controller, the method includes: Establishing a correspondence between the plurality of data link groups and the plurality of cable groups, the correspondence comprising a correspondence between data link identifiers and connector identifiers, and a correspondence between the connector identifiers and cable group identifiers; In the process of data transmission between the multiple processors and the reference device, according to the corresponding relationship and the fault status of each data link in the multiple groups of data links, detecting a target cable group with a fault from the multiple cable groups; Wherein, the detecting of a target cable group with a fault from the multiple cable groups includes: in a case where a fault state is detected in a first candidate data link for indicating a first data link with a fault, extracting a first data link identifier of the first data link from first fault information corresponding to the first data link, obtaining a first target connector identifier corresponding to the first data link identifier from a data link identifier and a first connector identifier having a corresponding relationship, and obtaining a target cable group identifier corresponding to the first target connector identifier from a first connector identifier and a cable group identifier having a corresponding relationship, and determining the cable group corresponding to the target cable group identifier as the target cable group, wherein the first fault information includes the fault state of the first data link and the first data link identifier of the first data link.

23. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in claim 22 when executed by a processor.

24. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to claim 22 are implemented.

25. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 22 are implemented.

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