A protection circuit against power consumption attacks for high-reliability anti-modeling double-layer APUF

Abstract

The invention relates to the field of digital integrated circuit design and security and anti-counterfeiting technology, and discloses a protection circuit for anti-power consumption attack of a high-reliability anti-modeling double-layer APUF, comprising a high-reliability anti-modeling double-layer APUF module and an anti-power consumption attack module, the high-reliability anti-modeling double-layer APUF module and the anti-power consumption attack module are connected by electrical signals, the high-reliability anti-modeling double-layer APUF module is used to resist external modeling attacks, the anti-power consumption attack module is used to resist external power consumption analysis of the circuit structure, and prevent the outside world from inferring the circuit structure inside the high-reliability anti-modeling double-layer APUF module, the high-reliability anti-modeling double-layer APUF module is composed of a first arbitrator, a second arbitrator and three basic units; and the protection circuit, by adding a path control unit, a path selection unit and an output recovery unit, makes the circuit more resistant to power consumption attacks, increases the difficulty of cracking, and increases the cracking time exponentially.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit design and security and anti-counterfeiting technology, and in particular to a protection circuit for a high-reliability anti-modeling double-layer APUF that is resistant to power consumption attacks. Background Art

[0002] The Physical Unclonable Function (PUF) mainly uses the inevitable random differences in the chip manufacturing process to generate a unique "chip fingerprint", which has natural anti-tampering and anti-cloning capabilities. Therefore, PUF can provide a low-cost and highly secure authentication and key generation method for the Internet of Things, which can effectively solve the security issues of digital technology products.

[0003] Traditional physical unclonable circuits, feedforward circuits, and anti-modeling dual-layer APUFs are a new type of PUF structure that can output extremely high responses while resisting modeling attacks, thus having higher stability and security. However, it also has some potential weaknesses. The correlation between its output and power consumption is relatively obvious. When there is a data dependency between the data processed by the device and its side channel leakage (running time, energy curve, electromagnetic radiation, power consumption, etc.), attackers can use this leaked information to gradually predict its response under specific conditions. Therefore, a protection circuit against power consumption attacks for highly reliable anti-modeling dual-layer APUFs is proposed to solve the above problem. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention provides a protection circuit for anti-power consumption attacks for a highly reliable and anti-modeling double-layer APUF, which has the advantages of strong resistance to power consumption attacks and high difficulty in cracking, and solves the problems mentioned in the above background technology.

[0005] To achieve the above-mentioned purpose of strong anti-power consumption attack capability and high cracking difficulty, the present invention provides the following technical solution: a protection circuit for anti-power consumption attack of a high-reliability anti-modeling double-layer APUF, characterized by comprising a high-reliability anti-modeling double-layer APUF module and an anti-power consumption attack module, the high-reliability anti-modeling double-layer APUF module and the anti-power consumption attack module being electrically connected, the high-reliability anti-modeling double-layer APUF module being used to resist external modeling attacks, and the anti-power consumption attack module being used to resist external power consumption analysis of the circuit structure, thereby preventing the outside world from inferring the internal circuit structure of the high-reliability anti-modeling double-layer APUF module;

[0006] The high-reliability, anti-modeling, double-layer APUF module consists of a first arbitrator, a second arbitrator, and three basic units. The first arbitrator and the second arbitrator are respectively set between any two basic units.

[0007] The anti-power consumption attack module includes a path selection unit, an arbitration unit, a decision unit and an output recovery unit, and the path selection unit, the arbitration unit, the decision unit and the output recovery unit are all connected to circuit signals;

[0008] The path selection unit consists of six multiplexers, each of which is electrically connected to the other. The path selection unit is used to disrupt the delay entering the arbitration unit through the control signal S to mask the power consumption generated by the actual delayed output.

[0009] The arbitration unit consists of six arbiters, all of which are based on D flip-flops. The arbitration unit is used to derive the mutual delay characteristic values ​​between delay paths.

[0010] The decision unit is composed of a custom algorithm and is used to find the two paths with the largest delay difference;

[0011] The output recovery unit is composed of a NOT gate and a two-to-one multiplexer, and is used to restore the correct output.

[0012] Preferably, the output ends of the high-reliability anti-modeling double-layer APUF module are four delay links A, B, C, and D from top to bottom. Pairing the four delay links A, B, C, and D in pairs will produce six results, namely, six combination results of AB, AC, AD, BC, BD, and CD, which serve as inputs of the path selection unit:

[0013] The low level and high level of the control signal S are both 0 and 1, and are positive integers. When the control signal S = 0, that is, the low level, each combination result is transmitted in parallel, and the delay path remains unchanged when output to the arbitration unit. When the control signal S = 1, that is, the high level, each combination result is cross-transmitted, and the delay path changes when output to the arbitration unit.

[0014] Preferably, the six combination results correspond to six D flip-flops in the arbitration unit. The output value of the D flip-flop represents a delay characteristic value of the delay relationship between two paths with inputs. Each D flip-flop is used to compare the delay relationship between the two inputs. Each D flip-flop has two lines, one close to the upper input and one close to the lower input. If the delay of the upper input of the D flip-flop is larger, it outputs 1, otherwise it outputs 0.

[0015] The decision unit performs delay sorting on the four-way delay according to the arbitration result of the delay difference output by the arbitration unit;

[0016] The input end of the NOT gate is electrically connected to the output end of the decision unit, the output end of the NOT gate is electrically connected to the input end of the two-to-one multiplexer, the input end of the two-to-one multiplexer is electrically connected to the output end of the high-reliability anti-modeling double-layer APUF module, the NOT gate is used to provide another path delay result, and the two-to-one multiplexer is used to select the appropriate path as the final output response.

[0017] Preferably, the control signal S is the result of an exclusive OR operation between the first arbitrator and the second arbitrator.

[0018] Preferably, when the results output by the decision units are the same, the two-to-one multiplexer selects the path that passes through the NOT gate for output; when the results output by the decision units are opposite, the two-to-one multiplexer selects the path that does not pass through the NOT gate for output.

[0019] Compared with the prior art, the present invention provides a protection circuit for a highly reliable and model-resistant double-layer APUF against power consumption attacks, which has the following beneficial effects:

[0020] 1. This protection circuit against power consumption attacks for high-reliability and anti-modeling double-layer APUF increases the circuit's resistance to power consumption attacks by adding a path control unit, a path selection unit, and an output recovery unit. This makes cracking more difficult and increases the cracking time exponentially.

[0021] 2. This protection circuit for high-reliability, anti-modeling, two-layer APUFs against power consumption attacks utilizes a two-to-two multiplexer to change the inputs of the D flip-flop, obfuscating the delay comparison results. The output recovery unit then restores the previously altered delays, significantly improving the APUF's resistance to power consumption attacks while ensuring the accuracy of the response results. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the protection circuit structure for a high-reliability, anti-modeling, double-layer APUF against power consumption attacks proposed by the present invention;

[0023] Figure 2 This is a schematic diagram of the internal structure of the power consumption attack protection circuit module for the high-reliability, anti-modeling, double-layer APUF.

[0024] Figure 3 This is a schematic diagram of a protection circuit path selection unit for a high-reliability, anti-modeling, double-layer APUF against power consumption attacks proposed by the present invention;

[0025] Figure 4 A schematic diagram of an arbitration unit for a protection circuit structure against power consumption attacks for a high-reliability, anti-modeling, double-layer APUF proposed by the present invention;

[0026] Figure 5A schematic diagram of a protection circuit structure judgment unit for a high-reliability, anti-modeling, double-layer APUF against power consumption attacks proposed by the present invention;

[0027] Figure 6 This is a schematic diagram of a protection circuit structure path recovery unit proposed by the present invention for a high-reliability, anti-modeling, double-layer APUF that resists power consumption attacks. DETAILED DESCRIPTION

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0029] See also Figure 1-6 A protection circuit for a high-reliability anti-modeling double-layer APUF against power consumption attacks includes a high-reliability anti-modeling double-layer APUF module and an anti-power consumption attack module. The high-reliability anti-modeling double-layer APUF module and the anti-power consumption attack module are electrically connected. The high-reliability anti-modeling double-layer APUF module is used to resist external modeling attacks. While increasing the diversity of signal transmission paths, it makes the circuit more reliable and the generated response more stable. The anti-power consumption attack module is used to resist external power consumption analysis of the circuit structure, preventing the outside world from inferring the circuit structure inside the high-reliability anti-modeling double-layer APUF module; reducing the correlation between device power consumption and stimulus response, and enhancing the double-layer APUF's ability to resist power consumption attacks.

[0030] The high-reliability, anti-modeling, double-layer APUF module consists of a first arbitrator, a second arbitrator, and three basic units. The first arbitrator and the second arbitrator are respectively set between any two basic units.

[0031] The high-reliability and anti-modeling dual-layer APUF module has the same dual-layer APUF circuit structure as the existing patent application number 202410079033.3, named high-reliability and anti-modeling dual-layer APUF circuit structure based on feedforward circuit.

[0032] The anti-power consumption attack module includes a path selection unit, an arbitration unit, a decision unit and an output recovery unit, and the path selection unit, the arbitration unit, the decision unit and the output recovery unit are all connected to circuit signals;

[0033] The path selection unit consists of six multiplexers, each of which is electrically connected to the other. The path selection unit is used to disrupt the delay entering the arbitration unit through the control signal S to mask the power consumption generated by the actual delayed output.

[0034] The arbitration unit consists of six arbiters, all of which are based on D flip-flops. The arbitration unit is used to derive the mutual delay characteristic values ​​between delay paths.

[0035] The decision unit is composed of a custom algorithm and is used to find the two paths with the largest delay difference;

[0036] Specifically, when the control signal S is 0, if the output of the six D flip-flops is '111111', the relationship between the four-way delay is A>B>C>D. Since the path delay relationship remains unchanged, '111111' is still the comparison result of A and B, A and C, A and D, B and C, B and D, and C and D. Therefore, the delay comparison output result of the D flip-flop remains unchanged, and the output recovery module does not work at this time; when S is 1, the two-choose-two multiplexer internal cross transmission changes the delay transmission path. At this time, the output of the D flip-flop is B and A, C and A, D and A The comparison results between C and B, D and B, and D and C are opposite to those when S is 0. Therefore, the four-path delay relationship represented by the output signal '000000' is still A>B>C>D. However, in the decision module, the delay relationship represented by '000000' is D>C>B>A, not A>B>C>D. This will cause the decision module to produce an incorrect output. The premise of anti-power attack is to ensure the correctness of the response. If the response is unstable and incorrect due to power attack, then the anti-power attack is meaningless. Therefore, we need to restore the result. The output recovery module reverses the response to restore the change caused by the previous path change. The final delay relationship remains A>B>C>D, and the response remains unchanged. In another case, when the output signal is '001011', the delay relationship of the four signals is C>B>A>D. When the control signal S is 0, the delay relationship does not change, the recovery module does not work, and the output delay relationship remains C>B>A>D; when the control signal S is 1, the output delay relationship becomes D>A>B>C, so the output restoration module is also required to reverse the response to obtain the correct result.

[0037] The output recovery unit is composed of a NOT gate and a two-to-one multiplexer, and is used to restore the correct output.

[0038] The output of the high-reliability, modeling-resistant, two-layer APUF module consists of four delay links, A, B, C, and D, from top to bottom. Pairing these delay links produces six possible combinations: AB, AC, AD, BC, BD, and CD, which serve as inputs to the path selection unit.

[0039] The low level and high level of the control signal S are both 0 and 1, and are positive integers. When the control signal S = 0, that is, the low level, each combination result is transmitted in parallel, and the delay path remains unchanged when output to the arbitration unit. When the control signal S = 1, that is, the high level, each combination result is cross-transmitted, and the delay path changes when output to the arbitration unit.

[0040] The six combination results correspond to the six D flip-flops in the arbitration unit. The output value of the D flip-flop represents the delay characteristic value of the delay size relationship between the two paths with inputs. Each D flip-flop is used to compare the delay size relationship between the two inputs. Each D flip-flop has two lines, one close to the upper input and one close to the lower input.

[0041] Each D flip-flop has two line inputs, one line input is the data end, that is, the D port, and the other line is the clock end, that is, the CLK port. If the data end signal of the D flip-flop arrives first, the output is 1, otherwise the output is 0;

[0042] Take D flip-flop 1 as an example, A is connected to the CLK input terminal, B is connected to the D input terminal, when the output value AB=1, it means that the rising edge of the A-way signal is slower than the rising edge of the B-way signal, that is, the delay of A is greater than the delay of B, then it can be judged that A>B; if the output value AB=0, it means that the rising edge of the A-way signal is faster than the rising edge of the B-way signal, that is, the delay of A is less than the delay of B, then it can be judged that A>B <B。

[0043] The decision unit performs delay sorting on the four-way delay according to the arbitration result of the delay difference output by the arbitration unit;

[0044] The decision unit sorts the four delay paths based on the arbitration result of the delay difference output by the arbitration unit. For example, when the six output signals are '111111', it can be determined that A>B>C>D. At this time, the delay difference between A and D is the largest, so selecting the output of trigger 3 as the response output is more reliable. However, at this time, the power consumption of the six D flip-flops also reaches its maximum, a feature that can be easily exploited by attackers and becomes the key to cracking the PUF. Therefore, we connect six two-to-two multiplexers before the flip-flops to control whether the four delay paths A, B, C, and D cross transmission. We also connect a two-to-one multiplexer with a NAND gate after the decision module to compensate for changes in the response caused by changing the transmission path. The control signal is S, and S is the result of the exclusive OR of the two arbiters, which can be regarded as a pseudo-random number.

[0045] The input end of the NOT gate is electrically connected to the output end of the decision unit, the output end of the NOT gate is electrically connected to the input end of the two-to-one multiplexer, the input end of the two-to-one multiplexer is electrically connected to the output end of the high-reliability anti-modeling double-layer APUF module, the NOT gate is used to provide another path delay result, and the two-to-one multiplexer is used to select the appropriate path as the final output response.

[0046] The control signal S is the XOR result of the first arbiter and the second arbiter.

[0047] To address the power consumption detection issue, attackers often monitor the power consumption of the D flip-flop. The power consumption difference between the D flip-flop's transition from 0 to 1 and from 1 to 0 is too large. We use a method to obfuscate the delay path to obfuscate this prominent feature of power consumption difference. Since the control signal S is the result of the XOR of the two arbiters and can be regarded as a pseudo-random number, the power consumption generated by the D flip-flop output transition will no longer have special power consumption characteristics. In other words, the detected power consumption has no obvious relationship with the output transition. The dependence of the D flip-flop output transition on power consumption is weakened, so attackers cannot use power consumption as a breakthrough point to crack the APUF, thereby achieving the purpose of resisting power consumption attacks.

[0048] When the results output by the decision unit are the same, the two-to-one multiplexer selects the path that passes through the NOT gate for output. When the results output by the decision unit are opposite, the two-to-one multiplexer selects the path that does not pass through the NOT gate for output.

[0049] In summary, the protection circuit against power consumption attacks for the high-reliability anti-modeling double-layer APUF, by adding a path control unit, a path selection unit and an output recovery unit, makes the circuit more resistant to power consumption attacks, increases the difficulty of cracking, and increases the cracking time exponentially.

[0050] In addition, by using a two-to-two multiplexer to change the input of the D flip-flop, the delay comparison result is confused, and the originally changed delay is restored through the output recovery unit. While ensuring the accuracy of the response result, the APUF's resistance to power consumption attacks is significantly improved.

[0051] It should be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0052] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A protection circuit for high-reliability anti-modeling double-layer APUF against power consumption attacks, characterized in that: It includes a high-reliability anti-modeling double-layer APUF module and an anti-power consumption attack module. The high-reliability anti-modeling double-layer APUF module and the anti-power consumption attack module are connected by electrical signals. The high-reliability anti-modeling double-layer APUF module is used to resist external modeling attacks. The anti-power consumption attack module is used to resist external power consumption analysis of the circuit structure, so as to prevent the outside world from speculating the internal circuit structure of the high-reliability anti-modeling double-layer APUF module. The high-reliability anti-modeling double-layer APUF module consists of a first arbitrator, a second arbitrator and three basic units, and the first arbitrator and the second arbitrator are respectively arranged between any two basic units; The anti-power consumption attack module includes a path selection unit, an arbitration unit, a decision unit and an output recovery unit, and the path selection unit, the arbitration unit, the decision unit and the output recovery unit are all connected with circuit signals; The path selection unit is composed of six multiplexers, and the six two-to-two multiplexers are connected by electrical signals. The path selection unit is used to disturb the delay entering the arbitration unit through the control signal S to cover up the power consumption generated by the real delay output; The arbitration unit is composed of six arbiters. The six arbiters are all based on D flip-flops. The arbitration unit is used to obtain the mutual delay characteristic values ​​between delay paths. The decision unit is used to find the two paths with the largest delay difference; The output recovery unit is composed of a NOT gate and a two-to-one multiplexer, and is used to restore the correct output.

2. A protection circuit for anti-power consumption attack of a high-reliability anti-modeling double-layer APUF according to claim 1, characterized in that: The output ends of the high-reliability anti-modeling double-layer APUF module are four delay links A, B, C, and D from top to bottom. Pairing the four delay links A, B, C, and D will produce six results, namely AB, AC, AD, BC, BD, and CD, which are used as inputs of the path selection unit: The low level and high level of the control signal S are both 0 and 1, and are positive integers. When the control signal S=0, that is, the low level, each combination result is transmitted in parallel, and the delay path remains unchanged when output to the arbitration unit. When the control signal S=1, that is, the high level, each combination result is cross-transmitted, and the delay path changes when output to the arbitration unit.

3. A protection circuit for anti-power consumption attack of a high-reliability anti-modeling double-layer APUF according to claim 2, characterized in that: The six combination results correspond to the six D flip-flops in the arbitration unit. The output value of the D flip-flop represents the delay characteristic value of the delay size relationship between the two paths with inputs. Each D flip-flop is used to compare the delay size relationship between the two inputs. Each D flip-flop has two lines, one for the upper input and one for the lower input. If the delay of the upper input of the D flip-flop is larger, the output is 1, otherwise the output is 0. The decision unit performs delay sorting on the four-way delays according to the arbitration result of the delay difference output by the arbitration unit; The input end of the NOT gate is electrically connected to the output end of the decision unit, the output end of the NOT gate is electrically connected to the input end of the two-to-one multiplexer, the input end of the two-to-one multiplexer is electrically connected to the output end of the high-reliability anti-modeling double-layer APUF module, the NOT gate is used to provide another path delay result, and the two-to-one multiplexer is used to select a suitable path as the final output response.

4. The protection circuit against power consumption attack for a high-reliability anti-modeling double-layer APUF according to claim 1, characterized in that: The control signal S is the result of the exclusive OR operation between the first arbitrator and the second arbitrator.

5. The protection circuit for anti-power consumption attack of high-reliability anti-modeling double-layer APUF according to claim 3 is characterized in that: When the results of the decision unit outputs are the same, the two-to-one multiplexer selects the path that passes through the NOT gate for output. When the results of the decision unit outputs are opposite, the two-to-one multiplexer selects the path that does not pass through the NOT gate for output.

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