Scalable and programmable quantum control processor

Abstract

An apparatus and method for quantum control of a processor. For example, one embodiment of a QCP includes: instruction fetch logic to fetch an instruction from memory, the instruction including a quantum instruction; a decode logic to decode the quantum instruction into a first plurality of quantum microoperations; a conversion logic to convert the first plurality of quantum microoperations to a second plurality of quantum microoperations based on characteristics of the plurality of quantum controller cores, where the quantum control processor is coupled to the quantum control processor; and publication logic to publish the second plurality of quantum microoperations synchronously in parallel to the plurality of quantum controller cores.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of quantum computing. More specifically, these embodiments relate to a scalable and programmable quantum control processor. Background Art

[0002] Quantum computing refers to a field of study related to computing systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can exist in multiple different states simultaneously) and entanglement (in which multiple quantum variables have correlated states regardless of the distance between these quantum variables in space or time), have no analogs in the world of classical computing and therefore cannot be implemented using classical computing devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention may be better understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0004] Figure 1A-1F Various views of an example quantum dot device are shown according to one embodiment;

[0005] Figure 2 One embodiment of a processor pipeline for processing quantum instructions and non-quantum instructions is shown;

[0006] Figure 3 An embodiment of a front-end circuit system for a processor for processing quantum instructions and non-quantum instructions is shown;

[0007] Figure 4A-4B An embodiment of a quantum-classical processor interface is shown;

[0008] Figure 5A-Figure 5B An example quantum circuit and program code for implementing the quantum circuit are shown;

[0009] Figure 6A-6B An example is shown in which a quantum instruction is generated by a compiler, decoded into a uop, and executed within a quantum execution engine;

[0010] Figure 7 A method according to an embodiment of the present invention is shown;

[0011] Figure 8 One embodiment of a qubit index generator for addressing quantum bits (qubits) within a quantum processor is shown;

[0012] Fig. 9 A method for determining a qubit index value for identifying a qubit is shown;

[0013] Fig.10An example of a system for decoding and correcting quantum errors is shown;

[0014] Fig.11 A typical quantum error correction cycle is shown;

[0015] Fig.12 A quantum control processor (QCP) according to an embodiment of the present invention is shown;

[0016] Fig.13 shows the front end and back end of a quantum control processor according to an embodiment of the present invention; and

[0017] Fig.14 A method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0018] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other examples, well-known structures and devices are shown in block diagram form to avoid obscuring the basic principles of embodiments of the invention.

[0019] introduction

[0020] Quantum computers use quantum mechanical phenomena (e.g., superposition and entanglement) to perform calculations. In contrast to digital computers that store data in one of two definite states (0 or 1), quantum computing uses quantum bits (qbits), which can be in a superposition of states. Quantum bits can be implemented using physically distinguishable quantum states of elementary particles (e.g., electrons and photons). For example, the polarization of photons can be used, where the two states are vertical polarization and horizontal polarization. Similarly, the spin of an electron may have distinguishable states (e.g., "spin up" and "spin down").

[0021] The states of a qubit are typically represented by the bracket symbols |0> and |1>. In a conventional computer system, a bit is in only one state or the other (i.e., "0" or "1"). However, a qbit in a quantum mechanical system can be in a superposition of both states at the same time, which is a unique and fundamental feature of quantum computing.

[0022] The algorithm executed by the quantum computing system contains quantum logic operations performed on qubits. The sequence of operations is statically compiled into a schedule, and the qubits are addressed using an indexing scheme. The algorithm is then executed a sufficient number of times until the confidence interval of the calculated answer is above a threshold (e.g., ~95+%). Reaching the threshold means that the desired algorithm result has been achieved.

[0023] Quantum bits have been implemented using a variety of different technologies that can manipulate and read quantum states. These include, but are not limited to (spin-based and space-based) quantum dot devices, trapped-ion devices, superconducting quantum computers, optical lattices, nuclear magnetic resonance computers, solid-state NMR Kane quantum devices, electron quantum computers on helium, cavity quantum electrodynamics (CQED) devices, molecular magnet computers, and fullerene-based ESR quantum computers, etc. Therefore, although quantum dot devices are described below with respect to specific embodiments of the present invention, the basic principles of the present invention can be used in combination with any type of quantum computer (including but not limited to those listed above). The specific physical implementation for qbit is orthogonal to the embodiments of the present invention described herein.

[0024] Quantum dot devices

[0025] Quantum dots are small semiconductor particles, typically a few nanometers in size. Due to their small size, quantum dots operate according to the rules of quantum mechanics and thus have optical and electronic properties that differ from those of macroscopic entities. Quantum dots are sometimes referred to as "artificial atoms," which refers to the fact that quantum dots are single objects with discrete, bound electronic states, just as is the case with atoms or molecules.

[0026] Figure 1A-1F are various views of a quantum dot device 100 that may be used with the embodiments of the present invention described below. Figure 1A 1 is a top view of a portion of a quantum dot device 100 with some material removed such that first gate line 102, second gate line 104, and third gate line 106 are visible. Although many of the drawings and descriptions herein may refer to a particular set of lines or gates as "barriers" or "quantum dot" lines or gates, respectively, this is for ease of discussion only, and in other embodiments, the roles of "barriers" and "quantum dot" lines and gates may be interchanged (e.g., barrier gates may be used alternatively as quantum dot gates, and vice versa). Figure 1B-Figure 1F yes Figure 1A A side cross-sectional view of a quantum dot device 100; specifically, Figure 1B It passes through Figure 1A A view of section BB, Figure 1C It passes through Figure 1AA view of section CC, Figure 1D It passes through Figure 1A A view of the cross section DD, Figure 1E It passes through Figure 1A A view of a cross section EE, and Figure 1F yes Figure 1A A cross-sectional view of FF.

[0027] Figure 1A The quantum dot device 100 can be operated in any of a variety of ways. For example, in some embodiments, an electrical signal such as a voltage, current, radio frequency (RF), and / or microwave signal can be provided to one or more of the first gate line 102, the second gate line 104, and / or the third gate line 106 to form a quantum dot (e.g., a quantum dot based on electron spin or a quantum dot based on hole spin) in a quantum well stack 146 below the third gate 166 of the third gate line 106. The electrical signal provided to the third gate line 106 can control the potential of the quantum well below the third gate 166 of the third gate line 106, and the electrical signal provided to the first gate line 102 (and / or the second gate line 104) can control the potential energy barrier between adjacent quantum wells below the first gate 162 of the first gate line 102 (and / or the second gate 164 of the second gate line 104). Quantum interactions between quantum dots in different quantum wells in quantum well stack 146 (eg, under different quantum dot gates) can be controlled in part by a potential energy barrier provided by a barrier potential applied between the quantum dots (eg, by intervening barrier gates).

[0028] In general, the quantum dot device 100 disclosed herein may also include a magnetic field source (not shown) that can be used to generate an energy difference in the state of a normally degenerate quantum dot (e.g., the spin state of a quantum dot based on electron spin), and the state of the quantum dot (e.g., the spin state) can be manipulated by applying electromagnetic energy to a gate line to produce a quantum bit capable of computation. The magnetic field source can be one or more magnetic lines of force, as described below. Thus, the quantum dot device 100 disclosed herein can manipulate the position, quantity, and quantum state (e.g., spin) of the quantum dots in the quantum well stack 146 by controlled application of electromagnetic energy.

[0029] In the quantum dot device 100 of FIG. 1 , a gate dielectric 114 may be disposed on a quantum well stack 146. The quantum well stack 146 may include at least one quantum well layer 152 (not shown in FIG. 1 ) in which quantum dots may be localized during operation of the quantum dot device 100. The gate dielectric 114 may be any suitable material (e.g., a high-k material). A plurality of parallel first gate lines 102 may be disposed on the gate dielectric 114, and a spacer material 118 may be disposed on the sides of the first gate lines 102. In some embodiments, a patterned hard mask 110 may be disposed on the first gate lines 102 (wherein the pattern corresponds to the pattern of the first gate lines 102), and the spacer material 118 may extend upward along the sides of the hard mask 110, as shown. Each of the first gate lines 102 may be a first gate 162. Different ones of the first gate lines 102 may be electrically controlled in any desired combination (eg, each first gate line 102 may be electrically controlled individually, or some or all of the first gate lines 102 may be shorted together in one or more groups as desired).

[0030] A plurality of parallel second gate lines 104 may be disposed above and between the first gate lines 102. As shown in FIG. 1 , the second gate lines 104 may be arranged perpendicular to the first gate lines 102. The second gate lines 104 may extend above the hard mask 110 and may include a second gate 164 extending downward toward the quantum well stack 146 and contacting the gate dielectric 114 between adjacent ones of the first gate lines 102, as shown in FIG. Figure 1DAs shown. In some embodiments, the second gate 164 may fill the area between adjacent first gate lines 102 / spacer material 118 structures in the first gate line 102 / spacer material 118 structure; in other embodiments, an insulating material (not shown) may be present between the first gate line 102 / spacer material 118 structure and the adjacent second gate 164. In some embodiments, the spacer material 118 may be disposed on the side of the second gate line 104; in other embodiments, the spacer material 118 may not be disposed on the side of the second gate line 104. In some embodiments, a hard mask 115 may be disposed above the second gate line 104. Multiple second gates 164 in the second gates 164 of the second gate lines 104 are electrically continuous (due to the shared conductive material of the second gate lines 104 above the hard mask 110). Different second gate lines 104 in the second gate lines 104 may be electrically controlled in any desired combination (for example, each second gate line 104 may be electrically controlled individually, or some or all of the second gate lines 104 may be short-circuited together in one or more groups as desired). The first gate lines 102 and the second gate lines 104 may together form a grid, as shown in FIG. 1 .

[0031] A plurality of parallel third gate lines 106 may be disposed above and between the first gate lines 102 and the second gate lines 104. As shown in FIG. 1 , the third gate lines 106 may be arranged diagonally with the first gate lines 102 and diagonally with the second gate lines 104. In particular, the third gate lines 106 may be arranged diagonally above openings in a grid formed by the first gate lines 102 and the second gate lines 104. The third gate lines 106 may include a third gate 166 extending downwardly to the gate dielectric 114 in the openings in the grid formed by the first gate lines 102 and the second gate lines 104; thus, each third gate 166 may be bounded by two different first gate lines 102 and two different second gate lines 104. In some embodiments, the third gate 166 may be bordered by the insulating material 128; in other embodiments, the third gate 166 may fill the openings in the grid (e.g., contacting the spacer material 118 disposed on the sides of the adjacent first gate line 102 and the second gate line 104, not shown). Additional insulating material 117 may be disposed on and / or around the third gate line 106. Multiple third gates 166 in the third gates 166 of the third gate line 106 are electrically continuous (due to the shared conductive material of the third gate lines 106 above the first gate line 102 and the second gate line 104). Different third gate lines 106 in the third gate lines 106 may be electrically controlled in any desired combination (e.g., each third gate line 106 may be electrically controlled individually, or some or all of the third gate lines 106 may be shorted together in one or more groups as desired).

[0032] although Figure 1A-1F A specific number of first gate lines 102, second gate lines 104, and third gate lines 106 are shown, but this is for illustration purposes only, and any number of first gate lines 102, second gate lines 104, and third gate lines 106 may be included in the quantum dot device 100. Other examples of arrangements of the first gate lines 102, second gate lines 104, and third gate lines 106 are possible. Electrical interconnects (e.g., vias and wires) may contact the first gate lines 102, second gate lines 104, and third gate lines 106 in any desired manner.

[0033] Not shown in FIG. 1 is an accumulation region of a quantum well layer that can be electrically coupled to the quantum well stack 146 (e.g., laterally proximate to the quantum well layer). The accumulation region can be separated from the gate line by a thin layer of intermediate dielectric material. The accumulation region can be a region where carriers accumulate (e.g., due to doping, or due to the presence of a large electrode that pulls carriers into the quantum well layer), and can be used as a reservoir for carriers that can be selectively pulled into the region of the quantum well layer below the third gate 166 (e.g., by controlling the voltage on the quantum dot gate, the first gate 162, and the second gate 164) to form a carrier-based quantum dot (e.g., an electron or hole quantum dot that includes a single charge carrier, multiple charge carriers, or no carriers). In other embodiments, the quantum dot device 100 may not include a lateral accumulation region, but may include doped layers within the quantum well stack 146. These doped layers can provide carriers to the quantum well layer. Any combination of accumulation regions (eg, doped or undoped) or doped layers in the quantum well stack 146 may be used in any of the embodiments of the quantum dot device 100 disclosed herein.

[0034] Device and method for hybrid classical quantum computer

[0035] After Richard Feynman proposed in 1982 whether quantum physics could be efficiently simulated using quantum computers, much research on quantum computers has focused on the universality of quantum computers and their efficiency compared to classical computing. One such example is the quantum Turing machine designed by David Deutsch in 1985, which can be programmed to perform any computational task that any physical object can perform.

[0036] Compared to theory and algorithms, quantum physical machines are still in their infancy. Efforts to build quantum information processing systems have so far been moderately successful. Small quantum computers that can perform a small set of quantum operations on very few qubits represent the state of the art in quantum computing. Additionally, quantum states are fragile in that they can only remain coherent for a finite duration. This gap between algorithms and physical machines has driven efforts to invent hybrid classical-quantum algorithms. Some recent quantum algorithm developments have focused on short-depth quantum circuits to perform quantum computations that are formed as subroutines embedded in larger classical optimization loops (e.g., variational eigensolvers (PJJ O'Malley, 2016)). Quantum languages, tools, and flows have been developed to provide a software layer / stack to convert and optimize applications to the quantum physics layer to cope with the strict resource constraints in quantum computing (Frederic T. Chong, September 14, 2017).

[0037] On the hardware side, classical computers have been used to perform error correction for quantum computing. The "quantum coprocessor" model is the most advantageous popular execution model, in which the classical CPU controls the quantum processing unit in a manner similar to the CPU and GPU interaction in modern computer systems. As described in (X. Fu, May 2016) and (X. Fu, 2018), the microarchitecture for the experimental superconducting quantum coprocessor includes features such as an arbitrator on the code acquisition data path for directing classical instructions to the host CPU and quantum instructions to the quantum coprocessor, a swap register file for synchronizing the register files between the host CPU and the quantum coprocessor, and a quantum instruction cache.

[0038] However, the microarchitecture of these mechanisms is not well defined, and lacks explicit support for hybrid classical-quantum programs. As a result, it is unclear how quantum coprocessors are implemented in quantum computers, especially those required to run a variety of quantum programs. Flexible and programmable models for executing hybrid classical-quantum algorithms have not yet been developed.

[0039] One embodiment of the present invention adds a quantum instruction set to the instruction set architecture (ISA) of a processor such as a CPU. By way of example, these instructions may be included in an extension of the ISA (e.g., the AVX-512 extension for the x86 platform). In addition, in one embodiment, a quantum engine is added to the execution unit of the processor, and the new quantum instructions are fetched, decoded, scheduled, and executed on the functional unit of the quantum engine. In one embodiment, the quantum engine uses a shared register file and / or system memory to interact with the classical execution engine. When executing a quantum instruction (or a quantum uop in the specific embodiments described herein), the quantum execution engine generates control signals to manipulate the state of the quantum bits within the quantum processor. The quantum engine also executes instructions to measure a specified set of quantum bits and stores the results. In these embodiments, the quantum / classical interface provides connectivity between the quantum engine and the quantum processor of the classical processor.

[0040] Figure 2 An embodiment of a processor or core 210 that utilizes the same pipeline resources as non-quantum instructions 201B to obtain, decode, and execute quantum instructions 201A and non-quantum instructions 201B is shown. The processor / core 210 of this embodiment supports quantum extensions to the existing ISA of the processor / core 210 (e.g., extending the ISA to include quantum instructions 201A). Program code 205C including quantum instructions and non-quantum instructions is generated by a compiler 205B based on source code 205A written by a programmer (e.g., utilizing an extended ISA). Examples of various source code / program code are provided below.

[0041] Quantum instructions 201A and non-quantum instructions 201B are fetched from memory 205 at the front end of the instruction pipeline and stored in a level 1 (L1) instruction cache 201. Instructions and data may also be stored in a level 2 or level 3 cache within a cache / memory subsystem 215, which manages memory requests and cache coherency.

[0042] Decoder 202 decodes instructions 201A-201B into micro-operations or uops 203A, which are scheduled for execution by scheduler 203 and executed by execution circuitry 204. In one embodiment, a particular stage of the pipeline is enhanced to include hardware support for processing quantum instructions 201B without changing other stages. For example, quantum decoding circuitry 202A may be added to decoder 202 for decoding quantum instructions 201A, just as non-quantum decoding circuitry 202B decodes non-quantum instructions 201B. Although for purposes of explanation, the embodiments of the present invention are not described herein. Figure 2 202A and non-quantum decoding circuitry 202B may include common or overlapping sets of circuitry and / or microcode. For example, in one embodiment, an existing decoder may be extended to include microcode support for quantum instructions (e.g., in a microcode ROM) to generate a new set of quantum uops. Depending on the processor architecture, decoder 202 includes other decoding circuitry (e.g., a set of decode table structures (see, e.g., Figure 3 and associated text)).

[0043] In one embodiment, decoder 202 generates a sequence of uops 203A in response to decoding instructions 201A-201B. In implementations with both quantum and non-quantum instructions, the uops may include a mix of quantum and non-quantum uops, which are then scheduled for execution by instruction scheduler 203.

[0044] The quantum uops and non-quantum uops 203A generated by decoder 202 may initially be queued for execution within one or more uop queues of scheduler 203, which dispatches uops from the uop queues based on dependencies and / or availability of execution resources. Embodiments of the invention may be implemented on a variety of different types of processors with different types of schedulers. For example, in one embodiment, a collection of execution "ports" couples scheduler 203 to execution circuitry 204, where each execution port is capable of issuing uops to a specific set of functional units 204C-204E. For example, in Figure 2In the example architecture shown, SIMD and floating point (FP) uops may be issued by scheduler 203 through FP / SIMD execution ports coupled to a set of FP / SIMD functional units 204C, and integer uops may be issued through integer ports coupled to a set of integer functional units 204D. Although only two types of non-quantum functional units are shown for simplicity, processor / core 210 may include various other / additional non-quantum functional units (e.g., load / store address generation units, branch units, additional SIMD and integer units, etc.).

[0045] exist Figure 2 In the particular embodiment shown, the quantum engine functional unit 204E shares the same set of register files 204A-204B used by the legacy processor functional units 204C-204D. In this particular example, the register files 204A-204B include an FP / SIMD register file 204A that stores floating point and SIMD operands used by the FP / SIMD functional unit 204C, and an integer register file 204B that stores integer operands for the integer functional unit 204D. In one implementation, the FP / SIMD register file 204A includes 512-bit vector registers and the integer register file 204B includes 64-bit scalar registers. Of course, different processor architectures will use different types of registers shared by the quantum engine functional unit 204E. Various other types of registers (e.g., a set of control / status registers and mask registers) may also be used.

[0046] In embodiments where quantum uops are mixed with non-quantum uops, the quantum uops are issued through one or more quantum ports to a collection of quantum engine functional units 204E, which execute the quantum uops to perform the underlying quantum operations. For example, in response to the quantum uops, the quantum engine functional unit 204E may generate control signals through the quantum-classical interface 206 to manipulate the qubits of the quantum processor 207 and perform measurements on the qubits of the quantum processor 207.

[0047] The quantum-classical interface 206 includes a digital-to-analog (DA) circuit system for converting the digital quantum control signals generated by the quantum engine functional unit 204E into analog signals required to control the quantum processor 207 (e.g., a codeword trigger pulse generation (CTPG) unit and an arbitrary waveform generator (AWG), as described below), and the quantum-classical interface 206 also includes an analog-to-digital (AD) circuit system for converting physical quantum bit measurements into digital result data.

[0048] In one embodiment, quantum-classical interface 206 is integrated on the same semiconductor chip as other components of the instruction processing pipeline (e.g., execution circuitry 204, scheduler 203, decoder 202, etc.). As discussed in detail below, different types of circuit / logic components may be used depending on the specific physical implementation of quantum processor 207.

[0049] Figure 3 An embodiment is shown where quantum instruction processing support is added to a low power processing pipeline that includes a pre-decode buffer 301B, a bidirectional decoder 302 with dual sets of quantum / non-quantum decoder circuitry 202A-202B, 302A-302B, dual lookup tables for instruction translation (XLAT), and a ucode ROM 304. In one embodiment, XLAT components 303, 305 and ucode ROM 304 are extended to support quantum instructions as indicated by logic blocks 303Q-305Q. Pre-decode buffer 301B detects and marks macroinstruction boundaries before being fully decoded into uops by bidirectional decoder 302.

[0050] Operands for quantum uops and non-quantum uops are stored in a set of shared registers 321 (as described above), and accessed by quantum functional unit 320 when executing a uop. QC interface 320 controls the operation of quantum processor 207 in response to quantum uops.

[0051] Figure 4A-4B Different examples of quantum-classical interface 206 are shown in . Figure 4A The QC interface 206 in the embodiment includes a plurality of uop units 401A-401C that, in response to uops executed by the quantum engine functional unit 204E, generate codewords to control the operation of a plurality of codeword trigger pulse generation (CTPG) units 402A-402C. In response, the CTPG units 402A-402C generate pulse sequences to control the qubits of the quantum processor 207. Once the quantum processor 207 has reached a specified execution state, quantum measurements are performed by one or more of the measurement discrimination units (MDUs) 403A-403B.

[0052] Figure 4BThe illustrated QC interface 206 includes a collection of components for performing microwave complex signal generation, including an RF microwave unit 451, a multi-channel arbitrary waveform generator (AWG) 452, one or more digital-to-analog converters (DACs) 453, and one or more measurement units 454. In one embodiment, the input to each of these components includes a set of codewords generated by the quantum engine functional unit 204E, and the output is an analog waveform that manipulates the state of the qubits of the quantum processor 207. The measurement unit 454 measures the current state associated with one or more qubits at a specified point in execution.

[0053] To further guide the analysis and discussion, Figure 5A A specific example is shown in Figure 5A A quantum circuit is shown for a time-evolving many-body disordered Hamiltonian. Note that the angles by which Rx and Ry are rotated are derived from multiple parameters. In particular, and (where k∈{0,1,…,5,6}) are randomly generated and used to simulate large many-body systems that require a much larger number of qubits than the underlying quantum chip supports.

[0054] Figure 5B An example of a quantum program that uses this circuit to perform part of its computation, including a mix of quantum and non-quantum instructions (as indicated by the comments to the right of the source code), is shown in . In this example, NR is the number of out-of-order realizations (i.e., many small random realizations to simulate a large many-body system), NQ is the number of qubits, NP is the number of iterations to achieve the required accuracy of the probability (Pr), NT is the number of Trotter steps, and a[i] accumulates qubit measurements. The probability of a qubit being in state |0> or |1> is obtained by repeated measurements (NP) and averaging.

[0055] This program structure shows how classical and quantum operations can be tightly interwoven and executed on the classical-quantum processing architecture described herein. The most efficient way to execute this program is to process all instructions in a pipeline such as those described above, where the quantum engine functional unit 204E for controlling qubits is configured as an execution engine that is equivalent to other classical execution engines 204A-204B (e.g., integer, floating point, etc.).

[0056] Figure 6A-6B Provided in response to Figure 5A Examples of quantum operations performed by using the program code in . In particular, Fig. 6A Shown is the method for implementing Figure 5A204B. The QASM code 601 is compiled into a hybrid processor program code 602 in memory 205. In this example, registers RBX and RBX+1 from shared register file 321 or 204B are used to hold qubit indices to address logical qubit #2 and logical qubit #3, respectively, in this particular example. The mapping of the relevant portion of the QASM code 601 to the hybrid processor program code 602 is indicated by the arrows.

[0057] Figure 6B How the quantum macroinstruction QCNOTUP (for implementing a CNOT gate) is decoded by decoder 202 into a series of uops 605 is shown. Uops 605 are executed by quantum engine functional unit 204E to generate codewords having a specified codeword or command packet format 606. In one particular format, the first data field indicates the qubit on which the operation is to be performed (qubit 3 in the example), the second data field indicates the channel on which the operation is to be transmitted (channel 4), the third field indicates the command state (e.g., single command state), and the fourth data field indicates the type of qubit (transmon qubit). Of course, the underlying principles of the invention are not limited to any particular encoding format.

[0058] Figure 7 A method according to one embodiment of the present invention is shown. The method can be implemented within the context of the above processor architecture, but is not limited to any particular processor or system architecture.

[0059] At 701, source code containing quantum instructions is compiled to generate runtime program code having quantum instructions and non-quantum instructions. At 702, quantum / non-quantum instructions are fetched from memory and stored in a local cache (e.g., L1 instruction cache) or instruction buffer. As mentioned, quantum instructions can be freely mixed with non-quantum instructions within the pipeline.

[0060] At 703, quantum instructions and non-quantum instructions are decoded into sets of quantum uops and non-quantum uops, respectively, and stored in queues prior to execution. At 704, quantum / non-quantum uops are scheduled for execution based on uop and / or resource dependencies. For example, if a first uop depends on the result of a second uop, the first uop may be scheduled for execution only if the data produced by the second uop is available in one of the registers. Similarly, if a particular functional unit is busy, the scheduler may wait for an indication that the functional unit is available before scheduling the uop that requires the functional unit. Various other / additional scheduling techniques (e.g., scheduling based on priority, register load, etc.) may be implemented.

[0061] The quantum uop and the non-quantum uop are executed on their respective functional units within the execution circuitry at 705. As mentioned, a set of shared registers may be used to store source and destination operands required by these uops.

[0062] At 706, the results generated by the execution of the quantum uop can be used as input to the interface unit to control the quantum state of the qubits in the quantum processor. In one embodiment, a series of codewords or command packets can be generated that identify the quantum channel, one or more qubits within the quantum processor, qubit types, and / or command states. The specific physical operations performed in response to the codewords or command packets are based on the underlying type of quantum processor used.

[0063] The embodiments described herein integrate quantum instructions within existing processor pipelines. Due to the tight integration, these embodiments significantly reduce various overheads / bottlenecks associated with current coprocessor designs. For example, these overheads / bottlenecks include communication between the classical computing layer / module and the quantum computing layer / module in the software stack, and communication between the classical CPU and the quantum chip via message queues. Given the relatively small size of quantum routines, current GPU-like coprocessor implementations are inefficient.

[0064] The hybrid coprocessor model reduces some of the overhead due to the added classical processing power. In one particular implementation that supports the hybrid coprocessor model, a number of new microarchitectural mechanisms are introduced. However, these microarchitectural mechanisms are not well defined, and so is the boundary between the classical CPU and the quantum coprocessor.

[0065] In contrast, in the hybrid architecture described herein, the classical computing pipeline is equipped to fully support a defined quantum instruction set that can be freely intermixed with non-quantum instructions both at the front end of the pipeline (i.e., at the macroinstruction level) and within the back end of the pipeline (e.g., where quantum uops are intermixed with non-quantum uops), and executed on functional units within the execution circuitry of the processor.

[0066] Scalable qubit addressing modes for quantum execution engines and / or coprocessors

[0067] In quantum computing, a qubit is the unit of quantum information. A qubit is the quantum analog of a classical binary bit. Computations are performed by applying quantum gates, which represent quantum logic operations, directly to qubits. Mathematically, this computational process is described as a qubit undergoing a unitary transformation. After the computation is complete, the qubit is measured to obtain information about the state of the qubit.

[0068] Therefore, in order to describe a quantum operation, it is necessary to identify the quantum bit or set of quantum bits to which the operation is applied. In a quantum program, each quantum instruction needs to encode both: the operation to be performed, and one or more quantum bits on which the operation is to be performed. In existing quantum instruction set architectures (e.g., QASM, Open QASM, QIS, etc.), register operands are typically encoded in the opcode of the instruction. This scheme is suitable for classical computing because the number of registers is very limited (e.g., 16, 32, 64, etc.). However, this scheme is not scalable for quantum computing because quantum instructions ultimately need to address a very large number of quantum bits. Therefore, encoding the quantum bit address in the opcode field of the quantum instruction will greatly increase the instruction width.

[0069] As described above, in one embodiment, quantum instructions and non-quantum instructions are processed together within a shared processor pipeline. Therefore, quantum instructions can rely on the same addressing modes as those available to non-quantum instructions. Therefore, qubits in this embodiment are addressed in a similar manner to non-quantum instructions that access system memory, thereby providing an address space large enough to accommodate a large number of qubits.

[0070] like Figure 8 As shown, in this embodiment, the quantum engine functional unit 204E includes a qubit index generation unit (QIG) 802, which determines a qubit index value or qubit ID in response to one or more uops 805. One or more quantum operation units 801 process the operation specified by the uop. Then, the qubit index value (e.g., 011 for qubit 3 in the example) is potentially incorporated into a codeword / command group 606 together with one or more commands, wherein the one or more commands are generated by the quantum operation unit 801 in response to processing the uop 805.

[0071] QIG 802 may operate according to different addressing modes supported by the processor. In one embodiment, an instruction identifies one of shared registers 321 that contains a qubit index value (sometimes also referred to as a qubit ID). The QIG 802 may then use the qubit index value to identify a qubit within a codeword / command packet 606, and / or perform an operation using the qubit index value to generate one or more additional qubit index values. For example, the QIG 802 may add the qubit ID value to an integer specified by a uop to generate a second qubit ID.

[0072] The following example shows one way that QIG 802 generates qubit IDs in response to a uop using x86 assembly syntax. These operations can be executed within an x86 pipeline extended to support quantum instructions. However, the same general principles can be implemented on any processor architecture.

[0073] A single qubit instruction "QIROTX[RDI],1" applies the X gate to the qubit number stored in RDI. Thus, if RDI contains 5, the X gate is applied to qubit number 5. In this example, QIG 802 simply determines the qubit ID by reading the value stored in RDI (which in this example is one of shared registers 321). In this embodiment, the RDI value was previously stored by another uop. As another example, if architectural register RBX contains a value of 2, a two qubit instruction "QCNOTUP[RBX+3]" applies a CNOT operation, where qubit 2 (q[2]) is the control qubit and qubit 5 (q[5]) is the target qubit. The QIG interprets the [RBX+3] notation as: the ID of the control qubit is stored in RBX, and the ID of the control qubit+3 is the target qubit ID. Thus, the addressing scheme is extended so that two different qubits can be addressed using a single instruction (i.e., CNOT). In contrast, in classical computing, each instruction addresses only one memory location.

[0074] Figure 8Also shown is a codeword trigger pulse generator (CTPG) 402A, which includes control logic and an analog-to-digital converter for interpreting codeword / command packets 606 to identify one or more qubits (Q3 in the example) and generating a sequence of pulses that implement the specified quantum operation. When all quantum operations as specified by program code 205C have been performed, quantum operation circuitry 801 and QIG 802 generate codeword / command packets 606 to cause one or more MDUs 403A-403B to perform measurements on one or more qubits (specified by QIG 802, which generates qubit indices). As mentioned, the MDU includes analog-to-digital circuitry to convert analog measurements to digital values, which are then processed by quantum error correction unit 808 to detect and potentially correct errors. If valid result data has been received, the valid result data may be stored in one or more of shared registers 321 and / or accumulated with previous measurement data. In addition to error correction, measurements can also be used for program flow control based on measurement feedback.

[0075] The quantum error correction unit 808 may implement various techniques for detecting and correcting quantum errors. For example, in one embodiment, an error decoder (within the QEC unit 808) decodes multi-qubit measurements from the quantum processor 207 to determine whether an error has been generated, and if an error has been generated, to implement corrective measures (which is possible). Error measurements may be made on multiple qubits in a manner that does not interfere with the quantum information in the encoded state of the qubits (e.g., using auxiliary qubits). In response, the QEC unit 808 generates error syndrome data, from which the error that has been generated may be identified and corrective actions may be implemented. In one embodiment, the error syndrome data includes a stabilizer code, such as a surface code. In some cases, the response may simply be to reinitialize the qbit and start over. However, in other cases, the quantum algorithm implemented in the quantum program code 205C may be modified to stabilize the region of the quantum processor responsible for the error (e.g., where the compiler 205B includes a just-in-time (JIT) compiler). In either case, the CTPG 402A performs the underlying physical operations under the control of the codeword / command packet 606 generated by the QEFU 204E. For example, the CTPG 402A may generate electromagnetic pulses to adjust the phase of one or more qbits based on a detected phase error, or to reset the phase / spin of all qbits if reinitialization is required.

[0076] The qubits are addressed in a manner similar to how the address memory of a classical CPU provides the scalable characteristics / attributes required by future quantum processor implementations. In particular, the above embodiments provide qubit indexing that is seamlessly integrated within existing processor ISAs and is scalable to large numbers of qubit systems. These embodiments also remove pressure from the quantum instruction opcode space by way of quantum extensions to x86 or other architectures to address the qubit space and integrate quantum operations into existing processor pipelines.

[0077] Fig. 9 A method according to an embodiment of the present invention is shown. The method can be implemented on the above architecture, but is not limited to any specific processor or system architecture.

[0078] At 901, quantum instructions and non-quantum instructions from runtime program code are fetched and decoded, thereby generating quantum uops and non-quantum uops. At 902, an index generation unit evaluates the quantum uop to determine a qubit index value, the quantum uop including a register identifier and one or more values ​​optionally included with the uop. As described above, various techniques may be used to generate the index, including reading the qubit index value from the register identified by the uop, and using an integer value included with the uop to generate additional qubit index values.

[0079] At 903, the quantum execution circuit system generates a codeword that specifies a quantum operation to be performed on the qubit identified by the calculated qubit index value. At 904, the quantum operation is performed on the specified qubit. At 905, a qubit measurement is performed in response to another codeword generated based on the additional uop. At 906, the analog measurement of one or more of the qubits is converted to a digital value. Error correction and / or flow control can then be performed based on the resulting digital result value stored in the register file of the processor.

[0080] Fig.10 A typical quantum computer arrangement with error detection and correction is shown. The example shown includes a quantum computer runtime 1001 (e.g., implemented in QASM program code) that is executed by a quantum execution pipeline 1005 of a quantum execution unit 1002. By way of example and not limitation, the quantum execution unit 1002 may be an application specific integrated circuit ASIC, a general purpose processor, or a programmable functional unit for executing quantum instructions.

[0081] In response to the execution of the quantum program code, the quantum execution pipeline 1005 transmits commands to the qubit drive controller 1010, which performs physical quantum operations on the quantum chip 1020. Depending on the implementation, this can be accomplished by a sequence of RF pulses for manipulating the qubits Q0-Q15 of the quantum chip 1020.

[0082] After all or a certain number of program operations have been completed, the measurement unit 1015 reads / estimates the quantum state of one or more qubits in the qubits Q0-Q15, and provides the measurement result to the decoding / error correction unit 1016, which decodes the measurement using an error correction decoding technique. For example, the decoding / error correction unit 1016 decodes the multi-qubit measurement from the quantum processor 1020 to determine whether an error has been generated, and if an error has been generated, a correction measure is implemented (if possible). Error measurements can be performed on multiple qubits in a manner that does not interfere with the quantum information in the encoded state of the qubit (for example, using an auxiliary qubit). In response, error check sub-data can be generated, and errors and correction operations can be identified based on the error check sub-data. In one embodiment, the error check sub-data includes a stable sub-code, for example, a surface code. In some cases, the response may simply be to reinitialize qbit Q0-Q15 and start over. However, in other cases, modifications to the quantum algorithm can be implemented in the quantum program code 1001.

[0083] The decoded / corrected results are provided to the quantum execution unit 1002 for further processing according to the quantum runtime 1001. The typical operation flow of current quantum computer designs is based on a fixed cycle time for each measurement made by the measurement unit 1015 and each quantum operation executed by the quantum execution pipeline 1005.

[0084] Fig.11 One embodiment of a quantum error correction cycle that can be implemented by the architecture described herein is shown. At 1101, the logical qubit state of the system is initialized. For example, if electron spins are used as quantum states, the electrons within the quantum system can be prepared (e.g., initialized to a specific spin orientation and / or entanglement using electromagnetic control signals from a quantum controller).

[0085] At 1102, the state of the quantum system evolves in response to additional electromagnetic inputs specified by the quantum runtime 1001 and implemented by the quantum controller 1010. For example, different sets of qubits, including auxiliary qubits, can be entangled and manipulated according to the quantum runtime 1001.

[0086] At 1103, a measurement of the quantum system is performed. For example, the current spin of one of the entangled electrons may be measured. The system may then be reinitialized before the next measurement (i.e., assuming that making a measurement or learning any information about the quantum system would destroy the quantum state). The physical qubits may be measured periodically during each error correction cycle.

[0087] At 1104, error detection / classification is performed on the measurements to determine if an error has occurred. The error cycle is completed at 1105 with an error correction operation using the specified code set that attempts to correct any detected errors.

[0088] Scalable and programmable quantum control processor

[0089] Many quantum algorithms require quantum systems with a large number of qubits. Furthermore, the timing limitations of these quantum systems require that many quantum operations be applied simultaneously on the qubits.

[0090] The larger number of qubits in a quantum processor leads to many challenges, including those related to scalability, calibration, performance, parallelism, and error correction. For example, in terms of scalability, there are challenges associated with the expansion of the control infrastructure for large quantum chips. For calibration, the challenge is related to the transmission of precise control pulses to the quantum bits, given the requirement for frequent calibration of the qubit chip. The performance challenge is related to improving the performance of the execution of quantum algorithms to meet the timing constraints of the qubits. For error correction, the challenge is related to how to manage error correction on shared qubit chips, control electronics, and computing hardware resources.

[0091] Embodiments of the present invention address these issues in a quantum control processor (QCP) with a scalable and modular architecture to control different quantum systems with a large and variable number of qubits. The modular QCP controls an arbitrary number of quantum controllers using a sequence of precisely timed and orchestrated control signals, such that the quantum controllers simultaneously generate control pulses to a large number of qubits while implementing error correction and calibration routines. The QCP takes as input an instruction set of a classical / quantum instruction set architecture and outputs a quantum control microcode, wherein the instruction set includes quantum instructions that conform to physical qubit chip technology. In particular, the quantum microcode includes quantum microoperations with an efficient and compact representation of control pulses to implement quantum operations on a target qubit chip.

[0092] Because qubits have a short lifetime, quantum systems have strict timing constraints when executing quantum algorithms. Therefore, it is useful in many cases to perform quantum operations on qubits simultaneously. When the system is scaled up, it may be necessary to use multiple qubit controllers ("qControllers") to control multiple groups of qubits simultaneously, where each qController contains multiple quantum control cores ("qCores"). One embodiment of the present invention includes a time-aware and scalable quantum control module (referred to herein as a "quantum control processor" or QCP), which is an accelerator in the quantum computing stack and orchestrates a collection of qControllers, and feeds the collection of qControllers with synchronized digital control pulse signals required to perform quantum operations.

[0093] In one embodiment, a quantum control processor works in conjunction with two different classical / quantum instruction sets, mapping an input ISA comprising quantum instructions to an output uISA comprising quantum microinstructions (also called micro-operations), and distributing the quantum micro-operations to multiple qubit controllers while addressing the timing requirements of the specific quantum circuits and control electronics used.

[0094] In short, one embodiment of a quantum control processor maintains synchronization of quantum operations across the platform; coordinates with a calibration engine to perform calibration routines; utilizes the latest calibration data to generate digital control pulses for each quantum operation; coordinates with an error correction engine to apply error detection and correction circuits; coordinates with multiple qControllers to apply analog pulses to the qubit chips; coordinates with a quantum runtime to handle interrupts, different modes of operation, and measurements from the qubit chips; and implements a communication protocol for shared resources.

[0095] Fig.12 The architecture according to some embodiments of the present invention is shown. The compiler 1205 and quantum runtime 1204 are executed on a classical computing resource 1210 (e.g., an x86 general-purpose processor and associated chipset). The memory 1215 coupled to the computing resource 1210 stores executable program code associated with the compiler 1205 and runtime 1204.

[0096] A quantum control processor 1225, also coupled to the memory 1215, executes the quantum kernel 1206 (e.g., according to a classical control flow pattern), which may include both quantum instructions and non-quantum instructions. In the illustrated embodiment, the QCP 1225 includes a plurality (k) of functional unit clusters 1240A-1240B, wherein each cluster includes at least one front end unit (front end unit 0 to front end unit k) for fetching and decoding instructions of the quantum kernel 1206, a plurality of back end units (BE 0 to BE m) for executing instructions, timing controller units 1221-1222, and memories 1223-1224.

[0097] The control electronics 1261 shown include multiple multi-qubit controllers, qControllers 1280-1281, and each qController 1280-1281 includes multiple quantum control cores (qCores) 1231-1232 and 1233-1234, respectively. For example, each qCore can be responsible for executing quantum microcode and responsively controlling one qubit of the qubit chip 1250. In some implementations, each backend unit BE0-BEm is capable of managing quantum micro-operations and issuing quantum micro-operations to at least one of the qCores 1231-1234. In these implementations, each qCore 1231-1234 includes a microcontroller to perform quantum micro-operations and control electronics 1261 to generate analog signals to manipulate the corresponding qubit of the qubit chip 1250.

[0098] Although the illustrated embodiment includes multiple back-end units for each front-end unit, other embodiments may include the same number of back-end units and front-end units per cluster or more front-end units than back-end units. In one implementation, cluster-level modularity allows the QCP 1225 to be efficiently constructed with different numbers of clusters based on the specific requirements of each quantum system. In addition, intra-cluster modularity simplifies the design of new clusters with different numbers of back-end units, front-end units, timing control units 1221, and local memories 1223. For example, if the front-end of the QCP 1225 becomes a bottleneck when expanding to a large number of qubits, additional front-end modules can be efficiently configured on the QCP. Therefore, the modular QCP architecture allows additional modules to be added to the pipeline as needed.

[0099] In some embodiments, non-quantum instructions are decoded by one of the front-end units 0-k and executed by an execution unit of one of the back-end units 0-m. Quantum instructions are decoded by the front-end units 0-k into quantum micro-operations and converted into qController / qCore micro-operations (i.e., native micro-operations based on the specific qController / qCore used; sometimes referred to herein as uqISA) in the back-end units 0-m, which are dispatched to the qCores 1231-1234 via the digital interface 1260. Based on the received uqISA micro-operations, a given qCore 1231-1234 generates and applies a corresponding sequence of analog control pulses directed to the qubits of the qubit chip 1250 via the analog interface 1262. The qCores 1231-1234 also measure the qubits and provide the measurement results to the QCP 1225, which are then passed to the quantum runtime 1204.

[0100] The timing controllers 1221-1222 perform time synchronization across multiple QCP front-ends and / or back-ends to ensure that quantum algorithms are scheduled and executed within the required timing constraints across a large platform. Local memories 1223-1224 can be used to store temporary results during instruction decoding, conversion, and execution.

[0101] Although QCP 1225 is capable of processing non-quantum instructions (also referred to herein as "classical" instructions), computationally expensive non-quantum tasks or processes may be offloaded and run on computing resources 1210. Decisions about where a particular program code module should be executed may be made by compiler 1205, runtime 1204 (e.g., through a runtime scheduler), or QCP 1225.

[0102] Reference Fig.13 , one embodiment of the QCP 1325 uses a modern microprocessor pipeline architecture with a quantum instruction extension qISA (e.g., an ISA with non-quantum instructions and quantum instructions) to process instructions 1390. In some implementations, quantum instructions are decoded and converted to quantum control microinstructions uqISA designed for a specific qController / qCore type. Because the QCP 1325 processes both classical and quantum instructions, the operation of a particular stage of the pipeline may be different from that in existing microprocessors.

[0103] exist Fig.13In the embodiment, the quantum control processor 1325 includes a front end 1300 having a cache 1301, a set of registers 1308, fetch logic 1305, decode logic 1306, and dispatch logic 1307. The back end 1310 includes an execution unit 1315, a write back unit 1317, and a set of conversion units 1320. The QCP 1325 also includes a configuration memory 1332, an error correction engine 1334, a calibration engine 1336, and a qController manager 1338.

[0104] In operation, the fetch logic 1305 fetches quantum instructions and non-quantum instructions 1390 from the cache 1307 and / or the memory 1215, and the decode logic 1306 decodes the fetched instructions. Fig.13 A single instruction cache 1301 is shown for both quantum instructions and non-quantum instructions, but separate instruction caches may be used for quantum instructions and non-quantum instructions.

[0105] The decoding logic 1306 may include separate decoding pipeline stages for quantum instructions and non-quantum instructions. In one embodiment, the decoding logic 1306 first determines whether the instruction is quantum or non-quantum. If the instruction is a quantum instruction, the decoder 1306 identifies the destination qCore 1341-1343 that will execute the corresponding microinstruction. For example, the decoder 1306 can access configuration data related to the set of available qCores 1341-1343 from the configuration memory 1332, and responsively identify a specific qCore. In one implementation, the back end 1310 includes a set of conversion units 1320A-1322A with corresponding issue queues 1320B-1322B, and each conversion unit in the set of conversion units 1320A-1322A is associated with a qCore in qCores 1341-1343. For example, conversion unit 0 1320A can be associated with qCore n 1341, conversion unit 1 1321A can be associated with qCore n-1 1342, and so on. After decoding by decoder 1306, dispatch logic 1307 dispatches each decoded quantum instruction to an issue queue 1320B-1322B corresponding to the identified qCore 1341-1343.

[0106] The resources (e.g., execution units, conversion units) used to execute each instruction can be allocated by dispatch logic 1307 based on the type of instruction. For example, non-quantum instructions are dispatched to non-quantum issue queues and executed by one or more execution units 1315. The results are stored to registers 1308 or memory 1215 (e.g., according to a standard processor pipeline) by write-back stage 1317. Conversely, dispatch unit 1307 dispatches decoded quantum instructions to issue queues 1320B-1322B associated with corresponding qCores 1341-1343.

[0107] When dispatching decoded quantum instructions to one of the issue queues 1320B-1322B, the dispatch logic 1307 is time-aware (e.g., coordinated with one or more of the timing control units 1221-1222) to satisfy the order and timing dependencies between the quantum instructions and ensure that parallel quantum instructions will be executed synchronously. To handle parallelism, there may be multiple backends in the distributed execution cluster architecture (e.g., as described in relation to Fig.12 ). In these implementations, all backends may operate in parallel to queue, convert, and issue quantum operations to qCores 1341-1343.

[0108] In one embodiment, the conversion unit 1320A-1322A of each back end converts the micro-operations (qISA) generated by the decoder 1306 into output quantum control micro-operations (uqISA). Therefore, the conversion unit efficiently performs another layer of decoding based on the target uqISA. Once the conversion is completed, the resulting uqISA micro-operations are written to the specific location allocated to the corresponding qCore 1341-1343 in the memory 1215 (for example, in the memory 1215 or the local memory 1222-1223, cache or buffer). In some embodiments, the memory 1215 can be a memory different from the memory used by the QCP 1325. For example, the memory used to store the uqISA micro-operations can be an ultra-low power static random access memory (SRAM) or other types of low-power memory.

[0109] The qController manager 1338 performs power management operations and handles synchronization across the set of qCores 1341-1343 and the qController 1380 (e.g., coordinating the issuance of micro-ops). For example, in one embodiment, the qController manager 1338 notifies the issue logic of the issue queues 1320A-1322A when a qCore is available and / or when the issue logic can write the converted micro-ops to memory. Additionally, the qController manager 1338 generates notifications when qubit measurement results are ready.

[0110] In one implementation, analog parameters of the analog control circuitry are stored in configuration memory 1332 to ensure that the correct signals are transmitted to qCores 1341-1343 via digital interface 1260. In particular, conversion units 1320A-1322A utilize the data in configuration memory 1332 to decode qISA micro-ops into uqISA micro-ops tailored for a particular set of qControllers.

[0111] A single backend unit (e.g., backend 1310) can concurrently generate micro-operations for one or more of qCores 1341-1343. For additional scalability, several qCores (e.g., n qCores in one implementation) can be grouped into a qController 1380. In this implementation, the quantum control processor 1225, 1325 controls a group of qCores, where each individual qCore is controlled by an individual backend unit. The qController manager 1338 can manage all qControllers and corresponding qCores.

[0112] Embodiments of the quantum control processor may support different modes of operation based on the underlying physical implementation of the qubit chip 1250. To implement this behavior, the QCP 1225, 1325 defines a qISA based on a set of native gates supported by one or more target qubit chips 1350. Thus, the compiler 1205 is configured to compile a quantum algorithm / circuit into a sequence of qISA instructions that targets a specific physical quantum chip 1250 and / or backend 1310.

[0113] As described above, configuration memory 1332 stores configuration data associated with a particular set of qCores 1341-1343 in the system. For example, the configuration data may include simulation parameters of the analog control circuit system and data related to calibration routines and error correction routines implemented by calibration engine and error correction engine 1334, respectively. In one embodiment, configuration memory 1332 also stores configuration data associated with qubit chip 1250. By way of example and not limitation, the configuration data may include qubit chip connectivity (i.e., physical connectivity between qubits) and native gate set implementation methods and recipes. Configuration memory 1332 may be on-chip memory or off-chip memory.

[0114] The dispatch logic 1307 in the front end 1300 is responsible for ensuring that the order of the sequence instructions is preserved and that quantum instructions / micro-operations are executed in parallel when possible. The dispatch logic 1307 also interacts with other controllers and manager units (e.g., qController manager 1338 and timing controller units 1221-1222).

[0115] The ideal control strategy for each individual quantum gate depends on the characteristics of the fundamental type of error generated by the qubit. In one implementation, calibration engine 1336 runs a programmed calibration routine and updates from configuration memory 1332 to collect calibration data based on detected errors (e.g., attempting to maintain the error rate below an acceptable threshold). For example, when executed by calibration engine 1336, the calibration routine identifies the physical characteristics and capabilities of each of the qubits of qubit chip 1250, which can then be used to update control parameters associated with these qubits, and can also be stored in configuration memory 1332 and used by various stages of the quantum control processor.

[0116] The calibration engine 1336 may be configured internally or externally to the QCP 1325 and may perform calibration via a software layer. If configured externally to the QCP 1325, the QCP is still responsible for managing the operation of the calibration engine 1336. In one implementation, the calibration engine runs a calibration routine periodically or on demand based on an interrupt.

[0117] The error correction engine 1334 is responsible for executing error correction routines to detect and correct errors when measurements are made on qubits. The error correction engine 1334 can also be configured inside or outside the QCP 1325 and can work in conjunction with the software layer to decode error syndromes. If configured outside the QCP 1325, the QCP is still responsible for managing its operation.

[0118] Fig.14 A method according to one embodiment of the invention is shown. The method can be performed on various architectures described herein, but is not limited to any particular architecture (quantum or classical).

[0119] At 1400, an instruction associated with a quantum core (e.g., one of quantum cores 1206) is fetched. At 1401, if the instruction is not a quantum instruction (e.g., an instruction designed to be decoded / converted and executed by a quantum controller), then at 1410, the instruction is decoded into one or more micro-operations (sometimes referred to as uops) and, at 1411, the micro-operations are dispatched and executed (e.g., on an execution unit). At 1412, the results of the micro-operations, if any, are written back to registers and / or a memory subsystem (e.g., cache memory, local memory, system memory, etc.).

[0120] If at 1401, the instruction is a quantum instruction, then at 1402, the quantum instruction is decoded into one or more micro-operations (e.g., the uISA micro-operations described above). As mentioned, quantum instructions can be processed through a different set of decoding stages than non-quantum instructions. In addition, a specific quantum controller can be identified at the decoding stage (e.g., in conjunction with configuration data from configuration memory 1332).

[0121] At 1403, upon receiving an indication that sufficient processing resources are available, the quantum micro-operation is dispatched to a release queue associated with the quantum controller. At 1404, the quantum micro-operation is converted into a quantum controller micro-operation (e.g., uqISA), for example, for micro-operations executed on a particular qCore or qController. The quantum controller micro-operation is stored in a memory or other storage device accessible to the target qCore. At 1405, the qCore, upon receiving the notification, obtains and executes the quantum control operation according to the set of timing signals (i.e., to ensure that the execution occurs at the correct time relative to the execution of other quantum controller micro-operations). The quantum control micro-operation, when executed, causes the qCore to generate a sequence of simulated pulses to manipulate one or more qubits of the quantum processor.

[0122] At 1406, the qCore may optionally perform a measurement on one or more of the qubits (e.g., via measurement discrimination units 403A-403B as described above). If a measurement is performed, error correction is performed at 1407, and the resulting measurement data is stored to a memory from which it can be combined with other measurement data, read, and analyzed.

[0123] Embodiments of the present invention solve various problems associated with scalability, calibration, and error correction on quantum systems with many qubits using a common instruction set that is decoded / converted and consumed by qubit controllers. A quantum control processor (QCP) includes a scalable and modular architecture that provides control of different quantum systems with a large and variable number of qubits. The modular QCP controls an arbitrary number of quantum controllers using a sequence of precisely timed and orchestrated control signals so that the quantum controllers simultaneously generate control pulses to a large number of qubits while implementing error correction and calibration routines. Using an instruction set architecture with a quantum extension as input, these embodiments generate quantum control microcode for a specific quantum controller and physical qubits of a quantum system.

[0124] In the above detailed description, reference is made to the accompanying drawings which form a part thereof, and in the accompanying drawings, embodiments that can be practiced are shown by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0125] Various operations can be described as multiple discrete actions or operations in turn in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must rely on the order. In particular, these operations may not be performed in the order presented. The described operations can be performed in an order different from the described embodiments. Various additional operations can be performed, and / or the described operations can be omitted in additional embodiments. Unless otherwise stated, terms such as "first", "second", "third", etc. do not imply a specific order.

[0126] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used with reference to a measurement range, the term "between" includes both ends of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0127] The description uses the phrases "in an embodiment" or "in embodiments," which phrases may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like as used with respect to the embodiments of the present disclosure are synonymous.

[0128] Example

[0129] The following are example implementations of different embodiments of the invention.

[0130] Example 1. A quantum control processor, comprising: an acquisition unit, the acquisition unit is used to acquire instructions from a memory, the instructions comprising quantum instructions; a decoder, the decoder is used to decode the quantum instructions into a first plurality of quantum micro-operations; conversion logic, the conversion logic is used to convert the first plurality of quantum micro-operations into a second plurality of quantum micro-operations based on characteristics of a plurality of quantum controller cores, wherein the plurality of quantum controller cores are coupled to the quantum control processor; and publishing logic, the publishing logic is used to synchronously publish the second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel.

[0131] Example 2. A quantum control processor according to Example 1, wherein the instruction also includes a non-quantum instruction, wherein the decoder is used to decode the non-quantum instruction into multiple non-quantum micro-operations, and the quantum control processor also includes: a dispatch unit, which is used to dispatch the multiple non-quantum micro-operations to one or more execution units and dispatch the first multiple quantum micro-operations to the conversion logic.

[0132] Example 3. A quantum control processor according to Example 1 or 2, wherein the conversion logic includes multiple conversion units, each conversion unit is associated with a quantum controller core among the multiple quantum controller cores, and each conversion unit is configured to convert one or more quantum micro-operations of the first plurality of quantum micro-operations into one or more quantum micro-operations of the second plurality of quantum micro-operations for execution by the quantum controller core.

[0133] Example 4. A quantum control processor according to any one of Examples 1-3, wherein the issuing logic includes a plurality of issuing queues, each issuing queue corresponding to a conversion unit in a plurality of conversion units, and each issuing queue is configured to store one or more quantum micro-operations in the first plurality of quantum micro-operations, or indications of the one or more quantum micro-operations in the first plurality of quantum micro-operations.

[0134] Example 5. According to any one of Examples 1-4, the quantum control processor further includes: a configuration memory for storing configuration data related to characteristics of the multiple quantum controller cores, wherein the decoder is used to read the configuration data to identify a first quantum controller core among the multiple quantum controller cores to execute one or more of a second plurality of quantum micro-operations associated with a first instruction among the multiple quantum instructions.

[0135] Example 6. The quantum control processor according to any one of Examples 1-5 further includes: a calibration engine for executing one or more calibration routines to generate at least a portion of the configuration data.

[0136] Example 7. According to any one of Examples 1-6, the quantum control processor further includes at least one of a modular front-end unit and a modular back-end unit, the modular front-end unit includes an acquisition unit and a decoder, the modular back-end unit includes conversion logic and publishing logic, and the quantum control processor also includes: a modular interface, which is used to couple a variable number of modular front-end units or modular back-end units.

[0137] Example 8. The quantum control processor according to any one of Examples 1-7 further includes: a modular cluster, wherein the modular cluster includes: a front-end unit, and zero or more additional front-end units, and a back-end unit, and zero or more additional back-end units.

[0138] Example 9. A quantum control processor according to any one of Examples 1-8, wherein the conversion logic is used to store a second plurality of quantum micro-operations in a memory, and the quantum control processor further comprises: a quantum controller manager, the quantum controller manager being used to communicate with the publishing logic so that a plurality of quantum controller cores access corresponding portions of the second plurality of quantum micro-operations from corresponding areas of the memory.

[0139] Example 10. The quantum control processor according to any one of Examples 1-9, further comprising: a sequential circuit system coupled to the publishing logic and the quantum controller manager, the publishing logic and / or the quantum controller manager being used to access the sequential circuit system to synchronously publish a second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel.

[0140] Example 11. A method comprising: retrieving an instruction from a memory, the instruction comprising a quantum instruction; decoding the quantum instruction into a first plurality of quantum micro-operations; converting the first plurality of quantum micro-operations into a second plurality of quantum micro-operations based on characteristics of a plurality of quantum controller cores; and synchronously issuing the second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel.

[0141] Example 12. A method according to Example 11, wherein the instruction also includes a non-quantum instruction, wherein the decoder is used to decode the non-quantum instruction into a plurality of non-quantum micro-operations, and the method further includes: dispatching the plurality of non-quantum micro-operations to one or more execution units, and dispatching the first plurality of quantum micro-operations to conversion logic.

[0142] Example 13. A method according to Example 11 or 12, wherein the conversion further includes: performing multiple separate conversions at least partially in parallel, each of the multiple separate conversions is associated with a different portion of the first plurality of quantum micro-operations and a quantum controller core in the plurality of quantum controller cores.

[0143] Example 14. A method according to any one of Examples 11-13, wherein synchronously publishing a second plurality of quantum micro-operations to multiple quantum controller cores in parallel also includes: storing each of the different parts of the first plurality of quantum micro-operations, or indications of each of the different parts, in a separate publishing queue, each publishing queue being associated with a quantum controller core among the multiple quantum controller cores.

[0144] Example 15. The method according to any one of Examples 11-14 further includes: storing configuration data related to characteristics of multiple quantum controller cores, reading the configuration data to identify a first quantum controller core among the multiple quantum controller cores to execute one or more of a second plurality of quantum micro-operations associated with a first instruction among the multiple quantum instructions.

[0145] Example 16. The method of any one of Examples 11-15, further comprising: performing one or more calibration routines to generate at least a portion of the configuration data.

[0146] Example 17. The method according to any one of Examples 11-16 further includes: storing a second plurality of quantum micro-operations in a memory so that a plurality of quantum controller cores access corresponding portions of the second plurality of quantum micro-operations from corresponding areas of the memory.

[0147] Example 18. A quantum system, comprising: a memory for storing instructions associated with a quantum runtime; a host processor for executing the instructions to implement the quantum runtime; a quantum control processor coupled to the memory, the quantum control processor comprising: an acquisition unit for acquiring instructions from the memory, the instructions comprising quantum instructions; a decoder for decoding the quantum instructions into a first plurality of quantum micro-operations; conversion logic for converting the first plurality of quantum micro-operations into a second plurality of quantum micro-operations based on characteristics of a plurality of quantum controller cores, wherein the plurality of quantum controller cores are coupled to the quantum control processor; and a publishing logic for synchronously publishing the second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel.

[0148] Example 19. A quantum system according to Example 18, wherein the instruction also includes a non-quantum instruction, wherein the decoder is used to decode the non-quantum instruction into multiple non-quantum micro-operations, and the quantum system further includes: a dispatch unit, the dispatch unit is used to dispatch the multiple non-quantum micro-operations to one or more execution units, and dispatch the first multiple quantum micro-operations to conversion logic.

[0149] Example 20. A quantum system according to Example 18 or 19, wherein the conversion logic includes multiple conversion units, each conversion unit is associated with a quantum controller core among the multiple quantum controller cores, and each conversion unit is configured to convert one or more quantum micro-operations in the first plurality of quantum micro-operations into one or more quantum micro-operations in the second plurality of quantum micro-operations for execution by the quantum controller core.

[0150] As described herein, instructions may refer to a specific configuration of hardware configured to perform a specific operation or have a predetermined function (e.g., an application specific integrated circuit (ASIC)) or software instructions stored in a memory embodied in a non-transitory computer-readable medium. Thus, the techniques shown in the figures may be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and / or with other electronic devices over a network) code and data using a computer machine-readable medium, such as a non-transitory computer machine-readable storage medium (e.g., a magnetic disk; an optical disk; a random access memory; a read-only memory; a flash memory device; a phase change memory) and a transitory computer machine-readable communication medium (e.g., an electrical, optical, acoustic, or other form of propagated signal—e.g., a carrier wave, an infrared signal, a digital signal, etc.).

[0151] In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components (e.g., one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens and / or displays), and network connections). The coupling of the set of processors and other components is typically through one or more buses and bridges (also referred to as bus controllers). The storage devices and the signals carrying network services represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device typically stores code and / or data for execution on the set of one or more processors of the electronic device. Of course, one or more parts of the embodiments of the present invention may be implemented using different combinations of software, firmware and / or hardware. Throughout the specific embodiments, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be practiced without some of these specific details. In specific instances, well-known structures and functions are not described in detail to avoid obscuring the subject matter of the present invention. Therefore, the scope and spirit of the present invention should be judged according to the appended claims.

[0152] Embodiments of the present invention may include the various steps described above. These steps may be embodied in machine executable instructions, which may be used to cause a general or special processor to perform these steps. Alternatively, these steps may be performed by specific hardware components containing hardwired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

Claims

1. A quantum control processor, comprising: Instruction fetching logic, the instruction fetching logic is used to fetch instructions from the memory, the instructions including quantum instructions; decoding logic for decoding the quantum instruction into a first plurality of quantum micro-operations; conversion logic for converting the first plurality of quantum micro-operations into a second plurality of quantum micro-operations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor; as well as The issuing logic is used to synchronously issue the second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel.

2. The quantum control processor according to claim 1, wherein: The instructions further include non-quantum instructions, wherein the decoding logic is used to decode the non-quantum instructions into a plurality of non-quantum micro-operations, and the quantum control processor further includes: The method further comprises: providing a dispatch logic for dispatching the plurality of non-quantum micro-operations to one or more execution units and dispatching the first plurality of quantum micro-operations to the conversion logic.

3. The quantum control processor according to claim 1 or 2, wherein: The conversion logic includes a plurality of conversion units, each conversion unit is associated with a quantum controller core among the plurality of quantum controller cores, and each conversion unit is configured to convert one or more quantum micro-operations among the first plurality of quantum micro-operations into one or more quantum micro-operations among the second plurality of quantum micro-operations for execution by the quantum controller core.

4. The quantum control processor according to claim 3, wherein: The issue logic includes a plurality of issue queues, each issue queue corresponding to a conversion unit in the plurality of conversion units, and each issue queue is configured to store the one or more quantum micro-operations in the first plurality of quantum micro-operations or indications of the one or more quantum micro-operations in the first plurality of quantum micro-operations.

5. The quantum control processor according to any one of claims 1 to 4, further comprising: a configuration memory for storing configuration data related to characteristics of the plurality of quantum controller cores, The decoding logic is used to read the configuration data to identify a first quantum controller core among the plurality of quantum controller cores to execute one or more of the second plurality of quantum micro-operations associated with a first instruction among the plurality of quantum instructions.

6. The quantum control processor according to claim 5, further comprising: Calibration logic for executing one or more calibration routines to generate at least a portion of the configuration data.

7. The quantum control processor according to any one of claims 1 to 6, further comprising at least one of a modular front-end unit and a modular back-end unit, wherein the modular front-end unit comprises the instruction acquisition logic and the decoding logic, and the modular back-end unit comprises the conversion logic and the publishing logic, and the quantum control processor further comprises: A modular interface is provided, which is used to couple a variable number of modular front-end units or modular back-end units.

8. The quantum control processor according to any one of claims 1 to 7, further comprising: A modular cluster comprising: a front end unit, and zero or more additional front end units, and a back end unit, and zero or more additional back end units.

9. The quantum control processor according to any one of claims 1 to 8, wherein: The conversion logic is used to store the second plurality of quantum micro-operations in a memory, and the quantum control processor further includes: A quantum controller manager is configured to communicate with the issuing logic to enable the plurality of quantum controller cores to access corresponding portions of the second plurality of quantum micro-operations from corresponding regions of the memory.

10. The quantum control processor according to claim 9, further comprising: A sequential circuit system is coupled to the issuing logic and the quantum controller manager, the issuing logic and / or the quantum controller manager being configured to access the sequential circuit system to synchronously issue the second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel.

11. A method comprising: Retrieving instructions from a memory, the instructions comprising quantum instructions; decoding the quantum instruction into a first plurality of quantum micro-operations; converting the first plurality of quantum micro-operations into a second plurality of quantum micro-operations based on characteristics of a plurality of quantum controller cores; as well as The second plurality of quantum micro-operations are synchronously issued to the plurality of quantum controller cores in parallel.

12. The method according to claim 11, wherein: The instructions further include non-quantum instructions, wherein the decoding logic is used to decode the non-quantum instructions into a plurality of non-quantum micro-operations, and the method further includes: The plurality of non-quantum micro-operations are dispatched to one or more execution units, and the first plurality of quantum micro-operations are dispatched to conversion logic.

13. The method according to claim 11 or 12, wherein: The transforming further includes performing, at least partially in parallel, a plurality of separate transformations, each of the plurality of separate transformations being associated with a different portion of the first plurality of quantum micro-operations and a quantum controller core of the plurality of quantum controller cores.

14. The method according to claim 13, wherein: Synchronously issuing the second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel further comprises storing each of the different portions of the first plurality of quantum micro-operations, or indications of each of the different portions, in a separate issue queue, each issue queue being associated with a quantum controller core of the plurality of quantum controller cores.

15. The method according to any one of claims 11 to 14, further comprising: storing configuration data related to characteristics of the plurality of quantum controller cores, The configuration data is read to identify a first quantum controller core of the plurality of quantum controller cores to execute one or more of the second plurality of quantum micro-operations associated with a first instruction of the plurality of quantum instructions.

16. The method according to claim 15, further comprising: One or more calibration routines are performed to generate at least a portion of the configuration data.

17. The method according to any one of claims 11 to 16, further comprising: storing the second plurality of quantum micro-operations in a memory, The plurality of quantum controller cores are caused to access corresponding portions of the second plurality of quantum micro-operations from corresponding regions of the memory.

18. A quantum system comprising: a memory for storing instructions associated with a quantum runtime, A host processor, the host processor is used to execute the instructions to implement the quantum runtime; a quantum control processor coupled to the memory, the quantum control processor comprising: Instruction fetching logic, the instruction fetching logic is used to fetch instructions from the memory, the instructions including quantum instructions; decoding logic for decoding the quantum instruction into a first plurality of quantum micro-operations; conversion logic for converting the first plurality of quantum micro-operations into a second plurality of quantum micro-operations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor; and The issuing logic is used to synchronously issue the second plurality of quantum micro-operations to the plurality of quantum controller cores in parallel.

19. A quantum system according to claim 18, wherein: The instructions further include non-quantum instructions, wherein the decoding logic is used to decode the non-quantum instructions into a plurality of non-quantum micro-operations, and the quantum system further includes: The method further comprises: providing a dispatch logic for dispatching the plurality of non-quantum micro-operations to one or more execution units and dispatching the first plurality of quantum micro-operations to the conversion logic.

20. A quantum system according to claim 18 or 19, wherein: The conversion logic includes a plurality of conversion units, each conversion unit is associated with a quantum controller core among the plurality of quantum controller cores, and each conversion unit is configured to convert one or more quantum micro-operations among the first plurality of quantum micro-operations into one or more quantum micro-operations among the second plurality of quantum micro-operations for execution by the quantum controller core.

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