Scanning driving circuit, display panel and display device

Abstract

The embodiment of the invention provides a scanning driving circuit, a display panel and a display device, and is characterized in that the input ends of the ith to (i + N) th gating units are electrically connected with the same first scanning signal line, and the input ends of the (i + N + 1) th to (i + N + M) th gating units are electrically connected with the same second scanning signal line; i > = 1, N > = 1, and M > = 2; the first end of the first communication unit is electrically connected with the first scanning signal line, and the second end of the first communication unit is electrically connected with the second scanning signal line; when the ith to (i + N + M) th gating units sequentially output the scanning signals, the holding time parts of the adjacent output scanning signals in the sequentially output scanning signals are overlapped; and in at least a part of time period when the (i + N) th-level gating unit and the (i + N + 1) th-level gating unit are opened, the first communication unit is opened, and the first scanning signal line and the second scanning signal line are electrically conducted. According to the scheme provided by the invention, the problem of cross grains at the junction of the display partitions can be effectively relieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a scan drive circuit, a display panel and a display device. Background Art

[0002] With the development of display technology and hardware technology, display panels are getting bigger and bigger. At the same time, in order to make full use of the display panel, a split-screen display function is proposed, that is, different display areas on the same display panel simultaneously display different operation interfaces, such as displaying news in some areas, displaying playing videos in some areas, or displaying different game perspectives in different areas, etc. Each display partition can be set with a different refresh rate, but how to ensure the display effect of the display partition has become an urgent problem to be solved. Summary of the invention

[0003] In view of this, the present application provides a scan driving circuit, a display panel and a display device.

[0004] In a first aspect, an embodiment of the present application provides a scan driving circuit, comprising Q cascaded shift registers and Q gating units, wherein an output end of the shift register is electrically connected to a control end of the gating unit and is used to control the gating unit to be turned on, an input end of the gating unit is electrically connected to a scan signal line and the scan signal line is used to transmit an initial scan signal to the gating unit, and an output end of the gating unit is electrically connected to a scan line and is used to output a scan signal to the scan line;

[0005] The scanning signal line includes a first scanning signal line and a second scanning signal line; the input ends of the i-th to (i+N)-th level gating units are all electrically connected to the same first scanning signal line, and the input ends of the (i+N+1)-th to (i+N+M)-th level gating units are all electrically connected to the same second scanning signal line; i≥1, N≥1, M≥2;

[0006] Wherein, the scan driving circuit also includes at least a first connecting unit, a first end of the first connecting unit is electrically connected to the first scan signal line and a second end of the first connecting unit is electrically connected to the second scan signal line; when the i-th to (i+N+M)-th selection units sequentially output scan signals, the maintenance time of adjacent scan signals output in the sequentially output scan signals partially overlaps; and in at least part of the time period when the (i+N)-th selection unit and the (i+N+1)-th selection unit are both turned on, the first connecting unit is turned on and electrically connects the first scan signal line and the second scan signal line.

[0007] In a second aspect, an embodiment of the present application provides a display panel, comprising a scan drive circuit as provided in the first aspect; the display panel comprises a display area, the display area comprises a first area and a second area, the first area and the second area both comprise a first scan line, the output end of the first selection unit is electrically connected to the first scan line in the first area, and the output end of the second selection unit is electrically connected to the first scan line in the second area.

[0008] In a third aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0009] Among the multiple gating units electrically connected to the first scanning signal line, the (i+N)th gating unit that outputs the scanning signal last, in at least a part of the time period when the scanning signal is output, because the first scanning signal line and the second scanning signal line are electrically connected through the first connecting unit, the first scanning signal line and the second scanning signal line are electrically connected to the (i+N)th gating unit and the (i+N+1)th gating unit at the same time period, so that the scanning signal output by the (i+N)th gating unit in the part of the time period is instantaneously pulled down. Therefore, the scanning signal output by the (i+N)th gating unit tends to be consistent with the scanning signals output by the i-th to (i+N-1)th gating units, which alleviates the problem of horizontal stripes at the junction of the display partitions. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 A schematic diagram of a scan drive circuit provided in an embodiment of the present application;

[0012] Figure 2 for Figure 1 A working timing diagram of the scan drive circuit shown;

[0013] Figure 3 is a schematic diagram of a scan driving circuit related to an embodiment of the present application;

[0014] Figure 4 for Figure 3 A working timing diagram of the scan drive circuit shown;

[0015] Figure 5 An equivalent circuit diagram of a pixel circuit related to an embodiment of the present application;

[0016] Figure 6A schematic diagram of a scan drive circuit provided in an embodiment of the present application;

[0017] Figure 7 A schematic diagram of a scan drive circuit provided in an embodiment of the present application;

[0018] Figure 8 for Figure 7 A working timing diagram of the scan drive circuit shown;

[0019] Fig. 9 for Figure 7 A working timing diagram of the scan drive circuit shown;

[0020] Fig.10 A schematic diagram of a scan drive circuit provided in an embodiment of the present application;

[0021] Fig.11 for Fig.10 A working timing diagram of the scan drive circuit shown;

[0022] Fig.12 A schematic diagram of a scan drive circuit provided in an embodiment of the present application;

[0023] Fig.13 for Fig.12 A working timing diagram of the scan drive circuit shown;

[0024] Fig.14 A schematic diagram of a scan drive circuit provided in an embodiment of the present application;

[0025] Fig.15 for Fig.14 A working timing diagram of the scan drive circuit shown;

[0026] Fig.16 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0027] Fig.17 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0029] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0030] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0031] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0032] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0033] It should be understood that although the terms first, second, etc. may be used to describe parts, protective layers, vertices, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish parts, protective layers, vertices, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first part may also be referred to as the second part, and similarly, the second part may also be referred to as the first part. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0034] Figure 1 A schematic diagram of a scan driving circuit provided in an embodiment of the present application is shown in FIG. Figure 2 for Figure 1 A working timing diagram of the scan drive circuit shown.

[0035] like Figure 1 As shown, the scan driving circuit provided by the embodiment of the present application includes Q cascaded shift registers 10 and Q gating units 20, the output end of the shift register 10 is electrically connected to the control end of the gating unit 20, and the input end of the gating unit 20 is electrically connected to the scan signal line 30, wherein the scan signal line 30 is used to transmit the initial scan signal PS to the gating unit 20. The output end of the shift register 10 outputs a trigger signal, and the trigger signal can trigger the shift register 10 of the next stage to work; in addition, the trigger signal output by the output end of the shift register 10 can turn on the gating unit 20 electrically connected to the output end.

[0036] The shift register 10 is used to control the gating unit 20 to start. Figure 1 and Figure 2, the output ends of the Q cascaded shift registers 10 start to output trigger signals TS1, TS2, ..., TSQ in sequence, and the Q gating units 20 are turned on in sequence. Among them, the Q gating units 20 can be regarded as the first stage gating units 20 to the Qth stage gating units 20 electrically connected to the first stage shift register 10 to the Qth stage shift register 10, respectively.

[0037] After receiving the initial scan signal PS, the gating unit 20 may process and output it, or may not process it and only output it. For the sake of clarity, the signal output from the output end of the gating unit 20 and related to the initial scan signal PS is called a scan signal. The gating unit 20 is used to output the scan signal to the scan line. Figure 1 and Figure 2 The first stage gating unit 20 to the Qth stage gating unit 20 are used to output scanning signals S1, S2, ..., SQ respectively. Among them, the scanning line can be electrically connected to the gates of multiple transistors, and the scanning signal refers to an enable signal for controlling the transistor to turn on.

[0038] In order to facilitate understanding with reference to the accompanying drawings, Figure 2 An example is given in which the trigger signal is a high-level voltage signal, the initial scanning signal PS is a high-level voltage signal, and the scanning signal is a high-level voltage signal.

[0039] Multi-frequency Display (MFD) products are products that can realize zoned frequency display, that is, products that can independently control the screen refresh rate of different display zones, where the display zones are different display areas in the display panel. In order to realize that the screen refresh rate of different display zones can be independently controlled, such as Figure 1As shown, Q selection units 20 can be divided into at least two selection unit groups 200, different selection unit groups 200 can correspond to different display partitions, each selection unit group 200 includes multiple selection units 20, the input ends of the selection units 20 in the same selection unit group 200 are electrically connected to the same scanning signal line 30, and the input ends of the selection units 20 in at least adjacent different selection unit groups 200 are electrically connected to different scanning signal lines 30. Although the 1st-stage shift register 10 to the Qth-stage shift register 10 can output trigger signals in sequence so that the 1st-stage selection unit 20 to the Qth-stage selection unit 20 are turned on in sequence, the selection units 20 in a selection unit group 200 will output scan signals in sequence only when the scan signal lines 30 electrically connected to the selection units 20 in the selection unit group 200 transmit the initial scan signal PS; when the scan signal lines 30 electrically connected to the selection units 20 in a selection unit group 200 do not transmit the initial scan signal PS, even if the selection units 20 in the selection unit group 200 are turned on in sequence, the selection units 20 in the selection unit group 200 will not output scan signals. Therefore, the embodiment of the present application can control the frequency of the initial scan signal PS transmitted by the scan signal line 30 electrically connected to a selection unit group 200, thereby controlling the frequency of the scan signal output by the selection unit 20 in the selection unit group 200, and thus controlling the screen refresh frequency of the display partition corresponding to the selection unit group 200.

[0040] by Figure 1 For example, the first-level gating unit 20 to the eighth-level gating unit 20 are divided into a first gating unit group 201 and a second gating unit group 202, wherein the scanning signal line 30 electrically connected to the first-level gating unit 20 to the fourth-level gating unit 20 included in the first gating unit group 201 is different from the scanning signal line 30 electrically connected to the fifth-level gating unit 20 to the eighth-level gating unit 20 included in the second gating unit group 202. Specifically, the input ends of the gating units 20 included in the first gating unit group 201 are all electrically connected to the scanning signal line 31, and the input ends of the gating units 20 included in the second gating unit group 202 are all electrically connected to the scanning signal line 32.

[0041] Combination Figure 1 and Figure 2In the first stage T1, the first-stage shift register 10 to the eighth-stage shift register 10 sequentially output trigger signals TS1, TS2, ..., TS8; and when the first-stage shift register 10 to the fourth-stage shift register 10 sequentially output trigger signals, the scan signal line 31 transmits the initial scan signal PS, then the first-stage selection unit 20 to the fourth-stage selection unit 20 sequentially output scan signals S1, S2, ..., S4; when the fifth-stage shift register 10 to the eighth-stage shift register 10 sequentially output trigger signals TS5, TS6, ..., TS8, the scan signal line 32 transmits the initial scan signal PS, then the fifth-stage selection unit 20 to the eighth-stage selection unit 20 sequentially output scan signals S5, S6, ..., S8.

[0042] Combination Figure 1 and Figure 2 In the first stage T1, the first-stage shift register 10 to the eighth-stage shift register 10 sequentially output trigger signals TS1, TS2, ..., TS8; and when the first-stage shift register 10 to the fourth-stage shift register 10 sequentially output trigger signals, the scan signal line 31 transmits the initial scan signal PS, and the first-stage selection unit 20 to the fourth-stage selection unit 20 sequentially output scan signals S1, S2, ..., S4; when the fifth-stage shift register 10 to the eighth-stage shift register 10 sequentially output trigger signals TS5, TS6, ..., TS8, the scan signal line 30 does not transmit the initial scan signal PS, and the fifth-stage selection unit 20 to the eighth-stage selection unit 20 do not output scan signals. That is, in one scan cycle, it can be achieved that before the first-stage selection unit 20 to the fourth-stage selection unit 20 sequentially output scan signals, the fifth-stage selection unit 20 to the eighth-stage selection unit 20 do not output scan signals.

[0043] Similarly, in one scanning cycle, it can be achieved that before the fifth-stage gating unit 20 to the eighth-stage gating unit 20 sequentially output scanning signals, the first-stage gating unit 20 to the fourth-stage gating unit 20 do not output scanning signals.

[0044] Therefore, the scan driving circuit provided in the embodiment of the present application can realize different display partitions having different picture refresh frequencies.

[0045] It should be noted that in one scanning cycle, the first stage shift register 10 to the Qth stage shift register sequentially output trigger signals TS1, TS2, ..., TSQ. It can also be understood that the period in which the first stage shift register 10 to the Qth stage shift register sequentially outputs a trigger signal is one scanning cycle.

[0046] In addition, the sustaining time of the scan signals outputted adjacently overlaps partially, that is, the sustaining time of the scan signals respectively outputted by the gating units 20 of adjacent stages overlaps partially. Figure 1 and Figure 2 In the first stage T1 and the second stage T2, when the first-stage selection unit 20 to the eighth-stage selection unit 20 sequentially output the scanning signals S1, S2, ..., S8, the start time of the first-stage selection unit 20 outputting the scanning signal S1 is earlier than the start time of the second-stage selection unit 20 outputting the scanning signal S2, and the maintenance time of the first-stage selection unit 20 outputting the scanning signal S1 partially overlaps with the time of the second-stage selection unit 20 outputting the scanning signal S2, and the start time of the second-stage selection unit 20 outputting the scanning signal S2 is shorter than the start time of the second-stage selection unit 20 outputting the scanning signal S2. The start time of the 7th level gating unit 20 outputting the scanning signal S7 is earlier than the start time of the 8th level gating unit 20 outputting the scanning signal S3, and the maintenance time of the 7th level gating unit 20 outputting the scanning signal S7 overlaps with the time of the 8th level gating unit 20 outputting the scanning signal S8. For example, in combination with Figure 1 and Figure 2 In the first stage T1, when the first-stage gating unit 20 to the fourth-stage gating unit 20 sequentially output the scanning signals S1, S2, S3, and S4, the start time of the first-stage gating unit 20 outputting the scanning signal S1 is earlier than the start time of the second-stage gating unit 20 outputting the scanning signal S2, and the maintenance time of the first-stage gating unit 20 outputting the scanning signal S1 partially overlaps with the time when the second-stage gating unit 20 outputs the scanning signal S2, and the start time of the second-stage gating unit 20 outputting the scanning signal S2 is The start time of the third-level enable unit 20 outputting the scan signal S3 is earlier than the start time of the third-level enable unit 20 outputting the scan signal S3, and the maintenance time of the second-level enable unit 20 outputting the scan signal S2 partially overlaps with the time when the third-level enable unit 20 outputs the scan signal S3; the start time of the third-level enable unit 20 outputting the scan signal S3 is earlier than the start time of the fourth-level enable unit 20 outputting the scan signal S4, and the maintenance time of the third-level enable unit 20 outputting the scan signal S3 partially overlaps with the time when the fourth-level enable unit 20 outputs the scan signal S4.

[0047] Different gating unit groups 200 are electrically connected to different scanning signal lines 30, and different gating units 20 in the gating unit group 200 can also maintain the same duration of outputting scanning signals. For example, when the first-level gating unit 20 to the fourth-level gating unit 20 included in the first gating unit group 201 sequentially output scanning signals S1, S2, S3 and S4, and the fifth-level gating unit 20 to the eighth-level gating unit 20 included in the second gating unit group 202 do not output scanning signals, although the scanning signal line 31 is still transmitting the initial scanning signal PS1 when the fifth-level gating unit 20 is turned on so that the fourth-level gating unit 20 maintains outputting the scanning signal S4, since the fifth-level gating unit 20 is not electrically connected to the scanning signal line 31 and the scanning signal line 32 does not transmit the scanning signal, the fifth-level gating unit 20 is turned on at this time but does not output the scanning signal, which also achieves that the duration of the fourth-level gating unit 20 maintaining the outputting of the scanning signal S4 is not limited by whether the fifth-level gating unit 20 outputs the scanning signal.

[0048] Figure 3 is a schematic diagram of a scan driving circuit related to an embodiment of the present application, Figure 4 for Figure 3 A working timing diagram of the scan drive circuit shown.

[0049] In a solution related to the present application, the initial scanning signal PS and the scanning signal are high level signals as an example for explanation. Figure 3 and Figure 4, while the first-stage gating unit 20 is still continuously outputting the scanning signal S1, the second-stage gating unit 20 starts to output the scanning signal S2, and the initial scanning signal PS1 transmitted on the first scanning signal line 31 is changed from being provided to the first-stage gating unit 20 to being provided to both the first-stage gating unit 20 and the second-stage gating unit 20. At this time, the scanning signal output by the first-stage gating unit 20 is pulled down momentarily. While the second-stage gating unit 20 is still continuously outputting the scanning signal S2, the third-stage gating unit 20 starts to output the scanning signal S3, and the initial scanning signal PS1 transmitted on the first scanning signal line 31 is changed from being provided to the second-stage gating unit 20 to being provided to both the second-stage gating unit 20 and the third-stage gating unit 20. At this time, the scanning signal S2 output by the second-stage gating unit 20 is pulled down momentarily. When the third-level selection unit 20 is still continuously outputting the scan signal S3, the fourth-level selection unit 20 starts to output the scan signal S4, and the initial scan signal PS1 transmitted on the first scan signal line 31 is changed from being provided to the third-level selection unit 20 to being provided to both the third-level selection unit 20 and the fourth-level selection unit 20. At this time, the scan signal S3 output by the third-level selection unit 20 is pulled down a little bit instantly. When the fourth-level selection unit 20 is continuously outputting the scan signal S4, the first scan signal line does not provide the initial scan signal PS1 to other selection units 20 except the fourth-level selection unit 20, and the scan signal S4 output by the fourth-level selection unit 20 will not be pulled down a little bit like the scan signal S1 output by the first-level selection unit 20, the scan signal S2 output by the second-level selection unit 20, and the scan signal S3 output by the third-level selection unit 20. This causes the display partition corresponding to the first selection unit group 201 to have the problem of displaying horizontal stripes.

[0050] It should be noted that the initial scan signal PS provided to the gating unit 20 means that the initial scan signal PS is transmitted to the enabled gating unit 20 so that the enabled gating unit 20 outputs a scan signal according to the initial scan signal PS.

[0051] In order to solve this problem, the embodiment of the present application connects the scan signal lines 30 electrically connected to the adjacent selection unit groups 200 to the same connection unit 40. At least when the selection unit 20 outputting the scan signal at the back in one selection unit group 200 and the selection unit 20 outputting the scan signal at the front in the next selection unit group 200 are turned on at the same time, the connection unit 40 makes the scan signal lines 30 electrically connected to the two selection unit groups 200 electrically conductive. When the scan signal lines 30 electrically connected to the two selection unit groups 200 are electrically conductive, the two selection unit groups 200 can be regarded as being electrically connected to the same scan signal line 30, and the scan signal actually output by the selection unit 20 outputting the scan signal at the back will be pulled down a little when the selection unit 20 outputting the scan signal at the front in the next selection unit group 200 is turned on, so that the scan signals output by different selection units 20 in the same selection unit group 200 are basically the same, thereby solving the above-mentioned horizontal stripe problem.

[0052] like Figure 1 As shown, the scan signal line 30 includes a first scan signal line 31 and a second scan signal line 32, the input ends of the i-th to (i+N)-th selection units 20 are all electrically connected to the same first scan signal line 31, and the input ends of the (i+N+1)-th to (i+N+M)-th selection units 20 are all electrically connected to the same second scan signal line 32. It can be considered that the first selection unit group 201 includes the i-th to (i+N)-th selection units 20 and the second selection unit group 202 includes the (i+N+1)-th to (i+N+M)-th selection units 20, each selection unit 20 in the first selection unit group 201 is electrically connected to the same first scan signal line 31, and each selection unit 20 in the second selection unit group 202 is electrically connected to the same second scan signal line 32.

[0053] Wherein, i≥1, N≥1, M≥2. Then the first gating unit group 201 and the second gating unit group 202 each include at least two gating units 20. For example, Figure 1 As shown, the first gating unit group 201 includes the first-stage gating unit 20 to the fourth-stage gating unit 20, then i=1 and N=3; the second gating unit group 202 includes the fifth-stage gating unit 20 to the eighth-stage gating unit 20, then M=4.

[0054] The working process of the scan driving circuit includes a first stage T1; in the first stage T1, the i-th to (i+N+M)-th selection units 20 sequentially output scan signals Si, S(i+1), ..., S(i+N+M), and among the sequentially output scan signals Si, S(i+1), ..., S(i+N+M), the maintenance time of adjacent output scan signals partially overlaps. That is, in the first stage T1, among the scan signals Si, S(i+1), ..., S(i+N+M) sequentially output by the i-th to (i+N+M)-th selection units 20, the scan signal Si at least partially overlaps with the scan signal S(i+1), the scan signal S(i+1) at least partially overlaps with the scan signal S(i+2), ..., the scan signal S(i+N+M-1) at least partially overlaps with the scan signal S(i+N+M). For example, Figure 1 As shown, i=1 and i+N+M=8, then in the first stage T1, among the scan signals S1, S2, ..., S8 sequentially output by the 1st to 8th level selection units 20, the scan signal S1 at least partially overlaps with the scan signal S2, the scan signal S2 at least partially overlaps with the scan signal S3, ..., the scan signal S7 at least partially overlaps with the scan signal S8.

[0055] In addition, in the embodiments of the present application, Figure 1 As shown, the scan driving circuit further includes at least a first connecting unit 41, a first end of the first connecting unit 41 is electrically connected to the first scan signal line 31 and a second end of the first connecting unit 41 is electrically connected to the second scan signal line 32. In at least a portion of the time period when the (i+N)th level gating unit 20 and the (i+N+1)th level gating unit 20 in the first stage T1 are both turned on, the first connecting unit 41 is turned on and electrically connects the first scan signal line 31 with the second scan signal line 32. That is, in at least a portion of the time period when the last level gating unit 20 in one gating unit group 200 and the frontmost level gating unit 20 in the next gating unit group 200 both output scan signals, the first connecting unit 41 electrically connects the scan signal lines 30 electrically connected to the two gating units 20.

[0056] In the embodiment of the present application, among the multiple gating units 20 electrically connected to the first scanning signal line 31, the (i+N)th level gating unit 20 that outputs the scanning signal last, in at least a part of the time period when the scanning signal is output, since the first scanning signal line 31 and the second scanning signal line 32 are electrically connected through the first connecting unit 41, the first scanning signal line 31 and the second scanning signal line 32 are electrically connected to the (i+N)th level gating unit 20 and the (i+N+1)th level gating unit 20 at the same time period, so that the scanning signal output by the (i+N)th level gating unit 20 in the part period is pulled down momentarily. Therefore, the scanning signal output by the (i+N)th level gating unit 20 tends to be consistent with the scanning signals output by the i-th to (i+N-1)th level gating units 20, which alleviates the problem of horizontal stripes at the junction of the display partitions.

[0057] For example, Figure 1 As shown, in at least a part of the period when the fourth-level selection unit 20 in the first selection unit group 201 outputs the scan signal S4, since the first scan signal line 31 and the second scan signal line 32 are electrically connected through the first connecting unit 41, the first scan signal line 31 and the second scan signal line 32 are electrically connected to the fourth-level selection unit 20 included in the first selection unit group 201 and the fifth-level selection unit 20 included in the second selection unit group 202. Then, at the moment when the first scan signal line 31 and the second scan line 32 are electrically connected and the fifth-level selection unit 20 is turned on, or at the moment when the fifth-level selection unit 20 is turned on and the first scan signal line 31 and the second scan line 32 are electrically connected, the scan signal S4 output by the fourth-level selection unit 20 is instantaneously pulled down. Therefore, the scanning signal output by the 4th level selection unit 20 in the first selection unit group 201 is consistent with the scanning signal output by the 1st to 3rd level selection units 20 being pulled down a little, alleviating the horizontal stripe problem at the position where the display partition corresponding to the first selection unit group 201 is close to the display partition corresponding to the second selection unit group 202.

[0058] In one embodiment of the present application, the initial scanning signal transmitted by the scanning signal line 30 is a high-level signal and the scanning signal output by the gating unit 20 is a high-level signal. When the scanning signal is a high-level signal, when the two gating units 20 are turned on at the same time, the scanning signal is pulled down instantly, resulting in the problem of horizontal stripes appearing in the display partition. At this time, the technical solution provided in the embodiment of the present application can effectively alleviate the above problems.

[0059] Figure 5 An equivalent circuit diagram of a pixel circuit related to an embodiment of the present application.

[0060] like Figure 5As shown, the pixel circuit includes a driving transistor M0, a data writing transistor M1, a threshold writing transistor M2, a first reset transistor M3, a second reset transistor M4, a power supply voltage writing transistor M5, a light emission control transistor M6 and a storage capacitor Cst. The first electrode of the driving transistor M0 is electrically connected to the data writing transistor M1 and the power supply voltage writing transistor M5, the second electrode of the driving transistor M0 is electrically connected to the first electrode of the threshold writing transistor M2 and the first electrode of the light emission control transistor M6, the gate of the driving transistor M0 is electrically connected to the first reset transistor M3 and the storage capacitor Cst, the second electrode of the threshold writing transistor M2 is electrically connected to the gate of the driving transistor M0, and the second electrode of the light emission control transistor M6 is electrically connected to the light emitting device LD and the second reset transistor M4.

[0061] Among them, when the first reset transistor M3 and the second reset transistor M4 are turned on, they are respectively used to reset the gate of the driving transistor M0 and the second electrode of the light-emitting control transistor M6; when the data writing transistor M1 and the threshold writing transistor M2 are turned on, they are respectively used to write the data voltage into the gate of the driving transistor M0; when the power supply voltage writing transistor M5 and the light-emitting control transistor M6 are turned on, they control the driving transistor M0 to generate a light-emitting driving current.

[0062] The stability of the data voltage written into the gate of the driving transistor M0 affects the reliability of the light-emitting driving current. In order to ensure that the data voltage is stably stored at the gate of the driving transistor M0, the first reset transistor M3 and the threshold write transistor M2 electrically connected to the gate of the driving transistor M0 may be N-channel transistors to alleviate the problem that the potential of the gate of the driving transistor M0 changes significantly due to leakage. Optionally, the semiconductor layer of the first reset transistor M3 and the threshold write transistor M2 may be a metal oxide semiconductor layer.

[0063] The scan drive circuit provided in the embodiment of the present application can be electrically connected to the gate of the first reset transistor M3 and / or the gate of the threshold write transistor M2 in the pixel circuit, that is, the scan signal output by the gating unit in the scan drive circuit is used to control the first reset transistor M3 to turn on and / or control the threshold write transistor M2 to turn on. When the pixel circuit includes the first reset transistor M3 and the threshold write transistor M2 at the same time and the first reset transistor M3 and the threshold write transistor M2 are both N-channel transistors, the first reset transistor M3 and the threshold write transistor M2 can be electrically connected to different scan drive circuits provided in the present application. When only the first reset transistor M3 in the pixel circuit is an N-channel transistor, the first reset transistor M3 can be electrically connected to the scan drive circuit provided in the present application. When only the threshold write transistor M2 in the pixel circuit is an N-channel transistor, the threshold write transistor M2 can be electrically connected to the scan drive circuit provided in the present application.

[0064] It should be noted that Figure 5 A possible pixel circuit related to the present application is given. In addition, the scan drive circuit provided in the embodiment of the present application can also be used in addition to Figure 5 The pixel circuits of other structures other than those described above are electrically connected, and this application does not limit this.

[0065] Figure 6 A schematic diagram of a scan driving circuit provided in an embodiment of the present application.

[0066] In one embodiment of the present application, Figure 6 As shown, the first connecting unit 41 includes at least one connecting transistor MC, then the first end of the first connecting unit 41 can be the first electrode of the connecting transistor MC, the second end can be the second electrode of the connecting transistor MC, and the control end can be the gate of the connecting transistor MC. When the first connecting unit 41 is turned on, the first electrode and the second electrode of the connecting transistor MC included therein are electrically connected.

[0067] In the embodiment of the present application, the at least one connection transistor MC is a P-channel transistor, and when a low-level control signal is received at the control end of the first connection unit 41, the first connection unit 41 is turned on. Since the connection transistor MC in the first connection unit 41 is a P-channel transistor, the first connection unit 41 is turned on more promptly when receiving a low-level control signal. In addition, when the scan signal is a high-level signal, the P-channel connection transistor MC is selected as the switch in the first connection unit 41 for realizing electrical conduction and electrical insulation between the first scan signal line 31 and the second scan signal line 32, which reduces the risk of the first connection unit 41 being mistakenly turned on by the high-level scan signal and the initial scan signal PS, so that the first connection unit 41 can play a better role.

[0068] For the convenience of description and illustration, the following description is given by taking the case where the first transistor in the first connecting unit 41 is a P-channel transistor as an example.

[0069] In one embodiment of the present application, Figure 6 As shown, the first connection unit 41 includes a connection transistor MC, that is, the first scan signal line 31 and the second scan signal line 32 are connected to one connection transistor MC. By providing fewer connection transistors MC to connect the first scan signal line 31 and the second scan signal line 32, the process difficulty can be reduced; and when the scan drive circuit is located in the frame area of ​​the display panel, it is conducive to realizing a narrow frame of the display panel.

[0070] Figure 7 A schematic diagram of a scan driving circuit provided in an embodiment of the present application.

[0071] In one embodiment of the present application, Figure 7 As shown, the first connection unit 41 includes at least two connection transistors MC, and the first electrodes of the at least two connection transistors MC are electrically connected to the first scan signal line 31, and the second electrodes of the at least two connection transistors MC are electrically connected to the second scan signal line 32. That is, the first scan signal line 31 and the second scan signal line 32 are connected to at least two connection transistors MC. By providing more connection transistors MC to connect the first scan signal line 31 and the second scan signal line 32, on the one hand, the risk of the first scan signal line 31 and the second scan signal line 32 being unable to be electrically connected due to damage of the connection transistors MC can be reduced; on the other hand, the impedance between the first scan signal line 31 and the second scan signal line 32 can be made smaller when the at least two connection transistors MC are turned on, so that the (i+N+1)th level gating unit can effectively pull down the scan signal S(i+N) output by the (i+N)th level gating unit 20.

[0072] When the first connection unit 41 includes at least two connection transistors MC, the at least two connection transistors MC may be disposed in a dispersed manner along the extending direction of the first scanning signal line 31 and the second scanning signal line 32. Figure 7 As shown, the first connecting unit 41 includes three connecting transistors MC and the three connecting transistors MC are respectively arranged at a position close to the upper end of the first scanning signal line 31 and the second scanning signal line 32, a position close to the lower end of the first scanning signal line 31 and the second scanning signal line 32, and a position close to the middle position of the first scanning signal line 31 and the second scanning signal line 32 in their extension direction.

[0073] In addition, if Figure 7 As shown, when the first connectivity unit 41 includes at least two connectivity transistors MC, the control terminals of the at least two connectivity transistors MC can be electrically connected to the same control signal line 400. Multiple connectivity transistors MC in the first selection unit 41 can be controlled to be turned on simultaneously through one control signal line 400, without setting too many control signal lines 400, which can reduce the process difficulty; and when the scan drive circuit is located in the frame area of ​​the display panel, it is conducive to realizing a narrow frame of the display panel.

[0074] In the embodiment of the present application, the time during which the first scan signal line 31 and the second scan signal line 32 are electrically connected can be determined according to the number of other scan signals overlapping with the sustaining time of the scan signal. The number of other scan signals overlapping with the sustaining time of the scan signal is substantially equal to the number of times the scan signals output by the other gating units 20 in the gating unit group 200, except for the gating unit 20 that outputs the scan signal later, are instantly pulled down.

[0075] Figure 8 for Figure 7A working timing diagram of the scan drive circuit shown.

[0076] For example, Figure 8 As shown, the number of other scan signals overlapping with the maintenance time of a scan signal is 1, then the scan signals S1, S2, ..., S(i+N-1) respectively output by the first-level selection unit 20, the second-level selection unit 20 and the third-level selection unit 20 in the first selection unit group 201 overlap with one adjacent output scan signal, that is, the scan signal S1 at least partially overlaps with the scan signal S2, the scan signal S2 at least partially overlaps with the scan signal S3, ..., the scan signal S(i+N-1) at least partially overlaps with the scan signal S(i+N). It can be understood that the number of times the scan signals S1, S2, ..., S(i+N-1) are instantly pulled down is 1, then the time for the first scan signal line 31 and the second scan signal line S2 to be electrically conductive should ensure that the scan signal S(i+N) is pulled down once. Therefore, as Figure 8 As shown, the scan control line 400 outputs at least part of the transmission enable signal Ctr (low level signal) of the scan signal when the (i+N)-th level selection unit 20 and the (i+N+1)-th level selection unit 20 simultaneously output the scan signal, that is, the first scan signal line 31 and the second scan signal line 32 are electrically conductive during at least part of the period when the (i+N)-th level selection unit 20 and the (i+N+1)-th level selection unit 20 simultaneously output the scan signal, so that the scan signal S(i+N) is pulled down twice.

[0077] Fig. 9 for Figure 7 A working timing diagram of the scan drive circuit shown.

[0078] For example, Fig. 9 As shown, the number of other scanning signals overlapping with the maintenance time of a scanning signal is 2, then the scanning signals S1, S2, ..., S(i+N-1) respectively output by the 1st-level selection unit 20, the 2nd-level selection unit 20, ..., and the (i+N-1)th-level selection unit 20 in the first selection unit group 201 overlap with two adjacent output scanning signals, that is, the scanning signal S1 at least partially overlaps with the scanning signal S2 and at least partially overlaps with the scanning signal S3, the scanning signal S2 at least partially overlaps with the scanning signal S3 and at least partially overlaps with the scanning signal S4, ... It can be understood that the number of times the scanning signals S1, S2, and S3 are pulled down momentarily is 2, the number of times the scanning signal S(i+N-1) is pulled down momentarily is 1, and the number of times the scanning signal S(i+N) is pulled down momentarily is 0, then the time for the first scanning signal line 31 and the second scanning signal line S2 to be electrically connected should ensure that the number of times the scanning signal S(i+N-1) and the scanning signal S(i+N) are pulled down momentarily is 2. Therefore, if Fig. 9As shown, the scan control line 400 transmits the enable signal Ctr (low level signal) during at least a portion of the period when the (i+N-1)th level gating unit 20, the (i+N)th level gating unit 20, and the (i+N+1)th level gating unit 20 simultaneously output the scan signal, that is, the first scan signal line 31 and the second scan signal line 32 are electrically conductive during at least a portion of the period when the (i+N-1)th level gating unit 20, the (i+N)th level gating unit 20, and the (i+N+1)th level gating unit 20 simultaneously output the scan signal, so that the scan signal S(i+N- 1) is pulled down once again, and the scanning signal S(i+N-1) is pulled down once; and, the scanning control line 400 transmits the enable signal Ctr (low level signal) during at least part of the period when the (i+N)-th level gating unit 20 and the (i+N+2)-th level gating unit 20 simultaneously output the scanning signal, that is, the first scanning signal line 31 and the second scanning signal line 32 are electrically conductive during at least part of the period when the (i+N)-th level gating unit 20 and the (i+N+2)-th level gating unit 20 simultaneously output the scanning signal, so that the scanning signal S(i+N) is pulled down once again.

[0079] In addition, when the i-th to (i+N)-th gating units 20 sequentially output scanning signals and the (i+N+1)-th to (i+N+M)-th gating units 20 remain in the off state, the maintenance time of the adjacent scanning signals outputted in the sequentially output scanning signals partially overlaps, and the first connecting unit 41 remains in the off state. Figure 8 and Fig. 9 As shown, the working process of the scan driving circuit includes a second stage T2. In the second stage T2, the selection units 20 in the first selection unit group 201 output scan signals in sequence and the selection units 202 in the second selection unit group 202 do not output scan signals. Then, the first connecting unit 41 remains in an off state in the second stage T2 to avoid the selection units 202 in the second selection unit group 202 from erroneously outputting scan signals.

[0080] Fig.10 A schematic diagram of a scan driving circuit provided in an embodiment of the present application.

[0081] In one embodiment of the present application, Q gating units 20 are divided into at least a first gating unit group 201, a second gating unit group 202 and a third gating unit group 203, and the first gating unit group 201, the second gating unit group 202 and the third gating unit group 203 each include a plurality of gating units 20 capable of outputting scan signals in sequence.

[0082] Specifically, Fig.10As shown, the first gating unit group 201 includes the i-th to (i+N)-th gating units 20, the second gating unit group 202 includes the (i+N+1)-th to (i+N+M)-th gating units 20, and the third gating unit group 203 includes the (i+N+M+1)-th to (i+N+M+K)-th gating units 20. Among them, the i-th to (i+N+M+K)-th shift registers 10 can sequentially output trigger signals TSi to trigger signals (i+N+M+K), and whether the multiple gating units 20 respectively included in the first gating unit group 201, the second gating unit group 202, and the third gating unit group 203 can output scan signals depends on whether the scan signal lines 30 electrically connected to them transmit primary scan signals when they are turned on. Among them, K≥2.

[0083] The working process of the scan driving circuit includes a third stage T3; in the third stage T3, the (i+N+1)th to (i+N+M+K)th level selection units 20 sequentially output S(i+N+1), S(i+N+M+1), ..., S(i+N+M+K), and among the sequentially output scan signals S(i+N+1), S(i+N+M+1), ..., S(i+N+M+K), the maintenance time of adjacent output scan signals partially overlaps. That is, in the third stage T3, among the scanning signals S(i+N+1), S(i+N+M+1), ..., S(i+N+M+K) sequentially output by the (i+N+1)th to (i+N+M+K)th gating units 20, the scanning signal S(i+N+1) at least partially overlaps with the scanning signal S(i+N+2), the scanning signal S(i+N+2) at least partially overlaps with the scanning signal S(i+N+3), ..., the scanning signal S(i+N+M+K-1) at least partially overlaps with the scanning signal S(i+N+M+K). For example, Fig.10 As shown, i+N+1=5 and i+N+M+K=12, then in the third stage T3, among the scan signals S5, S6, ..., S12 sequentially output by the 5th to 12th level selection units 20, the scan signal S5 at least partially overlaps with the scan signal S6, the scan signal S6 at least partially overlaps with the scan signal S7, ..., the scan signal S11 at least partially overlaps with the scan signal S12.

[0084] Among them, the scanning signal line 30 electrically connected to the input end of the (i+N+M+1)th to (i+N+M+K)th level selection unit 20 is different from the scanning signal line 30 electrically connected to the input end of the (i+N+1)th to (i+N+M)th level selection unit 20; and the scanning drive circuit also includes a second selection unit 42, a first end of the second connecting unit 42 is electrically connected to the second scanning signal line 32, and a second end of the second connecting unit 42 is electrically connected to the scanning signal line 30 electrically connected to the input end of the (i+N+M+1)th to (i+N+M+K)th level selection unit 20. Then, in at least a portion of the time period when the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 are both turned on in the third stage T3, the second connecting unit 42 is turned on and electrically connects the second scanning signal line 32 with the scanning signal line 30 electrically connected to the input ends of the (i+N+M+1)th to (i+N+M+K)th level gating units 20. That is, in at least a portion of the time period when the last level gating unit 20 in the second gating unit group 202 and the frontmost level gating unit 20 in the third gating unit group 203 both output scanning signals, the second connecting unit 42 electrically connects the scanning signal lines 30 electrically connected to the two gating units 20, respectively. Then, the second scanning signal line 32 is simultaneously connected to the turned-on (i+N+M)th level gating unit 20 and the turned-on (i+N+M+1)th level gating unit 20 in this part of the time period, so that the scanning signal output by the (i+N+M)th level gating unit 20 in this part of the time period is pulled down momentarily. Therefore, the scanning signal output by the (i+N+M)th level gating unit 20 is consistent with the scanning signal output by the (i+N+1)th to (i+N+M-1)th level gating units 20, which alleviates the horizontal stripe problem at the junction of the display partition corresponding to the second gating unit group 202 and the display partition corresponding to the third gating unit group 203.

[0085] Fig.11 for Fig.10 A working timing diagram of the scan drive circuit shown.

[0086] In a technical solution corresponding to this implementation, if Fig.10 As shown, the scan signal line 30 further includes a third scan signal line 33; the input ends of the (i+N+M+1)th to (i+N+M+K)th level gating units 20 are electrically connected to the same third scan signal line 33; the first end of the second connecting unit 42 is electrically connected to the second scan signal line 32 and the second end of the second connecting unit 42 is electrically connected to the third scan signal line 33. Fig.10 and Fig.11In the third stage T3, during at least a portion of the time period when both the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 are turned on, the second connecting unit 42 is turned on and electrically connects the second scanning signal line 32 and the third scanning signal line 33. Fig.11 As shown, the control signal line 402 electrically connected to the connecting transistor MC included in the second connecting unit 42 transmits the enable signal Ctr2 during at least a partial period when the (i+N+M)th level selection unit 20 and the (i+N+M+1)th level selection unit 20 are both turned on, so as to electrically connect the second scanning signal line 32 and the third scanning signal line 33.

[0087] In the present technical solution, the gating units 20 in the first gating unit group 201, the gating units 20 in the second gating unit group 202 and the gating units 20 in the third gating unit group 203 are electrically connected to different scanning signal lines 30 respectively, so that the picture refresh frequencies of the display partitions corresponding to the first gating unit group 201, the second gating unit group 202 and the third gating unit group 203 can be individually controlled and the horizontal stripe problem at the junction of adjacent display partitions can be alleviated.

[0088] Fig.12 A schematic diagram of a scan driving circuit provided in an embodiment of the present application is shown in FIG. Fig.13 for Fig.12 A working timing diagram of the scan drive circuit shown.

[0089] In a technical solution corresponding to this embodiment, as Fig.12 As shown, the scanning signal line 30 further includes a third scanning signal line 33; the input ends of the (i+N+M+1)th to (i+N+M+K)th level selection units 20 are electrically connected to the same third scanning signal line 33; the first end of the second connecting unit 42 is electrically connected to the first scanning signal line 31 and the second end of the second connecting unit 42 is electrically connected to the third scanning signal line 33. Fig.12 and Fig.13 In the third stage T3, during at least a portion of the time period when the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 are both turned on, the first connecting unit 201 and the second connecting unit 202 are both turned on and electrically connect the second scanning signal line 32 and the third scanning signal line 33. For example, Fig.13 As shown, the control signal line 401 electrically connected to the connecting transistor MC included in the first connecting unit 41 and the control signal line 402 electrically connected to the connecting transistor MC included in the second selection unit 42 respectively transmit enable signals Ctr1 and Ctr2 during at least a partial period of time when the (i+N+M)th level selection unit 20 and the (i+N+M+1)th level selection unit 20 are both turned on, so as to electrically connect the second scanning signal line 32 and the third scanning signal line 33.

[0090] Since when the first connecting unit 201 is turned on, the first scanning signal line 31 and the second scanning signal line 32 are electrically connected; when the second connecting unit 201 is turned on, the first scanning signal line 31 and the third scanning signal line 33 are electrically connected, when the first connecting unit 201 and the second connecting unit 202 are both turned on, the second scanning signal line 32 and the third scanning signal line 33 can be electrically connected.

[0091] It should be noted that the structure and working principle of the second gating unit 42 are similar to those of the first gating unit 41 , and will not be described in detail again.

[0092] Fig.14 A schematic diagram of a scan driving circuit provided in an embodiment of the present application is shown in FIG. Fig.15 for Fig.14 A working timing diagram of the scan drive circuit shown.

[0093] In a technical solution corresponding to this embodiment, as Fig.14 As shown, the input end of the (i+N+M+1)th to (i+N+M+K)th level gating unit 20 is electrically connected to the first scanning signal line 33; Fig.14 and Fig.15 , in at least part of the time period when the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 are both turned on in the third stage T3, the first connecting unit 201 is turned on and electrically connects the first scanning signal line 31 with the second scanning signal line 32. Since the input ends of the (i+N+M+1)th to (i+N+M+K)th level gating units 20 are electrically connected to the first scanning signal line 33, when the (i+N+M+1)th level gating unit 20 is turned on in the third stage T3, the first scanning signal line 31 transmits the initial scanning signal, thereby electrically connecting the first scanning signal line 31 with the second scanning signal line 32, and the second scanning signal line 32 is equivalent to electrically connecting the (i+N+M)th level gating unit 20 and the (i+N+M+1)th level gating unit 20 that are turned on at the same time. For example, Fig.11 As shown, the control signal line 400 electrically connected to the connecting transistor MC included in the first connecting unit 41 transmits the enable signal Ctr during at least a partial period of time when the (i+N+M)th level selection unit 20 and the (i+N+M+1)th level selection unit 20 are both turned on, so as to electrically connect the first scanning signal line 31 and the second scanning signal line 32.

[0094] It should be noted that the third stage T3 may or may not belong to the same scanning cycle as the first stage T1. The second stage T2 may or may not belong to the same scanning cycle as the first stage T1.

[0095] Fig.16 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0096] In one embodiment of the present application, Fig.16 As shown, the display panel 01 includes a display area AA and a non-display area NA, and the non-display area NA may surround the display area AA. The display panel 01 includes a scan drive circuit provided by any of the above embodiments. The scan drive circuit may be in the non-display area NA of the display panel. In a narrow-frame display panel or a frameless display panel, the scan drive circuit may also be located in the display area AA.

[0097] The display area AA includes a first area AA1 and a second area AA2, each of which includes a first scan line 50, and the output ends of the i-th to (i+N)-th level gating units 20 are electrically connected to the first scan line 50 in the first area AA1, and the output ends of the (i+N+1)-th to (i+N+M)-th level gating units 20 are electrically connected to the first scan line 50 in the second area AA2. That is, the gating units 20 in the first gating unit group 201 are electrically connected to the first scan line 50 in the first area AA1, and the gating units 20 in the second gating unit group 202 are electrically connected to the first scan line 50 in the second area AA2. The first area AA1 and the second area AA2 may be different display areas.

[0098] The technical solution provided in the embodiment of the present application can alleviate the problem of horizontal stripes at the junction of the first area AA1 and the second area AA2, thereby improving the display uniformity of the display panel 01.

[0099] In one technical solution, combining Figure 5 As shown, the first area AA1 and the second area AA2 also include a pixel circuit 60, the pixel circuit 60 includes a driving transistor M0 and a first transistor, the first transistor is electrically connected to the gate of the driving transistor M0 and the first transistor is an N-channel transistor. The first transistor can be a threshold write transistor M2 or a first reset transistor M3. It should be noted that Figure 5 The pixel circuit shown is only one possible implementation manner. In some embodiments, the pixel circuit may also be a pixel circuit with other structures.

[0100] The first scan line 60 is electrically connected to the gate of the first transistor, that is, the gate of the first transistor receives the scan signal output by the scan driving circuit provided in the embodiment of the present application through the first scan line.

[0101] In addition, the display panel 01 may further include a second scan line, a third scan line, etc., and the second scan line, the third scan line, etc. may be electrically connected to the gates of other transistors in the pixel circuit except the first transistor, respectively.

[0102] Fig.17 A schematic diagram of a display device provided in an embodiment of the present application.

[0103] The present application also provides a display device, such as Fig.17 As shown, the display device includes a display panel 01 as provided in any of the above embodiments. The display device provided in the embodiment of the present application may be an electronic device such as a mobile phone, a computer, a television, a vehicle-mounted display device, etc. The embodiment of the present application is not specifically limited.

[0104] The display uniformity of the display device provided by the embodiment of the present application can be significantly improved.

[0105] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A scanning driving circuit, characterized in that: It comprises Q cascaded shift registers and Q gating units, wherein the output end of the shift register is electrically connected to the control end of the gating unit and is used to control the gating unit to start, the input end of the gating unit is electrically connected to a scan signal line and the scan signal line is used to transmit an initial scan signal to the gating unit, and the output end of the gating unit is electrically connected to the scan line and is used to output a scan signal to the scan line; The scanning signal line includes a first scanning signal line and a second scanning signal line; the input ends of the gating units of the i-th to (i+N)-th levels are all electrically connected to the same first scanning signal line, and the input ends of the gating units of the (i+N+1)-th to (i+N+M)-th levels are all electrically connected to the same second scanning signal line; i≥1, N≥1, M≥2; Wherein, the scan driving circuit also includes at least a first connecting unit, a first end of the first connecting unit is electrically connected to the first scan signal line and a second end of the first connecting unit is electrically connected to the second scan signal line; when the selection units at the i-th level to the (i+N+M)-th level output the scan signals in sequence, the maintenance time of the adjacent scan signals output in the sequence overlaps partially; and in at least part of the time period when the (i+N)-th level selection unit and the (i+N+1)-th level selection unit are both turned on, the first connecting unit is turned on and electrically connects the first scan signal line with the second scan signal line.

2. The scanning driving circuit according to claim 1, characterized in that: When the gating units from the i-th to the (i+N)-th levels sequentially output the scanning signals and the gating units from the (i+N+1)-th to the (i+N+M)-th levels remain in the off state, the maintenance time of the adjacent scanning signals output in the sequentially output scanning signals partially overlaps, and the first connecting unit remains in the off state.

3. The scanning driving circuit according to claim 1, characterized in that: The scanning signal is a high level signal.

4. The scanning driving circuit according to claim 1 or 3, characterized in that: The first connection unit includes at least one connection transistor, and the at least one connection transistor is a P-channel transistor.

5. The scanning driving circuit according to claim 1, characterized in that: The first connection unit includes at least two connection transistors, first electrodes of the at least two connection transistors are electrically connected to the first scan signal line, and second electrodes of the at least two connection transistors are electrically connected to the second scan signal line.

6. The scanning driving circuit according to claim 1, characterized in that: The scanning signal line further includes a third scanning signal line; the input end of the gating unit of the (i+N+M+1)th to (i+N+M+K)th level is electrically connected to the same third scanning signal line, K≥2; The scan driving circuit further comprises a second connecting unit, a first end of the second connecting unit is electrically connected to the second scan signal line and a second end of the second connecting unit is electrically connected to the third scan signal line; Among them, when the selection units at the (i+N+1)th level to the (i+N+M+K)th level output the scanning signals in sequence, the maintenance time of the adjacent scanning signals output in the sequentially output scanning signals partially overlaps; during at least part of the time period when the selection unit at the (i+N+M)th level and the selection unit at the (i+N+M+1)th level are both turned on, the second connecting unit is turned on and electrically connects the second scanning signal line with the third scanning signal line.

7. The scanning driving circuit according to claim 1, characterized in that: The scanning signal line further includes a third scanning signal line; the input end of the gating unit of the (i+N+M+1)th to (i+N+M+K)th level is electrically connected to the same third scanning signal line, K≥2; The scan driving circuit further includes a second connecting unit, a first end of the second connecting unit is electrically connected to the first scan signal line and a second end of the second connecting unit is electrically connected to the third scan signal line; Among them, when the selection units at the (i+N+1)th level to the (i+N+M+K)th level output the scanning signals in sequence, the maintenance time of the adjacent scanning signals output in the sequentially output scanning signals partially overlaps; in at least a partial period of time when the selection unit at the (i+N+M)th level is turned on and the selection units at the (i+N+M+1)th level are both turned on, the first connecting unit and the second connecting unit are both turned on and the second scanning signal line is electrically connected to the third scanning signal line.

8. The scanning driving circuit according to claim 1, characterized in that: The input terminals of the gating units of the (i+N+M+1)th to (i+N+M+K)th stages are electrically connected to the same first scanning signal line, K≥2; Among them, when the selection units at the (i+N+1)th level to the (i+N+M+K)th level output the scanning signals in sequence, the maintenance time of the adjacent scanning signals among the scanning signals output in sequence partially overlaps; during at least part of the time period when the selection unit at the (i+N+M)th level and the selection unit at the (i+N+M+1)th level are both turned on, the first connecting unit is turned on and electrically connects the first scanning signal line with the second scanning signal line.

9. A display panel, characterized in that: A scanning driving circuit comprising the scanning driving circuit according to any one of claims 1 to 8; The display panel includes a display area, the display area includes a first area and a second area, the first area and the second area both include a first scan line, the output ends of the i-th to (i+N)-th level gating units are electrically connected to the first scan line in the first area, and the output ends of the (i+N+1)-th to (i+N+M)-th level gating units are electrically connected to the first scan line in the second area.

10. The display panel according to claim 9, characterized in that: The first area and the second area both further include a pixel circuit, wherein the pixel circuit includes a driving transistor and a first transistor, wherein the first transistor is electrically connected to a gate of the driving transistor and the first transistor is an N-channel transistor; The first scan line is electrically connected to a gate of the first transistor.

11. A display device, characterized in that: Comprising a display panel as described in any one of claims 9-10.

Images