Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a pixel circuit, the pixel circuit comprises a mirror current receiving module, a digital driving module and a light-emitting module, and light-emitting currents in corresponding light-emitting sub-loops are adjusted through the mirror current receiving units; and each digital driving unit adjusts the light-emitting time of the light-emitting module through the corresponding light-emitting sub-loop, so that the number of sub-frames required by the hybrid driving mode can be reduced under the condition of same gray scale display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In terms of grayscale implementation, the pixel circuit in the display panel mainly includes the following two driving modes:

[0003] Analog driving mode: The analog driving mode adjusts the luminous brightness of the light-emitting device by adjusting the luminous current flowing through the light-emitting device. In the analog driving mode, each gray scale corresponds to a data voltage, and a data voltage corresponds to a luminous brightness of the light-emitting device.

[0004] Digital driving mode: The digital driving mode adjusts the luminous brightness of the light-emitting device by adjusting the luminous time of the light-emitting device. The working state of the light-emitting device in the digital driving mode only includes the bright state and the dark state.

[0005] However, in order to achieve the same grayscale display, the digital driving method requires a larger number of sub-frames, which requires a larger amount of display data. Summary of the invention

[0006] The present application provides a display panel and a display device to alleviate the technical problem that a digital driving method requires more sub-frames to be implemented under the same grayscale display.

[0007] In a first aspect, the present application provides a display panel, which includes a pixel circuit, which includes a mirror current receiving module, a digital driving module and a light-emitting module. The mirror current receiving module includes N mirror current receiving units, and the control end of each mirror current receiving unit is connected to the same mirror current, and each mirror current receiving unit is connected in series in a light-emitting sub-circuit, where N is an integer greater than or equal to 2; the digital driving module includes N digital driving units, and each digital driving unit is connected in series in a light-emitting sub-circuit; the light-emitting module is connected to a total light-emitting circuit formed by each light-emitting sub-circuit.

[0008] In some of the embodiments, the mirror current receiving unit includes multiple receiving transistors, the gate of each receiving transistor is connected to the same mirror current, and each receiving transistor is connected in series in the light-emitting sub-circuit; wherein the channel width-to-length ratio of each receiving transistor in the same pixel circuit is different.

[0009] In some of the embodiments, the digital driving unit includes a switching transistor and a register, the switching transistor is connected in series in the light-emitting sub-circuit; the register is connected to the gate of the switching transistor, a scan line, and a data line.

[0010] In some embodiments, the temporary register includes an inverter, a first storage transistor, a second storage transistor, a third storage transistor, a fourth storage transistor, a fifth storage transistor and a sixth storage transistor, the input end of the inverter is connected to the data line; the first electrode of the first storage transistor is connected to the positive end of the power supply; the first electrode of the second storage transistor is connected to the second electrode of the first storage transistor and the gate of the switch transistor, the second electrode of the second storage transistor is connected to the negative end of the power supply, and the gate of the second storage transistor is connected to the gate of the first storage transistor; the first electrode of the third storage transistor is connected to the positive end of the power supply, the second electrode of the third storage transistor is connected to the gate of the first storage transistor, and the gate of the third storage transistor is connected to the second electrode of the first storage transistor; the first electrode of the fourth storage transistor is connected to the second electrode of the third storage transistor, the second electrode of the fourth storage transistor is connected to the negative end of the power supply, and the gate of the fourth storage transistor is connected to the gate of the third storage transistor; the first electrode of the fifth storage transistor is connected to the data line, the second electrode of the fifth storage transistor is connected to the gate of the second storage transistor, and the gate of the fifth storage transistor is connected to the scan line; the first electrode of the sixth storage transistor is connected to the output end of the inverter, the second electrode of the sixth storage transistor is connected to the gate of the third storage transistor, and the gate of the sixth storage transistor is connected to the gate of the fifth storage transistor.

[0011] In some implementations, each register in the same digital driving module is connected to the same scan line, and each register in the same digital driving module is connected to different data lines.

[0012] In some embodiments, the light-emitting module includes a light-emitting device, and the light-emitting device is connected in a total light-emitting circuit.

[0013] In some embodiments, the light-emitting module further includes a first mirror transistor and a second mirror transistor, wherein the first electrode of the first mirror transistor is connected to the positive terminal of the power supply, the gate of the first mirror transistor is connected to the second electrode of the first mirror transistor and each light-emitting sub-circuit; the gate of the second mirror transistor is connected to the gate of the first mirror transistor, the first electrode of the second mirror transistor is connected to the positive terminal of the power supply, the second electrode of the second mirror transistor is connected to the anode of the light-emitting device, and the cathode of the light-emitting device is connected to the negative terminal of the power supply.

[0014] In some of the embodiments, the display panel further includes a mirror current emission module for providing a mirror current, and the mirror current emission module is connected to the mirror current receiving module in each pixel circuit.

[0015] In some embodiments, the mirror current emission module includes a current source and a third mirror transistor, one end of the current source is connected to the positive end of the power supply; the first electrode of the third mirror transistor is connected to the other end of the current source and the gate of the third mirror transistor to provide a mirror current, and the second electrode of the third mirror transistor is connected to the negative end of the power supply.

[0016] In some embodiments, the mirror current emission module further includes a current source and a third mirror transistor, a fourth mirror transistor and a fifth mirror transistor, one end of the current source is connected to the positive end of the power supply; the first electrode of the third mirror transistor is connected to the other end of the current source and the gate of the third mirror transistor to provide a mirror current, and the second electrode of the third mirror transistor is connected to the negative end of the power supply; the gate of the fourth mirror transistor is connected to the gate of the third mirror transistor, and the first electrode of the fourth mirror transistor is connected to the negative end of the power supply; the first electrode of the fifth mirror transistor is connected to the positive end of the power supply, and the second electrode of the fifth mirror transistor is connected to the second electrode of the fourth mirror transistor and the gate of the fifth mirror transistor to provide a mirror current.

[0017] In some implementations, a column of pixel circuits with the same display color are all connected to the same mirror current, and columns of pixel circuits with different display colors are connected to different mirror currents.

[0018] In some of the embodiments, one frame of the pixel circuit includes an analog drive subframe and multiple digital drive subframes, and the duration of the analog drive subframe is the same as the duration of each digital drive subframe; wherein the analog drive subframe is used to adjust the light-emitting current flowing through the light-emitting module; and the digital drive subframe is used to adjust the light-emitting time of the light-emitting module.

[0019] In some of the embodiments, one frame of the pixel circuit further includes at least one black insertion driving subframe, and the duration of each black insertion driving subframe is the same as the duration of the analog driving subframe.

[0020] In some of the embodiments, in one frame, the analog driving subframe is located before all the digital driving subframes; the digital driving module includes four digital driving units, each of which includes a switching transistor and a register; in the analog driving subframe, each register is respectively connected to a bit value of a data signal to control the corresponding switching transistor to be in an on state or an off state.

[0021] In some implementations, in each digital driving subframe, each register is respectively connected to the same bit value of a data signal to control all the switch transistors to be in an on state or an off state.

[0022] In a second aspect, the present application provides a display device, which includes a terminal body and a display panel as described in at least one of the above embodiments and arranged on the terminal body.

[0023] The display panel and display device provided in the present application can realize a hybrid driving mode by adjusting the light-emitting current in the corresponding light-emitting sub-circuit through each mirror current receiving unit, and adjusting the light-emitting time of the light-emitting module through the corresponding light-emitting sub-circuit through each digital driving unit. Compared with a single digital driving mode, under the same grayscale display, this hybrid driving mode requires fewer sub-frames, thereby reducing the transmission amount of display data.

[0024] Furthermore, by controlling the luminous current flowing through multiple mirror current receiving units with the same mirror current, not only the number of mirror current transmitting modules used is reduced, but also the control accuracy of the luminous current is improved, thereby improving the control accuracy of the luminous brightness of the luminous module.

[0025] Furthermore, by controlling the luminous current flowing through multiple mirror current receiving units with the same mirror current, the luminous current can be controlled to change in a step-by-step manner compared to the continuous change of the luminous current in the analog driving method, which can effectively improve the drift of the luminous wavelength of the luminous module. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0027] Figure 1 It is a structural block diagram of a display panel in the related art.

[0028] Figure 2 This is a schematic diagram of neutron field segmentation in the related art.

[0029] Figure 3 This is a structural block diagram of a display panel provided in an embodiment of the present application.

[0030] Figure 4 A schematic diagram of the first structure of a display panel provided in an embodiment of the present application.

[0031] Figure 5 A second structural schematic diagram of a display panel provided in an embodiment of the present application.

[0032] Figure 6 A third structural schematic diagram of the display panel provided in an embodiment of the present application.

[0033] Figure 7 A first timing diagram of a pixel circuit provided in an embodiment of the present application.

[0034] Figure 8 A second timing diagram of a pixel circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0037] See also Figures 1 to 8 At present, the light-emitting system mainly includes two driving modes in terms of grayscale realization:

[0038] Analog driving: Analog driving adjusts the luminous brightness of the light emitting module 101 by adjusting the driving current flowing through the light emitting module 101 . In analog driving, each gray scale corresponds to a data voltage, and one data voltage corresponds to a luminous brightness of the light emitting module 101 .

[0039] Digital drive: Digital drive adjusts the brightness of the light emitting module 101 by adjusting the light emitting time of the light emitting module 101. The working state of the light emitting module 101 in digital drive only includes the bright state and the dark state. The working timing of the digital drive includes the "1" state timing and the "0" state timing, where the "1" state corresponds to the bright state of the light emitting module 101 and the "0" state corresponds to the dark state of the light emitting module 101. Digital drive realizes grayscale control by controlling the light emitting time of the light emitting module 101 (i.e., the duration of the bright state and the duration of the dark state).

[0040] In the analog driving scheme, the emission wavelength will change according to the size of the driving current (luminous current). Among them, when Micro-LED (micro light emitting diode) is driven by a small current, the emission brightness of each Micro-LED is quite different, which will cause serious uneven display. This phenomenon will be more serious in the tiny display panel 100. Therefore, for the driving of Micro-LED, digital driving schemes are still mostly used to avoid the above display problems.

[0041] Digital driving mostly uses subfield scanning to achieve grayscale display, that is, the scanning time of each frame of the display picture is divided into subfields of different sizes, and each subfield is controlled to emit light separately. The combination of the subfields can control the total light-emitting time in the frame, thereby controlling the lighting time of each display unit in the display panel 100, so as to achieve a display effect with different grayscales for each display unit.

[0042] At present, for monochrome array display drivers, usually use Figure 1 The display panel 100 shown includes a timing controller 300, a data processor 400, a column scanning circuit 300 and a row scanning circuit 500. The column scanning circuit 300 is connected to each data line DL, the row scanning circuit 500 is connected to each scanning line GL, and each pixel circuit 10 is arranged in the intersection area formed by the data line DL and the scanning line GL.

[0043] The above-mentioned monochrome array display driver also often uses the digital sub-field scanning method, such as Figure 2 As shown, a frame (1H) includes multiple subframes, each subframe has a different weighting value, and each subframe includes a data writing phase P1 and a light-emitting phase P2. The different weighting values ​​of each subframe means that the duration of the light-emitting phase P2 in each subframe is different, that is, the lighting duration of the light-emitting module 101 is different. The weighting value can be set in a standard binary weighting value increment or a non-standard binary weighting value increment. For example, Figure 2 A frame includes 8 subframes, namely subframe F1, subframe F2, subframe F3, subframe F4, subframe F5, subframe F6, subframe F7 and subframe F8. The standard binary weight value increment method is adopted, and the weight value ratio of each subframe is 1(2 0 ):2(2 1 ):4(2 2 ):8(2 3 ):16(2 4 ):32(2 5 ):64(2 6 ):128(2 7 ), a frame of display data is the grayscale superposition of each subframe, thereby realizing 256 grayscale display. In order to improve the luminous brightness of the grayscale L255 of the display unit, when the scanning signal scans the display unit of each row, the display unit of each row can emit light immediately after the addressing scanning time, and each display unit can continue to emit light during the driving time of the entire frame display picture.

[0044] However, Figure 2The pure digital driving scheme shown is prone to flickering due to the long continuous time of the high grayscale subfield and the uneven subfield division. In order to improve this flicker phenomenon, the current common practice is to divide the original 8 subfields of different durations into 19 subframes of equal duration, and then scan and read data of different bit planes 19 times in the 19 subframes within a frame, so as to improve the flicker phenomenon that can be obviously felt by the human eye. In this case, each subframe needs to transmit a large amount of data.

[0045] In addition, with the increasing requirements for resolution, frame rate and grayscale display, the clock frequency requirements of the digital sub-field scanning method have reached a peak level even for monochrome display. Based on this solution, it is already difficult to achieve 256 grayscales. If you want to make an 8-bit display that meets GAM2.2, you need to increase the grayscale to 1024.

[0046] Furthermore, in order to achieve the same grayscale display, digital driving requires more sub-frames, which requires more display data.

[0047] In view of this, the present embodiment provides a display panel 100. Figure 1 The display panel 100 shown, Figure 3 The display panel 100 shown is further provided with a mirror current emission module 200 , which can accurately provide a light-emitting current to the corresponding pixel circuit 10 through a mirroring effect, thereby being able to more accurately control the light-emitting brightness of the light-emitting module 101 .

[0048] It should be noted that the external application processor sends an image signal to the timing controller 300, and the timing controller 300 separates the corresponding data signal and timing signal from the image signal. The data signal is processed by the data processor 400 and the column scanning circuit 300 in turn and then written to the corresponding pixel circuit 10 through the data line DL. The timing signal controls the row scanning circuit 500 to output the corresponding scanning signal through the scanning line GL to realize the addressing scanning of the pixel circuit 10.

[0049] In one embodiment, if Figure 4 , Figure 5 as well as Figure 6 As shown, the mirror current transmitting module 200 providing the mirror current is connected to the mirror current receiving module 102 in each pixel circuit 10, so that the mirror current receiving module 102 receives the mirror current.

[0050] It can be understood that by controlling the light-emitting current flowing through multiple mirror current receiving units 1021 through the same mirror current, not only the number of mirror current transmitting modules 200 used is reduced, but also the control accuracy of the light-emitting current is improved, thereby improving the control accuracy of the light-emitting brightness of the light-emitting module 101.

[0051] Furthermore, by controlling the luminous current flowing through the plurality of mirror current receiving units 1021 with the same mirror current, the luminous current can be controlled to change in a step-by-step manner compared to the continuous change of the luminous current in the analog driving method, which can effectively improve the drift of the luminous wavelength of the luminous module 101.

[0052] That is to say, in this embodiment, the light emitting current controlled by the mirror current changes in steps rather than continuously like an analog quantity.

[0053] In one embodiment, if Figure 4 As shown, a column of pixel circuits 10 with the same display color are all connected to the same mirror current, and each column of pixel circuits 10 with different display colors are connected to different mirror currents.

[0054] It should be noted that the number of the wholes formed by the fourth mirror transistor T13 and the fifth mirror transistor T12 may be the same as the number of columns of the pixel circuits 10 in the display panel 100; and / or, the number of the wholes formed by the fourth mirror transistor T13 and the fifth mirror transistor T12 may be the same as the number of colors that the pixel circuits 10 can display. For example, if the pixel circuit 10 can display red (R), green (G), and blue (B), then the number of the wholes formed by the fourth mirror transistor T13 and the fifth mirror transistor T12 is 3, so that one of the wholes is connected to the pixel circuit 10 displaying one color.

[0055] In some embodiments, the fourth mirror transistor T13 and the fifth mirror transistor T12 respectively connected to the pixel circuits 10 displaying red (R), green (G), and blue (B) may have different channel width-to-length ratios, so as to adjust the brightness of the pixel circuits 10 of different colors and / or different columns. In some other embodiments, the fourth mirror transistor T13 and the fifth mirror transistor T12 respectively connected to the pixel circuits 10 displaying red (R), green (G), and blue (B) may also have the same channel width-to-length ratio, so as to save the number of the fourth mirror transistor T13 and the fifth mirror transistor T12.

[0056] This not only saves the number of the above-mentioned components, but also reduces the brightness difference between pixel circuits 10 of different colors and / or different columns, thereby improving the brightness uniformity of the display panel 100 .

[0057] The first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0058] In one embodiment, if Figure 6 As shown, the mirror current transmitting module 200 further includes a current source A1 and a third mirror transistor T14, one end of the current source A1 is connected to the positive power supply terminal VDD; a first electrode of the third mirror transistor T14 is connected to the other end of the current source A1 and the gate of the third mirror transistor T14 to provide a mirror current, and a second electrode of the third mirror transistor T14 is connected to the negative power supply terminal VM.

[0059] It should be noted that, in some other embodiments, the current source A1 may also be connected in series between the third mirror transistor T14 and the negative power terminal VM, which can also achieve the desired function.

[0060] The current source A1 may also be a controlled current source. By adding a corresponding register in the display panel 100 or the mirror current emission module 200 to control the current of the current source A1, the response speed and sensitivity of the control can be improved.

[0061] In one embodiment, if Figure 4 , Figure 5 As shown, the mirror current transmitting module 200 includes a current source A1 and a third mirror transistor T14, a fourth mirror transistor T13 and a fifth mirror transistor T12, one end of the current source A1 is connected to the positive end VDD of the power supply; the first electrode of the third mirror transistor T14 is connected to the other end of the current source A1 and the gate of the third mirror transistor T14, and the second electrode of the third mirror transistor T14 is connected to the negative end VM of the power supply; the gate of the fourth mirror transistor T13 is connected to the gate of the third mirror transistor T14, and the first electrode of the fourth mirror transistor T13 is connected to the negative end VM of the power supply; the first electrode of the fifth mirror transistor T12 is connected to the positive end VDD of the power supply, and the second electrode of the fifth mirror transistor T12 is connected to the second electrode of the fourth mirror transistor T13 and the gate of the fifth mirror transistor T12 to provide a mirror current.

[0062] It should be noted that in this embodiment, a fourth mirror transistor T13 and a fifth mirror transistor T12 are newly added to the mirror current emission module 200, and the magnitude of the light-emitting current can be changed by adjusting the channel width-to-length ratio of the fourth mirror transistor T13 or the fifth mirror transistor T12, thereby providing more means for adjusting the light-emitting current.

[0063] In one embodiment, the display panel 100 includes a pixel circuit 10, the pixel circuit 10 includes a mirror current receiving module 102, a digital driving module 103 and a light-emitting module 101, the mirror current receiving module 102 includes N mirror current receiving units 1021, the control end of each mirror current receiving unit 1021 is connected to the same mirror current, each mirror current receiving unit 1021 is connected in series in a light-emitting sub-circuit, and N is an integer greater than or equal to 2; the digital driving module 103 includes N digital driving units 13, each digital driving unit 13 is connected in series in a light-emitting sub-circuit; the light-emitting module 101 is connected to the total light-emitting circuit formed by each light-emitting sub-circuit.

[0064] It can be understood that the display panel 100 provided in this embodiment can realize a hybrid driving mode by adjusting the light-emitting current in the corresponding light-emitting sub-circuit through each mirror current receiving unit 1021, and adjusting the light-emitting time of the light-emitting module 101 through the corresponding light-emitting sub-circuit. Compared with a single digital driving mode, under the same grayscale display, this hybrid driving mode requires fewer sub-frames, thereby reducing the transmission amount of display data.

[0065] Compared with the situation in which the luminous efficiency is low due to too small luminous current at low gray scale in single analog driving, the luminous current can be increased by reducing the luminous time, thereby improving the luminous efficiency.

[0066] In one embodiment, if Figure 5 , Figure 6 As shown, the mirror current receiving unit 1021 includes multiple receiving transistors, the gate of each receiving transistor is connected to the mirror current, and each receiving transistor is connected in series in the light-emitting sub-circuit; wherein, the channel width-to-length ratios of each receiving transistor in the same pixel circuit 10 are different.

[0067] It should be noted that the receiving transistor can operate in a linear region, which consumes lower power than in a saturation region, thereby further saving power consumption.

[0068] The channel width-to-length ratio of the receiving transistor can adjust the size of the light-emitting current flowing through the receiving transistor, and then more grayscale displays can be combined through different light-emitting currents provided by each receiving transistor in the same pixel circuit 10.

[0069] In one embodiment, if Figure 5 , Figure 6 As shown, the digital driving unit 13 includes a switch transistor 1032 and a register 1031. The switch transistor 1032 is connected in series in the light-emitting sub-circuit; the register 1031 is connected to the gate of the switch transistor 1032, a scan line GL, and a data line DL.

[0070] It should be noted that the register 1031 is used to store the digital signal (data signal) sent by the application processor, and the digital signal, i.e., 0 / 1, controls whether the light-emitting module 101 emits light through the switch transistor 1032. The register 1031 can store data permanently, and the stored data will not disappear as long as the pixel circuit 10 is not powered off, and there is no need to dynamically refresh the data.

[0071] Among them, when the switch transistor 1032 is a P-channel transistor, 0 represents light emission and 1 represents no light emission; or, when the switch transistor 1032 is an N-channel transistor, 1 represents light emission and 0 represents no light emission.

[0072] It should be noted that the receiving transistor T8 and the switch transistor T71 can form a light-emitting sub-circuit; the receiving transistor T9 and the switch transistor T72 can form another light-emitting sub-circuit; the receiving transistor T10 and the switch transistor T73 can form another light-emitting sub-circuit; the receiving transistor T11 and the switch transistor T74 can form another light-emitting sub-circuit. Each light-emitting sub-circuit is connected in parallel to form a total light-emitting circuit.

[0073] In order to realize the display of different numbers of grayscales, the number of light-emitting sub-circuits can be adjusted accordingly, for example, it can be 1, 2, 3, 4 or more integers.

[0074] The switch transistor 1032 can operate in a linear region, which consumes less power than in a saturation region, thereby further saving power consumption.

[0075] In one embodiment, if Figure 5 , Figure 6As shown, the temporary register 1031 includes an inverter INV, a first storage transistor T1, a second storage transistor T3, a third storage transistor T2, a fourth storage transistor T4, a fifth storage transistor T5 and a sixth storage transistor T6, the input end of the inverter INV is connected to the data line DL; the first electrode of the first storage transistor T1 is connected to the positive power supply terminal VDD; the first electrode of the second storage transistor T3 is connected to the second electrode of the first storage transistor T1 and the gate of the switch transistor 1032, the second electrode of the second storage transistor T3 is connected to the negative power supply terminal VM, and the gate of the second storage transistor T3 is connected to the gate of the first storage transistor T1; the first electrode of the third storage transistor T2 is connected to the positive power supply terminal VDD, the second electrode of the third storage transistor T2 is connected to the gate of the first storage transistor T1 The gate of the third storage transistor T2 is connected to the second electrode of the first storage transistor T1; the first electrode of the fourth storage transistor T4 is connected to the second electrode of the third storage transistor T2, the second electrode of the fourth storage transistor T4 is connected to the negative power supply terminal VM, and the gate of the fourth storage transistor T4 is connected to the gate of the third storage transistor T2; the first electrode of the fifth storage transistor T5 is connected to the data line DL, the second electrode of the fifth storage transistor T5 is connected to the gate of the second storage transistor T3, and the gate of the fifth storage transistor T5 is connected to the scanning line GL; the first electrode of the sixth storage transistor T6 is connected to the output end of the inverter INV, the second electrode of the sixth storage transistor T6 is connected to the gate of the third storage transistor T2, and the gate of the sixth storage transistor T6 is connected to the gate of the fifth storage transistor T5.

[0076] It should be noted that, in this embodiment, when the register 1031 is connected to logic 0 through the data line DL, the register 1031 can output the corresponding logic 1. In other embodiments, the register 1031 can also output the corresponding logic 0 when it is connected to logic 0; or, the register 1031 can also output the corresponding logic 1 when it is connected to logic 1.

[0077] Specifically, when the data line DL0 / DL1 / DL2 / DL3 transmits logic 0, the high potential provided by the scan line GL turns on the fifth storage transistor T5 and the sixth storage transistor T6, the logic 0 turns on the first storage transistor T1 and turns off the second storage transistor T3, and the first storage transistor T1 outputs logic 1; synchronously, the logic 0 is converted into logic 1 through the inverter INV, the logic 1 turns off the third storage transistor T2 and turns on the fourth storage transistor T4 through the sixth storage transistor T6, and the fourth storage transistor T4 outputs logic 0. Since the first storage transistor T1 and the sixth storage transistor T6 both output logic 1, the register 1031 outputs logic 1. It can be understood that, conversely, when the data line DL0 / DL1 / DL2 / DL3 transmits logic 1, the register 1031 outputs logic 0.

[0078] In one embodiment, if Figure 5 , Figure 6 As shown, each register 1031 in the same digital driving module 103 is connected to the same scan line GL, and each register 1031 in the same digital driving module 103 is connected to different data lines DL respectively.

[0079] It should be noted that, in this embodiment, each register 1031 in the same digital driving module 103 can be synchronously written and output corresponding logic values, and different data lines DL can flexibly configure the combination of logic values ​​output by each register 1031. In addition, compared with the case where the same pixel circuit 10 requires multiple scan lines GL, this embodiment can also save the number of scan lines GL used.

[0080] In one embodiment, if Figure 5 As shown, the light emitting module 101 includes a light emitting device LED, and the light emitting device LED is connected in a total light emitting circuit.

[0081] It should be noted that the light emitting current in the total light emitting circuit is determined by the combination of the channel width-to-length ratio of each receiving transistor and the switching state of each switch transistor 1032. In the case of four light emitting sub-circuits, the light emitting module 101 can realize 256 different grayscale displays.

[0082] The light emitting device LED may be an organic light emitting diode, a micro light emitting diode, a mini light emitting diode or a quantum dot light emitting diode. Preferably, the light emitting device LED is a micro light emitting diode (Micro-LED).

[0083] In one embodiment, if Figure 6 As shown, the light emitting module 101 further includes a first mirror transistor T17 and a second mirror transistor T18, wherein a first electrode of the first mirror transistor T17 is connected to a positive power supply terminal VDD, a gate of the first mirror transistor T17 is connected to a second electrode of the first mirror transistor T17 and each light emitting sub-circuit; a gate of the second mirror transistor T18 is connected to a gate of the first mirror transistor T17, a first electrode of the second mirror transistor T18 is connected to a positive power supply terminal VDD, a second electrode of the second mirror transistor T18 is connected to an anode of the light emitting device LED, and a cathode of the light emitting device LED is connected to a negative power supply terminal VM.

[0084] It should be noted that compared with Figure 5In the light-emitting module 101 shown in the present embodiment, a first mirror transistor T17 and a second mirror transistor T18 are newly added. The first mirror transistor T17 and the second mirror transistor T18 can constitute a mirror current circuit. In this case, the light-emitting current flowing through each light-emitting sub-circuit can be reduced, and the channel width-to-length ratio of the second mirror transistor T18 can be increased to increase the light-emitting current flowing through the total light-emitting circuit, thereby reducing the power consumption of the pixel circuit 10.

[0085] Based on the above analysis, it can be seen that, assuming that the current provided by the current source A1 is Iref, the light-emitting current of each pixel circuit 10 in the display panel 100 is a corresponding proportion of Iref (the corresponding relationship of the specific proportion can be referred to as follows about Figure 5 , Figure 6 ), which makes the light emitting brightness of each pixel circuit 10 highly consistent, and can improve the brightness uniformity of the display panel 100.

[0086] exist Figure 5 In the embodiment, the third mirror transistor T14 and the fourth mirror transistor T13 form a first-stage mirror current circuit, the fifth mirror transistor T12 and each receiving transistor form a second-stage mirror transistor, and the current flowing through the fourth mirror transistor T13 is equal to the current flowing through the fifth mirror transistor T12.

[0087] Therefore, the current flowing through the fourth mirror transistor T13 or the current flowing through the fifth mirror transistor T12 is K1*Iref. Wherein, K1=(W13 / L13) / (W14 / L14). Wherein, W13 and L13 are respectively the width and length of the channel of the fourth mirror transistor T13, and W14 and L14 are respectively the width and length of the channel of the third mirror transistor T14.

[0088] By adjusting the channel width-to-length ratios of the receiving transistors T8, T9, T10, and T11, the currents flowing through the receiving transistors T8, T9, T10, and T11 are respectively 1*K1*K2*Iref, 2*K1*K2*Iref, 4*K1*K2*Iref, and 8*K1*K2*Iref, where K2 is the ratio of the channel width-to-length ratio of each receiving transistor to the channel width-to-length ratio of the fifth mirror transistor T12.

[0089] In this case, the ratio of the light-emitting currents flowing through the receiving transistor T8, the receiving transistor T9, the receiving transistor T10, and the receiving transistor T11 is 1:2:4:8. When the four registers 1031 receive different logic values, there are 16 different light-emitting currents flowing through the light-emitting module 101.

[0090] exist Figure 6 In the pixel circuit 10 shown, the first mirror transistor T17 and the second mirror transistor T18 can form a mirror current circuit. In this case, by adjusting the channel width-to-length ratios of the receiving transistors T8, T9, T10, and T11, the currents flowing through the receiving transistors T8, T9, T10, and T11 are 1*J1*Iref, 2*J1*Iref, 4*J1*Iref, and 8*J1*Iref, respectively. Wherein, J1 is the ratio of the channel width-to-length ratio of each receiving transistor to the channel width-to-length ratio of the third mirror transistor T14.

[0091] The current flowing through the first mirror transistor T17 is 15*J1*Iref, and the current flowing through the second mirror transistor T18 is 15*J1*J2*Iref, where J2 is the ratio of the channel width-to-length ratio of the first mirror transistor T17 to the channel width-to-length ratio of the second mirror transistor T18.

[0092] In this way, the light-emitting current flowing through the first mirror transistor T17 can be reduced, and the light-emitting current flowing through the light-emitting device LED can be increased by increasing the channel width-to-length ratio of the second mirror transistor T18, thereby reducing the overall power consumption.

[0093] Figure 7 A first timing diagram of the pixel circuit 10 provided in an embodiment of the present application. The timing scheme divides a complete frame (e.g., a duration of 8333us) into 16 subframes of the same duration, namely F1-F16, and the duration of each subframe is 520us. Among them, the first subframe, namely F1, is an analog drive subframe (PAM), and the following 15 subframes, namely F2-F16, are digital drive frames (PWM). As the grayscale increases from 0, the luminous current in the analog drive subframe also increases. The four luminous sub-circuits can combine 16 luminous currents of different gears. When the luminous current in the analog drive subframe reaches the maximum gear, the pixel circuit 10 enters the second subframe, namely F2, and so on. In the 16 subframes, 16 luminous currents of different gears can be achieved, and these can be combined to achieve 256 different grayscales.

[0094] It should be noted that, compared with a single digital drive that requires 19 subframes to achieve 256 grayscales, the present application uses 16 subframes to achieve 256 grayscales, reducing the number of subframes and thereby reducing the amount of data transmission.

[0095] Figure 8 This is a second timing diagram of the pixel circuit 10 provided in the embodiment of the present application. Figure 7In contrast, the timing scheme inserts at least one black-insertion driving subframe after an analog driving subframe of a frame, and the at least one black-insertion driving subframe can be dispersed or concentrated before or after different digital driving frames. The duration of each black-insertion driving subframe is the same as the duration of the analog driving subframe.

[0096] It should be noted that the black insertion driving subframe can play an equivalent role to adjusting the switching frequency of the switching transistor 1032, thereby reducing the flicker risk. In the black insertion driving subframe, the corresponding light emitting device LED displays 0 grayscale.

[0097] In one embodiment, a frame of the pixel circuit 10 includes an analog driving subframe and multiple digital driving subframes, and the duration of the analog driving subframe is the same as the duration of each digital driving subframe; wherein the analog driving subframe is used to adjust the light-emitting current flowing through the light-emitting module 101; and the digital driving subframe is used to adjust the light-emitting time of the light-emitting module 101.

[0098] It should be noted that, in one embodiment, each of the above transistors may be one of a P-channel thin film transistor and an N-channel thin film transistor. In another embodiment, each of the above transistors may be another of a P-channel thin film transistor and an N-channel thin film transistor. The two transistors in the same mirror current circuit have the same channel type.

[0099] In one embodiment, if Figure 7 , Figure 8 As shown, in one frame, the analog driving sub-frame is located before all the digital driving sub-frames.

[0100] It should be noted that this embodiment is formulated based on the specific algorithm of this application and cannot be changed at will. The specific description of the algorithm will be expanded later.

[0101] In order to realize the display of 256 gray levels, the digital driving module 103 is configured to include four digital driving units 13, each of which includes a switching transistor 1032 and a register 1031; in the analog driving subframe, each register 1031 is respectively connected to a bit value of a data signal to control the corresponding switching transistor 1032 to be in an on state or an off state.

[0102] It should be noted that, as part of the above algorithm, the four switch transistors 1032 can respectively control the conduction or disconnection of a photon circuit, and because the channel width-to-length ratio of the receiving transistors connected in series in each photon circuit is different, the light-emitting current flowing through each photon circuit when it is turned on is also different. In this way, the four registers 1031 control the four switch transistors 1032 to be in the on state according to the four bit values ​​connected, and 16 different light-emitting currents can be achieved. For example, the bit value combination transmitted by the data lines DL0 / DL1 / DL2 / DL3 can be from 0000-1111.

[0103] In one embodiment, in each digital driving sub-frame, each register 1031 is respectively connected to the same bit value of a data signal to control all the switch transistors 1032 to be in the on state or the off state.

[0104] It should be noted that, in this embodiment as another part of the above algorithm, in each digital driving subframe, each register 1031 is connected to a bit value of 0 or 1. In this case, all switch transistors 1032 are in an on state or an off state.

[0105] Finally, the display of the corresponding gray scale in one frame is realized through the combination of the light emitting brightness and light emitting time in one analog driving subframe and fifteen digital driving subframes.

[0106] In one embodiment, the present embodiment provides a display device, which includes a terminal body and a display panel 100 as described in at least one of the above embodiments and disposed on the terminal body.

[0107] It can be understood that since the display device provided in this embodiment includes the display panel 100 in at least one of the above-mentioned embodiments, it is also possible to adjust the light-emitting current in the corresponding light-emitting sub-circuit through each mirror current receiving unit 1021, and each digital driving unit 13 can adjust the light-emitting time of the light-emitting module 101 through the corresponding light-emitting sub-circuit, thereby realizing a hybrid driving method. Compared with a single digital driving method, under the same grayscale display, this hybrid driving method requires fewer sub-frames, thereby reducing the transmission amount of display data.

[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] The display panel 100 and the display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a pixel circuit, and the pixel circuit includes: A mirror current receiving module, wherein the mirror current receiving module comprises N mirror current receiving units, wherein the control end of each mirror current receiving unit is connected to the same mirror current, and each mirror current receiving unit is connected in series in a photon circuit, wherein N is an integer greater than or equal to 2; A digital driving module, the digital driving module comprising N digital driving units, each of which is connected in series in one of the light-emitting sub-circuits; A light-emitting module is connected to the total light-emitting circuit formed by the light-emitting sub-circuits.

2. The display panel according to claim 1, characterized in that: The mirror current receiving unit includes a plurality of receiving transistors, the gate of each receiving transistor is connected to the same mirror current, and each receiving transistor is connected in series in the light-emitting sub-circuit; Wherein, the channel width-to-length ratios of the receiving transistors in the same pixel circuit are different.

3. The display panel according to claim 1, characterized in that: The digital drive unit comprises: A switching transistor, wherein the switching transistor is connected in series in the light-emitting sub-circuit; The register is connected to the gate of the switch transistor, a scan line, and a data line.

4. The display panel according to claim 3, characterized in that: The temporary register comprises: An inverter, an input end of which is connected to the data line; a first storage transistor, wherein a first electrode of the first storage transistor is connected to a positive terminal of a power supply; a second storage transistor, wherein a first electrode of the second storage transistor is connected to a second electrode of the first storage transistor and a gate of the switch transistor, a second electrode of the second storage transistor is connected to a negative terminal of a power supply, and a gate of the second storage transistor is connected to a gate of the first storage transistor; a third storage transistor, wherein a first electrode of the third storage transistor is connected to the positive terminal of the power supply, a second electrode of the third storage transistor is connected to the gate of the first storage transistor, and the gate of the third storage transistor is connected to the second electrode of the first storage transistor; a fourth storage transistor, wherein a first electrode of the fourth storage transistor is connected to a second electrode of the third storage transistor, a second electrode of the fourth storage transistor is connected to a negative terminal of the power supply, and a gate of the fourth storage transistor is connected to a gate of the third storage transistor; a fifth storage transistor, wherein a first electrode of the fifth storage transistor is connected to the data line, a second electrode of the fifth storage transistor is connected to a gate of the second storage transistor, and a gate of the fifth storage transistor is connected to the scan line; A sixth storage transistor, wherein a first electrode of the sixth storage transistor is connected to the output end of the inverter, a second electrode of the sixth storage transistor is connected to the gate of the third storage transistor, and a gate of the sixth storage transistor is connected to the gate of the fifth storage transistor.

5. The display panel according to claim 3, characterized in that: Each register in the same digital driving module is connected to the same scanning line, and each register in the same digital driving module is connected to different data lines respectively.

6. The display panel according to claim 1, characterized in that: The light-emitting module comprises a light-emitting device, and the light-emitting device is connected to the total light-emitting circuit.

7. The display panel according to claim 6, characterized in that: The light emitting module further comprises: A first mirror transistor, wherein a first electrode of the first mirror transistor is connected to a positive terminal of a power supply, and a gate of the first mirror transistor is connected to a second electrode of the first mirror transistor and each of the light-emitting sub-circuits; a second mirror transistor, wherein a gate of the second mirror transistor is connected to the gate of the first mirror transistor, a first electrode of the second mirror transistor is connected to the positive terminal of the power supply, a second electrode of the second mirror transistor is connected to the anode of the light emitting device, and a cathode of the light emitting device is connected to the negative terminal of the power supply.

8. The display panel according to claim 1, characterized in that: The display panel further includes a mirror current emission module for providing the mirror current, and the mirror current emission module is connected to the mirror current receiving module in each of the pixel circuits.

9. The display panel according to claim 8, characterized in that: The mirror current emission module comprises: A current source, one end of which is connected to the positive end of the power supply; A third mirror transistor, wherein a first electrode of the third mirror transistor is connected to the other end of the current source and the gate of the third mirror transistor to provide the mirror current, and a second electrode of the third mirror transistor is connected to the negative end of the power supply.

10. The display panel according to claim 8, characterized in that: The mirror current emission module comprises: A current source, one end of which is connected to the positive end of the power supply; a third mirror transistor, wherein a first electrode of the third mirror transistor is connected to the other end of the current source and the gate of the third mirror transistor, and a second electrode of the third mirror transistor is connected to the negative end of the power supply; a fourth mirror transistor, wherein a gate of the fourth mirror transistor is connected to the gate of the third mirror transistor, and a first electrode of the fourth mirror transistor is connected to the negative terminal of the power supply; A fifth mirror transistor, wherein a first electrode of the fifth mirror transistor is connected to a positive terminal of a power supply, and a second electrode of the fifth mirror transistor is connected to a second electrode of the fourth mirror transistor and a gate of the fifth mirror transistor to provide the mirror current.

11. The display panel according to claim 10, characterized in that: The pixel circuits in a column with the same display color are all connected to the same mirror current, and the pixel circuits in each column with different display colors are connected to different mirror currents.

12. The display panel according to any one of claims 1 to 11, characterized in that: One frame of the pixel circuit includes an analog driving subframe and a plurality of digital driving subframes, and the duration of the analog driving subframe is the same as the duration of each of the digital driving subframes; The analog driving subframe is used to adjust the light-emitting current flowing through the light-emitting module; and the digital driving subframe is used to adjust the light-emitting time of the light-emitting module.

13. The display panel according to claim 12, characterized in that: One frame of the pixel circuit further includes at least one black insertion driving subframe, and the duration of each black insertion driving subframe is the same as the duration of the analog driving subframe.

14. The display panel according to claim 12, characterized in that: In one frame, the analog driving subframe is located before all the digital driving subframes; the digital driving module includes four digital driving units, each of which includes a switching transistor and a register; In the analog driving subframe, each of the registers is respectively connected to a bit value of a data signal to control the corresponding switch transistor to be in an on state or an off state.

15. The display panel according to claim 14, characterized in that: In each of the digital driving sub-frames, each of the registers is respectively connected to the same bit value of a data signal to control all of the switch transistors to be in an on state or an off state.

16. A display device, characterized in that: The display device comprises a terminal body and a display panel according to any one of claims 1 to 15 arranged on the terminal body.

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