A device and method for improving PTP timestamp precision based on phase shift encoding

Abstract

The application discloses a device for improving PTP timestamp precision based on phase shift encoding, comprising a first FPGA PLL module, a reference clock generated by the first FPGA PLL module is input into a second FPGA PLL module to generate N phase clocks, a coding module extracts a hardware timestamp when a physical layer PHY chip transmits and receives a data valid signal from an RTC timing module, and the hardware timestamp is encoded by using the reference clock and the phase clocks, so that a corrected timestamp is generated. The application also discloses a method for improving PTP timestamp precision based on phase shift encoding, clock phase splitting and encoding are realized by using an FPGA, so that the timestamp precision of a time synchronization message received by a receiving end is improved. The application greatly improves the timestamp precision of the receiving end without improving the clock frequency and saving FPGA logic resources, and further improves the PTP time synchronization precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of time synchronization, in particular to a device for improving PTP timestamp precision based on phase-shift encoding, and a method for improving PTP timestamp precision based on phase-shift encoding. BACKGROUND

[0002] As a network time synchronization technology based on Ethernet, PTP can achieve sub-microsecond level precise time synchronization, and has been widely applied in fields such as navigation, positioning, communication, rail transit, smart grid, etc. PTP records time stamps at the network physical layer, and exchanges message data through master-slave links. The slave node calculates the average delay of the master-slave link and the clock offset Offset of the master-slave node according to the t1, t2, t3, t4 four time stamps obtained by sending and receiving, and performs time correction, so as to realize time synchronization of the master-slave nodes. As shown in the formula: Figure 1

[0003]

[0004] Wherein, Offset is the clock offset of the master-slave node; t1 is the time stamp of the time when the PTP master node sends the Sync message; t2 is the time stamp of the time when the PTP slave node receives the Sync message; t3 is the time stamp of the time when the PTP slave node sends the Delay_Req message in the PTP message cycle; t4 is the time stamp of the time when the PTP master node receives the Delay_Req message.

[0005] For the transmitting end, recording time stamp is completed at the rising edge of the clock, so t1 and t3 time stamps are accurate; while for the receiving end, local clock sampling is needed when receiving data. When the receiving data valid signal RX_DV output by the physical layer PHY chip comes, the hardware time stamp is recorded when the rising edge of the local clock comes. Because there is delay in the transmission process, the time when the data arrives at the receiving end and the time when the rising edge of the local clock of the receiving end arrives are not consistent, so the frequency of the local clock of the receiving end limits the time synchronization precision of PTP.

[0006] The traditional method can improve the resolution of the marked time stamp by improving the clock frequency, but because the highest frequency that can be reached by the FPGA digital phase-locked loop is related to its technology and speed grade, when the reference clock is too high, a series of metastable state problems will be caused. Therefore, the traditional method is very limited in improving the time stamp precision. The clock phase splitting technology can generate multiple phase clocks through the digital phase-locked loop, and then multiple phase splitting phase clocks sample the signal, so as to improve the time stamp precision. But this greatly consumes digital logic resources, and has high requirements for FPGA timing. SUMMARY

[0007] ​The purpose of the present invention is to address the above-mentioned problems existing in the prior art and to provide a device for improving the accuracy of PTP timestamps based on phase-shift coding, and also to provide a method for improving the accuracy of PTP timestamps based on phase-shift coding.

[0008] In order to achieve the above-mentioned purpose, the present invention adopts the following technical measures:

[0009] A device for improving PTP timestamp accuracy based on phase-shift coding includes a clock module, which outputs a system input clock CLK to a first FPGA PLL module. The first FPGA PLL module divides the input system input clock CLK to generate a physical layer PHY chip working clock CLK_PHY and a reference clock, with the reference clock being denoted as clock CLK_0. The physical layer PHY chip working clock CLK_PHY provides a working clock for the physical layer PHY chip, and clock CLK_0 is input to a second FPGA PLL module, an encoding module, and an RTC timing module. The second FPGA PLL module generates N phase clocks, denoted as clocks CLK_i, where i∈{1, 2, ...N}, and i represents the sequence number of the phase clock. Clock CLK_i is also input to the encoding module. After receiving a data message, the physical layer PHY chip generates a receive data valid signal RX_DV to the encoding module. Simultaneously, the encoding module extracts the hardware timestamp at that time from the RTC timing module. The hardware timestamp is encoded by the encoding module to generate a corrected timestamp.

[0010] As mentioned above, the total number and phase interval of the phase clocks satisfy the following formula:

[0011]

[0012] Where N is the total number of phase clocks, and N is a positive odd number. is the phase interval.

[0013] In the encoding module described above, the clocks CLK_i, i∈{1, 2, ...N} are respectively input into the corresponding D flip-flops in the encoding module. When each D flip-flop receives the rising edge of the receive data valid signal RX_DV, each D flip-flop latches the level value of the corresponding clock and temporarily stores it in the register array A of the array register of the encoding module. The array register of the encoding module is also provided with a binary reference array M. The reference array M is input into the shift register of the encoding module and shifted N times. Each shift obtains the corresponding comparison array M. b ; After the clock level value is temporarily stored in register array A, register array A is compared with array M b The data is input to the FPGA logic operation module of the encoding module and matched, and the FPGA logic operation module calculates the corrected timestamp.

[0014] The above-mentioned device for improving the accuracy of PTP timestamp based on phase shift coding is built on both the PTP master node and the PTP slave node.

[0015] As mentioned above, the PTP slave node also builds a slave node CPU processing unit, which receives the data message forwarded by the physical layer PHY chip of the PTP slave node and parses the corresponding timestamp. The slave node CPU processing unit also receives the corrected timestamp output by the encoding module, and outputs the master-slave node clock deviation from the slave node CPU processing unit.

[0016] A method for improving PTP timestamp accuracy based on phase-shift coding, using the device for improving PTP timestamp accuracy based on phase-shift coding as described above, comprises the following steps:

[0017] Step 1, a device for improving PTP timestamp accuracy based on phase-shift coding is built in both the PTP master node and the PTP slave node, and after a stable Ethernet link is established between the physical layer PHY chip of the PTP master node and the physical layer PHY chip of the PTP slave node, the PTP time synchronization calibration of the PTP master node and the PTP slave node is performed;

[0018] Step 2: In each PTP message cycle, when the encoding module at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip at the receiving end, the encoding module obtains the hardware timestamp from the RTC timing module, calculates and outputs the corrected timestamp.

[0019] A method for improving PTP timestamp accuracy based on phase-shift coding, using the device for improving PTP timestamp accuracy based on phase-shift coding as described above, comprises the following steps:

[0020] Step 1, a device for improving PTP timestamp accuracy based on phase-shift coding is built in both the PTP master node and the PTP slave node, and after a stable Ethernet link is established between the physical layer PHY chip of the PTP master node and the physical layer PHY chip of the PTP slave node, the PTP time synchronization calibration of the PTP master node and the PTP slave node is performed;

[0021] Step 2: In each PTP message cycle,

[0022] The physical layer PHY chip of the PTP master node sends a Sync message to the physical layer PHY chip of the PTP slave node. The physical layer PHY chip of the PTP master node records the time when the Sync message is sent as timestamp t1, and the timestamp t1 is encapsulated into the Sync message;

[0023] After the physical layer PHY chip of the PTP slave node receives the Sync message, the physical layer PHY chip of the PTP slave node sends the Sync message to the slave node CPU processing unit to parse the timestamp t1. At the same time, the encoding module of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, which is recorded as timestamp t 2p ; Then the encoding module will timestamp t 2p Send to the slave node CPU processing unit;

[0024] The physical layer PHY chip of the PTP slave node sends a Delay_Req message to the physical layer PHY chip of the PTP master node. The physical layer PHY chip of the PTP slave node records the time when the Delay_Req message is sent, which is recorded as the timestamp t3. The physical layer PHY chip of the PTP slave node sends the timestamp t3 to the CPU processing unit of the slave node;

[0025] After the physical layer PHY chip of the PTP master node receives the Delay_Req message, the encoding module of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, which is recorded as timestamp t 4p ;

[0026] The physical layer PHY chip of the PTP master node sends the Delay_Resp message to the physical layer PHY chip of the PTP slave node, and the timestamp is t 4p Encapsulate into Delay_Resp message;

[0027] The PTP slave node's physical layer PHY chip receives the Delay_Resp message and sends it to the slave node's CPU processing unit, which parses the timestamp t 4p Combined with timestamp t1 and timestamp t 2p The master-slave node clock offset Offset is calculated using the timestamp t3:

[0028]

[0029] Where Offset is the clock deviation between the master and slave nodes; t1 is the timestamp of the time when the PTP master node sends the Sync message; t 2p is the corrected timestamp of the moment when the PTP slave node receives the Sync message; t3 is the timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4p The corrected timestamp of the time when the PTP master node receives the Delay_Req message.

[0030] Obtaining the corrected timestamp as described above specifically includes the following steps:

[0031] Step 2.1, when the encoding module at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip, the encoding module obtains the hardware timestamp timestamp from the RTC timing module, and the (N+1) D flip-flops in the encoding module at the receiving end latch the corresponding clock level value at the rising edge of the receive data valid signal RX_DV and store it in the register array A, A=[x0,x1,x2,...,x i ,...,x N ], x i is the level value corresponding to the clock CLK_i latched by the D flip-flop, i∈{0,1,…N}, N is the total number of phase clocks;

[0032] For Sync messages, the receiving end is the PTP slave node; for Delay_Req messages, the receiving end is the PTP master node;

[0033] Step 2.2: In the array register of the encoding module, the value of the binary reference array M is cyclically shifted left bit by bit, and each left shift results in the corresponding comparison array M. b , the comparison array M obtained by left shifting the bth cycle b The number of shifts relative to the reference array M is denoted as the number of shifts m b , compare array serial number b∈{0,1,…N}, where the comparison array M0 is equal to the reference array M. Starting from the first loop, each loop is left-shifted by 1 bit based on the previous loop;

[0034] Step 2.3: In the encoding module, the FPGA logic operation module converts the register array A and the comparison array M after circular left shift b ,b∈{0,1,…N} to match, and determine whether there is an integer b∈[0,N] that makes the register array A and the comparison array M b The same, then calculate the corrected timestamp timestamp_precise of the data message received by the receiving end;

[0035]

[0036] Where timestamp is the hardware timestamp; b represents the comparison array number, b is an integer, b∈{0, 1, ...N}; T represents the period of the reference clock and phase clock, and the periods of the reference clock and phase clock are equal; m b Indicates the number of shifts, m0=0; M b Represents the comparison array, M0=M; A is the register array; reference array Indicates any Indicates existence;

[0037] For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module of the PTP slave node after the physical layer PHY chip of the PTP slave node receives the Sync message and sends the receive data valid signal RX_DV to the encoding module of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ;

[0038] For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module of the PTP master node after the physical layer PHY chip of the PTP master node receives the Delay_Req message and sends the receive data valid signal RX_DV to the encoding module of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention addresses a factor that affects the accuracy of PTP time synchronization, namely, the timestamp accuracy of data received by the receiving end. By using a clock phase division technology based on shift coding, the timestamp accuracy of data received by the receiving end is increased by (N+1) times while reducing logic resource consumption, thereby improving the PTP time synchronization accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a schematic diagram of the PTP message end-to-end single-step mode delay request-response mechanism.

[0042] Figure 2 A block diagram of a device for improving PTP timestamp accuracy based on phase-shift coding;

[0043] Among them, 1—clock module; 2—first FPGA PLL module; 3—physical layer PHY chip; 4—second FPGA PLL module; 5—encoding module; 6—RTC timing module;

[0044] CLK—is the system input clock, provided by the clock module;

[0045] CLK_PHY—is the physical layer PHY chip working clock, generated by the first FPGA PLL module;

[0046] CLK_0—is the reference clock, generated by the first FPGA PLL module, and is recorded as clock CLK_0;

[0047] CLK_1, CLK_2, CLK_3, CLK_4, CLK_5, CLK_6, ..., CLK_N—phase clocks, generated by the second FPGA PLL module, recorded as clocks CLK_1, CLK_2, CLK_3, CLK_4, CLK_5, CLK_6, ..., CLK_N;

[0048] RX_DV—is the valid signal for receiving data, output by the physical layer PHY chip;

[0049] timestamp—is the hardware timestamp, output by the RTC timing module;

[0050] timestamp_precise—is the corrected timestamp, output by the encoding module.

[0051] Figure 3 The figure is a schematic diagram of a specific implementation method for improving the PTP timestamp accuracy based on phase-shift coding. DETAILED DESCRIPTION

[0052] In order to facilitate those skilled in the art to understand and apply the present invention, the present invention is further described in detail below in conjunction with implementation examples. It should be understood that the implementation examples described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0053] Example 1

[0054] This embodiment provides a device for improving the accuracy of PTP timestamp based on phase shift coding, which is respectively built on the PTP master node and the PTP slave node. Figure 2 As shown, it includes a clock module 1, a first FPGA PLL module 2, a physical layer PHY chip 3, a second FPGA PLL module 4, an encoding module 5 and an RTC timing module 6.

[0055] The connection relationship between the above components is as follows:

[0056] Clock module 1 provides a system input clock CLK and inputs it to the first FPGA PLL module 2. The first FPGA PLL module 2 divides the input system input clock CLK to generate the physical layer PHY chip operating clock CLK_PHY and a reference clock. The reference clock is recorded as clock CLK_0. The physical layer PHY chip operating clock CLK_PHY provides the operating clock for the physical layer PHY chip 3. Clock CLK_0 is input to the second FPGA PLL module 4, encoding module 5, and RTC timing module 6, respectively, and provides the operating clock for the second FPGA PLL module 4, encoding module 5, and RTC timing module 6. The second FPGA PLL module 4 generates N phase clocks through phase division. Each phase clock is recorded as: clock CLK_1, clock CLK_2, ..., clock CLK_i, ..., clock CLK_N, where i is the phase clock sequence number, i∈{1,2,...N}, and N is the total number of phase clocks. Each phase clock is also input to the encoding module 5. After receiving the data message, the physical layer PHY chip 3 generates a valid signal RX_DV to the encoding module 5. At the same time, the encoding module 5 extracts the hardware timestamp at this time from the RTC timing module 6. The hardware timestamp is encoded by the encoding module 5 to generate a corrected timestamp. For the PTP slave node, the received data message is a Sync message, and the corrected timestamp corresponding to the moment when the PTP slave node receives the Sync message is recorded as timestamp t 2p For the PTP master node, the received data message is the Delay_Req message, and the corrected timestamp of the moment when the PTP master node receives the Delay_Req message is the timestamp t 4p .

[0057] In this embodiment, the frequency of the system input clock CLK output by the clock module 1 is 10 MHz; the clock frequency of the physical layer PHY chip working clock CLK_PHY generated by the first FPGA PLL module 2 is 125 MHz; the clock CLK_0 generated by the first FPGA PLL module 2 (that is, the clock CLK_0 input by the second FPGA PLL module 4) is 125 MHz; the total number N of phase clocks output by the second FPGA PLL module 4 is equal to 7 and the clock frequencies of the 7 phase clocks are all 125 MHz.

[0058] The first FPGA PLL module 2 , the second FPGA PLL module 4 , the encoding module 5 and the RTC timing module 6 are all implemented based on FPGA.

[0059] The total number N of phase clocks and the phase interval Satisfies the formula: N is a positive odd number. In this embodiment, the second FPGA PLL module 4 performs clock phase shifting according to the clock CLK_0 with an input frequency of 125 MHz to generate 7 phase intervals. The phases of the clocks CLK_1, CLK_2, ..., and CLK_7 are 45°, of which the phase of the clock CLK_0 is 0. The clocks CLK_0, CLK_1, CLK_2, ..., and CLK_7 are all provided to the encoding module 5. After receiving the data message, the physical layer PHY chip 3 generates a receive data valid signal RX_DV to the encoding module 5. At the same time, the encoding module 5 extracts the hardware timestamp at this time from the RTC timing module 6 and generates a corrected timestamp after encoding:

[0060] In the encoding module 5, the clocks CLK_0, CLK_1, CLK_i, ..., and CLK_N are input into the corresponding D flip-flops in the encoding module 5. When each D flip-flop receives the rising edge of the receive data valid signal RX_DV output from the physical layer PHY chip 3, each D flip-flop latches the level value of the corresponding clock (including the reference clock and the phase clock) and temporarily stores it in the register array A of the array register of the encoding module 5, A = [x0, x1, x i ,…,x N ]; The array register of the encoding module 5 is also provided with a binary reference array M, The reference array M is input into the shift register of the encoding module 5 and shifted N times. Each shift generates the corresponding comparison array M. b ; After the clock level value is temporarily stored in register array A, register array A is compared with array M b The data is input to the FPGA logic operation module of the encoding module 5 and matched. The FPGA logic operation module obtains the corrected timestamp according to the following formula:

[0061]

[0062] Wherein, timestamp is the hardware timestamp, timestamp_precise is the corrected timestamp. In this embodiment, both the hardware timestamp and the corrected timestamp are 64 bits. b represents the comparison array index, b is an integer, b∈{0, 1, ...N}; N is the total number of phase clocks; T represents the period of the reference clock and the phase clock, and the periods of the reference clock and the phase clock are equal. m b Indicates the number of shifts, m0=0; M b Represents the comparison array, M0=M; A is the register array; reference array The value of the reference array M is fixed. Indicates any Indicates existence.

[0063] For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP slave node after the physical layer PHY chip 3 of the PTP slave node receives the Sync message and sends the receive data valid signal RX_DV to the encoding module 5 of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ;

[0064] For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP master node after the physical layer PHY chip 3 of the PTP master node receives the Delay_Req message and sends the receive data valid signal RX_DV to the encoding module 5 of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

[0065] Furthermore, in order to use the corrected timestamp (ie, timestamp t 2p and timestamp t 4p ) to obtain a more accurate master-slave node clock deviation, the PTP slave node also builds a slave node CPU processing unit, the slave node CPU processing unit receives the data message (including Sync message and Delay_Req message) forwarded by the physical layer PHY chip 3 of the PTP slave node and parses the corresponding timestamp (parses the timestamp t1 from the Sync message and parses the timestamp t from the Delay_Resp message) 4p ), the slave node CPU processing unit also receives the corrected timestamp output by the encoding module 5, and then outputs the master-slave node clock deviation:

[0066]

[0067] Where Offset is the clock deviation between the master and slave nodes; t1 is the timestamp of the time when the PTP master node sends the Sync message; t 2p is the corrected timestamp of the moment when the PTP slave node receives the Sync message; t3 is the timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4p The corrected timestamp of the time when the PTP master node receives the Delay_Req message.

[0068] Example 2

[0069] A method for improving the accuracy of PTP timestamps based on phase-shift coding, using the device for improving the accuracy of PTP timestamps based on phase-shift coding described in Example 1, such as Figure 3 As shown, the specific steps include:

[0070] Step 1: A device for improving the accuracy of PTP timestamps based on phase-shift coding as described in Example 1 is built on both the PTP master node and the PTP slave node, and after a stable Ethernet link is established between the physical layer PHY chip 3 of the PTP master node and the physical layer PHY chip 3 of the PTP slave node, the PTP time synchronization of the PTP master node and the PTP slave node is calibrated;

[0071] At this time, the second FPGA PLL module 4 splits the input clock CLK_0 into phases to generate N phase clocks. The total number N of phase clocks and the phase interval of the phase clocks satisfy the following formula:

[0072]

[0073] Wherein, N is the total number of phase clocks and is a positive odd number; is the phase interval.

[0074] Step 2: In each PTP message cycle, when the encoding module 5 at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip 3, the encoding module 5 obtains the hardware timestamp from the RTC timing module 6, calculates and outputs the corrected timestamp.

[0075] Specifically: the physical layer PHY chip 3 of the PTP master node sends a Sync message to the physical layer PHY chip 3 of the PTP slave node. The physical layer PHY chip 3 of the PTP master node records the time of sending the Sync message as timestamp t1, and the timestamp t1 is encapsulated into the Sync message;

[0076] After the physical layer PHY chip 3 of the PTP slave node receives the Sync message, the physical layer PHY chip 3 of the PTP slave node sends the Sync message to the slave node CPU processing unit to parse the timestamp t1. At the same time, the encoding module 5 of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, which is recorded as timestamp t 2p ; Then the encoding module 5 will timestamp t 2p Send to the slave node CPU processing unit;

[0077] The physical layer PHY chip 3 of the PTP slave node sends a Delay_Req message to the physical layer PHY chip 3 of the PTP master node. The physical layer PHY chip 3 of the PTP slave node records the time when the Delay_Req message is sent, which is recorded as the timestamp t3. At the same time, the physical layer PHY chip 3 of the PTP slave node sends the timestamp t3 to the CPU processing unit of the slave node;

[0078] After the physical layer PHY chip 3 of the PTP master node receives the Delay_Req message, the encoding module 5 of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, which is recorded as timestamp t 4p ;

[0079] The physical layer PHY chip 3 of the PTP master node sends a Delay_Resp message to the physical layer PHY chip 3 of the PTP slave node, and the timestamp is t 4p Encapsulate into Delay_Resp message;

[0080] The physical layer PHY chip 3 of the PTP slave node receives the Delay_Resp message and sends the Delay_Resp message to the slave node CPU processing unit, which parses the timestamp t 4p Combined with timestamp t1 and timestamp t 2p The master-slave node clock offset Offset is calculated using the timestamp t3.

[0081] The encoding module 5 of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, and the encoding module 5 of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, both of which include the following steps:

[0082] Step 2.1, when the encoding module 5 of the receiving end (for Sync message, the receiving end is the PTP slave node; for Delay_Req message, the receiving end is the PTP master node) receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip 3, the encoding module 5 obtains the hardware timestamp timestamp from the RTC timing module 6, and the (N+1) D flip-flops in the encoding module 5 of the receiving end respectively latch the level value of the corresponding clock (the clock includes the reference clock and the phase clock, and one D flip-flop corresponds to one clock) at the rising edge of the receive data valid signal RX_DV, and store it in the register array A, A = [x0, x1, x2, ..., x i ,...,x N ], x i is the level value corresponding to the clock CLK_i latched by the D flip-flop, i∈{0,1,…N}, and N is the total number of phase clocks.

[0083] In the embodiment, the number of D flip-flops is 8. The order of latching the level values of each clock in the corresponding register array A is: A=[x0, x1, x2, x3, x4, x5, x6, x7], wherein x0, x1, x2, x3, x4, x5, x6, x7 are respectively the level values of the 8 D flip-flops latched at the time when the data valid signal RX_DV arrives.

[0084] Step 2.2, the binary reference array M is set in the array register of the encoding module 5, and the value of the reference array M is cyclically left shifted by one bit each time to obtain a corresponding comparison array, denoted as comparison array M b , the comparison array M obtained by the b-th cyclic left shift b , b∈{0,1,…N}. The shift bit number relative to the reference array M is denoted as shift bit number m b , b∈{0,1,…N}. The comparison array M0 is equal to the reference array M, and in each cycle from the first cycle, the left shift is performed by one bit step by step based on the last cycle. In the embodiment, after 8 left shift cycles, the comparison array M b is equal to the reference array M, as shown in Table 1.

[0085] Table 1: Encoding table of the method for improving PTP timestamp precision based on phase shift encoding

[0086]

[0087] , wherein A is the register array, m b is the shift bit number, M b is the comparison array, b is the cycle number, and timestamp is the hardware timestamp, and timestamp_precise is the modified timestamp.

[0088] Step 2.3, in the encoding module 5, the FPGA logic operation module matches the register array A and the comparison array M b , b∈{0,1,…N} to determine whether there is an integer b∈[0,N] that makes the register array A and the comparison array M b the same, and then calculates the modified timestamp timestamp_precise of the received data packet at the receiving end according to the following formula:

[0089]

[0090] Wherein, timestamp is the hardware timestamp, timestamp_precise is the corrected timestamp. In this embodiment, both the hardware timestamp and the corrected timestamp are 64 bits. b represents the comparison array index, b is an integer, b∈{0, 1, ...N}; N is the total number of phase clocks; T represents the period of the reference clock and the phase clock, and the periods of the reference clock and the phase clock are equal. m b Indicates the number of shifts, m0=0; M b Represents the comparison array, M0=M; A is the register array; reference array The value of the reference array M is fixed. Indicates any Indicates existence.

[0091] For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP slave node after the physical layer PHY chip 3 of the PTP slave node receives the Sync message and sends the receive data valid signal RX_DV to the encoding module 5 of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ;

[0092] For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP master node after the physical layer PHY chip 3 of the PTP master node receives the Delay_Req message and sends the receive data valid signal RX_DV to the encoding module 5 of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

[0093] Using clocks CLK_0, CLK_1, ..., and CLK_7 to collect the valid receive data signal RX_DV will result in 8 times the resource consumption, and the higher the clock frequency, the more difficult it is to distinguish which clock first collects the arrival time of the RX_DV signal. Therefore, this solution uses the rising edge of the valid receive data signal RX_DV in conjunction with a D flip-flop to collect the level values ​​of clocks CLK_0, CLK_1, ..., and CLK_7 corresponding to the rising edge of the valid receive data signal RX_DV. Then, based on the data code of the collected level value, that is, register array A, it is determined between which two clocks the rising edge of the valid receive data signal RX_DV is. The judgment method is: cyclically shift the reference array M left by m. b Bit, determine which register array A and which comparison array M b Equal, then use the hardware timestamp timestamp to subtract the corresponding correction time △t, △t = mb *T / (N+1) to get a more accurate corrected timestamp timestamp_precise. The corrected time △t represents the time difference between the rising edge of the receive data valid signal RX_DV and the rising edge of the first clock CLK_0 after the receive data valid signal RX_DV (the hardware timestamp timestamp is based on the clock CLK_0). If no comparison array M with the same size as the register array A is found b , it means that the rising edge of the receive data valid signal RX_DV coincides with a rising edge of clock CLK_0, clock CLK_1, ..., clock CLK_7, or there is a counting error. At this time, the hardware timestamp timestamp is used as the corrected timestamp of the data message received by the receiving end.

[0094] In this embodiment, a total of 8 clocks are set. Correspondingly, the accuracy of the corrected timestamp timestamp_precise is improved by 8 times compared with the hardware timestamp timestamp.

[0095] Through the above steps 2.1-2.3, the timestamp of the data message arrival time can be corrected at the receiving end, thereby improving the accuracy of the hardware timestamp by (N+1) times. The corrected timestamp can be used when PTP calculates the round-trip path delay, making the calculation more accurate, thereby improving the accuracy of PTP time synchronization. In each PTP message cycle, when the PTP slave node receives the Delay_Resp message, the slave node CPU processing unit uses the obtained corrected timestamp to calculate the master-slave node clock offset Offset to satisfy the formula:

[0096]

[0097] Where Offset is the clock deviation between the master and slave nodes; t1 is the timestamp of the time when the PTP master node sends the Sync message; t 2p is the corrected timestamp of the moment when the PTP slave node receives the Sync message; t3 is the timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4p The corrected timestamp of the time when the PTP master node receives the Delay_Req message.

[0098] It should be noted that the specific embodiments described herein are merely illustrative of the spirit of the present invention. Persons skilled in the art may make various modifications, additions, or substitutions to the described specific embodiments without departing from the spirit of the present invention or exceeding the scope of the appended claims.

Claims

1. A device for improving PTP timestamp accuracy based on phase shift coding, characterized in that: The invention comprises a clock module (1), wherein the clock module (1) outputs a system input clock CLK to a first FPGA PLL module (2), and the first FPGA PLL module (2) divides the input system input clock CLK to generate a physical layer PHY chip working clock CLK_PHY and a reference clock, wherein the reference clock is recorded as clock CLK_0; the physical layer PHY chip working clock CLK_PHY provides a working clock for the physical layer PHY chip (3), and the clock CLK_0 is respectively input to a second FPGA PLL module (4), an encoding module (5), and an RTC timing module (6); the second FPGA The PLL module (4) generates N phase clocks in phase, which are recorded as clocks CLK_i, i∈{1, 2, ... N}, and i represents the sequence number of the phase clock; the clock CLK_i is also input into the encoding module (5); after receiving the data message, the physical layer PHY chip (3) generates a valid received data signal RX_DV to the encoding module (5); at the same time, the encoding module (5) extracts the hardware timestamp at this time from the RTC timing module (6), and the hardware timestamp is encoded by the encoding module (5) to generate a corrected timestamp; The total number and phase interval of the phase clocks satisfy the following formula: Where N is the total number of phase clocks, and N is a positive odd number. is the phase interval; In the encoding module (5), clocks CLK_i, i∈{1, 2, ...N} are respectively input into corresponding D flip-flops in the encoding module (5); when each D flip-flop receives a rising edge of a valid receive data signal RX_DV, each D flip-flop latches a level value of the corresponding clock and temporarily stores it in a register array A of an array register of the encoding module (5); a binary reference array M is also provided in the array register of the encoding module (5); the reference array M is input into a shift register of the encoding module (5) and shifted N times, and each shift obtains a corresponding comparison array M b ; After the clock level value is temporarily stored in register array A, register array A is compared with array M b The data is input to the FPGA logic operation module of the encoding module (5) and matched, and the FPGA logic operation module calculates the corrected timestamp.

2. The device for improving PTP timestamp accuracy based on phase shift coding according to claim 1, characterized in that: The device for improving the PTP timestamp accuracy based on phase-shift coding is built on both the PTP master node and the PTP slave node.

3. The device for improving PTP timestamp accuracy based on phase shift coding according to claim 2, characterized in that: The PTP slave node also has a slave node CPU processing unit, which receives data messages forwarded by the physical layer PHY chip (3) of the PTP slave node and parses out corresponding timestamps. The slave node CPU processing unit also receives the corrected timestamp output by the encoding module (5), and outputs the master-slave node clock deviation from the slave node CPU processing unit.

4. A method for improving PTP timestamp accuracy based on phase-shift coding, using the device for improving PTP timestamp accuracy based on phase-shift coding according to claim 2, characterized in that: The following steps are involved: Step 1: A device for improving the accuracy of a PTP timestamp based on phase shift coding is built on both a PTP master node and a PTP slave node, and after a stable Ethernet link is established between a physical layer PHY chip (3) of the PTP master node and a physical layer PHY chip (3) of the PTP slave node, the PTP time synchronization of the PTP master node and the PTP slave node is calibrated; Step 2: In each PTP message cycle, when the encoding module (5) at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip (3) at the receiving end, the encoding module (5) obtains the hardware timestamp from the RTC timing module (6), calculates and outputs the corrected timestamp.

5. A method for improving PTP timestamp accuracy based on phase-shift coding, using the device for improving PTP timestamp accuracy based on phase-shift coding according to claim 3, characterized in that: The following steps are involved: Step 1: A device for improving the accuracy of a PTP timestamp based on phase shift coding is built on both a PTP master node and a PTP slave node, and after a stable Ethernet link is established between a physical layer PHY chip (3) of the PTP master node and a physical layer PHY chip (3) of the PTP slave node, the PTP time synchronization of the PTP master node and the PTP slave node is calibrated; Step 2: In each PTP message cycle, The physical layer PHY chip (3) of the PTP master node sends a Sync message to the physical layer PHY chip (3) of the PTP slave node. The physical layer PHY chip (3) of the PTP master node records the time of sending the Sync message as a timestamp t1, and the timestamp t1 is encapsulated into the Sync message. After the physical layer PHY chip (3) of the PTP slave node receives the Sync message, the physical layer PHY chip (3) of the PTP slave node sends the Sync message to the slave node CPU processing unit to parse out the timestamp t1. At the same time, the encoding module (5) of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, which is recorded as timestamp t 2p ; Then the encoding module (5) timestamps t 2p Send to the slave node CPU processing unit; The physical layer PHY chip (3) of the PTP slave node sends a Delay_Req message to the physical layer PHY chip (3) of the PTP master node. The physical layer PHY chip (3) of the PTP slave node records the time of sending the Delay_Req message as a timestamp t3. The physical layer PHY chip (3) of the PTP slave node sends the timestamp t3 to the CPU processing unit of the slave node. After the physical layer PHY chip (3) of the PTP master node receives the Delay_Req message, the encoding module (5) of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, which is recorded as timestamp t 4p ; The physical layer PHY chip (3) of the PTP master node sends a Delay_Resp message to the physical layer PHY chip (3) of the PTP slave node, and the timestamp is t 4p Encapsulate into Delay_Resp message; The physical layer PHY chip (3) of the PTP slave node receives the Delay_Resp message and sends the Delay_Resp message to the slave node CPU processing unit, which parses the timestamp t 4p Combined with timestamp t1 and timestamp t 2p The master-slave node clock offset Offset is calculated using the timestamp t3: Where Offset is the clock deviation between the master and slave nodes; t1 is the timestamp of the time when the PTP master node sends the Sync message; t 2p The corrected timestamp of the moment when the PTP slave node receives the Sync message; t3 is the timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4p The corrected timestamp of the time when the PTP master node receives the Delay_Req message.

6. The method for improving PTP timestamp accuracy based on phase shift coding according to any one of claims 4 or 5, characterized in that: Obtaining the corrected timestamp specifically includes the following steps: Step 2.1, when the encoding module (5) at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip (3), the encoding module (5) obtains the hardware timestamp timestamp from the RTC timing module (6), and the (N+1) D flip-flops in the encoding module (5) at the receiving end latch the corresponding clock level value at the rising edge of the receive data valid signal RX_DV and store it in the register array A, A=[x0,x1,x2,...,x i ,...,x N ], x i is the level value corresponding to the clock CLK_i latched by the D flip-flop, i∈{0,1,…N}, N is the total number of phase clocks; For Sync messages, the receiving end is the PTP slave node; for Delay_Req messages, the receiving end is the PTP master node; Step 2.2: In the array register of the encoding module (5), the value of the binary reference array M is cyclically shifted left bit by bit, and each left shift results in the corresponding comparison array M. b , the comparison array M obtained by left shifting the bth cycle b The number of shifts relative to the reference array M is denoted as the number of shifts m b , compare array serial number b∈{0,1,…N}, where the comparison array M0 is equal to the reference array M. Starting from the first loop, each loop is left-shifted by 1 bit based on the previous loop; Step 2.3: In the encoding module (5), the FPGA logic operation module converts the register array A and the comparison array M after circular left shift into b ,b∈{0,1,…N} to match, and determine whether there is an integer b∈[0,N] that makes the register array A and the comparison array M b The same, then calculate the corrected timestamp timestamp_precise of the data message received by the receiving end; Where timestamp is the hardware timestamp; b represents the comparison array number, b is an integer, b∈{0, 1, ...N}; T represents the period of the reference clock and phase clock, and the periods of the reference clock and phase clock are equal; m b Indicates the number of shifts; M b Represents the comparison array, M0=M; A is the register array; reference array Indicates any Indicates existence; For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module (5) of the PTP slave node after the physical layer PHY chip (3) of the PTP slave node receives the Sync message and sends the receive data valid signal RX_DV to the encoding module (5) of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ; For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module (5) of the PTP master node after the physical layer PHY chip (3) of the PTP master node receives the Delay_Req message and sends the receive data valid signal RX_DV to the encoding module (5) of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

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