Base station front transmission interface protocol stack data dedicated processor and message processing method

Abstract

The present invention provides a dedicated processor for base station front-haul interface protocol stack data and a message processing method, belonging to the field of communication technology, the processor includes: a register group module, an operation module, a message processing module, a program control module, an instruction storage module and a decoder module; the operation module, driven by the current execution instruction, obtains operands from the register group module for operation and completes the execution of the current execution instruction to obtain the operation result; the program control module arbitrates according to the program count change request sent by the operation module after obtaining the operation result, and determines the message processing instruction; the message processing module processes the message data under the drive of the message processing instruction. The present invention processes message data through the constructed ASIP and accelerator new architecture, pre-sets a dedicated processing instruction set for the operation characteristics of the message data protocol stack, and realizes a high-speed, high-throughput dedicated processor for the base station front-haul interface protocol stack for the message data processing requirements of the protocol stack.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a base station fronthaul interface protocol stack data dedicated processor and a message processing method. Background Art

[0002] The fronthaul interface is the data transmission bridge between the air interface and the base station processing unit. The performance of the fronthaul interface processor in parsing and encapsulating message data will affect the execution effect of the upper-layer application software.

[0003] Currently, network processors that support the eCPRI protocol, O-RAN protocol, and similar protocols generally have the disadvantages of high cost, slow processing speed, and can only support relatively small data throughput when processing message data.

[0004] Therefore, it is necessary to provide a low-cost, high-speed, high-throughput, and dedicated processor for the base station fronthaul interface protocol stack. Summary of the invention

[0005] The present invention provides a base station fronthaul interface protocol stack data dedicated processor and a message processing method, which are used to solve the defects of the network processor in the prior art, such as high cost, slow processing speed and only supporting relatively small data throughput, and realize a base station fronthaul interface protocol stack dedicated processor with high speed and large throughput for the protocol stack message data processing requirements.

[0006] The present invention provides a base station front transmission interface protocol stack data dedicated processor, comprising:

[0007] A register group module consisting of an operation module, a message processing module, a program control module, an instruction storage module, a decoder module and a plurality of registers;

[0008] The operation module is used to obtain operands from the register group module under the drive of the current execution instruction, and to operate on the operands to complete the execution of the current execution instruction and obtain the operation result; the current execution instruction is composed of special processing instructions in the special processing instruction set;

[0009] The program control module is used to manage the program count and arbitrate the program count change request sent by the operation module after obtaining the operation result to determine the message processing instruction;

[0010] The instruction storage module is used to store the currently executed instruction and the message processing instruction;

[0011] The decoder module is used to decode the message processing instruction and distribute the decoding result to the message processing module;

[0012] The message processing module is used to process the message data under the drive of the message processing instruction.

[0013] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, the type of the currently executed instruction is a data change instruction, a bit operation instruction or a bit arbitration instruction.

[0014] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, when the currently executed instruction is the data change instruction, the currently executed instruction includes a change method, a first operand, a target register number and a first target address; the first operand includes a first bit starting position and a first bit length;

[0015] The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes:

[0016] Acquire first bit data having a length of the first bit length starting from the first bit starting position;

[0017] The first bit of data is moved to the first target address in the target register corresponding to the target register number according to the changing method.

[0018] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, when the currently executed instruction is the bit operation instruction, the currently executed instruction includes an operation method, a second operand, a third operand, and a second target address; the second operand includes a second bit starting position, a second bit length, and a first bit number; the third operand includes a third bit starting position, a third bit length, and a second bit number;

[0019] The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes:

[0020] Acquire second bit data having a length of the second bit length starting from the second bit starting position, and shift the second bit data left by the first bit position;

[0021] Acquire third bit data having a length of the third bit length starting from the third bit starting position, and shift the third bit data left by the second bit position;

[0022] The second bit data after the left shift and the third bit data after the left shift are operated according to the operation method, and the operation result is stored in the second target address.

[0023] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, the operation module includes a first masker, a second masker, a first shifter, a second shifter and an operator;

[0024] The first masker is used to perform a mask operation on an operand based on the currently executed instruction to obtain a first mask result;

[0025] The second masker is used to perform a mask operation on another operand based on the currently executed instruction to obtain a second mask result;

[0026] The first shifter is used to perform a shift operation on the first mask result to obtain a first shift result;

[0027] The second shifter is used to perform a shift operation on the second mask result to obtain a second shift result;

[0028] The operator is used to operate on the first shift result and the second shift result to complete the execution of the current execution instruction.

[0029] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, when the currently executed instruction is the bit arbitration instruction, the currently executed instruction includes an arbitration method, a fourth operand, a fifth operand and a relative jump address; the fourth operand includes a fourth bit starting position and a fourth bit length; the fifth operand includes a fifth bit starting position and a fifth bit length;

[0030] The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes:

[0031] Acquire fourth bit data having a length of the fourth bit length starting from the fourth bit starting position;

[0032] Acquire fifth bit data having a length of the fifth bit length starting from the fifth bit starting position;

[0033] The fourth bit data and the fifth bit data are compared according to the arbitration method. If the comparison is successful, jump to the target address determined based on the relative jump address; if the comparison fails, execute the next execution instruction of the current execution instruction in the instruction sequence.

[0034] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, when the currently executed instruction is the bit arbitration instruction, the currently executed instruction includes an arbitration method, a sixth operand, an immediate number and a relative jump address; the sixth operand includes a sixth bit starting position and a sixth bit length; the operand is obtained from the register group module, and the operand is operated to complete the execution of the currently executed instruction, including:

[0035] Acquire sixth bit data having a length of the sixth bit starting from the sixth bit starting position;

[0036] The sixth bit data and the immediate value are compared according to the arbitration method. If the comparison is successful, jump to the target address determined based on the relative jump address; if the comparison fails, execute the next execution instruction of the current execution instruction in the instruction sequence.

[0037] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, the operation result includes a first block move control word and a data recovery control word;

[0038] The message processing module includes: a first block moving module, a data recovery module and a first cache;

[0039] The first block moving module is used to move the message data from the register group module based on the first block moving control word, and write the message data into the first cache;

[0040] The data recovery module is used to load the message data from the first cache based on the data recovery control word, restore the data bit width and size of the message data, and send the recovered message data until the sending of one message data is completed.

[0041] According to a base station fronthaul interface protocol stack data dedicated processor provided by the present invention, the operation result includes a second block move control word;

[0042] The message processing module includes: a second block moving module, a data integration module and a second cache;

[0043] The second block moving module is used to move the compressed message data from the second cache to the register group module based on the second block moving control word; the compressed message data is stored in the second cache after the data bit width and size of the message data are compressed by the data integration module according to a pre-configured data integration control word.

[0044] The present invention also provides a message processing method based on any of the above-mentioned base station front transmission interface protocol stack data dedicated processors, comprising:

[0045] The control operation module, under the drive of the current execution instruction, obtains operands from the register group module, operates on the operands and completes the execution of the current execution instruction to obtain the operation result; the current execution instruction is composed of special processing instructions in the special processing instruction set; the register group module includes a plurality of registers;

[0046] The control program control module manages the program count and arbitrates the program count change request sent by the operation module after obtaining the operation result to determine the message processing instruction;

[0047] Controlling the decoder module to decode the message processing instruction and distribute the decoding result to the message processing module;

[0048] The message processing module is controlled to process the message data under the drive of the message processing instruction.

[0049] The base station fronthaul interface protocol stack data dedicated processor and message processing method provided by the present invention pre-set a dedicated processing instruction set according to the operation characteristics of the protocol stack in the message data processing field, and program an instruction sequence with the dedicated processing instruction set so that the operation module can quickly execute to obtain the operation result, and then drive the message processing module to execute certain functions of itself to process the message data. In fact, the message data is processed based on the new ASIP and ASIC accelerator architecture constructed in the processor, which can reduce the number of instructions required to be programmed for executing the instruction sequence, and at the same time reduce the clock overhead and instruction overhead of executing the instructions, and obtain the operation result of driving the message processing module to work more quickly in a low-cost manner, thereby improving the speed of message data processing, and realizing a base station fronthaul interface protocol stack dedicated processor that meets the high-speed, large-throughput and protocol stack message data processing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 It is a structural schematic diagram of a dedicated processor for base station fronthaul interface protocol stack data provided by the present invention.

[0052] Figure 2 It is a flow chart of message data processing provided by the present invention.

[0053] Figure 3 It is a schematic diagram of the effect of replacing data by the operation module provided by the present invention.

[0054] Figure 4 It is a schematic diagram of the effect of inserting data by the operation module provided by the present invention.

[0055] Figure 5 It is a schematic diagram of the effect of the operation module provided by the present invention accurately adding data bit fields.

[0056] Figure 6 It is a structural schematic diagram of the operation module provided by the present invention.

[0057] Figure 7 It is a flow chart of a message processing method based on a dedicated processor for base station fronthaul interface protocol stack data provided by the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] It should be noted that, in the description of the present invention, the term "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0061] Combine the following Figure 1-Figure 7 The present invention describes a base station fronthaul interface protocol stack data dedicated processor and a message processing method.

[0062] Application Specific Instruction Set Processor (ASIP), also known as a dedicated processor, is a programmable platform that is customized for a specific operation or a certain type of algorithm. It has both software programming capabilities and is oriented to accelerated processing in a specific field. It can use the same chip on multiple related applications, different versions of applications, and even future applications. It has the advantages of sharing the chip design cost on a large number of chips, having enough functions and flexibility to deal with chip modifications during product development, and extending the product life cycle. ASIP is often programmed for specific fields and has strong specialization. It has a significant performance improvement over general-purpose processors.

[0063] Corresponding to ASIP, Application Specific Integrated Circuit (ASIC) is specially used to implement a certain type of customized circuit algorithm. In comparison, ASIC has higher performance but poorer flexibility, while ASIP has slightly lower performance than ASIC but has greater flexibility.

[0064] In the design and implementation of LTE (Long Time Evolution) and 5G NR (New Radio), the baseband processing unit (Building Baseband Unit, BBU) and the remote radio unit (Remote Radio Unit, RRU) are usually split and connected using optical fiber. The interface between the RRU and BBU is called the fronthaul interface.

[0065] Common fronthaul interfaces include Common Public Radio Interface (CPRI) and enhanced CPRI (eCPRI). The CPRI protocol is block-based data transmission, and its application scenarios are relatively simple. In addition, there are a large number of custom fields, which makes the CPRI protocol poorly adaptable. Compared with the CPRI protocol, the eCPRI protocol is used in the implementation of 5G. The eCPRI protocol is carried on the Ethernet, MAC layer or TCP / IP layer to integrate the eCPRI protocol into the TCP / IP protocol family. Compared with the proprietary CPRI protocol, the universality of the eCPRI protocol allows the RRU to no longer be attached to the BBU, thus acting as an independent network element. The network management center can directly manage the RRU, and no longer needs to rely on the BBU to manage the RRU. The protocol between the BBU and the RRU can be standardized, which provides an architectural guarantee for the interconnection and interoperability of BBU and RRU from different manufacturers, and greatly improves the universality.

[0066] The Open Radio Access Network (O-RAN) protocol is a specific implementation of the eCPRI protocol. The eCPRI protocol is only a transport layer protocol and does not define application layer protocol specifications such as IQ data format and real-time control plane data format above the service access point. The O-RAN protocol defines in detail the specific usage details when used as the fronthaul interface of NR, making the fronthaul interface implemented using the O-RAN protocol have good adaptability.

[0067] The eCPRI protocol and O-RAN protocol have the following characteristics when applied: First, both the eCPRI protocol and the O-RAN protocol are relatively new, and hardware devices that can support the eCPRI protocol and the O-RAN protocol (such as those based on FAGA (Field Programmable Gate There are not many ASICs that can be implemented, but they all have the defects of high cost, slow processing speed and can only support relatively small data throughput; secondly, the eCPRI protocol and O-RAN protocol are in the process of continuous evolution. If ASIC is used, the form risk is high and it is difficult to cope with subsequent protocol upgrades; thirdly, the eCPRI protocol and O-RAN protocol work on the fronthaul interface, which is the transmission bridge between the air interface and the base station processing unit data, requiring high real-time and high accuracy that traditional network processors cannot achieve; finally, due to the characteristics of the fronthaul interface service, in order to reduce the complexity of hardware design, improve the data transmission efficiency of the fronthaul interface, and reduce the system bandwidth, the message data of the fronthaul interface will be compressed before transmission, resulting in changes in the data bit width and size of the message data, and the boundary of the message data is no longer aligned with the transmission bit width, which requires the network processor to have the ability to process non-aligned data when processing message data. For example, when parsing message data, the network processor needs to have the ability to decompress non-aligned data, and for another example, when encapsulating message data, the network processor needs to have the ability to compress message data.

[0068] In view of the characteristics of the eCPRI protocol and the O-RAN protocol in their applications, the processor that supports the eCPRI protocol and the O-RAN protocol needs to achieve at least one of the following requirements: (1) high speed and large throughput. Taking the fronthaul interface of the 5G NR 4-transmit 4-receive small base station as an example, the processor needs to achieve at least an average throughput of 10 Gbps and support a burst throughput processing capability of 60 Gbps; (2) support compressed source message data and / or compressed source message data recovery; (3) support message data reordering; (4) support message data sending, parsing and encapsulation.

[0069] In view of this, the base station fronthaul interface protocol stack data dedicated processor provided by the present invention is a network processor (NP) based on ASIP, which can support the message processing work of the eCPRI protocol, O-RAN protocol and similar protocols when working on the base station fronthaul interface, and can process data packets and data frames in the network in real time at line speed, and can be widely used in scenarios where message data needs to be processed in mobile communications, broadband communications, industrial control and other fields.

[0070] Figure 1 Schematic diagram of the structure of the dedicated processor for the base station fronthaul interface protocol stack data provided by the present invention, such as Figure 1 As shown, the base station fronthaul interface protocol stack data dedicated processor includes but is not limited to an operation module 101, a message processing module 102, a program control module 103, an instruction storage module 104, a decoder module 105 and a register group module 106 composed of multiple registers.

[0071] The operation module 101 is used to obtain operands from the register group module 106 under the drive of the current execution instruction, and to operate on the operands to complete the execution of the current execution instruction and obtain the operation result.

[0072] The program control module 103 is used to manage the program count and arbitrate the program count change request sent by the operation module 101 after obtaining the operation result to determine the message processing instruction.

[0073] The instruction storage module 104 is used to store the currently executed instructions and message processing instructions.

[0074] The decoder module 105 is used to decode the message processing instruction and distribute the decoding result to the message processing module 102.

[0075] The message processing module 102 is used to process message data under the drive of the message processing instruction.

[0076] Among them, the currently executed instruction is determined from the instruction sequence to be currently executed, and is composed of the dedicated processing instructions in the dedicated processing instruction set, and the dedicated processing instructions in the dedicated processing instruction set are designed for the operation characteristics of the protocol stack data in the message data processing field. When executing the message data processing task, the programmer uses the dedicated processing instruction set to program the execution instruction in advance, so that the operation module 101 can obtain the operand to perform the operation under the drive of the currently executed instruction, and then drive the message processing module 102 to work based on the obtained operation result.

[0077] The message processing instruction is an instruction for driving the message processing module 102 to perform message processing.

[0078] The register group module 106 is used to temporarily store message data and operation results of the operation module.

[0079] Figure 2 It is a flow chart of message data processing provided by the present invention, such as Figure 2 As shown, when the message data is transmitted to the dedicated processor of the base station front transmission interface protocol stack data, the operation module 101, under the drive of the current execution instruction, obtains the operands required for the operation from the message data temporarily stored in the register group module 106 according to the current execution instruction, and uses the operands to perform operations based on the current execution instruction to obtain the operation results, and sends a program count change request to the program control module 103 based on the operation results.

[0080] The operations performed by the operation module 101 on the operands include but are not limited to insertion, replacement, addition, subtraction, multiplication, and, or, XOR, equal to, not equal to, greater than, greater than or equal to, less than, less than or equal to, etc.

[0081] The program control module 103 for managing the program count arbitrates the received program count change request based on the calculation result of the calculation module 101, and determines the next message processing instruction to be executed according to the arbitration result. The decoder module 105 decodes the message processing instruction extracted from the instruction storage module 104, and distributes the decoding result to the message processing module 102. The message processing module 102 processes the message data according to the decoding result under the drive of the message processing instruction.

[0082] When traditional general-purpose processors process message data through calculations, programmers are often required to perform a large amount of programming using general-purpose instruction sets in order to control the traditional general-purpose processors to perform calculations on protocol stack data. This results in problems of high cost, high instruction overhead, and high clock overhead. Especially when faced with high-throughput protocol stack message data, general-purpose processors process message data slowly and with high processing delays.

[0083] The dedicated processor for protocol stack data of the base station fronthaul interface provided by the present invention sets a dedicated processing instruction set in advance according to the operation characteristics of the protocol stack in the field of message data processing, and programs an instruction sequence with the dedicated processing instruction set so that the operation module can quickly execute the operation result, and then drive the message processing module to execute certain functions of itself to process the message data. In fact, the message data processing is performed based on the new ASIP and ASIC accelerator architecture constructed in the processor, which can reduce the number of instructions required to be programmed for executing the instruction sequence, and at the same time reduce the clock overhead and instruction overhead of executing the instructions, and obtain the operation result of driving the message processing module to work more quickly in a low-cost manner, thereby improving the speed of message data processing, and realizing a dedicated processor for protocol stack of the base station fronthaul interface that meets the high-speed, large-throughput and protocol stack message data processing requirements.

[0084] Based on the above embodiment, as an optional embodiment, the type of the currently executed instruction is a data change instruction, a bit operation instruction or a bit arbitration instruction.

[0085] Specifically, the type of the currently executed instruction is one of the possible types of each executed instruction in the instruction sequence, including any one of a data change instruction, a bit operation instruction, and a bit arbitration instruction.

[0086] Among them, data change instructions are instructions for inserting, replacing and other operations on data; bit operation instructions are instructions for splicing any two bits of data in two message data, including but not limited to addition, subtraction, multiplication, AND, OR, XOR and the like of bit data; bit arbitration instructions are instructions for comparing any two bits of data in two message data, including but not limited to instructions with comparison conditions of equal, not equal, greater than, less than or equal to, etc.

[0087] The base station fronthaul interface protocol stack data dedicated processor provided by the present invention can further reduce the number of instructions required to be programmed in the execution instruction sequence by classifying the execution instructions into data change instructions, bit operation instructions and bit arbitration instructions according to the execution characteristics of different execution instructions in the message data processing field, while reducing the clock overhead and instruction overhead of the execution instructions, so that the operation module can improve the speed of executing different types of instructions, thereby improving the speed of message data processing.

[0088] Based on the above embodiment, as an optional embodiment, when the currently executed instruction is the data change instruction, the currently executed instruction includes a change method, a first operand and a first target address; the first operand includes a first bit starting position and a first bit length;

[0089] The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes:

[0090] Acquire first bit data having a length of the first bit length starting from the first bit starting position;

[0091] The first bit of data is moved to the first target address in the target register corresponding to the target register number according to the changing method.

[0092] Specifically, when the currently executed instruction is a data change instruction, the currently executed instruction includes a data change method (such as replacement, insertion, etc.), a first operand rs1, a target register number rd and a first target address c, and the first operand rs1 includes a first bit starting position d and a first bit length e.

[0093] Correspondingly, under the drive of the current execution instruction which is a data change instruction, the operation module will fixedly obtain the first bit data of the first bit length e as the operand from the first bit starting position d of the register in the register group module corresponding to the first operand rs1, and then insert the first bit data into the c bit position of the target register corresponding to the target register number rd according to the change method of the current execution instruction, thereby completing the change of the message data.

[0094] Taking replacement as an example, the above process can be expressed in code form as a data replacement instruction "Replace rd[c],rs1[d,e]", where "Replace" represents the replacement of message data during the message data parsing process, that is, the bit data starting from position d in register rs1 with a length of e is intercepted and replaced with the original bit data starting from position c in another register rd.

[0095] Figure 3 Schematic diagram of the effect of replacing data by the computing module provided by the present invention. Figure 3 As shown, after the operation module executes the data replacement instruction, the P segment bit data in rs1 will replace the P segment bit data in rd.

[0096] Taking insertion as an example, the above process can be expressed in code form as a data insertion instruction "Insert rd[c],rs1[d,e]", where "Insert" represents the insertion of message data during the message data encapsulation process, that is, the bit data starting from position d in register rs1 with a length of e is intercepted and inserted into position c in another register rd. The original bit data after position c in another register rd will be moved to a higher position.

[0097] Figure 4 Schematic diagram of the effect of inserting data into the computing module provided by the present invention. Figure 4 As shown, after the operation module executes the data insertion instruction, the P segment bit data in rs1 will be inserted into the N position in rd, the MP segment bit data in rd will move to the higher position, and the highest bit data with the same length as the P segment bit data will be removed.

[0098] The base station fronthaul interface protocol stack data dedicated processor provided by the present invention takes into account the commonality of operations of message data replacement in the process of message data parsing and message data insertion in the process of message data encapsulation by the operation module, fixes the way of changing, replacing and inserting message data by the operation module, so that the operation module can simultaneously have the functions of replacing data when parsing the message and inserting data when encapsulating the message, that is, the processor can handle tasks related to message parsing and encapsulation at the same time, reducing the processor cost of message parsing and encapsulation; at the same time, the programmer only needs to write one instruction to implement a data change operation. When facing high-throughput message data processing, it can greatly reduce programming costs and time, and at the same time reduce the instruction overhead and clock overhead of the processor, thereby greatly improving the processing speed of message data.

[0099] Based on the above embodiment, as an optional embodiment, when the currently executed instruction is the bit operation instruction, the currently executed instruction includes an operation method, a second operand, a third operand, and a second target address; the second operand includes a second bit starting position, a second bit length, and a first bit number; the third operand includes a third bit starting position, a third bit length, and a second bit number;

[0100] The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes:

[0101] Acquire second bit data having a length of the second bit length starting from the second bit starting position, and shift the second bit data left by the first bit position;

[0102] Acquire third bit data having a length of the third bit length starting from the third bit starting position, and shift the third bit data left by the second bit position;

[0103] The second bit data after the left shift and the third bit data after the left shift are operated according to the operation method, and the operation result is stored in the second target address.

[0104] Specifically, when the currently executed instruction is a bit operation instruction, the currently executed instruction includes an operation method (such as addition, subtraction, multiplication, AND, OR, XOR, etc.), a second operand rs1, a third operand rs2 and a second target address rd, and the second operand rs1 includes a second bit starting position d, a second bit length e and a first bit number f, and the third operand rs2 includes a third bit starting position g, a third bit length h and a second bit number i.

[0105] Accordingly, driven by the current execution instruction belonging to the bit operation instruction, the operation module will fixedly obtain the second bit data of the second bit length e from the second bit starting position d of the register in the register group module corresponding to the second operand rs1, and shift the second bit data left by the first bit position f, and the second bit data after the left shift is number 1; at the same time, fixedly obtain the third bit data of the third bit length h from the third bit starting position g in the register corresponding to the third operand rs2, and shift the third bit data left by the second bit position i, and the third bit data after the left shift is number 2. The operation module further operates on number 1 and number 2 according to the operation method, and stores them in the second target address rd, thereby completing the operation of the message data.

[0106] Taking addition as an example, the above process is presented in code form, which can be expressed as a bit-domain precise addition instruction "Bpadd rd,rs1[d,e,f],rs2[g,h,i]", where "Bpadd" means precise addition of the bit-domains of two data.

[0107] For example, when the bit-domain precise addition instruction is "Bpadd n2,n0[8,12,0],n1[4,4,12]", the operation module intercepts bits [19:8] from the n0 register, shifts left by 0 bits, and obtains the number 1; intercepts bits [7:4] from the n1 register, shifts left by 12 bits, and obtains the number 2; and adds the numbers 1 and 2 to complete the bit-domain precise addition of the message data.

[0108] Figure 5 Schematic diagram of the effect of the operation module provided by the present invention accurately adding the data bit domain, such as Figure 5 As shown, after the operation module executes the bit domain precise addition instruction, the specific segment bit data in rs1 will be added to the specific segment bit data in rs2 and then written into rd.

[0109] Taking subtraction as an example, the above process is presented in code form, which can be expressed as a bit-domain precise subtraction instruction "Bpsub rd,rs1[d,e,f],rs2[g,h,i]", where "Bpsub" means precise subtraction of the bit fields of two data.

[0110] Taking multiplication as an example, the above process can be expressed in code form as a bit-domain precise multiplication instruction "Bpmul rd,rs1[d,e,f],rs2[g,h,i]", where "Bpmul" means precise multiplication of the bit fields of two data.

[0111] Taking the operation method as an example, the above process is presented in code form, which can be expressed as a bit field precise AND instruction "Bpand rd,rs1[d,e,f],rs2[g,h,i]", where "Bpand" means performing precise AND on the bit fields of two data.

[0112] Taking the operation method of OR as an example, the above process is presented in code form, which can be expressed as a bit field exact OR instruction "Bpor rd,rs1[d,e,f],rs2[g,h,i]", where "Bpor" means to perform exact OR on the bit fields of two data.

[0113] Taking the XOR operation as an example, the above process is presented in code form, which can be expressed as a bit-domain precise XOR instruction "Bpxor rd,rs1[d,e,f],rs2[g,h,i]", where "Bpxor" means performing a precise XOR on the bit fields of two data.

[0114] The base station fronthaul interface protocol stack data dedicated processor provided by the present invention considers the commonality of operations performed by the operation module when adding, subtracting, multiplying, ANDing, ORing, and XORing message data in the process of implementing message data parsing and encapsulation processing, fixes the way in which the operation module operates on two bit fields, speeds up the operation speed, and allows the operation module to simultaneously complete the precise interception and operation of data; further, these instructions can be flexibly used to write instruction sequences in the message processing processes of message data parsing and message data encapsulation, thereby reducing the processor cost of message parsing and encapsulation; and the processing of these execution instructions by the operation module has been fixed in hardware, which can greatly reduce programming costs and time when facing high-throughput message data processing, while reducing the instruction overhead and clock overhead of the processor, thereby greatly improving the processing speed of message data.

[0115] Figure 6 is a schematic diagram of the structure of the operation module provided by the present invention, such as Figure 6 As shown, the operation module includes a first masker 611 , a second masker 612 , a first shifter 621 , a second shifter 622 and an operator 630 .

[0116] The first masker 611 is used to perform a mask operation on an operand based on the currently executed instruction to obtain a first mask result.

[0117] The second masker 612 is used to perform a mask operation on another operand based on the currently executed instruction to obtain a second mask result.

[0118] The first shifter 621 is used to perform a shift operation on the first mask result to obtain a first shift result.

[0119] The second shifter 622 is used to perform a shift operation on the second mask result to obtain a second shift result.

[0120] The operator 630 is used to perform an operation on the first shift result and the second shift result to complete the execution of the current execution instruction.

[0121] Specifically, when the currently executed instruction is a bit operation instruction, the first masker 611 in the operation module first determines the first mask based on the second bit starting position and the second bit length, and then uses the first mask to perform a mask operation on the second bit data to obtain a first mask result; the second masker 612 first determines the second mask based on the third bit starting position and the third bit length, and then uses the second mask to perform a mask operation on the third bit data to obtain a second mask result.

[0122] The first shifter 621 performs a left shift operation on the first mask result according to the first bit number to obtain a first shift result; the second shifter 622 performs a left shift operation on the second mask result according to the second bit number to obtain a second shift result.

[0123] The operator 630 operates on the first shift result and the second shift result according to the operation method in the currently executed instruction (such as addition, subtraction, multiplication, AND, OR, XOR, etc.), and writes the obtained operation result to the second target address, thereby completing the instruction of the currently executed instruction.

[0124] The base station front transmission interface protocol stack data dedicated processor provided by the present invention, by arranging two maskers, two shifters and an operator in the operation module, aims at the commonality of the operations of message data processing in the message data parsing and encapsulation processing process, and fixes the operation module in a hardware manner to perform precise addition, precise subtraction, precise multiplication, precise AND, precise OR, and precise XOR of two bit fields, thereby improving the speed of message data processing.

[0125] Based on the above embodiment, as an optional embodiment, when the currently executed instruction is the bit arbitration instruction, the currently executed instruction includes an arbitration method, a fourth operand, a fifth operand, and a relative jump address; the fourth operand includes a fourth bit starting position and a fourth bit length; the fifth operand includes a fifth bit starting position and a fifth bit length;

[0126] The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes:

[0127] Acquire fourth bit data having a length of the fourth bit length starting from the fourth bit starting position;

[0128] Acquire fifth bit data having a length of the fifth bit length starting from the fifth bit starting position;

[0129] The fourth bit data and the fifth bit data are compared according to the arbitration method. If the comparison is successful, jump to the target address determined based on the relative jump address; if the comparison fails, execute the next execution instruction of the current execution instruction in the instruction sequence.

[0130] Specifically, when the currently executed instruction is a bit arbitration instruction, the currently executed instruction includes an arbitration method (such as a comparison condition of equal to, not equal to, greater than, less than or equal to, etc.), a fourth operand rd, a fifth operand rs1 and a relative jump address pcrel, and the fourth operand rd includes a fourth bit starting position a and a fourth bit length b, and the fifth operand rs1 includes a fifth bit starting position d and a fifth bit length e.

[0131] Accordingly, under the drive of the current execution instruction belonging to the bit arbitration module, the operation module will fixedly obtain the fourth bit data of the fourth bit length b from the fourth bit starting position a in the register of the register group module corresponding to the fourth operand rd, and fixedly obtain the fifth bit data of the fifth bit length e from the fifth bit starting position d in the register corresponding to the fifth operand rs1. The operation module further compares the fourth bit data and the fifth bit data according to the arbitration method, and if the comparison is successful, jumps to the target address determined by calculating the PC (Program Counter) address according to the relative jump address pcrel; if the comparison fails, executes the next execution instruction of the current execution instruction in the instruction sequence.

[0132] Taking the comparison condition of the arbitration method as an example, the above process is presented in code form, which can be expressed as the first bit-domain precise branch instruction "Bpbeq rd[a,b],rs1[d,e],pcrel" with the comparison condition being equal, where "Bpbeq" means to compare the two operands for equality. For example, when the first bit-domain precise branch instruction is "Bpbeq n1[12,12],n0[0,12],res", the operation module intercepts 12 bits of data starting from the bit12 position of the n1 register, which is number 1, and compares the 12 bits of data intercepted starting from the bit0 position of the n0 register, which is number 2, for equality. If the comparison succeeds, that is, the two operands are equal, then jump to the target address determined by calculating the PC address based on the relative jump address res; if the comparison fails, that is, the two operands are not equal, then execute the next execution instruction.

[0133] Taking the comparison condition of the arbitration method as inequality as an example, the above process is presented in code form, which can be expressed as the second bit-domain precise branch instruction "Bpbneq rd[a,b],rs1[d,e],pcrel" with the comparison condition being inequality, where "Bpbneq" means performing an inequality comparison on the two operands.

[0134] Taking the comparison condition of the arbitration method as greater than as an example, the above process is presented in code form, which can be expressed as the third bit field precise branch instruction "Bpbgt rd[a,b],rs1[d,e],pcrel" with the comparison condition as greater than, where "Bpbgt" means a greater than comparison is performed on the two operands.

[0135] Taking the comparison condition of the arbitration method as less than or equal to as an example, the above process is presented in code form, which can be expressed as the fourth bit field precise branch instruction "Bpble rd[a,b],rs1[d,e],pcrel" with the comparison condition less than or equal to, where "Bpble" means to compare the two operands for less than or equal to.

[0136] The base station front transmission interface protocol stack data dedicated processor provided by the present invention accelerates the operation speed by considering the common arbitration characteristics of the operation module when performing comparisons such as equal, greater than, not equal, less than or equal to, etc. on message data during the message data parsing and encapsulation processing, and fixing the way in which the operation module arbitrates two bit fields; further, these instructions can be flexibly used to write instruction sequences during the message data parsing and message data encapsulation message processing, thereby reducing the processor cost of message parsing and encapsulation; and the processing of these execution instructions by the operation module has been fixed in hardware, which can greatly reduce programming costs and time when facing high-throughput message data processing, while reducing the instruction overhead and clock overhead of the processor, thereby greatly improving the processing speed of message data.

[0137] Based on the above embodiment, as an optional embodiment, when the currently executed instruction is the bit arbitration instruction, the currently executed instruction includes an arbitration method, a sixth operand, an immediate number, and a relative jump address; the sixth operand includes a sixth bit starting position and a sixth bit length;

[0138] The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes:

[0139] Acquire sixth bit data having a length of the sixth bit starting from the sixth bit starting position;

[0140] The sixth bit data and the immediate value are compared according to the arbitration method. If the comparison is successful, jump to the target address determined based on the relative jump address; if the comparison fails, execute the next execution instruction of the current execution instruction in the instruction sequence.

[0141] Specifically, when the currently executed instruction is a bit arbitration instruction, the currently executed instruction includes an arbitration method, a sixth operand rd, an immediate number imm and a relative jump address pcrel, and the sixth operand rd includes a sixth bit starting position a and a sixth bit length b.

[0142] Accordingly, the operation module, driven by the current execution instruction belonging to the bit arbitration instruction, will fixedly start from the sixth bit starting position a in the register corresponding to the sixth operand rd in the register group module, and obtain the sixth bit data with a length of the sixth bit length b, that is, the sixth bit data comes from the register corresponding to the sixth operand rd in the register group module. At the same time, the immediate number imm from the current execution instruction is fixedly used as another operand. The operation module further compares the sixth bit data with the immediate number according to the arbitration method. If the comparison is successful, it jumps to the target address determined by calculating the PC address according to the relative jump address pcrel; if the comparison fails, it executes the next execution instruction of the current execution instruction in the instruction sequence.

[0143] Taking the comparison condition of the arbitration method as equal as an example, the above process is presented in code form, which can be expressed as the fifth bit field precise branch instruction "Bpbeqi rd[a,b],imm,pcrel" with the comparison condition being equal, where "Bpbeqi" means to compare the two operands for equality.

[0144] Taking the comparison condition of the arbitration method as inequality as an example, the above process is presented in code form, which can be expressed as the sixth bit field precise branch instruction "Bpbneqi rd[a,b],imm,pcrel" with the comparison condition as inequality, where "Bpbneqi" means to compare the two operands for inequality.

[0145] Taking the comparison condition of the arbitration method as greater than as an example, the above process is presented in code form, which can be expressed as the seventh bit field precise branch instruction "Bpbgti rd[a,b],imm,pcrel" with the comparison condition as greater than, where "Bpbgti" means a greater than comparison is performed on the two operands.

[0146] Taking the comparison condition of the arbitration method as less than or equal to as an example, the above process is presented in code form, which can be expressed as the eighth bit field precise branch instruction "Bpblei rd[a,b],imm,pcrel" with the comparison condition less than or equal to, where "Bpblei" means comparing the two operands for less than or equal to.

[0147] The base station front transmission interface protocol stack data dedicated processor provided by the present invention accelerates the operation speed by considering the commonality of arbitration of equal, greater than, not equal to, less than or equal to, etc. of the operation module in the process of implementing message data parsing and encapsulation processing, and fixing the operation module to obtain an operand from the register, use the immediate number as another operand, and arbitrate the two bit fields; further, these instructions can be flexibly used to write instruction sequences in the message processing process of message data parsing and message data encapsulation, thereby reducing the processor cost of message parsing and encapsulation; and the processing of these execution instructions by the operation module has been fixed in hardware, when facing high-throughput message data processing, it can greatly reduce programming cost and time, while reducing the instruction overhead and clock overhead of the processor, thereby greatly improving the processing speed of message data.

[0148] As an optional embodiment, the register group module is mapped with a data input interface and a data output interface.

[0149] When the instruction sequence is used to encapsulate message data, the data input interface and the data output interface are externally connected to a sending link, and the register group module and the sending link complete data writing based on a hardware handshake method.

[0150] When the instruction sequence is used to parse message data, the data input interface and the data output interface are externally connected to an Ethernet switch, and the register group module and the Ethernet switch complete data writing based on a hardware handshake method.

[0151] Optionally, the register group module and the Ethernet switch complete data writing based on a handshake method of hardware Semaphone (semaphore); the register group module and the transmission link complete data writing based on a handshake method of hardware Semaphone.

[0152] The base station fronthaul interface protocol stack data dedicated processor provided by the present invention maps the data interface and the control interface to a general register group and uses a hardware handshake method to complete data writing, thereby omitting the step of temporarily storing the message data in a cache in the traditional method, so that the data input to the processor can directly participate in the calculation, saving the time for reading the message data, optimizing the timing of message data processing and simplifying the programming difficulty of the instruction sequence.

[0153] Based on the above embodiment, as an optional embodiment, the operation result includes a first block move control word and a data recovery control word;

[0154] The message processing module includes: a first block moving module, a data recovery module and a first cache;

[0155] The first block moving module is used to move the message data from the register group module based on the first block moving control word, and write the message data into the first cache;

[0156] The data recovery module is used to load the message data from the first cache based on the data recovery control word, restore the data bit width and size of the message data, and send the recovered message data until the sending of one message data is completed.

[0157] Specifically, when the calculation result obtained by the calculation module includes the first block move control word and the data recovery control word, the message processing instruction determined by the program control module is the message parsing instruction under the message parsing scenario, and the message parsing instruction includes the first block move instruction and the data recovery instruction. The first block move instruction includes the first block move control word in the calculation result, and the data recovery instruction includes the data recovery control word in the calculation result.

[0158] Driven by the first block move instruction, the first block move module is configured according to the generated first block move control word, so that the first block move module continuously moves the payload in the message data from the register group module according to the first block move control word, and writes the payload in the message data into the first cache.

[0159] Wait for the timed sending signal, and after receiving the timed sending signal and responding, configure the data recovery module according to the generated data recovery control word, and the data recovery module loads the payload of the written message data from the first cache according to the data recovery control word, restores the payload in the message data to the original data bit width and size, and sends the recovered message data until the sending of one message data is finally completed, thereby completing the parsing of the currently processed message data.

[0160] The base station fronthaul interface protocol stack data dedicated processor provided by the present invention integrates other modules required for message data parsing, and sets a dedicated processing instruction set in advance according to the operation characteristics of the message data protocol stack, thereby accelerating the process of calculating block movement control words and data recovery control words, and improving the speed of message data parsing; in addition, the control words for realizing block movement function and data recovery function are generated by the operation module, that is, the control words for realizing block movement function and data recovery function in the processor are configured by ASIP, and a new architecture for collaborative parsing of message data by ASIP and ASIC accelerator is constructed in the processor, which has low cost and can improve the rate of special functions such as block movement function and data recovery function in the message data parsing process, thereby improving the processing speed of message data parsing and meeting the real-time requirements of message processing at the same time, and realizing a high-speed and large-throughput processor in the message data parsing scenario of the base station fronthaul interface; when processing message data, the processed message data is temporarily stored in the cache first, and is sent only after receiving the timing sending signal, that is, the timing requirements of the 5G fronthaul interface and the wireless system are realized through the cache and the external control signal, and the network jitter is eliminated at the same time.

[0161] Based on the above embodiment, as an optional embodiment, the operation result includes a second block move control word;

[0162] The message processing module includes: a second block moving module, a data integration module and a second cache;

[0163] The second block moving module is used to move the compressed message data from the second cache to the register group module based on the second block moving control word; the compressed message data is stored in the second cache after the data bit width and size of the message data are compressed by the data integration module according to a pre-configured data integration control word.

[0164] Specifically, when the calculation result obtained by the calculation module includes the second block move control word, the message processing instruction determined by the program control module is a message encapsulation instruction in the message encapsulation scenario, and the message encapsulation instruction includes the second block move instruction, and the second block move instruction includes the second block move control word in the calculation result.

[0165] In the message data encapsulation scenario, after the dedicated data processor of the base station fronthaul interface protocol stack starts working, it polls and receives the packet request signal transmitted by the uplink every time there is new data to be sent. After responding to the packet request signal, the data integration module starts to compress the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and writes the compressed message data into the second cache.

[0166] Driven by the current execution instruction, the operation module extracts the control information of the message data to be sent, processes it and obtains the operation result, and then generates the second block of movement control words and the header of the message data to be sent according to the operation result.

[0167] Waiting for the timing sending signal, after receiving the timing sending signal, the operation module sends the header of the message data to be sent through the register group module. Driven by the second moving instruction, the second moving module moves the compressed message data from the second cache to the register group module, and sends the compressed message data through the register group module until the sending of a message data (such as an eCPRI message or an O-RAN message) is finally completed, thereby completing the encapsulation of the currently processed message data.

[0168] Furthermore, after completing the encapsulation of the currently processed message data, the base station fronthaul interface protocol stack data dedicated processor continues to poll and receive the packet request signal of the uplink transmission, and after receiving the next packet request signal and responding, the data integration module compresses the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and starts the step of writing the compressed message data into the second cache to encapsulate the next message data.

[0169] The dedicated processor for base station fronthaul interface protocol stack data provided by the present invention integrates other modules required for message data encapsulation, and sets a dedicated processing instruction set in advance according to the budget characteristics of the message data protocol stack, thereby accelerating the process of calculating the block movement control word, thereby improving the speed of message data encapsulation; in addition, the operation module processes the message data under the drive of the instruction sequence obtained by flexible programming based on the dedicated processing instruction set, and generates a control word for realizing the block movement function, that is, the control word for realizing the block movement function in the processor is configured by ASIP, and a new architecture for ASIP and accelerator to collaboratively encapsulate message data is constructed in the processor, which has low cost and can improve the rate of special functions such as the block movement function in the message data parsing process, thereby improving the message data. The processing speed of message data encapsulation is improved while meeting the real-time requirements of message processing, realizing a high-speed, high-throughput processor in the message data encapsulation scenario of the base station fronthaul interface; by using a dedicated processing instruction set when pre-programming the instruction sequence, the number of execution instructions required to be programmed by the operator when encapsulating the message data can be reduced, the instruction overhead can be reduced and the message data encapsulation speed can be increased; by sending the message data through the register group module, the timing of message data encapsulation can be optimized and the programming difficulty of the instruction sequence can be simplified; by writing the compressed message data to be sent into the cache through the data integration module, and using the register group module to send the message data after waiting for the timing sending signal, the network jitter of data processing can be overcome and the timing requirements of the 5G fronthaul interface and the wireless system can be met.

[0170] Optionally, when the dedicated processor for data of the base station fronthaul interface protocol stack has functions of both message data parsing and message data encapsulation, the first cache and the second cache are the same cache.

[0171] Figure 7 Schematic diagram of the flow of the message processing method based on the dedicated processor of the base station front transmission interface protocol stack data provided by the present invention, such as Figure 7 As shown, the message processing method includes but is not limited to steps 701 to 704.

[0172] Step 701: under the drive of the current execution instruction, the control operation module obtains operands from the register group module, operates on the operands and completes the execution of the current execution instruction to obtain the operation result.

[0173] The currently executed instructions are composed of special processing instructions in a special processing instruction set.

[0174] The register group module includes a plurality of registers.

[0175] Step 702: The control program control module manages the program count, and arbitrates the program count change request sent by the operation module after obtaining the operation result, so as to determine the message processing instruction.

[0176] Step 703: Control the decoder module to decode the message processing instruction and distribute the decoding result to the message processing module.

[0177] Step 704: Control the message processing module to process the message data under the drive of the message processing instruction.

[0178] It should be noted that the message processing method provided by the present invention, when specifically executed, can be based on the base station fronthaul interface protocol stack data dedicated processor described in any of the above embodiments, which will not be elaborated in this embodiment.

[0179] The message processing method based on the dedicated processor of the protocol stack data of the base station fronthaul interface provided by the present invention sets a dedicated processing instruction set in advance according to the operation characteristics of the protocol stack in the field of message data processing, and programs an instruction sequence by the dedicated processing instruction set, so that the operation module can quickly execute and obtain the operation result, and then drive the message processing module to execute certain functions of itself to process the message data. In fact, the message data processing is performed based on the new ASIP and ASIC architecture constructed in the processor, which can reduce the number of instructions required to be programmed for executing the instruction sequence, and at the same time reduce the clock overhead and instruction overhead of executing the instructions, and obtain the operation result of driving the message processing module to work more quickly in a low-cost manner, thereby improving the speed of message data processing, and realizing a dedicated processor of the protocol stack of the base station fronthaul interface that meets the high-speed, large-throughput and protocol stack message data processing requirements.

[0180] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0181] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0182] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A base station fronthaul interface protocol stack data dedicated processor, characterized in that: include: A register group module consisting of an operation module, a message processing module, a program control module, an instruction storage module, a decoder module and a plurality of registers; the register group module is mapped with a data input interface and a data output interface; The operation module is used to obtain operands from the register group module under the drive of the current execution instruction, and to operate on the operands to complete the execution of the current execution instruction and obtain the operation result; the current execution instruction is composed of special processing instructions in the special processing instruction set; The program control module is used to manage the program count and arbitrate the program count change request sent by the operation module after obtaining the operation result to determine the message processing instruction; The instruction storage module is used to store the currently executed instruction and the message processing instruction; The decoder module is used to decode the message processing instruction and distribute the decoding result to the message processing module; The message processing module is used to process the message data under the drive of the message processing instruction; The type of the currently executed instruction is a data change instruction, a bit operation instruction or a bit arbitration instruction; When the currently executed instruction is the data change instruction, the currently executed instruction includes a change method, a first operand, a target register number and a first target address; the first operand includes a first bit starting position and a first bit length; the change method includes replacement and insertion; When the currently executed instruction is the bit operation instruction, the currently executed instruction includes an operation method, a second operand, a third operand, and a second target address; the second operand includes a second bit starting position, a second bit length, and a first bit number; the third operand includes a third bit starting position, a third bit length, and a second bit number; the operation method includes addition, subtraction, multiplication, AND, OR, and XOR; When the currently executed instruction is the bit arbitration instruction, the currently executed instruction includes an arbitration method, a fourth operand, a fifth operand and a relative jump address; the fourth operand includes a fourth bit starting position and a fourth bit length; the fifth operand includes a fifth bit starting position and a fifth bit length; and the comparison conditions of the arbitration method include equal to and not equal to.

2. The base station fronthaul interface protocol stack data dedicated processor according to claim 1, characterized in that: When the currently executed instruction is the data change instruction, obtaining an operand from the register group module and performing operations on the operand to complete the execution of the currently executed instruction includes: Acquire first bit data having a length of the first bit length starting from the first bit starting position; The first bit of data is moved to the first target address in the target register corresponding to the target register number according to the changing method.

3. The base station fronthaul interface protocol stack data dedicated processor according to claim 1, characterized in that: When the currently executed instruction is the bit operation instruction, obtaining an operand from the register group module and operating the operand to complete the execution of the currently executed instruction includes: Acquire second bit data having a length of the second bit length starting from the second bit starting position, and shift the second bit data left by the first bit position; Acquire third bit data having a length of the third bit length starting from the third bit starting position, and shift the third bit data left by the second bit position; The second bit data after the left shift and the third bit data after the left shift are operated according to the operation method, and the operation result is stored in the second target address.

4. The base station fronthaul interface protocol stack data dedicated processor according to claim 3, characterized in that: The operation module includes a first masker, a second masker, a first shifter, a second shifter and an operator; The first masker is used to perform a mask operation on an operand based on the currently executed instruction to obtain a first mask result; The second masker is used to perform a mask operation on another operand based on the currently executed instruction to obtain a second mask result; The first shifter is used to perform a shift operation on the first mask result to obtain a first shift result; The second shifter is used to perform a shift operation on the second mask result to obtain a second shift result; The operator is used to operate on the first shift result and the second shift result to complete the execution of the current execution instruction.

5. The base station fronthaul interface protocol stack data dedicated processor according to claim 1, characterized in that: When the currently executed instruction is the bit arbitration instruction, acquiring an operand from the register group module and performing operations on the operand to complete the execution of the currently executed instruction includes: Acquire fourth bit data having a length of the fourth bit length starting from the fourth bit starting position; Acquire fifth bit data having a length of the fifth bit length starting from the fifth bit starting position; The fourth bit data and the fifth bit data are compared according to the arbitration method. If the comparison is successful, jump to the target address determined based on the relative jump address; if the comparison fails, execute the next execution instruction of the current execution instruction in the instruction sequence.

6. The base station fronthaul interface protocol stack data dedicated processor according to claim 1, characterized in that: When the currently executed instruction is the bit arbitration instruction, the currently executed instruction includes an arbitration method, a sixth operand, an immediate number, and a relative jump address; the sixth operand includes a sixth bit starting position and a sixth bit length; The obtaining of operands from the register group module and performing operations on the operands to complete the execution of the currently executed instruction includes: Acquire sixth bit data having a length of the sixth bit starting from the sixth bit starting position; The sixth bit data and the immediate value are compared according to the arbitration method. If the comparison is successful, jump to the target address determined based on the relative jump address; if the comparison fails, execute the next execution instruction of the current execution instruction in the instruction sequence.

7. The base station fronthaul interface protocol stack data dedicated processor according to claim 6, characterized in that: The operation result includes a first block moving control word and a data recovery control word; The message processing module includes: a first block moving module, a data recovery module and a first cache; The first block moving module is used to move the message data from the register group module based on the first block moving control word, and write the message data into the first cache; The data recovery module is used to load the message data from the first cache based on the data recovery control word, restore the data bit width and size of the message data, and send the recovered message data until the sending of one message data is completed.

8. The base station fronthaul interface protocol stack data dedicated processor according to claim 6, characterized in that: The operation result includes a second block movement control word; The message processing module includes: a second block moving module, a data integration module and a second cache; The second block moving module is used to move the compressed message data from the second cache to the register group module based on the second block moving control word; the compressed message data is stored in the second cache after the data bit width and size of the message data are compressed by the data integration module according to a pre-configured data integration control word.

9. A message processing method based on the dedicated processor for base station fronthaul interface protocol stack data according to any one of claims 1 to 8, characterized in that: include: The control operation module, under the drive of the current execution instruction, obtains operands from the register group module, operates on the operands and completes the execution of the current execution instruction to obtain the operation result; the current execution instruction is composed of special processing instructions in the special processing instruction set; the register group module includes a plurality of registers; The control program control module manages the program count and arbitrates the program count change request sent by the operation module after obtaining the operation result to determine the message processing instruction; Controlling the decoder module to decode the message processing instruction and distribute the decoding result to the message processing module; The message processing module is controlled to process the message data under the drive of the message processing instruction.

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