Memory device and method of manufacturing the same

Abstract

The present technology relates to a memory device and a method of manufacturing the same. A memory device according to an embodiment of the present disclosure includes a main chip region, a chip protection region disposed adjacent to the main chip region, a plurality of chip protection patterns formed in the chip protection region, and a buffer slit formed in a space between the plurality of chip protection patterns.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202111201531.3 (application date: October 15, 2021, invention name: memory device and manufacturing method thereof). Technical Field

[0002] The present disclosure relates to a memory device and a method for manufacturing the same, and more particularly, to a three-dimensional memory device and a method for manufacturing the same. Background Art

[0003] Recently, the paradigm of computer environment has shifted to ubiquitous computing, which enables computer systems to be used anywhere, anytime. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has increased rapidly. Such portable electronic devices generally use a memory system that uses a memory device, i.e., a data storage device. The data storage device is used as a primary storage device or an auxiliary storage device of the portable electronic device.

[0004] Since there is no mechanical drive, the data storage device using the memory device has the advantages of stability and durability. In addition, the access speed of information is very fast and the power consumption is low. As an example of a memory system having these advantages, the data storage device includes a universal serial bus (USB) memory device, a memory card with various interfaces, a solid state drive (SSD), etc.

[0005] Memory devices are roughly divided into volatile memory devices and nonvolatile memory devices.

[0006] The writing speed and reading speed of non-volatile memory devices are relatively slow. However, even if the power is turned off, the non-volatile memory device still maintains the stored data. Therefore, the non-volatile memory device is used to store data that is to be maintained regardless of the power supply. Non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is divided into NOR type and NAND type.

[0007] Recently, as the integration degree of a two-dimensional nonvolatile memory device in which memory cells are formed in a single layer on a substrate reaches its limit, a three-dimensional nonvolatile memory device in which memory cells are vertically stacked on a substrate is being proposed.

[0008] A three-dimensional nonvolatile memory device includes interlayer insulating layers and gate electrodes alternately stacked, a channel layer passing through the interlayer insulating layers and the gate electrodes, and memory cells stacked along the channel layer. Various structures and manufacturing methods are being developed to improve the operational reliability and manufacturing yield of a nonvolatile memory device having such a three-dimensional structure. Summary of the invention

[0009] According to an embodiment of the present disclosure, a memory device includes a main chip region, a chip protection region disposed adjacent to the main chip region, a plurality of chip protection patterns formed in the chip protection region, and a buffer slit formed in a space between the plurality of chip protection patterns.

[0010] According to an embodiment of the present disclosure, a method for manufacturing a memory device includes the following steps: forming a stack in which multiple sacrificial layers and multiple interlayer insulating layers are alternately stacked on a substrate in a main chip area, a scribe area, and a chip protection area between the main chip area and the scribe area; forming a plurality of grooves passing through the stack in the chip protection area; forming a sacrificial pattern in the plurality of grooves; forming a slit passing through the stack in a space between the plurality of grooves; removing the sacrificial layer exposed by the slit and forming a plurality of plate electrodes in the space where the sacrificial layer is removed; removing the sacrificial pattern and forming a chip protection pattern in the space where the sacrificial pattern is removed; and forming a buffer slit in the slit.

[0011] According to an embodiment of the present disclosure, a method for manufacturing a memory device includes the following steps: forming a stack in which multiple sacrificial layers and multiple interlayer insulating layers are alternately stacked on a substrate in a main chip area and a chip protection area; forming a plurality of grooves passing through the stack in the chip protection area; forming a sacrificial pattern in the plurality of grooves; forming a plurality of first slits passing through the stack on the main chip area and forming a second slit passing through the stack in a space between the plurality of grooves; removing the sacrificial layer exposed by the first slits and the second slits, and then forming a plurality of plate electrodes in the space where the sacrificial layer is removed; after removing the sacrificial pattern, forming a plurality of chip protection patterns by filling each of the plurality of grooves with a conductive material; and forming a buffer slit in the second slit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0014] Figure 3 and Figure 4 is a perspective view showing a memory device according to an embodiment of the present disclosure.

[0015] Figure 5A and Figure 5B are a plan view and a cross-sectional view showing a memory device according to an embodiment of the present disclosure.

[0016] Figure 6 is a plan view showing a memory device according to another embodiment of the present disclosure.

[0017] 7A to 7H are a plan view and a cross-sectional view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0018] Figure 8 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0019] Fig. 9 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0020] Fig.10 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0021] Fig.11 is a block diagram illustrating a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Below, the most preferred embodiment of the present disclosure is described. In the accompanying drawings, thickness and distance are expressed for convenience of description and may be exaggerated compared to actual physical thickness. When describing the present disclosure, well-known configurations that are irrelevant to the subject matter of the present disclosure may be omitted. When adding reference numerals to the components of the various figures, it should be noted that, even if the components are indicated on different figures, only the same components have the same reference numerals as much as possible.

[0023] Embodiments of the present disclosure provide a memory device having an easy manufacturing process and a stable structure and a method of manufacturing the same.

[0024] According to the present technology, by forming a chip protection pattern in a chip protection region between a main chip region and a scribe region and forming a buffer slit in a space between the chip protection patterns, cracks caused by chip stress and defects of superimposed vertical bonds formed on the scribe region can be improved.

[0025] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1 , the memory device 10 may include a peripheral circuit PC and a memory cell array 20 .

[0027] The peripheral circuit PC may be configured to perform a program operation for storing data in the memory cell array 20 , a read operation for outputting data stored in the memory cell array 20 , and an erase operation for erasing data stored in the memory cell array 20 .

[0028] As an embodiment, the peripheral circuit PC may include a voltage generator 31 , a row decoder 33 , a control circuit 35 , and a page buffer group 37 .

[0029] The memory cell array 20 may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells storing data.

[0030] The memory cell array 20 may be connected to the row decoder 33 through word lines WL and may be connected to the page buffer group 37 through bit lines BL.

[0031] The control circuit 35 may control the peripheral circuit PC in response to the command CMD and the address ADD.

[0032] The voltage generator 31 may generate various operating voltages for program operations, read operations, and erase operations in response to the control of the control circuit 35. These operating voltages may include a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, and the like.

[0033] The row decoder 33 may provide the operating voltage generated by the voltage generator 31 to the memory cell array 20 in response to the control circuit 35. For example, the row decoder 33 may provide the operating voltage generated by the voltage generator 31 to at least one memory block selected from among a plurality of memory blocks included in the memory cell array 20.

[0034] The page buffer group 37 may be connected to the memory cell array 20 through the bit line BL. The page buffer group 37 may temporarily store data received from an input / output circuit (not shown) in response to the control circuit 35 during a program operation, and control the potential of the bit line BL based on the temporarily stored data. The page buffer group 37 may sense the voltage or current of the bit line BL in response to the control circuit 35 during a read operation or a verification operation.

[0035] Structurally, the memory cell array 20 may be disposed on the peripheral circuit PC. The memory cell array 20 may overlap a portion of the peripheral circuit PC.

[0036] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0037] Reference Figure 2, the memory cell array 20 may include a plurality of cell strings CS1 and CS2 connected between a source line SL and a plurality of bit lines BL. The plurality of cell strings CS1 and CS2 may be commonly connected to a plurality of word lines WL1 to WLn.

[0038] Each of the plurality of cell strings CS1 and CS2 may include at least one source select transistor SST connected to a source line SL, at least one drain select transistor DST connected to a bit line BL, and a plurality of memory cells MC1 to MCn connected in series between the source select transistor SST and the drain select transistor DST.

[0039] The gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn spaced apart and stacked from each other. The plurality of word lines WL1 to WLn may be disposed between a source selection line SSL and two or more drain selection lines DSL1 and DSL2. The two or more drain selection lines DSL1 and DSL2 may be spaced apart from each other at the same level.

[0040] A gate of the source select transistor SST may be connected to a source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

[0041] The source line SL may be connected to the source of the source selection transistor SST. The drain of the drain selection transistor DST may be connected to a bit line corresponding to the drain of the drain selection transistor DST.

[0042] A plurality of cell strings CS1 and CS2 may be divided into string groups connected to two or more drain selection lines DSL1 and DSL2, respectively. Cell strings connected to the same word line and the same bit line may be independently controlled by different drain selection lines. In addition, cell strings connected to the same drain selection line may be independently controlled by different bit lines.

[0043] As an embodiment, the two or more drain selection lines DSL1 and DSL2 may include a first drain selection line DSL1 and a second drain selection line DSL2. The plurality of cell strings CS1 and CS2 may include a first cell string CS1 of a first string group connected to the first drain selection line DSL1 and a second cell string CS2 of a second string group connected to the second drain selection line DSL2.

[0044] Figure 3 and Figure 4 is a perspective view showing a memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 3 and Figure 4, each of the memory devices 10A and 10B may include a peripheral circuit PC disposed on a substrate SUB and a gate stack GST overlapping the peripheral circuit PC.

[0046] Each gate stack GST may include a source select line SSL, a plurality of word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 separated from each other at the same level by a first slit S1 .

[0047] The source selection line SSL and the plurality of word lines WL1 to WLn may extend in a first direction X and a second direction Y and may be formed in a flat plate shape parallel to the upper surface of the substrate SUB. The first direction X may be a direction in which an X-axis of an XYZ coordinate system points, and the second direction Y may be a direction in which a Y-axis of the XYZ coordinate system points.

[0048] The plurality of word lines WL1 to WLn may be spaced apart from each other and stacked in a third direction Z. The third direction Z may be a direction in which a Z axis of an XYZ coordinate system points. The plurality of word lines WL1 to WLn may be disposed between two or more drain selection lines DSL1 and DSL2 and a source selection line SSL.

[0049] The gate stacks GST may be separated from each other by the second slits S2. The first slits S1 may be formed to be shorter than the second slits S2 in the third direction Z, and may overlap the plurality of word lines WL1 to WLn.

[0050] Each of the first slit S1 and the second slit S2 may extend in a straight line, a zigzag shape, or a wavy shape. A width of each of the first slit S1 and the second slit S2 may be variously changed according to a design rule.

[0051] Reference Figure 3 According to an embodiment, the source select line SSL may be disposed closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2.

[0052] The memory device 10A may include a source line SL disposed between a gate stack GST and a peripheral circuit PC and a plurality of bit lines BL spaced farther from the peripheral circuit PC than the source line SL. The gate stack GST may be disposed between the plurality of bit lines BL and the source line SL.

[0053] Reference Figure 4 According to an embodiment, two or more drain select lines DSL1 and DSL2 may be disposed closer to the peripheral circuit PC than the source select line SSL.

[0054] The memory device 10B may include a plurality of bit lines BL disposed between the gate stack GST and the peripheral circuit PC, and may include a source line SL farther from the peripheral circuit PC than the plurality of bit lines BL. The gate stack GST may be disposed between the plurality of bit lines BL and the source line SL.

[0055] In the above Figures 1 to 4 In a memory device, a plurality of memory cells and peripheral circuits may be formed in a main chip region of a wafer during a manufacturing process, and an overlay fine-tuning key for aligning a plurality of masks used in the manufacturing process may be formed in a scribe line region which is an edge region of the wafer.

[0056] Figure 5A and Figure 5B are a plan view and a cross-sectional view showing a memory device according to an embodiment of the present disclosure.

[0057] Reference Figure 5A The memory device 100 may be formed on a substrate defined as a main chip region MainChip_R, a scribe line region SL_R, and a chip protection region CG_R located between the main chip region MainChip_R and the scribe line region SL_R.

[0058] A plurality of memory cells and a peripheral circuit for driving the plurality of memory cells may be formed on the substrate of the main chip region Main Chip_R.

[0059] An overlay fine tuning key for aligning a plurality of masks used in a manufacturing process of a memory device may be provided on the scribe line region SL_R.

[0060] A plurality of chip guards Chip Guard may be disposed in the chip protection region CG_R between the main chip region Main Chip_R and the scribe line region SL_R, and a buffer slit Buffer Slit may be formed in a space between the plurality of chip guards Chip Guard.

[0061] The plurality of chip guards may be arranged in a line shape parallel to each other. The plurality of chip guards may prevent cracks from spreading in the direction of the main chip region Main Chip_R during a sawing process of cutting the scribe line region SL_R, and may prevent impurities from flowing through an oxide layer exposed through a cutting surface.

[0062] The buffer slit Buffer Slit may relieve stress generated in the main chip region Main Chip_R during a manufacturing process and may suppress misalignment of an overlay fine tuning key formed on the scribe line region SL_R due to the stress generated in the main chip region MainChip_R.

[0063] Reference Figure 5B In the main chip region MainChip_R, a plurality of cell plugs CP are formed, and the plurality of cell plugs CP pass through a stack ST in which a plurality of interlayer insulating layers 12 and a plurality of plate electrodes 41 serving as word lines are alternately stacked. The plurality of cell plugs CP may include a memory layer 21, a channel layer 22, and a core insulating layer 23. A slit pattern 27 that electrically separates the plurality of plate electrodes 41 by passing through the stack ST may be formed between the plurality of cell plugs CP. The slit pattern 27 may correspond to the above Figure 3 or Figure 4 The second slit S2.

[0064] In the chip protection region CG_R adjacent to the main chip region Main Chip_R, a stack ST in which sacrificial layers 11 and interlayer insulating layers 12 are alternately stacked and a plurality of chip protection Chip Guards passing through the stack ST may be provided. The plurality of chip protection Chip Guards may be formed together during a process of forming a contact plug (not shown) of the main chip region Main Chip_R. In addition, a buffer slit Buffer Slit passing through the stack ST may be provided in a space between the plurality of chip protection Chip Guards, and the buffer slit Buffer Slit may be formed together during a process of forming a slit pattern 27 of the main chip region Main Chip_R. In addition, the buffer slit Buffer Slit and the plurality of chip protection Chip Guards may be connected to each other through a plurality of plate electrodes 41.

[0065] Figure 6 is a plan view showing a memory device according to another embodiment of the present disclosure.

[0066] In the above Figure 5A , an example is illustrated in which a plurality of chip guards are provided in the chip protection region CG_R and the plurality of chip guards are provided in a parallel line shape.

[0067] According to an embodiment of the present disclosure, a plurality of chip guards may be formed in various shapes. Figure 6, each of the plurality of chip guards may have a concave-convex portion and may be arranged to extend in one direction. The concave portion of each of the plurality of chip guards may be arranged to face the convex portion of the adjacent chip guard. Compared with a line shape, the plurality of chip guards having concave-convex portions may disperse external stress.

[0068] 7A to 7H are a plan view and a cross-sectional view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0069] In an embodiment of the present disclosure, a process of forming a plurality of cell plugs and a chip protection pattern on a substrate region including a main chip region MainChip_R and a chip protection region CG_R is described. The main chip region Main Chip_R and the chip protection region CG_R may be adjacent to each other, and the chip protection region CG_R may be defined as an area between the main chip region Main Chip_R and a scribe line region.

[0070] Reference Fig. 7A , a stack ST may be formed in which sacrificial layers 11 and interlayer insulating layers 12 are alternately stacked on a substrate (not shown) region including a main chip region MainChip_R and a chip protection region CG_R. The stack ST may be formed on a substrate including a peripheral circuit.

[0071] The sacrificial layer 11 may be formed of a material different from that of the interlayer insulating layer 12. For example, the interlayer insulating layer 12 may be formed of an oxide such as a silicon oxide layer. The sacrificial layer 11 may be formed of a material having an etching rate different from that of the interlayer insulating layer 12. For example, the sacrificial layer 11 may be formed of a nitride such as a silicon nitride layer.

[0072] Thereafter, a region OP1 where a cell plug is to be formed may be formed using the first hard mask pattern 13 , the region OP1 being in an opening of the first hard mask pattern 13 in the main chip region MainChip_R on the stack ST.

[0073] Reference Figure 7B , an etching process using the first hard mask pattern 13 may be performed to form a plurality of holes H1 passing through the stack ST on the main chip region Main Chip_R. Thereafter, a cell plug CP may be formed in the hole H1. The cell plug CP may be formed by sequentially stacking a memory layer 21, a channel layer 22, and a core insulating layer 23 on the sidewall of the hole H1.

[0074] The memory layer 21 may be formed as a plurality of layers. For example, the memory layer 21 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer. The blocking insulating layer may be formed on the sidewalls of the hole H1. The blocking insulating layer may include an oxide layer capable of blocking charges. As an embodiment, the blocking insulating layer may be formed of Al2O3. The charge storage layer may be formed on the sidewalls of the blocking insulating layer. The charge storage layer may be formed of a charge capture layer, may be formed of a material layer having conductive nanodots, or may be formed of a phase change material layer. For example, the charge storage layer may use Fowler-Nordheim tunneling to store changed data. To this end, the charge storage layer may be formed of a silicon nitride layer capable of charge capture. The tunnel insulating layer may be formed on the sidewalls of the charge storage layer. The tunnel insulating layer may be formed of a silicon oxide layer capable of charge tunneling.

[0075] The channel layer 22 may include a semiconductor layer. As an embodiment, the channel layer 22 may include silicon.

[0076] The core insulating layer 23 may be formed to fill the central region of the hole H1. The core insulating layer may be formed of an oxide layer.

[0077] Reference Figure 7C , the upper portion of the cell plug CP may be etched to a predetermined thickness. For example, the upper portion of the cell plug CP may be etched to a predetermined thickness so that the height of the upper surface of the cell plug CP1 is higher than the upper surface of the sacrificial layer 11 located at the highest portion and is equal to or lower than the height of the upper surface of the interlayer insulating layer 12 located at the highest portion.

[0078] Thereafter, the first hard mask pattern 13 may be removed, and a region OP2 where a chip protection pattern is to be formed may be formed using the second hard mask pattern 24 in an opening of the second hard mask pattern 24 in the chip protection region CG_R on the stack ST.

[0079] At least two trenches T1 and T2 passing through the stack ST in the chip protection region CG_R may be formed by performing an etching process using the second hard mask pattern 24. The at least two trenches T1 and T2 may be formed to be spaced apart from each other by a predetermined distance.

[0080] Contact plugs (not shown) may be disposed under at least two trenches T1 and T2 passing through the stack ST in the chip protection region CG_R. That is, at least two trenches T1 and T2 may be formed such that upper portions of contact plugs formed on the substrate of the chip protection region CG_R are exposed.

[0081] Fig.7D Yes Execution Figure 7C A plan view of a memory device showing the process steps. Fig.7D, at least two trenches T1 and T2 may be spaced apart from each other by a predetermined distance in the chip protection region CG_R and may be disposed in parallel with each other. At least two trenches T1 and T2 may be disposed in a line shape parallel to each other.

[0082] In the embodiment of the present disclosure, an embodiment in which at least two trenches T1 and T2 are formed in parallel line shapes is shown and described. Figure 6 As shown, when a plurality of chip protections are formed to have concave-convex portions, at least two trenches T1 and T2 may be formed to have concave-convex portions. That is, at least two trenches T1 and T2 may extend in one direction, and the concave portion of the first trench T1 may be formed to face the convex portion of the adjacent second trench T2.

[0083] Figure 7F Yes Execution Fig. 7E A plan view of a memory device showing the process steps. Fig. 7E and Figure 7F At least two trenches formed in the chip protection region CG_R are filled with a sacrificial material layer to form at least two sacrificial patterns 25. The sacrificial material layer may be an oxide layer.

[0084] Thereafter, a third hard mask pattern 26 may be formed on the main chip region MainChip_R and the chip protection region CG_R. The third hard mask pattern 26 may be formed so that the region of the second slit S2 formed between the cell plugs CP and formed on the main chip region MainChip_R is opened. In addition, the third hard mask pattern 26 may be formed so that the space between at least two sacrificial patterns 25 formed in the chip protection region CG_R is opened.

[0085] Thereafter, an etching process using the third hard mask pattern 26 may be performed to form a second slit S2 between the cell plugs CP formed on the main chip region MainChip_R. The second slit S2 corresponds to Figure 3 or Figure 4 In addition, during the etching process for forming the second slit S2, the space between the at least two sacrificial patterns 25 of the chip protection region CG_R may be etched to form a third slit S3.

[0086] Thereafter, a heat treatment process may be performed to improve etching damage generated due to the etching process, and stress may be generated at each of the at least two sacrificial patterns 25 by expanding in a direction opposite to the stress direction generated in the main chip region Main Chip_R and the chip protection region CG_R during the heat treatment process, that is, a direction of the main chip region and a direction of a scribe line region (not shown). Therefore, each of the at least two sacrificial patterns 25 may relieve stress generated in the main chip region and the scribe line region.

[0087] Reference Figure 7G , the sacrificial layer on the main chip region Main Chip_R exposed by the second slit S2 may be removed. In addition, the sacrificial layer between the sacrificial patterns 25 may be removed by the third slit S3.

[0088] Thereafter, the plate electrode 41 may be formed by filling the space where the sacrificial layer is removed with a conductive material of the word line.

[0089] Thereafter, a slit pattern 27 that insulates the plate electrodes 41 from each other may be formed by filling an insulating layer in the second slit S2. The slit pattern 27 may be formed of an oxide layer. In addition, a buffer slit 28 may be formed by filling a polysilicon layer in the third slit S3. As another example, the buffer slit 28 may be formed by filling an insulating layer in the third slit S3. In this case, the buffer slit 28 and the slit pattern 27 may be formed together by the same process.

[0090] Reference Figure 7H , at least two sacrificial patterns of the chip protection region CG_R may be removed. Thereafter, a chip protection pattern 29 may be formed by filling the space where the at least two sacrificial patterns are removed with a conductive material. The chip protection patterns 29 adjacent to each other may be electrically connected to each other through the plate electrode 41 and the buffer slit S3.

[0091] According to the above-described embodiments of the present disclosure, a plurality of chip protection patterns may be formed in a chip protection region between a main chip region and a scribe region, and a buffer slit may be formed between the chip protection patterns. Therefore, the stress generated in the main chip region during the manufacturing process may be prevented from diffusing to the scribe region. In addition, the stress generated in the main chip region may be relieved by filling an oxide layer in a groove for forming the plurality of chip protection patterns.

[0092] Figure 8 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0093] Reference Figure 8 , a memory system 1000 according to an embodiment of the present disclosure includes a memory device 1200 and a controller 1100 .

[0094] The memory device 1200 is used to store data information having various data types such as text, graphics, and software codes. The memory device 1200 may be a non-volatile memory and may be configured according to the above reference. 7A to 7H Since the structure of the memory device 1200 and the method of manufacturing the memory device 1200 are the same as those described above, detailed descriptions thereof are omitted.

[0095] The controller 1100 may be connected to the host and the memory device 1200 and configured to access the memory device 1200 in response to a request from the host. For example, the controller 1100 may be configured to control read operations, write operations, erase operations, background operations, etc. of the memory device 1200.

[0096] The controller 1100 may include a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code circuit 1140 , a memory interface 1150 , and the like.

[0097] Here, the RAM 1110 may be used as an operation memory of the CPU 1120, a cache memory between the memory device 1200 and the host, a buffer memory between the memory device 1200 and the host, etc. For reference, the RAM 1110 may be replaced by a static random access memory (SRAM), a read-only memory (ROM), etc.

[0098] The CPU 1120 may be configured to control the overall operation of the controller 1100. For example, the CPU 1120 may be configured to operate firmware such as a flash translation layer (FTL) stored in the RAM 1110.

[0099] The host interface 1130 may be configured to interface with the host. For example, the controller 1100 may communicate with the host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol.

[0100] The ECC circuit 1140 is configured to detect and correct an error included in data read from the memory device 1200 using an error correction code (ECC).

[0101] The memory interface 1150 may be configured to interface with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface.

[0102] For reference, the controller 1100 may further include a buffer memory (not shown) for temporarily storing data. Here, the buffer memory may be used to temporarily store data transmitted to an external device through the host interface 1130 or temporarily store data transmitted from the memory device 1200 through the memory interface 1150. In addition, the controller 1100 may further include a ROM storing code data for interfacing with the host.

[0103] As described above, since the memory system 1000 includes the memory device 1200 having improved integration and improved characteristics, the integration and characteristics of the memory system 1000 may also be improved.

[0104] Fig. 9 1 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above descriptions are omitted.

[0105] Reference Fig. 9 , the memory system 1000' may include a memory device 1200' and a controller 1100. In addition, the controller 1100 may include a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, and the like.

[0106] The memory device 1200' may be a non-volatile memory and may be configured as described above with reference to 7A to 7H Since the structure of the memory device 1200' and the method of manufacturing the memory device 1200' are the same as those described above, a detailed description thereof will be omitted.

[0107] In addition, the memory device 1200' may be a multi-chip package configured by a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups, and the plurality of groups may be configured to communicate with the controller 1100 through the first channel CH1 to the kth channel CHk. In addition, the memory chips belonging to one group may be configured to communicate with the controller 1100 through a common channel. For reference, the memory system 1000' may be modified so that one memory chip is connected to one channel.

[0108] As described above, since the memory system 1000' includes the memory device 1200' having improved integration and improved characteristics, the integration and characteristics of the memory system 1000' may also be improved. Specifically, by configuring the memory device 1200' in a multi-chip package, the data storage capacity of the memory system 1000' may be increased and the driving speed may be improved.

[0109] Fig.10 Detailed description of the present invention is omitted.

[0110] Reference Fig.10 , the computing system 2000 may include a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, and the like.

[0111] The memory device 2100 may store data provided through the user interface 2400, data processed by the CPU 2200, and the like. In addition, the memory device 2100 may be electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, and the like through the system bus 2600. For example, the memory device 2100 may be connected to the system bus 2600 through a controller (not shown) or may be directly connected to the system bus 2600. When the memory device 2100 is directly connected to the system bus 2600, the function of the controller may be performed by the CPU 2200, the RAM 2300, and the like.

[0112] Here, the memory device 2100 may be a nonvolatile memory and may be configured according to the above reference. 7A to 7H Since the structure of the memory device 2100 and the method of manufacturing the memory device 2100 are the same as those described above, detailed descriptions thereof are omitted.

[0113] In addition, the memory device 2100 may include Fig. 9 A multi-chip package of multiple memory chips is described.

[0114] A computing system having such a configuration may be a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder and a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a remote information network, an RFID device, etc.

[0115] As described above, since the computing system 2000 includes the memory device 2100 having improved integration and improved characteristics, the characteristics of the computing system 2000 may also be improved.

[0116] Fig.11 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.

[0117] Reference Fig.11 , the computing system 3000 may include a software layer including an operating system 3200 , an application 3100 , a file system 3300 , a translation layer 3400 , etc. In addition, the computing system 3000 includes a hardware layer such as a memory device 3500 .

[0118] The operating system 3200 may be used to manage software and hardware resources of the computing system 3000 and control program execution of the central processing unit. The application 3100 may be various application programs executed on the computing system 3000 and may be a utility program executed by the operating system 3200.

[0119] The file system 3300 refers to a logical structure for managing data, files, etc. existing in the computing system 3000, and organizes files or data to be stored in the memory device 3500 according to rules. The file system 3300 may be determined according to the operating system 3200 used in the computing system 3000. For example, when the operating system 3200 is a Windows system of Microsoft Corporation, the file system 3300 may be a file allocation table (FAT), an NT file system (NTFS), etc. In addition, when the operating system 3200 is a Unix / Linux system, the file system 3300 may be an extended file system (EXT), a Unix file system (UFS), a journaled file system (JFS), etc.

[0120] Although the operating system 3200 , the application 3100 , and the file system 3300 are illustrated as separate blocks in this figure, the application 3100 and the file system 3300 may be included in the operating system 3200 .

[0121] In response to a request from the file system 3300, the translation layer 3400 may translate an address in a form suitable for the memory device 3500. For example, the translation layer 3400 may translate a logical address generated by the file system 3300 into a physical address of the memory device 3500. Here, mapping information of the logical address and the physical address may be stored in an address translation table. For example, the translation layer 3400 may be a flash translation layer (FTL), a universal flash link layer (ULL), etc.

[0122] The memory device 3500 may be a non-volatile memory and may be configured according to the above reference. 7A to 7H Since the structure of the memory device 3500 and the method of manufacturing the memory device 3500 are the same as those described above, a detailed description thereof will be omitted.

[0123] The computing system 3000 having such a configuration may be divided into an operating system layer executed in an upper region and a controller layer executed in a lower region. Here, the application 3100, the operating system 3200, and the file system 3300 may be included in the operating system layer and may be driven by an operating memory of the computing system 3000. In addition, the conversion layer 3400 may be included in the operating system layer or in the controller layer.

[0124] As described above, since the computing system 3000 includes the memory device 3500 having improved integration and improved characteristics, the characteristics of the computing system 3000 may also be improved.

[0125] Although the technical spirit of the present disclosure is specifically described according to the above preferred embodiments, it should be noted that the above embodiments are for description rather than limitation. In addition, ordinary technicians in the technical field of the present disclosure can understand that various embodiments are possible within the scope of the technical spirit of the present disclosure.

[0126] CROSS-REFERENCE TO RELATED APPLICATIONS

[0127] This application claims the priority of Korean Patent Application No. 10-2021-0028918 filed on March 4, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: Main chip area; a chip protection area, the chip protection area being arranged adjacent to the main chip area; a plurality of chip protection patterns, wherein the plurality of chip protection patterns are formed in the chip protection region; as well as a buffer slit formed in a space between the plurality of chip protection patterns, wherein a plurality of plate electrodes and a plurality of interlayer insulating layers are alternately stacked in spaces between the plurality of chip protection patterns in the chip protection region, and a plurality of sacrificial layers and the plurality of interlayer insulating layers are alternately stacked in other spaces in the chip protection region, and The chip protection patterns adjacent to each other are electrically connected to each other through the plate electrode and the buffer slit.

2. The memory device according to claim 1, wherein: The plurality of chip protection patterns have line shapes parallel to each other.

3. The memory device according to claim 1, wherein: Each of the plurality of chip protection patterns has a concavo-convex portion and extends in one direction.

4. The memory device according to claim 3, wherein: The concave portion of each of the plurality of chip protection patterns faces the convex portion of an adjacent chip protection pattern.

5. The memory device according to claim 1, further comprising: a first stack, wherein the plurality of plate electrodes and the plurality of interlayer insulating layers are alternately stacked on the main chip region; as well as A plurality of unit plugs are provided, and the plurality of unit plugs pass through the first stack in a vertical direction.

6. The memory device according to claim 5, wherein: Each of the plurality of chip protection patterns passes through a portion in the chip protection region in a vertical direction where a stack in which the plurality of plate electrodes and the plurality of interlayer insulating layers are alternately stacked and a stack in which the plurality of sacrificial layers and the plurality of interlayer insulating layers are alternately stacked are adjacent to each other.

7. The memory device according to claim 6, wherein: The plurality of chip protection patterns are spaced apart from each other in a horizontal direction in the chip protection region.

8. The memory device according to claim 7, wherein: The buffer slit passes through the plurality of plate electrodes and the plurality of interlayer insulating layers stacked in the space between the plurality of chip protection patterns.

9. The memory device according to claim 8, wherein: The buffer slit is formed of a polysilicon layer.

10. A method of manufacturing a memory device, the method comprising the steps of: forming a stack of a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked on a substrate in a main chip region, a scribe line region, and a chip protection region between the main chip region and the scribe line region; forming a plurality of trenches through the stack in the chip protection region; forming a sacrificial pattern in the plurality of trenches; forming slits through the stack in spaces between the plurality of grooves; removing the sacrificial layer exposed through the slit and forming a plurality of plate electrodes in a space where the sacrificial layer is removed; removing the sacrificial pattern and forming a chip protection pattern in a space where the sacrificial pattern is removed; as well as forming a buffer slit in the slit, The chip protection patterns adjacent to each other are electrically connected to each other through the plate electrode and the buffer slit.

11. The method according to claim 10, wherein: The sacrificial pattern is formed of an oxide layer.

12. The method according to claim 10, further comprising the steps of: After forming the slits, a heat treatment process is performed, wherein the sacrificial pattern generates stress in directions of the main chip region and the scribe line region during the heat treatment process.

13. The method according to claim 10, wherein: The chip protection pattern is formed of a metal layer.

14. The method according to claim 10, wherein: The buffer slit is formed of a polysilicon layer.

15. A method of manufacturing a memory device, the method comprising the steps of: forming a stack in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked on a substrate in a main chip region and a chip protection region; forming a plurality of trenches through the stack in the chip protection region; forming a sacrificial pattern in the plurality of trenches; forming a plurality of first slits through the stack on the main chip region and forming second slits through the stack in spaces between the plurality of grooves; removing the sacrificial layer exposed by the first slit and the second slit, and then forming a plurality of plate electrodes in the space where the sacrificial layer is removed; After removing the sacrificial pattern, forming a plurality of chip protection patterns by filling each of the plurality of trenches with a conductive material; as well as forming a buffer slit in the second slit, The chip protection patterns adjacent to each other are electrically connected to each other through the plate electrode and the buffer slit.

16. The method according to claim 15, wherein: The sacrificial pattern is formed of an oxide layer.

17. The method according to claim 15, further comprising the steps of: After forming the first slit and the second slit, performing a heat treatment process, The sacrificial pattern generates stress in the direction of the main chip region during the thermal treatment process.

18. The method according to claim 15, wherein: The chip protection pattern is formed of a metal layer.

19. The method according to claim 15, wherein: The buffer slit is formed of a polysilicon layer.

20. The method according to claim 15, wherein: The plurality of grooves are formed to have a smooth line shape parallel to each other in one direction in which each groove extends or to have a line shape with concavo-convex portions.

Images