Light-emitting diode and light-emitting diode preparation method

Abstract

The invention provides a light emitting diode and a light emitting diode preparation method. The light-emitting diode comprises a substrate, an epitaxial structure and a reflecting layer, the epitaxial structure is of a step structure, and the epitaxial structure is further provided with an isolation groove extending to the substrate; the reflecting layer covers the step structure and one part of the isolation groove, and the other part of the isolation groove is exposed out of the substrate. The reflecting layer only covers part of the area of the isolation groove, the other part of the area is not covered by the reflecting layer to expose the substrate, and the scribing of the light-emitting diode is carried out at the position of the substrate not covered by the reflecting layer, so that the problem that the reflecting layer is easy to damage and even fall off in the scribing process is avoided, and the scribing efficiency is improved. And the stability and the brightness of the light-emitting diode are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for preparing the light-emitting diode. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor device that can emit light. It has the advantages of energy saving, high brightness, high durability, long life and light weight. It has been widely used in two major fields: backlight display and direct display.

[0003] The related art provides a light emitting diode, the structure of which includes a substrate, an epitaxial structure, a reflective layer and the like.

[0004] In the manufacturing process of the above-mentioned light-emitting diodes, the chips need to be separated by dicing, and the reflective layer is easily damaged or even falls off during the dicing process. Summary of the invention

[0005] The embodiments of the present disclosure provide a light emitting diode and a method for manufacturing a light emitting diode, which can avoid the problem that the reflective layer is easily damaged or even falls off during the dicing process. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a light emitting diode, the light emitting diode comprising: a substrate, an epitaxial structure and a reflective layer;

[0007] The epitaxial structure is a step structure, and an isolation groove extending to the substrate is formed in the epitaxial structure; the reflective layer covers the step structure and a portion of the isolation groove, and another portion of the isolation groove is exposed from the substrate.

[0008] Optionally, a width of a region of the isolation trench that exposes the substrate is 6-8 μm.

[0009] Optionally, the substrate is a patterned sapphire substrate with a layer of SiO2 deposited on the surface.

[0010] Optionally, the reflective layer is a DBR structure.

[0011] Optionally, the light-emitting diode further comprises a current blocking layer, a transparent conductive layer, a first electrode and a second electrode; the current blocking layer and the transparent conductive layer are located on the top surface of the step structure, and the transparent conductive layer covers the current blocking layer;

[0012] The first electrode is located on the transparent conductive layer, and the second electrode is located on the bottom surface of the step structure.

[0013] Optionally, the light-emitting diode further includes a first electrode pad and a second electrode pad; the first electrode pad is electrically connected to the first electrode through the reflective layer, and the second electrode pad is electrically connected to the second electrode through the reflective layer.

[0014] In another aspect, an embodiment of the present disclosure provides a method for preparing a light emitting diode, the method comprising:

[0015] Fabricating an epitaxial structure on a substrate, wherein the epitaxial structure is a step structure and is further provided with an isolation groove extending to the substrate;

[0016] A reflective layer is manufactured, wherein the reflective layer covers the step structure and a portion of the isolation groove, and another portion of the isolation groove exposes the substrate.

[0017] Optionally, a width of a region of the isolation trench that exposes the substrate is 6-8 μm.

[0018] Optionally, the substrate is a patterned sapphire substrate with a layer of SiO2 deposited on the surface.

[0019] Optionally, the manufacturing of the reflective layer includes:

[0020] Manufacturing a DBR stack, wherein the DBR stack covers the step structure and the isolation groove;

[0021] The DBR stack is patterned to remove a portion of the DBR stack located in the isolation groove, and a first electrode through hole and a second electrode through hole are formed on the DBR stack to obtain the reflective layer.

[0022] Optionally, the method further comprises:

[0023] A current blocking layer, a transparent conductive layer, a first electrode and a second electrode are manufactured. The current blocking layer and the transparent conductive layer are located on the top surface of the step of the step structure, and the transparent conductive layer covers the current blocking layer. The first electrode is located on the transparent conductive layer, and the second electrode is located on the bottom surface of the step of the step structure.

[0024] Optionally, the method further comprises:

[0025] A first electrode pad and a second electrode pad are manufactured; the first electrode pad is electrically connected to the first electrode through the first electrode through hole, and the second electrode pad is electrically connected to the second electrode through the second electrode through hole.

[0026] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0027] In the embodiment of the present disclosure, the reflective layer only covers a portion of the isolation groove, while the other portion is not covered by the reflective layer and the substrate is exposed. When the light-emitting diode is diced, it is also performed on the substrate not covered by the reflective layer, thereby avoiding the problem of damage or even falling off of the reflective layer during the dicing process, thereby improving the stability and brightness of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0030] Figure 2 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0031] Figure 3 This is a flow chart of another method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0032] The reference numerals are as follows:

[0033] 10: substrate; 20: epitaxial structure; 30: reflective layer; 40: current blocking layer; 50: transparent conductive layer; 60: first electrode; 70: second electrode; 80: first electrode pad; 90: second electrode pad;

[0034] 101: first semiconductor layer; 102: active layer; 103: second semiconductor layer; 111: step structure; 112: isolation trench. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0036] Figure 1 A schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 The light emitting diode includes: a substrate 10, an epitaxial structure 20 and a reflective layer 30.

[0037] The epitaxial structure 20 is a step structure 111 , and the epitaxial structure 20 is also provided with an isolation groove (ISO) 112 extending to the substrate 10 ; the reflective layer 30 covers the step structure 111 and a portion of the isolation groove 112 , and another portion of the isolation groove 112 is exposed from the substrate 10 .

[0038] In the embodiment of the present disclosure, the reflective layer only covers a portion of the isolation groove, while the other portion is not covered by the reflective layer and the substrate is exposed. When the light-emitting diode is diced, it is also performed on the substrate not covered by the reflective layer, thereby avoiding the problem of damage or even falling off of the reflective layer during the dicing process, thereby improving the stability and brightness of the light-emitting diode.

[0039] like Figure 1 As shown, the light-emitting diode also includes a current blocking layer 40, a transparent conductive layer 50, a first electrode 60 and a second electrode 70; the current blocking layer 40 and the transparent conductive layer 50 are located on the top surface of the step of the step structure 111, and the transparent conductive layer 50 covers the current blocking layer 40.

[0040] The first electrode 60 is located on the transparent conductive layer 50 , and the second electrode 70 is located on the bottom surface of the step structure 111 .

[0041] In this implementation, by providing a current blocking layer and a transparent conductive layer, current expansion can be better achieved and luminous efficiency can be improved.

[0042] like Figure 1 As shown, the light emitting diode further includes a first electrode pad 80 and a second electrode pad 90 ; the first electrode pad 80 is electrically connected to the first electrode 60 through the reflective layer 30 , and the second electrode pad 90 is electrically connected to the second electrode 70 through the reflective layer 30 .

[0043] In the embodiment of the present disclosure, the substrate 10 may be a sapphire substrate.

[0044] Exemplarily, the substrate 10 is a patterned sapphire substrate (PSS) with a layer of SiO 2 deposited on the surface, that is, SiO 2 PSS.

[0045] When the SiO2 PSS is made, a layer of SiO2 is deposited on the surface of the sapphire substrate, and then the substrate is processed in a graphic manner. The purpose is to improve the conversion efficiency of light through the refraction of different oxide materials, thereby improving the brightness. However, the substrate is sensitive to the laser used for slicing during cutting, so the cutting power of the slicing is often adjusted during the processing to reduce the damage to the side wall after the laser reflection. After the cutting power of the slicing is adjusted, some chips cannot be completely slit by the laser and need to be forcibly slit by the external force of the slicing machine. Due to the bonding force between SiO2 and the sapphire substrate, the DBR above the SiO2 at the slicing path often has invisible hidden injuries. For example, after the DBR on the side wall of the slicing path falls off, the side wall loses its protective effect, which is easy to cause leakage and metal migration caused by the exposure of the side wall during subsequent use. The solution provided by the embodiment of the present disclosure solves the above problems, so that while using SiO2 PSS to improve brightness, the problem of DBR falling off caused by slicing is avoided.

[0046] In the embodiment of the present disclosure, the epitaxial structure 10 includes a first semiconductor layer 101 , an active layer 102 and a second semiconductor layer 103 .

[0047] The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 are sequentially stacked on the substrate 10. The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 are provided with a step structure 111 extending to the first semiconductor 102, that is, the step surface is located in the first semiconductor layer 101. The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 are also provided with an isolation groove 112 extending to the surface of the substrate 10. The current blocking layer 40 is located on the surface of the second semiconductor layer 103.

[0048] In the embodiment of the present disclosure, the first semiconductor layer 101 may be an N-type semiconductor layer, and the second semiconductor layer 103 may be a P-type semiconductor layer.

[0049] In the embodiment of the present disclosure, the active layer 102 may be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.

[0050] For example, the first semiconductor layer 101 may be an N-type GaN layer, and the second semiconductor layer 103 may be a P-type GaN layer.

[0051] In other embodiments, the first semiconductor layer 101 may be a P-type semiconductor layer, and the second semiconductor layer 103 may be an N-type semiconductor layer.

[0052] In the embodiment of the present disclosure, the reflective layer 30 may be a distributed Bragg reflector (DBR) layer.

[0053] Exemplarily, the DBR layer may include a plurality of periodically alternately stacked Ti3O5 layers and SiO2 layers.

[0054] In the embodiment of the present disclosure, the current blocking layer 40 may be an AlGaN or SiO 2 layer.

[0055] In a possible implementation of the present disclosure, the region of the isolation trench 112 that exposes the substrate 10 is a rectangular ring region.

[0056] In the embodiment of the present disclosure, the width A of the region of the isolation trench 112 that exposes the substrate 10 is 6-8 μm.

[0057] In this implementation, by setting a region with a width of 6 to 8 μm not covered by the reflective layer 30 , the requirement of not damaging the reflective layer during dicing can be met, while the design and distribution of the light-emitting diodes will not be affected by the excessive width of the region.

[0058] Exemplarily, the width A of the region of the isolation trench 112 that exposes the substrate 10 is 6 μm.

[0059] In other possible implementations, the region of the isolation trench 112 that exposes the substrate 10 is in other shapes, such as a ring.

[0060] Exemplarily, the current blocking layer 40 is an AlGaN current blocking layer.

[0061] In the embodiment of the present disclosure, the transparent conductive layer 50 may be an indium tin oxide (ITO) layer. ITO has good transparency and conductivity and can conduct current to form an electrical connection while allowing light to pass through.

[0062] In the embodiment of the present disclosure, the first electrode 60 and the second electrode 70 may be AuGe / Au electrodes or AuBe / Au electrodes.

[0063] Exemplarily, the first electrode is an AuBe / Au electrode, and the second electrode is an AuGe / Au electrode.

[0064] In the embodiment of the present disclosure, the first electrode pad 80 and the second electrode pad 90 may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt, Au and AuSn.

[0065] Exemplarily, the first electrode pad 80 and the second electrode pad 90 are stacked layers of Cr, Al, AlCu, Ti, Ni, Pt, Au, and AuSn.

[0066] It is worth noting that in the embodiments of the present disclosure, structures may be selectively increased or decreased based on the structure of the above-mentioned light emitting diode, and the present disclosure does not impose any limitation on this.

[0067] Figure 2 A flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure. Figure 2 The method steps include:

[0068] S11, fabricating an epitaxial structure on a substrate, wherein the epitaxial structure is a step structure and is further provided with an isolation groove extending to the substrate.

[0069] In the embodiment of the present disclosure, the substrate may be a sapphire substrate.

[0070] The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer.

[0071] The first semiconductor layer, the active layer and the second semiconductor layer are stacked on the substrate in sequence. The first semiconductor layer, the active layer and the second semiconductor layer are provided with a step structure extending to the first semiconductor, that is, the step surface is located in the first semiconductor layer. The first semiconductor layer, the active layer and the second semiconductor layer are also provided with an isolation groove extending to the surface of the substrate.

[0072] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type semiconductor layer, and the second semiconductor layer may be a P-type semiconductor layer.

[0073] In the embodiment of the present disclosure, the active layer may be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.

[0074] For example, the first semiconductor layer may be an N-type GaN layer, and the second semiconductor layer may be a P-type GaN layer.

[0075] In other embodiments, the first semiconductor layer may be a P-type semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer.

[0076] S12, manufacturing a reflective layer, wherein the reflective layer covers the step structure and a portion of the isolation groove, and another portion of the isolation groove exposes the substrate.

[0077] In the embodiment of the present disclosure, the reflective layer may be a DBR layer.

[0078] Exemplarily, the DBR layer may include a plurality of periodically alternately stacked Ti3O5 layers and SiO2 layers.

[0079] In the embodiment of the present disclosure, the reflective layer only covers a portion of the isolation groove, while the other portion is not covered by the reflective layer and the substrate is exposed. When the light-emitting diode is diced, it is also performed on the substrate not covered by the reflective layer, thereby avoiding the problem of damage or even falling off of the reflective layer during the dicing process, thereby improving the stability and brightness of the light-emitting diode.

[0080] Figure 3 Another light emitting diode manufacturing method provided by the present disclosure is a flow chart. Figure 3 The method steps include:

[0081] S21. Forming a first semiconductor layer, an active layer, and a second semiconductor layer in sequence on a substrate, wherein the first semiconductor layer, the active layer, and the second semiconductor layer constitute an epitaxial structure.

[0082] The substrate may be a sapphire substrate.

[0083] Exemplarily, the substrate 10 is PSS with a layer of SiO 2 deposited on the surface, that is, SiO 2 PSS.

[0084] When the SiO2 PSS is made, a layer of SiO2 is deposited on the surface of the sapphire substrate, and then the substrate is processed in a graphic manner. The purpose is to improve the conversion efficiency of light through the refraction of different oxide materials, thereby improving the brightness. However, the substrate is sensitive to the laser used for slicing during cutting, so the cutting power of the slicing is often adjusted during the processing to reduce the damage to the side wall after the laser reflection. After the cutting power of the slicing is adjusted, some chips cannot be completely slit by the laser and need to be forcibly slit by the external force of the slicing machine. Due to the bonding force between SiO2 and the sapphire substrate, the DBR above the SiO2 at the slicing path often has invisible hidden injuries. For example, after the DBR on the side wall of the slicing path falls off, the side wall loses its protective effect, which is easy to cause leakage and metal migration caused by the exposure of the side wall during subsequent use. The solution provided by the embodiment of the present disclosure solves the above problems, so that while using SiO2 PSS to improve brightness, the problem of DBR falling off caused by slicing is avoided.

[0085] In one example, step S21 includes:

[0086] The first step is to make the first semiconductor layer.

[0087] In the embodiment of the present disclosure, the first semiconductor layer is an N-type GaN layer, such as an InGaN / GaN multi-quantum well layer.

[0088] The second step is to make the active layer.

[0089] In the embodiment of the present disclosure, the active layer is a multi-quantum well layer.

[0090] The third step is to make the second semiconductor layer.

[0091] In the embodiment of the present disclosure, the second semiconductor layer is a P-type GaN layer.

[0092] In the embodiment of the present disclosure, the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked on the substrate.

[0093] In the disclosed embodiment, VeecoK465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition (MOCVD)) equipment or AIXTRON metal organic compound chemical vapor deposition equipment can be used to achieve the growth of the above semiconductor layer. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as a carrier gas, high-purity NH3 is used as an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) are used as gallium sources, trimethyl indium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethylaluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl) magnesium (CP2Mg) is used as a P-type dopant.

[0094] It is worth noting that other equipment may also be used to manufacture the semiconductor layer, and the present disclosure does not impose any limitation on this.

[0095] S22, performing graphic processing on the epitaxial structure to form a step structure and an isolation groove.

[0096] In the disclosed embodiment, the first semiconductor layer, the active layer and the second semiconductor layer are in a step structure extending to the first semiconductor, that is, the step surface is located in the first semiconductor layer. The first semiconductor layer, the active layer and the second semiconductor layer are also provided with an isolation groove, and the bottom of the isolation groove is located in the substrate.

[0097] Exemplarily, step S22 may include:

[0098] A patterned mask layer is formed on the surface of the second semiconductor layer; under the protection of the mask layer, the epitaxial structure is etched to form a step extending to the first semiconductor layer and an isolation groove extending to the substrate.

[0099] S23, manufacturing a current blocking layer on the epitaxial structure, wherein the current blocking layer is located on the top surface of the step of the step structure.

[0100] In the embodiment of the present disclosure, the current blocking layer may be an AlGaN or SiO2 layer.

[0101] Exemplarily, the current blocking layer is an AlGaN current blocking layer.

[0102] Exemplarily, step S23 may include:

[0103] An electron beam evaporation device is used to evaporate a current blocking layer on the top surface of the step structure.

[0104] S24, forming a transparent conductive layer on the current blocking layer, wherein the transparent conductive layer covers the current blocking layer.

[0105] In the embodiment of the present disclosure, the transparent conductive layer may be an ITO layer. ITO has excellent transparency and conductivity. It allows light to pass through while also conducting current to form an electrical connection.

[0106] Exemplarily, step S24 may include:

[0107] Depositing an ITO film; and patterning the ITO film to obtain an ITO conductive layer.

[0108] The ITO film may be formed by evaporation. Patterning the ITO film may include: spin coating photoresist; forming a mask pattern by exposure and development; and wet etching the ITO film under the protection of the mask pattern.

[0109] S25, manufacturing a first electrode and a second electrode, wherein the first electrode is located on the transparent conductive layer, and the second electrode is located on the bottom surface of the step structure.

[0110] Exemplarily, step S25 may include:

[0111] A first electrode is formed on the bottom surface of the step structure, and a second electrode is formed on the transparent conductive layer.

[0112] The first electrode and the second electrode can be manufactured by a deposition process.

[0113] In the embodiment of the present disclosure, the first electrode and the second electrode may be AuGe / Au electrodes or AuBe / Au electrodes.

[0114] Exemplarily, the first electrode is an AuBe / Au electrode, and the second electrode is an AuGe / Au electrode.

[0115] S26, making a DBR stack, wherein the DBR stack covers the first electrode and the second electrode, the step structure and the isolation groove.

[0116] In the embodiment of the present disclosure, the DBR stack may include a plurality of periodically alternately stacked Ti3O5 layers and SiO2 layers, wherein the DBR stack may be manufactured by an evaporation process.

[0117] S27, performing a patterning process on the DBR stack, removing a portion of the DBR stack located in the isolation groove, and forming a first electrode through hole and a second electrode through hole on the DBR stack to obtain a reflective layer.

[0118] In a possible implementation of the present disclosure, the region of the isolation trench 112 that exposes the substrate 10 is a rectangular ring region.

[0119] In the disclosed embodiment, after the above-mentioned patterning process, the width of the region of the isolation trench that exposes the substrate is 6-8 μm.

[0120] In this implementation, by setting a region with a width of 6 to 8 μm not covered by the reflective layer, the requirement of not damaging the reflective layer during dicing can be met, while the design and distribution of the light-emitting diodes will not be affected due to the excessive width of the region.

[0121] Exemplarily, a width A of a region of the isolation trench that exposes the substrate is 6 μm.

[0122] In other possible implementations, the region of the isolation trench 112 that exposes the substrate 10 is in other shapes, such as a ring.

[0123] In this implementation, the portion of the DBR stack located in the isolation groove is removed by etching in sequence, and the first electrode through hole and the second electrode through hole are formed on the DBR stack to obtain the reflective layer without adding additional process steps.

[0124] The first electrode through hole is connected to the first electrode, and the second electrode through hole is connected to the second electrode.

[0125] S28, manufacturing a first electrode pad and a second electrode pad.

[0126] The first electrode pad is electrically connected to the first electrode through the first electrode through-hole, and the second electrode pad is electrically connected to the second electrode through the second electrode through-hole.

[0127] After completing the above-mentioned manufacturing, the method further comprises scribing, wherein scribing is performed at the isolation grooves not covered by the reflective layer.

[0128] The disclosed embodiment proposes a new design scheme for the scribing lane (isolation groove) to solve the chip leakage and metal migration problems caused by the stick-like shedding of the scribing lane due to the matching problem between the substrate and the scribing laser, thereby improving the stability and light efficiency.

[0129] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode comprises: a substrate (10), an epitaxial structure (20) and a reflective layer (30); The epitaxial structure (20) is in the form of a step structure (111), and the epitaxial structure (20) is also provided with an isolation groove (112) extending to the substrate (10); the reflective layer (30) covers the step structure (111) and a portion of the isolation groove (112), and another portion of the isolation groove (112) is exposed from the substrate (10).

2. The light emitting diode according to claim 1, characterized in that: The width of the region of the isolation groove (112) that exposes the substrate (10) is 6 to 8 μm.

3. The light emitting diode according to claim 1 or 2, characterized in that: The substrate (10) is a patterned sapphire substrate with a layer of SiO2 deposited on the surface.

4. The light emitting diode according to claim 1 or 2, characterized in that: The reflective layer (30) is a DBR structure.

5. The light emitting diode according to claim 1 or 2, characterized in that: The light-emitting diode further comprises a current blocking layer (40), a transparent conductive layer (50), a first electrode (60), a second electrode (70), a first electrode pad (80), and a second electrode pad (90); the current blocking layer (40) and the transparent conductive layer (50) are located on the top surface of the step of the step structure (111), and the transparent conductive layer (50) covers the current blocking layer (40); The first electrode (60) is located on the transparent conductive layer (50), and the second electrode (70) is located on the bottom surface of the step structure (111); The light-emitting diode further comprises a first electrode pad (80) and a second electrode pad (90); the first electrode pad (80) is electrically connected to the first electrode (60) through the reflective layer (30), and the second electrode pad (90) is electrically connected to the second electrode (70) through the reflective layer (30).

6. A method for preparing a light emitting diode, characterized in that: The method comprises: Fabricating an epitaxial structure on a substrate, wherein the epitaxial structure is a step structure and is further provided with an isolation groove extending to the substrate; A reflective layer is manufactured, wherein the reflective layer covers the step structure and a portion of the isolation groove, and another portion of the isolation groove exposes the substrate.

7. The method for preparing a light emitting diode according to claim 6, characterized in that: The width of the region of the isolation trench that exposes the substrate is 6-8 μm.

8. The method for preparing a light emitting diode according to claim 6 or 7, characterized in that: The substrate is a patterned sapphire substrate with a layer of SiO2 deposited on the surface.

9. The method for preparing a light emitting diode according to claim 6 or 7, characterized in that: The manufacturing of the reflective layer comprises: Manufacturing a DBR stack, wherein the DBR stack covers the step structure and the isolation groove; The DBR stack is patterned to remove a portion of the DBR stack located in the isolation groove, and a first electrode through hole and a second electrode through hole are formed on the DBR stack to obtain the reflective layer.

10. The method for preparing a light emitting diode according to claim 9, characterized in that: The method further comprises: A current blocking layer, a transparent conductive layer, a first electrode and a second electrode are manufactured, wherein the current blocking layer and the transparent conductive layer are located on the top surface of the step of the step structure, and the transparent conductive layer covers the current blocking layer; the first electrode is located on the transparent conductive layer, and the second electrode is located on the bottom surface of the step of the step structure; A first electrode pad and a second electrode pad are manufactured; the first electrode pad is electrically connected to the first electrode through the first electrode through hole, and the second electrode pad is electrically connected to the second electrode through the second electrode through hole.

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