Array substrate, display panel and display device

Abstract

According to the array substrate, the display panel and the display device provided by the invention, in the array substrate, the first reference signal is provided for the pixel unit in the display area, and the second reference signal is provided for the pixel unit in the opening area, so that different reference signals can be provided for the pixel unit in the display area and the pixel unit in the opening area; therefore, the problem of poor display effect of the perforated area is effectively improved. Meanwhile, the first reference signal is input into the display area through the second sub-reference signal lines, and the second sub-reference signal lines are connected into a net shape through the first sub-reference signal lines, so that the display uniformity of the display area can be further improved; the second reference signal is input into the display area through the third sub-reference signal lines, and the third sub-reference signal lines are connected into a net shape through the fourth sub-reference signal lines, so that the display uniformity of the perforated area can be further improved, and the display effect of the product is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the invention

[0004] In view of this, the purpose of the present application is to propose an array substrate, a display panel, and a display device, which can provide different reference signals for the display area and the opening area, thereby improving the display effect of the product.

[0005] Based on the above purpose, the present application provides an array substrate, which includes:

[0006] A display area and an opening area located in the display area;

[0007] Reference signal lines, the reference signal lines comprising a first reference signal line and a second reference signal line;

[0008] The first reference signal line includes a plurality of first sub-reference signal lines arranged along a first direction and extending along a second direction, and a plurality of second sub-reference signal lines arranged along the second direction and extending along the first direction; the first sub-reference signal line is partially located in the display area and partially located in the opening area; the second sub-reference signal line is located in the display area; the first sub-reference signal line and the second sub-reference signal line are located in different layers and are connected at the intersection through a dielectric layer via;

[0009] The second reference signal line includes a plurality of third sub-reference signal lines arranged along the first direction and extending along the second direction, and a plurality of fourth sub-reference signal lines arranged along the second direction and extending along the first direction; the third sub-reference signal line is partially located in the display area and partially located in the opening area; the fourth sub-reference signal line is located in the opening area; the third sub-reference signal line and the fourth sub-reference signal line are located in different layers and are connected at the intersection through a dielectric layer via;

[0010] A signal input module is configured to configure a first reference signal on the second sub-reference signal line and a second reference signal on the third sub-reference signal line.

[0011] In one embodiment, the signal input module includes a first reference signal input module and a second reference signal input module;

[0012] The first reference signal input module is connected to the second sub-reference signal line, and the first reference signal input module configures a first reference signal on the second sub-reference signal line;

[0013] The second reference signal input module is connected to the third sub-reference signal line, and the second reference signal input module configures a second reference signal on the third sub-reference signal line.

[0014] In one embodiment, the array substrate further includes:

[0015] a frame area, the frame area at least partially surrounding the display area, the frame area comprising a first frame area, a second frame area and a third frame area, the first frame area, the display area and the second frame area are arranged along the first direction, and the display area and the third frame area are arranged along the second direction;

[0016] The first frame area and the second frame area are both provided with the first reference signal input module, and two ends of the second sub-reference signal line are respectively connected to the first reference signal input modules in the first frame area and the second frame area;

[0017] The third frame area is provided with the second reference signal input module, and one end of the third sub-reference signal line close to the third frame area is connected to the second reference signal input module.

[0018] In one embodiment, the array substrate further includes:

[0019] A plurality of pixel units, some of which are located in the display area and some of which are located in the opening area; the pixel unit includes a pixel circuit, the pixel circuit includes a driving module for driving the light-emitting device to emit light, a first reset module for resetting the gate of the driving module, and a second reset module for resetting the anode of the light-emitting module, and the reference signal line includes a gate reset signal line connected to the first reset module, and an anode reset signal line connected to the second reset module.

[0020] In one embodiment, the first sub-reference signal line in the gate reset signal line, the third sub-reference signal line in the gate reset signal line, the first sub-reference signal line in the anode reset signal line, and the third sub-reference signal line in the anode reset signal line are arranged in the same layer.

[0021] In one embodiment, the pixel unit further includes a third reset module for resetting the source of the driving module, and the reference signal line includes a source reset signal line connected to the third reset module.

[0022] In one embodiment, the first sub-reference signal line in the gate reset signal line, the third sub-reference signal line in the gate reset signal line, the first sub-reference signal line in the anode reset signal line and the third sub-reference signal line in the anode reset signal line are arranged on the same layer, and the first sub-reference signal line in the source reset signal line and the third sub-reference signal line in the source reset signal line are arranged on the same layer.

[0023] In one embodiment, the first sub-reference signal line and the third sub-reference signal line are disposed in the same layer and are alternately arranged in the first direction;

[0024] Preferably, the second sub-reference signal lines are arranged continuously in the second direction;

[0025] Preferably, part of the second sub-reference signal lines are disconnected in the opening area;

[0026] Preferably, the fourth sub-reference signal lines are arranged continuously in the second direction and are located in a disconnected area of ​​the second sub-reference signal lines;

[0027] Preferably, the second sub-reference signal line and the fourth sub-reference signal line are arranged in the same layer.

[0028] Based on the same inventive concept, the present application also discloses a display panel, which includes the array substrate as described above.

[0029] Based on the same inventive concept, the present application also discloses a display device, which includes the display panel as described above.

[0030] Compared with the prior art, the array substrate provided by the present application can provide different reference signals for the pixel units in the display area and the opening area, which can effectively improve the problem of poor display effect in the opening area. At the same time, connecting the reference signal lines into a mesh can further improve the uniformity of the display and effectively improve the display effect of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a schematic diagram of a related array substrate;

[0033] Figure 2 A schematic diagram of an array substrate provided in one embodiment of the present application;

[0034] Figure 3 for Figure 2 A partial schematic diagram of an array substrate;

[0035] Figure 4 for Figure 2 A partial schematic diagram of the array substrate;

[0036] Figure 5 A schematic diagram of an array substrate provided in another embodiment of the present application;

[0037] Figure 6 A schematic diagram of an array substrate provided in another embodiment of the present application;

[0038] Figure 7 A schematic diagram of a pixel circuit provided by another embodiment of the present application;

[0039] Figure 8 A circuit diagram of a pixel circuit provided in accordance with another embodiment of the present application.

[0040] Marking Description:

[0041] 100, array substrate; 110, display area; 120, opening area; 130, frame area; 131, first frame area; 132, second frame area; 133, third frame area; 134, fourth frame area;

[0042] 2. first reference signal line; 21. first sub-reference signal line; 22. second sub-reference signal line;

[0043] 3. second reference signal line; 31. third sub-reference signal line; 32. fourth sub-reference signal line;

[0044] 4. First reference signal input module;

[0045] 5. Second reference signal input module;

[0046] 200. Pixel circuit. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0048] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] Reference Figure 1 As shown, a related array substrate 100 includes a display area 110 and an opening area 120 located in the display area 110 . The opening area 120 is usually used to accommodate a camera or the like.

[0050] Among them, due to requirements such as transmittance, the pixel units in the opening area 120 and the pixel units in the display area 110 are usually designed differently. For example, the pixel units in the opening area 120 are usually smaller. Therefore, under the same driving signal, the display effects of the pixel units in the opening area 120 and the pixel units in the display area 110 are different, and the display effect of the opening area 120 is poor, resulting in the Mura (uneven display) phenomenon.

[0051] Based on this, the present application provides an array substrate solution to solve the above problems, with specific reference to the following embodiments.

[0052] Reference Figure 2-4 As shown, an embodiment of the present application discloses an array substrate 100 , which includes a display area 110 and an opening area 120 located in the display area 110 , and the opening area 120 is used to accommodate a camera and the like.

[0053] The array substrate 100 further includes reference signal lines and a signal input module. The reference signal lines include a first reference signal line 2 and a second reference signal line 3 .

[0054] Among them, the first reference signal line 2 includes a plurality of first sub-reference signal lines 21 arranged along a first direction (such as the X direction in the figure) and extending along a second direction (such as the Y direction in the figure), and a plurality of second sub-reference signal lines 22 arranged along the second direction and extending along the first direction; the first sub-reference signal line 21 is partially located in the display area 110, and partially located in the opening area 120; the second sub-reference signal line 22 is located in the display area 110; the first sub-reference signal line 21 and the second sub-reference signal line 22 are located in different layers and are connected at the intersection through a dielectric layer via.

[0055] The second reference signal line 3 includes a plurality of third sub-reference signal lines 31 arranged along the first direction and extending along the second direction, and a plurality of fourth sub-reference signal lines 32 arranged along the second direction and extending along the first direction; the third sub-reference signal line 31 is partially located in the display area 110, and partially located in the opening area 120; the fourth sub-reference signal line 32 is located in the opening area 120; the third sub-reference signal line 31 and the fourth sub-reference signal line 32 are located in different layers and are connected at the intersection through a dielectric layer via.

[0056] The signal input module configures a first reference signal on the second sub-reference signal line 22 and configures a second reference signal on the third sub-reference signal line 31 .

[0057] Among them, the pixel units in the opening area 120 are different from the pixel units in the display area 110. The first reference signal is used to provide to the pixel units in the display area 110, and the second reference signal is used to provide to the pixel units in the opening area 120. Different reference signals can be provided to the pixel units in the display area 110 and the pixel units in the opening area 120, thereby effectively improving the problem of poor display effect in the opening area 120.

[0058] At the same time, the first reference signal is input into the display area 110 through the second sub-reference signal line 22, and the second sub-reference signal line 22 is connected into a mesh through the first sub-reference signal line 21, which can further improve the display uniformity of the display area 110; the second reference signal is input into the display area 110 through the third sub-reference signal line 31, and the third sub-reference signal line 31 is connected into a mesh through the fourth sub-reference signal line 32, which can further improve the display uniformity of the opening area 120, thereby effectively improving the product display effect.

[0059] In one embodiment, the first sub-reference signal line 21 and the third sub-reference signal line 31 are arranged in the same layer and are alternately arranged in the first direction. Because the first sub-reference signal line 21 and the third sub-reference signal line 31 are both routed along the second direction and are continuous along the second direction, therefore, they only need to be spaced one by one along the first direction to achieve the same layer arrangement without interfering with each other.

[0060] Preferably, second sub-reference signal lines 22 are continuously arranged in the second direction; further, some second sub-reference signal lines 22 are disconnected in opening area 120 , that is, second sub-reference signal lines 22 do not go through opening area 120 .

[0061] Preferably, fourth sub-reference signal lines 32 are continuously arranged in the second direction and located in the disconnection region of second sub-reference signal lines 22 , ie, located in opening region 120 , to achieve disconnection between second sub-reference signal lines 22 and fourth sub-reference signal lines 32 .

[0062] In one embodiment, second sub-reference signal line 22 and fourth sub-reference signal line 32 are disposed in the same layer, so that second sub-reference signal line 22 and fourth sub-reference signal line 32 can be prepared and interrupted at the same time. In another embodiment, second sub-reference signal line 22 and fourth sub-reference signal line 32 are located in different layers.

[0063] Please continue to refer to Figure 2 As shown, in one embodiment, the signal input module includes a first reference signal input module 4 and a second reference signal input module 5; the first reference signal input module 4 is connected to the second sub-reference signal line 22, and the first reference signal input module 4 configures the first reference signal on the second sub-reference signal line 22; the second reference signal input module 5 is connected to the third sub-reference signal line 31, and the second reference signal input module 5 configures the second reference signal on the third sub-reference signal line 31.

[0064] By setting two reference signal input modules, two different reference signals can be provided for the display area 110 and the opening area 120, respectively, thereby effectively improving the problem of poor display effect in the opening area 120. In another embodiment, the same reference signal input module can also be used to provide two different reference signals in a time-sharing driving manner.

[0065] Reference Figure 5 and 6 As shown, in one embodiment, the array substrate 100 also includes a border area 130, and the border area 130 is at least partially arranged around the display area 110. The border area 130 includes a first border area 131, a second border area 132 and a third border area 133. The first border area 131, the display area 110 and the second border area 132 are arranged along a first direction, and the display area 110 and the third border area 133 are arranged along a second direction.

[0066] The first border area 131 and the second border area 132 are both provided with a first reference signal input module 4, and the two ends of the second sub-reference signal line 22 are respectively connected to the first reference signal input module 4 in the first border area 131 and the second border area 132; the third border area 133 is provided with a second reference signal input module 5, and the end of the third sub-reference signal line 31 close to the third border area 133 is connected to the second reference signal input module 5.

[0067] Among them, since the second sub-reference signal line 22 and the fourth sub-reference signal line 32 are both extended along the first direction, and the fourth sub-reference signal line 32 is located in the display area 110, due to the existence of the opening area 120, along the second direction, the second sub-reference signal lines 22 on both sides of the opening area 120 are not connected, and the reference signal cannot be transmitted from the second sub-reference signal line 22 on one side of the opening area 120 to the second sub-reference signal line 22 on the other side. Therefore, the first reference signal input module 4 is provided in the first frame area 131 and the second frame area 132, so that the first reference signal can be input into the second sub-reference signal lines 22 on both sides of the opening area 120. In the second direction, the third sub-reference signal line 31 is continuous, and it is only necessary to provide the second reference signal input module 5 at one end of the third sub-reference signal line 31.

[0068] Furthermore, the frame area 130 further includes a fourth frame area 134, which is located at one end of the display area 110 away from the third frame area 133, that is, the fourth frame area 134, the display area 110, and the third frame area 133 are arranged along the second direction. The third frame area 133 is usually a lower frame, and the fourth frame area 134 is usually an upper frame.

[0069] In one embodiment, the array substrate 100 further includes a plurality of pixel units, some of which are located in the display area 110, and some of which are located in the opening area 120. The pixel units include a pixel circuit 200, and the pixel circuit 200 includes a driving module for driving the light-emitting device to emit light, a first reset module for resetting the gate of the driving module, and a second reset module for resetting the anode of the light-emitting module. The reference signal line includes a gate reset signal line Vref1 connected to the first reset module, and an anode reset signal line Vref2 connected to the second reset module. Figure 7 shown.

[0070] Before the light-emitting module emits light, the gate of the driving module needs to be reset by the first reset module to improve the driving effect of the driving module, and then the anode of the light-emitting module needs to be reset by the second reset module to improve the light-emitting effect of the light-emitting module.

[0071] It should be noted that the pixel units in the display area 110 and the pixel units in the opening area are different in size, but have the same driving circuit structure.

[0072] In one embodiment, the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2, and the third sub-reference signal line 31 in the anode reset signal line Vref2 are arranged on the same layer.

[0073] Specifically, the gate reset signal line Vref1 includes a first reference signal line 2 and a second reference signal line 3, and the anode reset signal line Vref2 also includes a first reference signal line 2 and a second reference signal line 3. Because the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2, and the third sub-reference signal line 31 in the anode reset signal line Vref2 are all routed along the second direction and are continuous along the second direction. Therefore, they only need to be spaced one by one along the first direction to achieve the same-layer arrangement without interfering with each other.

[0074] Please continue to refer to Figure 7 As shown, in one embodiment, the pixel circuit 200 further includes a third reset module for resetting the source of the driving module, and the reference signal line includes a source reset signal line Vref3 connected to the third reset module. Before the first reset module resets the gate of the driving module, the signal on the source reset signal line Vref3 resets the source of the driving module.

[0075] In one embodiment, the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2 and the third sub-reference signal line 31 in the anode reset signal line Vref2 are arranged on the same layer, and the first sub-reference signal line 21 in the source reset signal line Vref3 and the third sub-reference signal line 31 in the source reset signal line Vref3 are arranged on the same layer.

[0076] Specifically, the gate reset signal line Vref1 includes a first reference signal line 2 and a second reference signal line 3, the anode reset signal line Vref2 also includes a first reference signal line 2 and a second reference signal line 3, and the source reset signal line Vref3 also includes a first reference signal line 2 and a second reference signal line 3. Because the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2, the third sub-reference signal line 31 in the anode reset signal line Vref2, the first sub-reference signal line 21 in the source reset signal line Vref3, and the third sub-reference signal line 31 in the source reset signal line Vref3 are all routed along the second direction and are continuous along the second direction. Therefore, they only need to be spaced one by one along the first direction to achieve the same-layer arrangement without interfering with each other, which is convenient for preparation.

[0077] Furthermore, a control terminal of the first reset module is connected to a scan signal SN1, and a control terminal of the second reset module and a control terminal of the third reset module are connected to a scan signal SP2.

[0078] Furthermore, the pixel circuit 200 also includes a data writing module, a control end of the data writing module is connected to the scanning signal line SP1, a first end of the data writing module is connected to the data line Vdata, and a second end of the data writing module is connected to the first end of the driving module. The data writing module is used to respond to the signal on the scanning signal line SP1, and write a voltage related to the data voltage on the data line Vdata to the control end of the driving module during the data writing stage, so that the driving module can generate a driving current according to the data voltage during the light-emitting stage to drive the light-emitting module to emit light.

[0079] Furthermore, the pixel circuit 200 also includes a storage module, which is connected to the control end of the driving module and is used to store the voltage of the control end of the driving module; further, the storage module includes a storage capacitor, a first end of the storage capacitor is connected to the control end of the driving module, and a second end of the storage capacitor is connected to the first end of the driving module.

[0080] Furthermore, the pixel circuit 200 also includes a compensation module, a control end of the compensation module is connected to the fourth scanning signal line SN2, a first end of the compensation module is connected to the control end of the driving module, and a second end of the compensation module is connected to the second end of the driving module, and the compensation module is used to compensate for the threshold voltage of the driving module.

[0081] Reference Figure 8As shown, in a specific embodiment, the pixel circuit 200 is an 8T1C circuit as an example. The driving module includes a transistor T1, the light emitting module includes an OLED or an AMOLED, the data writing module includes a transistor T2, the compensation module includes a transistor T3, the first reset module includes a transistor T4, the first light emitting control module includes a transistor T6, the second light emitting control module includes a transistor T5, the second reset module includes a transistor T7, and the third reset module includes a transistor T8. The transistor T3 and the transistor T4 are NMOS transistors, and the transistors T1, T2, T5, T6, T7, and T8 are PMOS transistors.

[0082] Another embodiment of the present application discloses a display panel, which includes the array substrate 100 in the above embodiment.

[0083] The display panel provided in this embodiment, wherein the array substrate 100 can provide different reference signals for the pixel units in the display area 110 and the opening area 120, can effectively improve the problem of poor display effect in the opening area 120. At the same time, the reference signal lines are connected into a mesh shape, which can further improve the uniformity of the display and is conducive to improving the display performance of the display panel.

[0084] Another embodiment of the present embodiment discloses a display device, which includes the display panel in the above embodiment. The display device can be mounted on a smart device (such as a mobile phone, VR device, computer, TV, car display, etc.).

[0085] In the display device provided in this embodiment, the array substrate 100 in the display panel can provide different reference signals for the pixel units in the display area 110 and the opening area 120, which can effectively improve the problem of poor display effect in the opening area 120. At the same time, the reference signal lines are connected into a mesh shape, which can further improve the uniformity of the display and is conducive to improving the display performance of the display device.

[0086] Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0087] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0088] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: A display area and an opening area located in the display area; Reference signal lines, the reference signal lines comprising a first reference signal line and a second reference signal line; The first reference signal line includes a plurality of first sub-reference signal lines arranged along a first direction and extending along a second direction, and a plurality of second sub-reference signal lines arranged along the second direction and extending along the first direction; the first sub-reference signal line is partially located in the display area and partially located in the opening area; the second sub-reference signal line is located in the display area; the first sub-reference signal line and the second sub-reference signal line are located in different layers and are connected at the intersection through a dielectric layer via; The second reference signal line includes a plurality of third sub-reference signal lines arranged along the first direction and extending along the second direction, and a plurality of fourth sub-reference signal lines arranged along the second direction and extending along the first direction; the third sub-reference signal line is partially located in the display area and partially located in the opening area; the fourth sub-reference signal line is located in the opening area; the third sub-reference signal line and the fourth sub-reference signal line are located in different layers and are connected at the intersection through a dielectric layer via; A signal input module is configured to configure a first reference signal on the second sub-reference signal line and a second reference signal on the third sub-reference signal line.

2. The array substrate according to claim 1, characterized in that: The signal input module includes a first reference signal input module and a second reference signal input module; The first reference signal input module is connected to the second sub-reference signal line, and the first reference signal input module configures a first reference signal on the second sub-reference signal line; The second reference signal input module is connected to the third sub-reference signal line, and the second reference signal input module configures a second reference signal on the third sub-reference signal line.

3. The array substrate according to claim 2, characterized in that: The array substrate further includes: a frame area, the frame area at least partially surrounding the display area, the frame area comprising a first frame area, a second frame area and a third frame area, the first frame area, the display area and the second frame area are arranged along the first direction, and the display area and the third frame area are arranged along the second direction; The first frame area and the second frame area are both provided with the first reference signal input module, and two ends of the second sub-reference signal line are respectively connected to the first reference signal input modules in the first frame area and the second frame area; The third frame area is provided with the second reference signal input module, and one end of the third sub-reference signal line close to the third frame area is connected to the second reference signal input module.

4. The array substrate according to claim 1, wherein: The array substrate further includes: A plurality of pixel units, some of which are located in the display area and some of which are located in the opening area; the pixel unit includes a pixel circuit, the pixel circuit includes a driving module for driving the light-emitting device to emit light, a first reset module for resetting the gate of the driving module, and a second reset module for resetting the anode of the light-emitting module, and the reference signal line includes a gate reset signal line connected to the first reset module, and an anode reset signal line connected to the second reset module.

5. The array substrate according to claim 4, characterized in that: The first sub-reference signal line in the gate reset signal line, the third sub-reference signal line in the gate reset signal line, the first sub-reference signal line in the anode reset signal line, and the third sub-reference signal line in the anode reset signal line are arranged in the same layer.

6. The array substrate according to claim 4, characterized in that: The pixel unit further includes a third reset module for resetting the source of the driving module, and the reference signal line includes a source reset signal line connected to the third reset module.

7. The array substrate according to claim 6, characterized in that: The first sub-reference signal line in the gate reset signal line, the third sub-reference signal line in the gate reset signal line, the first sub-reference signal line in the anode reset signal line and the third sub-reference signal line in the anode reset signal line are arranged on the same layer, and the first sub-reference signal line in the source reset signal line and the third sub-reference signal line in the source reset signal line are arranged on the same layer.

8. The array substrate according to claim 1, wherein: The first sub-reference signal line and the third sub-reference signal line are arranged in the same layer and are alternately arranged in the first direction; Preferably, the second sub-reference signal lines are arranged continuously in the second direction; Preferably, part of the second sub-reference signal lines are disconnected in the opening area; Preferably, the fourth sub-reference signal lines are arranged continuously in the second direction and are located in a disconnected area of ​​the second sub-reference signal lines; Preferably, the second sub-reference signal line and the fourth sub-reference signal line are arranged in the same layer.

9. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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