Self-selection memory based on 1S1R structure and preparation method and equipment thereof

Abstract

The invention relates to a self-selection memory based on a 1S1R structure and a preparation method and equipment thereof, an intermediate layer is additionally arranged between a gate layer and a resistive layer, the thermal conductivity of the intermediate layer is smaller than that of the resistive layer, the intermediate layer is arranged between the resistive layer and the gate layer, heat of the gate layer can be prevented from being transmitted to the resistive layer, the temperature rise rate of the gate layer can be increased, and the performance of the memory is improved. Therefore, the gate layer is quickly raised to the starting temperature, the starting voltage of the gate layer of the self-selection memory can be reduced, and the self-selection memory realizes self-selection storage; meanwhile, the intermediate layer can improve the thermal stability of the gating layer, delay the temperature reduction of the gating layer, and reduce the overall write voltage and read voltage of the self-selection memory; and performance degradation of the self-selection memory caused by mutual diffusion of materials of the gating layer and the resistive layer can be avoided, and the reliability and the performance stability of the self-selection memory are improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a self-selecting memory based on a 1S1R structure and a preparation method and device thereof. Background Art

[0002] Resistive Random Access Memory (RRAM) has the characteristics of simple structure, small feature size, fast programming / erasing speed, etc., and has great development potential. At present, RRAM memory mostly adopts the 1T1R architecture integrating the gate transistor and the memristor device. The feature size of the 1T1R architecture is large, which limits the scalability of RRAM memory and is not conducive to three-dimensional integration.

[0003] The 1S1R architecture RRAM memory, in which the selector is integrated as a threshold switch device and a memristor device, has a smaller feature size. The threshold transition characteristics of the selector can suppress the leakage current on the low-resistance RRAM in the non-selected unit. The 1S1R unit composed of the selector and the resistive memory is suitable for both storage and the realization of neuromorphic computing systems.

[0004] However, there are still many problems with 1S1R architecture RRAM memory that limit its application. Summary of the invention

[0005] Based on this, it is necessary to provide a self-selecting memory based on a 1S1R structure and a preparation method and device thereof to address the problem of limited application of RRAM memory with a 1S1R architecture in the prior art.

[0006] In a first aspect, the present disclosure provides a self-selection memory based on a 1S1R structure, comprising a first functional layer, an intermediate layer, and a second functional layer sequentially stacked on a substrate, wherein the second functional layer is separated from the first functional layer by the intermediate layer, the first functional layer is connected to a first electrode, and the second functional layer is connected to a second electrode;

[0007] One of the first functional layer and the second functional layer is a gating layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is smaller than the thermal conductivity of the resistive switching layer.

[0008] Optionally, the thermal conductivity of the gating layer is 0.3W / m·K-1.5W / m·K; the thermal conductivity of the resistive switching layer is 2.2W / m·K-5W / m·K;

[0009] The thermal conductivity of the intermediate layer is 0.2W / m·K-2W / m·K; the electrical conductivity of the intermediate layer is 10 -7 S / m-10 -2 S / m.

[0010] Optionally, the thermal conductivity of a side of the middle layer close to the resistive layer is smaller than the thermal conductivity of a side of the middle layer close to the gating layer.

[0011] Optionally, the thermal conductivity of the intermediate layer decreases from the gating layer toward the resistive switching layer.

[0012] Optionally, the material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0013] Optionally, the material of the gating layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride;

[0014] The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0015] Optionally, the first functional layer is a gating layer, and the second functional layer is a resistive switching layer;

[0016] The material of the first functional layer includes niobium oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes tantalum oxide.

[0017] Optionally, the first functional layer is a resistive switching layer, and the second functional layer is a gating layer;

[0018] The material of the first functional layer includes tantalum oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes niobium oxide.

[0019] In a second aspect, the present disclosure provides a method for preparing a self-selection memory based on a 1S1R structure, comprising the following steps:

[0020] providing a substrate, and forming a first electrode on the substrate;

[0021] forming a first functional layer on the first electrode;

[0022] forming an intermediate layer on the first functional layer;

[0023] A second functional layer is formed on the intermediate layer, wherein the second functional layer is separated from the first functional layer by the intermediate layer; one of the first functional layer and the second functional layer is a gating layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is less than the thermal conductivity of the resistive switching layer;

[0024] A second electrode is formed on the second functional layer.

[0025] Optionally, the thermal conductivity of the gating layer is 0.3W / m·K-1.5W / m·K; the thermal conductivity of the resistive switching layer is 2.2W / m·K-5W / m·K;

[0026] The thermal conductivity of the intermediate layer is 0.2W / m·K-2W / m·K; the electrical conductivity of the intermediate layer is 10 -7 S / m-10 -2 S / m.

[0027] Optionally, the thermal conductivity of a side of the middle layer close to the resistive layer is smaller than the thermal conductivity of a side of the middle layer close to the gating layer.

[0028] Optionally, the thermal conductivity of the intermediate layer decreases from the gating layer toward the resistive switching layer.

[0029] Optionally, the material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0030] Optionally, the material of the gating layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride;

[0031] The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0032] Optionally, after forming an intermediate layer on the first functional layer, the method further comprises:

[0033] The first gas is ionized to generate plasma, and the intermediate layer is treated with the plasma.

[0034] Optionally, the first functional layer is a gating layer, and the second functional layer is a resistive switching layer; the material of the first functional layer includes niobium oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes tantalum oxide.

[0035] Optionally, the first functional layer is a resistive layer, and the second functional layer is a gating layer; the material of the first functional layer includes tantalum oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes niobium oxide.

[0036] In a third aspect, the present disclosure provides an electronic device, comprising a self-selection memory based on a 1S1R structure as described in the first aspect, or a self-selection memory based on a 1S1R structure manufactured by the preparation method of a self-selection memory based on a 1S1R structure as described in the second aspect.

[0037] The self-selective memory based on the 1S1R structure disclosed herein and its preparation method and device, add an intermediate layer between the selection layer and the resistive layer, the thermal conductivity of the intermediate layer is less than the thermal conductivity of the resistive layer, and the intermediate layer is arranged between the resistive layer and the selection layer, which can hinder the heat of the selection layer from being transferred to the resistive layer, and can increase the temperature rise rate of the selection layer so that the selection layer can quickly rise to the turn-on temperature, and can reduce the turn-on voltage of the selection layer of the self-selective memory, so that the self-selective memory realizes self-selective storage; at the same time, the intermediate layer can improve the thermal stability of the selection layer, delay the temperature reduction of the selection layer, and reduce the overall write voltage and read voltage of the self-selective memory; it can also avoid the mutual diffusion of materials of the selection layer and the resistive layer, which leads to the performance degradation of the self-selective memory, thereby improving the reliability and performance stability of the self-selective memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 A schematic diagram of a self-selection memory based on a 1S1R structure provided in an exemplary embodiment;

[0040] Figure 2 A schematic diagram of the structure of a self-selection memory based on a 1S1R structure provided in another exemplary embodiment;

[0041] Figure 3 The process flow chart of a method for preparing a self-selection memory based on a 1S1R structure provided in an exemplary embodiment. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] According to an exemplary embodiment, the present disclosure provides a self-selection memory based on a 1S1R structure, referring to Figure 1 , Figure 2 , including a first functional layer 30, an intermediate layer 40 and a second functional layer 50 stacked in sequence on a substrate 10, the second functional layer 50 is separated from the first functional layer 30 by the intermediate layer 40, the first functional layer 30 is connected to the first electrode 20, and the second functional layer 50 is connected to the second electrode 60; one of the first functional layer 30 and the second functional layer 50 is a gating layer 110, and the other is a resistive layer 120; the thermal conductivity of the intermediate layer 40 is less than the thermal conductivity of the resistive layer 120.

[0045] In the self-selection memory based on the 1S1R structure of this embodiment, an intermediate layer 40 is additionally provided between the gate layer 110 and the resistive switching layer 120. On the one hand, the thermal conductivity of the intermediate layer 40 is lower than that of the resistive switching layer 120. The intermediate layer 40 is provided between the resistive switching layer 120 and the gate layer 110, and can prevent the heat of the gate layer 110 from being transferred to the resistive switching layer 120, so that the gate layer 110 quickly rises to the turn-on temperature, and can reduce the turn-on voltage (V th ), the self-selection memory realizes self-selection storage; at the same time, the intermediate layer 40 can improve the thermal stability of the selection layer 110, delay the temperature drop of the selection layer 110, and reduce the overall write voltage and read voltage of the self-selection memory; on the other hand, the intermediate layer 40 can also prevent the mutual diffusion of materials between the selection layer 110 and the resistive layer 120, which leads to the performance degradation of the self-selection memory, thereby improving the reliability and performance stability of the self-selection memory.

[0046] In one embodiment, referring to Figure 1 , Figure 2 , the thermal conductivity of the intermediate layer 40 is greater than the thermal conductivity of the gate layer 110. In this way, the intermediate layer 40 is prevented from affecting the temperature rise of the gate layer 110.

[0047] In one embodiment, the thermal conductivity of the gating layer 110 is 0.3 W / m·K-1.5 W / m·K; by way of example, the thermal conductivity of the gating layer 110 may be 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.8 W / m·K, 0.9 W / m·K, 1.0 W / m·K, 1.1 W / m·K, 1.2 W / m·K, 1.3 W / m·K or 1.5 W / m·K.

[0048] The thermal conductivity of the resistive layer 120 is 2.2 W / m·K-5 W / m·K. By way of example, the thermal conductivity of the resistive layer 120 may be 2.2 W / m·K, 2.3 W / m·K, 2.4 W / m·K, 2.5 W / m·K, 2.6 W / m·K, 2.7 W / m·K, 3 W / m·K, 3.5 W / m·K, 4 W / m·K, 4.5 W / m·K or 5 W / m·K.

[0049] The thermal conductivity of the intermediate layer 40 is 0.2 W / m·K-2 W / m·K. For example, the thermal conductivity of the intermediate layer 40 may be 0.2 W / m·K, 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.72 W / m·K, 0.75 W / m·K, 0.8 W / m·K, 1.0 W / m·K, 1.2 W / m·K, 1.4 W / m·K, 1.5 W / m·K, 1.6 W / m·K, 1.7 W / m·K, 1.9 W / m·K or 2.0 W / m·K.

[0050] The conductivity of the intermediate layer 40 is 10 -7 S / m-10 -2 S / m. Example, 10 -7 S / m, 10 -6 S / m, 10 -5 S / m, 10 -4 S / m, 10 -3 S / m or 10 -2 S / m.

[0051] The thermal conductivity of the intermediate layer 40 is between 0.2W / m·K and 2W / m·K, and the electrical conductivity is between 10 -7 S / m-10 -2 S / m, the middle layer 40 has good conductivity and certain heat insulation. In this way, the middle layer 40 is arranged between the selection layer 110 and the resistive layer 120 without affecting the conduction between the selection layer 110 and the resistive layer 120, and can also reduce the start-up voltage of the self-selection memory.

[0052] In one embodiment, referring to Figure 1 , Figure 2, the thermal conductivity of the middle layer 40 close to the resistive layer 120 is smaller than the thermal conductivity of the middle layer 40 close to the gate layer 110 .

[0053] It can be understood that the middle layer 40 is equivalent to providing a "lid" on the gating layer 110. The middle layer 40 prevents the gating layer 110 from transferring heat to the outside and stores the heat inside the gating layer 110. The thermal conductivity of the middle layer 40 close to the gating layer 110 is greater than the thermal conductivity of the middle layer 40 close to the resistive layer 120. That is, the difficulty of transferring the heat of the gating layer 110 to the outside through the middle layer 40 increases, further improving the temperature rise rate of the gating layer 110, so that the gating layer 110 quickly rises to the turn-on temperature.

[0054] The thermal conductivity of the middle layer 40 near the resistive layer 120 is smaller than the thermal conductivity of the middle layer 40 near the gating layer 110. The resistive layer 120 may be provided as a multilayer, and the thermal conductivity of the material layer of the middle layer 40 near the resistive layer 120 is smaller than the thermal conductivity of the material layer near the gating layer 110. Alternatively, the thermal conductivity may be achieved by adjusting any one or more of the component content or doping of the material in the middle layer 40. For example, the thermal conductivity of the middle layer 40 may be adjusted by adjusting the concentration of doping ions in the middle layer 40.

[0055] In one embodiment, the thermal conductivity of the middle layer 40 decreases from the gate layer 110 to the resistive layer 120 .

[0056] The intermediate layer 40 may include multiple material layers stacked between the gate layer 110 and the resistive switching layer 120, and the thermal conductivity of each material layer of the intermediate layer 40 decreases in sequence from the gate layer 110 to the resistive switching layer 120. Alternatively, the deposition process for forming the intermediate layer 40 may be controlled so that the material composition of the intermediate layer 40 gradually changes from the gate layer 110 to the resistive switching layer 120, and the thermal conductivity of the intermediate layer 40 gradually decreases.

[0057] In one example, the intermediate layer 40 includes a first intermediate layer and a second intermediate layer sequentially stacked from the gate layer 110 to the resistive layer 120 , and the thermal conductivity of the second intermediate layer is smaller than that of the first intermediate layer.

[0058] In another example, the intermediate layer 40 includes a first intermediate layer, a second intermediate layer and a third intermediate layer sequentially stacked from the gate layer 110 to the resistive layer 120 , and the thermal conductivities of the first intermediate layer, the second intermediate layer and the third intermediate layer decrease sequentially.

[0059] In one embodiment, the thermal conductivity of the side of the gating layer 110 close to the middle layer 40 is smaller than the thermal conductivity of the side of the gating layer 110 far from the middle layer 40. In this way, from the gating layer 110 to the resistive layer 120, the gating layer 110 and the middle layer 40 form a stack with gradually decreasing thermal conductivity, which can further improve the thermal stability of the gating layer 110, delay the temperature drop of the gating layer, and reduce the overall write voltage and read voltage of the self-selection memory.

[0060] The gating layer 110 may be a single-layer structure, and the thermal conductivity of the gating layer 110 may be modulated by adjusting any one or more of the component content or doping of the material in the gating layer 110. The gating layer 110 may also be a multi-layer structure, and the thermal conductivity of the gating layer 110 may be modulated by adjusting the multi-layer material layers of the gating layer 110.

[0061] In one embodiment, referring to Figure 1 , Figure 2 , the thermal conductivity of the side of the resistive layer 120 away from the middle layer 40 is less than the thermal conductivity of the side of the gate layer 110 close to the middle layer 40. In this way, from the gate layer 110 to the resistive layer 120, the gate layer 110, the middle layer 40 and the resistive layer 120 form a stacked layer with gradually decreasing thermal conductivity, which can further improve the thermal stability of the gate layer 110 and improve the performance of the self-selection memory.

[0062] Likewise, the material of the resistive layer 120 may be a single-layer structure or a multi-layer structure.

[0063] In one embodiment, the material of the intermediate layer 40 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0064] The intermediate layer 40 may be a single-layer structure or a multi-layer structure. For example, the intermediate layer 40 may include a single-layer amorphous carbon layer; for another example, the intermediate layer 40 may include a stacked amorphous carbon layer and an indium gallium zinc oxide layer.

[0065] In some embodiments, the material of the intermediate layer 40 includes amorphous carbon, which has good electrical conductivity as well as good thermal conductivity and heat preservation properties. This is beneficial for maintaining the temperature of the selection layer 110, improving the threshold transition characteristics of the selection layer 110, and facilitating the three-dimensional integration of the self-selection memory.

[0066] In one embodiment, the material of the gating layer 110 includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

[0067] The material of the resistive layer 120 includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0068] In this way, by reasonably setting the materials of the selection layer 110 and the resistive layer 120 of the self-selection memory, the materials of the selection layer 110 and the resistive layer 120 are matched, so that the self-selection memory has a self-rectification effect, which can effectively suppress the leakage current generated by the self-selection memory, which is conducive to further reducing the size of the self-selection memory, and forming the self-selection memory into an integrated array, which is conducive to expanding the application fields and application scenarios applicable to the self-selection memory.

[0069] For example, the material of the resistive variable layer 120 includes tantalum oxide, and the material of the gate layer 110 includes niobium oxide. In this way, the self-rectification capability of the variable memory can be further improved, and leakage current generated by the self-select memory can be suppressed.

[0070] In one embodiment, the gating layer 110 is doped with a thermally conductive material, and the thermally conductive material is used to improve the thermal conductivity of the gating layer 110 and to increase the temperature rise rate and thermal stability of the gating layer 110 .

[0071] For example, the thermal conductive material may include one or more of Al, Cu, Au, Ti, etc.

[0072] It is understood that the concentration of the thermally conductive material doped in the gate layer 110 can be controlled to make the thermal conductivity of the gate layer 110 close to the middle layer 40 smaller than the thermal conductivity of the gate layer 110 away from the middle layer 40 .

[0073] In one embodiment, the material of the first electrode 20 may include at least one of vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), yttrium (Ir), yttrium oxide (IrO2), indium tin oxide (ITO), aluminum titanium nitride (TiAlN), aluminum nitride (AlNx), aluminum titanium nitride (TiAlN) or (AlTiN), hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), platinum (Pt), palladium (Pd), and copper (Cu). The first electrode 20 may be a single-layer structure or a multi-layer structure.

[0074] The selection range of the material of the second electrode 60 is the same as that of the first electrode 20 , and will not be described in detail.

[0075] It can be understood that in actual production, the first electrode 20 and the second electrode 60 may include the same material or different materials.

[0076] In one embodiment, referring to Figure 1 , the first functional layer 30 is a gate layer 110, and the second functional layer 50 is a resistive variable layer 120; the material of the first functional layer 30 includes niobium oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes tantalum oxide. The first electrode 20, the gate layer 110, the intermediate layer 40, the resistive variable layer 120, and the second electrode 60 are sequentially stacked on the substrate 10. In this way, the self-rectification capability of the variable memory can be further improved, and the leakage current generated by the self-selection memory can be suppressed.

[0077] In one embodiment, referring to Figure 2 , the first functional layer 30 is a resistive switching layer 120, and the second functional layer 50 is a gate layer 110; the material of the first functional layer 30 includes tantalum oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes niobium oxide. The first electrode 20, the resistive switching layer 120, the intermediate layer 40, the gate layer 110, and the second electrode 60 are sequentially stacked on the substrate 10. In this way, the self-rectification capability of the variable memory can be further improved, and the leakage current generated by the self-selection memory can be suppressed.

[0078] According to an exemplary embodiment, Figure 3 As shown, the present disclosure provides a method for preparing a self-selection memory based on a 1S1R structure, comprising the following steps:

[0079] Step S10: providing a substrate, and forming a first electrode on the substrate;

[0080] Step S20: forming a first functional layer on the first electrode;

[0081] Step S30: forming an intermediate layer on the first functional layer;

[0082] Step S40: forming a second functional layer on the intermediate layer, wherein the second functional layer is separated from the first functional layer by the intermediate layer, one of the first functional layer and the second functional layer is a gate layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is less than the thermal conductivity of the resistive switching layer;

[0083] Step S50: forming a second electrode on the second functional layer.

[0084] In the preparation method of the self-selective memory based on the 1S1R structure of the present embodiment, an intermediate layer is formed between the selection layer and the resistive layer. The thermal conductivity of the intermediate layer is less than that of the resistive layer. The intermediate layer is arranged between the resistive layer and the selection layer, and can hinder the heat of the selection layer from being transferred to the resistive layer, and can increase the temperature rise rate of the selection layer so that the selection layer quickly rises to the turn-on temperature, and can reduce the turn-on voltage of the selection layer of the self-selective memory, so that the self-selective memory realizes self-selective storage; at the same time, the intermediate layer can improve the thermal stability of the selection layer, delay the temperature drop of the selection layer, and reduce the overall write voltage and read voltage of the self-selective memory; it can also avoid the mutual diffusion of materials of the selection layer and the resistive layer, which leads to the performance degradation of the self-selective memory, and improves the reliability and performance stability of the self-selective memory.

[0085] In step S10, referring to Figure 1 or Figure 2 The substrate 10 may be a semiconductor substrate. The semiconductor substrate material may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. Alternatively, in some cases, the substrate 10 may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP).

[0086] The first electrode 20 is formed by deposition on the substrate 10 by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0087] The material of the first electrode 20 may include one or more of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, aluminum nitride titanium aluminum, aluminum nitride, aluminum nitride, aluminum titanium nitride, AlTiN, hafnium, iridium, manganese, zinc, platinum, palladium, copper, or alloys of the above materials. The first electrode 20 may be a single-layer structure or a multi-layer structure.

[0088] The thickness of the first electrode 20 may be 10 nm-2500 nm. For example, the thickness of the first electrode 20 may be 10 nm, 100 nm, 500 nm, 1000 nm, 1500 nm, 2000 nm or 2500 nm.

[0089] In step S20, referring to Figure 1 or Figure 2The first functional layer 30 can be formed by PVD, CVD, PECVD, ALD, ion beam sputtering, electron beam evaporation or thermal evaporation. The first functional layer 30 is one of the gating layer 110 and the resistive layer 120. The first functional layer 30 can be a single layer structure or a multi-layer structure.

[0090] In step S30, referring to Figure 1 or Figure 2 The intermediate layer 40 may be formed by deposition using processes such as PVD, ALD, CVD, atmospheric pressure chemical vapor deposition (APCVD), PECVD or low pressure chemical vapor deposition (LPCVD). The intermediate layer 40 may be a single-layer structure or a multi-layer structure.

[0091] In step S40, referring to Figure 1 or Figure 2 The second functional layer 50 can be formed by PVD, CVD, PECVD, ALD, ion beam sputtering, electron beam evaporation or thermal evaporation. The second functional layer 50 is one of the resistive layer 120 and the gate layer 110. The second functional layer 50 can be a single layer structure or a multi-layer structure.

[0092] One of the first functional layer 30 and the second functional layer 50 is the gating layer 110 , and the other is the resistive switching layer 120 . The thermal conductivity of the intermediate layer 40 is smaller than that of the resistive switching layer 120 .

[0093] In step S50, referring to Figure 1 or Figure 2 PVD, CVD, PECVD, or ALD deposition is used to form the second electrode 60. The selection range of the material of the second electrode 60 is the same as that of the first electrode 20, and will not be described in detail herein.

[0094] The thickness of the second electrode 60 may be 10 nm-2500 nm. For example, the thickness of the second electrode 60 may be 10 nm, 100 nm, 500 nm, 1000 nm, 1500 nm, 2000 nm or 2500 nm.

[0095] In one embodiment, the thermal conductivity of the intermediate layer 40 is greater than the thermal conductivity of the gate layer 110. In this way, the intermediate layer 40 is prevented from affecting the temperature rise of the gate layer 110.

[0096] In one embodiment, the thermal conductivity of the gating layer 110 is 0.3 W / m·K-1.5 W / m·K; by way of example, the thermal conductivity of the gating layer 110 may be 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.8 W / m·K, 0.9 W / m·K, 1.0 W / m·K, 1.1 W / m·K, 1.2 W / m·K, 1.3 W / m·K or 1.5 W / m·K.

[0097] The thermal conductivity of the resistive layer 120 is 2.2 W / m·K-5 W / m·K. By way of example, the thermal conductivity of the resistive layer 120 may be 2.2 W / m·K, 2.3 W / m·K, 2.4 W / m·K, 2.5 W / m·K, 2.6 W / m·K, 2.7 W / m·K, 3 W / m·K, 3.5 W / m·K, 4 W / m·K, 4.5 W / m·K or 5 W / m·K.

[0098] The thermal conductivity of the intermediate layer 40 is 0.2 W / m·K-2 W / m·K. For example, the thermal conductivity of the intermediate layer 40 may be 0.2 W / m·K, 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.72 W / m·K, 0.75 W / m·K, 0.8 W / m·K, 1.0 W / m·K, 1.2 W / m·K, 1.4 W / m·K, 1.5 W / m·K, 1.6 W / m·K, 1.7 W / m·K, 1.9 W / m·K or 2.0 W / m·K.

[0099] The conductivity of the intermediate layer 40 is 10 -7 S / m-10 -2 S / m. Example, 10 -7 S / m, 10 -6 S / m, 10 -5 S / m, 10 -4 S / m, 10 -3 S / m or 10 -2 S / m.

[0100] The thermal conductivity of the intermediate layer 40 is between 0.2W / m·K and 2W / m·K, and the electrical conductivity is between 10 -7 S / m-10 -2 S / m, the middle layer 40 has good conductivity and certain heat insulation. In this way, the middle layer 40 is arranged between the selection layer 110 and the resistive layer 120 without affecting the conduction between the selection layer 110 and the resistive layer 120, and can also reduce the start-up voltage of the self-selection memory.

[0101] In one embodiment, the thermal conductivity of the middle layer 40 on the side close to the resistive layer 120 is smaller than the thermal conductivity of the middle layer 40 on the side close to the gate layer 110 .

[0102] When forming the intermediate layer 40 , at least two layers may be deposited so that the thermal conductivity of the material layer of the intermediate layer 40 close to the resistive layer 120 is smaller than the thermal conductivity of the material layer of the intermediate layer 40 close to the gate layer 110 .

[0103] Alternatively, when forming the intermediate layer 40 , ions may be doped into the intermediate layer 40 , and the concentration of the doped ions may be controlled so that the thermal conductivity of the material layer of the intermediate layer 40 close to the resistive layer 120 is smaller than the thermal conductivity of the material layer of the intermediate layer 40 close to the gate layer 110 .

[0104] In one embodiment, the thermal conductivity of the middle layer 40 decreases from the gate layer 110 to the resistive layer 120 .

[0105] In one embodiment, the material of the intermediate layer 40 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0106] For example, the material of the intermediate layer 40 may include amorphous carbon.

[0107] In one embodiment, the material of the gating layer 110 includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

[0108] The material of the resistive layer 120 includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0109] In this way, by reasonably setting the materials of the selection layer 110 and the resistive layer 120 of the self-selection memory, the materials of the selection layer 110 and the resistive layer 120 are matched, so that the self-selection memory has a self-rectification effect, which can effectively suppress the leakage current generated by the self-selection memory, which is conducive to further reducing the size of the self-selection memory, and forming the self-selection memory into an integrated array, which is conducive to expanding the application fields and application scenarios applicable to the self-selection memory.

[0110] In one embodiment, referring to Figure 1The first functional layer 30 is a gate layer 110, and the second functional layer 50 is a resistive layer 120; the material of the first functional layer 30 includes niobium oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes tantalum oxide.

[0111] In one embodiment, referring to Figure 2 The first functional layer 30 is a resistive layer 120 , and the second functional layer 50 is a gate layer 110 ; the material of the first functional layer 30 includes tantalum oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes niobium oxide.

[0112] In one embodiment, when forming the gating layer 110 , a thermally conductive material may be doped into the gating layer 110 to improve the thermal conductivity of the gating layer 110 and to increase the temperature rise rate and thermal stability of the gating layer 110 .

[0113] For example, the thermally conductive material may include one or more of Al, Cu, Au, Ti, etc. Doping process is preferred.

[0114] For example, the thermal conductive material may be doped into the gate layer 110 by ion implantation IMP and / or co-sputtering.

[0115] In one embodiment, after forming the intermediate layer 40 on the first functional layer 30, the method further includes:

[0116] Step S60 : ionizing the first gas to generate plasma, and using the plasma to process the intermediate layer 40 .

[0117] N2 can be ionized to generate nitrogen plasma, which improves the film density of the gating layer 110, is beneficial to reducing the thermal budget for forming the intermediate layer 40, reduces production costs, and improves production efficiency.

[0118] According to an exemplary embodiment, this embodiment provides an electronic device, including the self-selection memory based on the 1S1R structure of the above embodiment, or the self-selection memory based on the 1S1R structure manufactured by the preparation method of the self-selection memory based on the 1S1R structure of the above embodiment.

[0119] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A self-selection memory based on a 1S1R structure, characterized in that: The method comprises a first functional layer, an intermediate layer, and a second functional layer sequentially stacked on a substrate, wherein the second functional layer is separated from the first functional layer by the intermediate layer, the first functional layer is connected to a first electrode, and the second functional layer is connected to a second electrode; One of the first functional layer and the second functional layer is a gating layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is smaller than the thermal conductivity of the resistive switching layer.

2. The self-selection memory based on 1S1R structure according to claim 1, characterized in that: The thermal conductivity of the gating layer is 0.3W / m·K-1.5W / m·K; the thermal conductivity of the resistive layer is 2.2W / m·K-5W / m·K; The thermal conductivity of the intermediate layer is 0.2W / m·K-2W / m·K; the electrical conductivity of the intermediate layer is 10 -7 S / m-10 -2 S / m.

3. The self-selection memory based on 1S1R structure according to claim 2, characterized in that: The thermal conductivity of a side of the middle layer close to the resistive layer is smaller than the thermal conductivity of a side of the middle layer close to the gating layer.

4. The self-selection memory based on 1S1R structure according to claim 3, characterized in that: The thermal conductivity of the middle layer decreases from the gating layer to the resistive switching layer.

5. The self-selection memory based on 1S1R structure according to any one of claims 2 to 4, characterized in that: The material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

6. The self-selection memory based on 1S1R structure according to claim 1, characterized in that: The material of the gating layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride; The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

7. The self-selection memory based on 1S1R structure according to any one of claims 1 to 4, characterized in that: The first functional layer is a gating layer, and the second functional layer is a resistive switching layer; The material of the first functional layer includes niobium oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes tantalum oxide.

8. The self-selection memory based on 1S1R structure according to any one of claims 1 to 4, characterized in that: The first functional layer is a resistive switching layer, and the second functional layer is a gating layer; The material of the first functional layer includes tantalum oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes niobium oxide.

9. A method for preparing a self-selection memory based on a 1S1R structure, characterized in that: The following steps are involved: providing a substrate, and forming a first electrode on the substrate; forming a first functional layer on the first electrode; forming an intermediate layer on the first functional layer; A second functional layer is formed on the intermediate layer, wherein the second functional layer is separated from the first functional layer by the intermediate layer; one of the first functional layer and the second functional layer is a gating layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is less than the thermal conductivity of the resistive switching layer; A second electrode is formed on the second functional layer.

10. The method for preparing a self-selection memory based on a 1S1R structure according to claim 9, characterized in that: The thermal conductivity of the gating layer is 0.3W / m·K-1.5W / m·K; the thermal conductivity of the resistive layer is 2.2W / m·K-5W / m·K; The thermal conductivity of the intermediate layer is 0.2W / m·K-2W / m·K; the electrical conductivity of the intermediate layer is 10 -7 S / m-10 -2 S / m.

11. The method for preparing a self-selection memory based on a 1S1R structure according to claim 10, characterized in that: The thermal conductivity of a side of the middle layer close to the resistive layer is smaller than the thermal conductivity of a side of the middle layer close to the gating layer.

12. The method for preparing a self-selection memory based on a 1S1R structure according to claim 10, characterized in that: The thermal conductivity of the middle layer decreases from the gating layer to the resistive switching layer.

13. The method for preparing a self-selection memory based on a 1S1R structure according to any one of claims 10 to 12, characterized in that: The material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

14. The method for preparing a self-selection memory based on a 1S1R structure according to claim 9, characterized in that: The material of the gating layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride; The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

15. The method for preparing a self-selection memory based on a 1S1R structure according to any one of claims 9 to 12, characterized in that: After forming an intermediate layer on the first functional layer, the method further comprises: The first gas is ionized to generate plasma, and the intermediate layer is treated with the plasma.

16. The method for preparing a self-selection memory based on a 1S1R structure according to any one of claims 9 to 12, characterized in that: The first functional layer is a gating layer, and the second functional layer is a resistive switching layer; the material of the first functional layer includes niobium oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes tantalum oxide.

17. The method for preparing a self-selection memory based on a 1S1R structure according to any one of claims 9 to 12, characterized in that: The first functional layer is a resistive layer, and the second functional layer is a gating layer; the material of the first functional layer includes tantalum oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes niobium oxide.

18. An electronic device, characterized in that: A self-selection memory based on a 1S1R structure comprising the self-selection memory based on a 1S1R structure as claimed in any one of claims 1-8, or a self-selection memory based on a 1S1R structure manufactured by the preparation method of the self-selection memory based on a 1S1R structure as claimed in any one of claims 9-17.

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