A high sampling rate echo segmented pulse compression method based on FPGA

Abstract

The present invention discloses a method for echo segmented pulse compression at a high sampling rate based on FPGA. The present invention first performs downsampling preprocessing on the signal sampled by ADC with a sampling rate of 124MHz. The sampling rate is reduced to 62MHz under the premise that no spectrum aliasing occurs in the signal. Then, the 1PRT echo signal is segmented and distance-directed pulse compressed to reduce the total processing volume by 40%, which can significantly reduce the amount of data calculation, improve the operation speed and data processing efficiency, and save FPGA logic resources. In addition, a method of synthesizing 1000 PRTs is used to realize short-time 1s echo pulse compression preprocessing, which greatly reduces the communication data rate. In conjunction with the operation of other components of the surface scene deformation monitoring system, the system reliability is improved, ensuring that the scene deformation monitoring task can be carried out smoothly.

Description

Technical Field

[0001] The present invention relates to the technical field of radar and satellite navigation, and in particular to an echo segmented pulse compression method at a high sampling rate based on FPGA. Background Art

[0002] Beidou-based three-dimensional deformation monitoring technology for surface scenes is an important means of monitoring and early warning for geological hazards such as landslides. Equipment deployed outside the monitoring area receives reflected signals and monitors surface scene deformation, addressing the spatial discontinuity of differential satellite navigation deformation monitoring. Baseband signal processing for surface scene monitoring involves synchronous sampling of intermediate frequency (IF) signals and online real-time processing. This includes capturing, tracking, and positioning the direct-arrival signal, as well as time-frequency synchronization, phase synchronization, and pulse compression of the echo signal. The time-frequency correspondence of the Beidou signal's CA code waveform differs significantly from that of the chirp signal, leading to limitations in the traditional 20% oversampling of chirp signals. To improve imaging range resolution and minimize signal-to-noise ratio loss, Beidou signals must be sampled within a 40MHz bandwidth, resulting in a sampling rate greater than 80MHz. Furthermore, pulse compression of the short, 1s echo signal is required to reduce the communication data rate. In traditional processing methods, the entire signal after ADC sampling is usually directly subjected to FFT and IFFT. This method requires too much calculation and a long processing time, which may take 5 hours. It is inefficient and cannot be implemented in hardware. Summary of the Invention

[0003] In view of this, the present invention provides an echo segmented pulse compression method at a high sampling rate based on FPGA, which can perform real-time pulse compression processing on the echo signal, has high processing efficiency, and can reduce the data processing volume and communication data volume. It is achievable in hardware and can be used for engineering applications.

[0004] To improve imaging range resolution and minimize signal-to-noise ratio loss, the direct wave and echo Beidou signals are sampled within a 40MHz bandwidth, including the main lobe and first sidelobe. To prevent aliasing, a 124MHz clock is used for sampling, resulting in real signals with a data rate of 124MHz. To reduce data processing, the sampled digital real signals are pre-processed by downsampling. After decimation, the 124MHz direct wave and echo digital real signals are converted to 62MHz direct wave and echo digital IQ signals. Standard navigation processing, including acquisition, tracking, and position determination, is performed on the direct wave IQ signals. The direct wave tracking loop obtains the accurate Doppler frequency, which is then synchronously used to perform carrier orthogonal down-conversion of the direct wave and echo IQ signals. The down-converted echo IQ signals and the local CA code signal of the direct wave undergo short 1ms range-directed pulse compression. If the complete 1ms echo data is directly pulse compressed, the sampling point count is 62,000. Performing a 62,000-point FFT in an FPGA is extremely complex and obviously impractical. Therefore, a segmented echo pulse compression method is proposed. This streamlined approach reduces the number of pulse compression points by segmenting the 1ms pulse compression. Since the 1ms pulse is decimated by 2, its length is 62,000 points. The 1ms echo sampling data is divided into 50 segments, each 20us segment having a length of 1240 points. Therefore, a 2048-point FFT is required. The 50 20us pulse compression results are coherently accumulated, and the result is the pulse compression result for the 1ms echo. To ensure accurate imaging results, atmospheric phase removal at the transmitter is required. Therefore, phase compensation is performed after each 1ms pulse compression. The coherent accumulation of 1000 phase-compensated 1ms echo pulse compression results is combined. The combined pulse compression result of 1000 PRTs is the final processed 1s echo pulse compression result. Using 1-second echo pulse compression preprocessing can significantly reduce the amount of data transmitted between the device and the edge, which is of great significance for the practical application and engineering of equipment. This segmented pulse compression can significantly reduce the amount of data calculation, increase the operation speed, and save FPGA resources.

[0005] The specific steps of the FPGA-based high sampling rate echo segmented pulse compression method of the present invention are as follows:

[0006] S1. The receiver converts the received direct wave and echo RF signals into intermediate frequency analog signals through the RF module circuit. The analog intermediate frequency is 91.48MHz.

[0007] S2, using a 124MHz clock and a 14-bit quantized ADC triggered by the same rising edge, performs synchronous intermediate frequency sampling on the Beidou direct wave and echo signal within a 40MHz bandwidth, including the main lobe and the first side lobe. The digital intermediate frequency after sampling is 32.52MHz.

[0008] S3, performing downsampling preprocessing on the sampled direct wave and echo digital real signal, the specific steps include:

[0009] S31, synchronously storing the direct wave and echo signal with a data rate of 124 MHz and an intermediate frequency of 32.52 MHz into a multi-channel data FIFO buffer for cross-clock domain processing;

[0010] S32, perform DC removal averaging on the direct wave and echo signal every 2048 points;

[0011] S33. Use the same carrier frequency of 32.5 MHz to synchronously perform down-conversion on the direct wave and the echo signal. The direct wave and the echo signal after down-conversion are IQ signals with an intermediate frequency of 20 kHz respectively.

[0012] S34, preventing spectrum aliasing when extracting the signal, and performing low-pass filtering on the direct wave and echo IQ signal;

[0013] S35, performing 2-out-of-1 processing on the direct wave and echo signal after low-pass filtering, extracting the down-sampled signal with a data rate of 62 MHz, sending it to the FIFO buffer, and reading it out with the divided 62 MHz clock;

[0014] S36. The extracted direct wave and echo signals enter the AGC module for automatic gain amplification and truncation processing; the direct wave signal output by the AGC is sent to the capture and tracking module, and the echo signal output by the AGC is sent to the pulse compression module.

[0015] S4, the direct wave signal is quickly captured and tracked, the Doppler frequency of the direct wave signal is obtained by tracking the carrier loop, and the direct wave and echo signal are synchronously subjected to carrier orthogonal down-conversion processing using the Doppler frequency;

[0016] S5. Perform short-time 1PRT range-wise segmented pulse compression processing on the echo signal after carrier stripping and the local CA code of the direct wave signal. The specific steps include:

[0017] S51. After downsampling preprocessing, the echo signal sampling rate is 62MHz. In order to meet the requirement of the actual application scenario of the system that the monitoring distance is greater than 2km, the following calculation is used:

[0018]

[0019] Where c is the speed of light, t is the sampling time, and f s is the sampling rate of the echo signal after downsampling;

[0020] The number of points of 1ms echo data is f s *1e -3 Point, the 1ms echo data is segmented and the number of points N in each pulse pressure segment is greater than L*f s / c points, so the number of points calculated by FFT is N fft point, where N fft Take L*f upwards s / cThe value of the nearest integer power of 2;

[0021] S52: The direct wave channel outputs a CA code cycle start pulse every 1ms. This pulse periodically divides the echo signal. When this pulse arrives, the 1ms echo signal and one period of the local CA code signal are synchronously read. The 1ms echo signal is divided into 50 segments. At the start of each segment, 2048 points of data are read sequentially. The local CA code signal is divided into 50 segments, each segment containing 1240 points, with the last 808 points padded with zeros. The read echo data for each segment and the direct wave CA code data are stored in ping-pong DRAM.

[0022] S53, the 20us echo data and direct wave CA code data read from the Ping-Pong DRAM are pulse compressed using a frequency domain method. The 20us pulse compression principle block diagram is shown in the figure. Figure 2 As shown in the figure, the echo signal is subjected to a 2048-point FFT calculation, and the direct wave CA code signal is subjected to a 2048-point FFT calculation and conjugated. The echo FFT calculation result and the conjugate result of the direct wave CA code FFT calculation are complex multiplied, and then an IFFT operation is performed to output the echo 20us pulse compression result data.

[0023] The S54 and FFT modules use a 214MHz clock. To save FPGA logic resources, the FFT module is time-division multiplexed within 20us, and the Ping-Pong DRAM is also multiplexed;

[0024] S55, coherently accumulate the compression results of 50 adjacent 20us echo pulses to obtain the echo range pulse compression result of each 1ms;

[0025] S6. To remove the influence of the atmospheric phase at the transmitting end, the direct wave compensation phase is obtained in the direct wave channel and conjugate multiplied to compensate for the echo pulse compression result every 1ms.

[0026] S7. To significantly reduce the amount of data transmitted between the edge and the device, simulations have demonstrated that 1000 PRTs are performed on the 1ms echo pulse compression data. This means that 1000 phase-compensated 1ms echo pulse compression results are coherently accumulated. After the accumulation, the first 800 points of data are taken to output the 1s echo pulse compression result.

[0027] S8. Quantify and package the echo 1s pulse compression result data and upload it through the Gigabit Ethernet port.

[0028] Beneficial effects:

[0029] The signal sampled by the 124MHz ADC is pre-processed by downsampling, reducing the sampling rate to 62MHz without spectral aliasing. The 1PRT echo signal is then segmented and pulse-compressed, reducing the total processing throughput by 40%. This significantly reduces the amount of data computation, improves computational speed and data processing efficiency, and conserves FPGA logic resources. Furthermore, a method for synthesizing 1000 PRTs is used to achieve short-duration 1s echo pulse compression pre-processing, significantly reducing the communication data rate. This, in conjunction with other components of the surface scene deformation monitoring system, improves system reliability and ensures the smooth execution of the scene deformation monitoring task. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Flowchart for downsampling preprocessing of direct wave echo signal;

[0031] Figure 2 This is the block diagram of the echo 20us pulse compression principle;

[0032] Figure 3 This is the principle block diagram for implementing echo 1s pulse compression;

[0033] Figure 4 Design diagram for low-pass filter;

[0034] Figure 5 Schematic diagram of the time relationship of the data flow for pulse compression processing;

[0035] Figure 6 Implement the block diagram for the FFT multiplexing state machine;

[0036] Figure 7 Schematic diagram of the echo pulse compression phase compensation process;

[0037] Figure 8 This is the block diagram of the entire echo pulse compression processing FPGA implementation;

[0038] Figure 9 This is the B3I frequency pulse pressure diagram of PRN21 satellite;

[0039] Figure 10This is the pulse pressure diagram of the B2a frequency point of the PRN22 satellite;

[0040] Figure 11 This is the pulse pressure diagram of the B2b frequency point of PRN34 satellite. DETAILED DESCRIPTION

[0041] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0042] The present invention provides an FPGA-based high sampling rate echo segmented pulse compression method, comprising the following steps:

[0043] S1. The receiver converts the received direct wave and echo RF signals into intermediate frequency analog signals through the RF module circuit. The analog intermediate frequency is 91.48MHz.

[0044] S2, the intermediate frequency synchronous ADC is triggered by the same rising edge and performs synchronous intermediate frequency sampling on the Beidou direct wave and echo signal within the 40MHz bandwidth, including the main lobe and the first side lobe;

[0045] The ADC input is a multi-channel analog intermediate frequency signal with a sampling rate of 124MHz and a quantization bit number of 14 bits. The output is a multi-channel intermediate frequency digital signal with a digital intermediate frequency of 32.52MHz.

[0046] S3, perform downsampling preprocessing on the sampled direct wave and echo digital real signal. The downsampling preprocessing flow chart is as follows: Figure 1 As shown, the specific steps include:

[0047] S31, synchronously storing the direct wave and echo signal with a data rate of 124 MHz and an intermediate frequency of 32.52 MHz into a multi-channel data FIFO buffer for cross-clock domain processing;

[0048] After synchronous acquisition, the echo and direct waves are directly stored in a FIFO with a bit width twice the ADC bit width. The FIFO write clock is the ADC sampling clock, and the FIFO read clock is the operating clock with the same frequency as the write clock.

[0049] S32, perform DC removal averaging on the direct wave and echo signal every 2048 points;

[0050] The direct wave and echo signals read from the FIFO are averaged every 2048 points. The previous average value is subtracted from the data of each point of the direct wave and echo signals to remove DC.

[0051] S33. Use the same carrier frequency of 32.5 MHz to synchronously perform down-conversion on the direct wave and the echo signal. The direct wave and the echo signal after down-conversion are IQ signals with an intermediate frequency of 20 kHz respectively.

[0052] The DDC (Digital Down Converson) module directly uses the sin and cos values ​​output by the DDS (Direct Digital Synthetic) in the capture and tracking module to multiply the direct wave and echo respectively to obtain the direct wave and echo I and Q branch signals.

[0053] S34, preventing spectrum aliasing when extracting the signal, and performing low-pass filtering on the direct wave and echo IQ signal;

[0054] The low-pass filter is designed in Matlab using an FIR digital filter with a sampling rate of 124MHz, a passband cutoff frequency of 20MHz, and a stopband cutoff frequency of 25MHz. The order of the filter is 63. The low-pass filter design is as follows: Figure 4 As shown in the figure, the coefficients of the designed filter are quantized to 16 bits in MATLAB and then the COE coefficient file is output and loaded into the FIR IP core in the FPGA for use.

[0055] S35, performing 2-out-of-1 processing on the direct wave and echo signal after low-pass filtering, extracting the down-sampled signal with a data rate of 62 MHz, sending it to the FIFO buffer, and reading it out with the divided 62 MHz clock;

[0056] The 124MHz is divided by 2, and the 62MHz clock after division is used to perform 2-to-1 extraction on the direct wave and echo signal after low-pass filtering. The extracted data is sent to the FIFO for buffering. The write clock of the FIFO is 124MHz before division, and the read clock of the FIFO is 62MHz after division.

[0057] S36. The extracted direct wave and echo signals enter the AGC (Automatic Gain Control) module for automatic gain amplification and truncation processing; the direct wave signal output by the AGC is sent to the capture and tracking module, and the echo signal output by the AGC is sent to the pulse compression module.

[0058] S4, the direct wave signal is quickly captured and tracked, the Doppler frequency of the direct wave signal is obtained by tracking the carrier loop, and the direct wave and echo signal are synchronously subjected to carrier orthogonal down-conversion processing using the Doppler frequency;

[0059] The DDC module directly uses the sin and cos values ​​output by the DDS in the capture and tracking module and multiplies them with the direct wave and echo, respectively, to obtain the direct wave and echo I and Q branch signals. After tracking is initiated, these two signals are stored in DRAM. After the aforementioned 2x decimation, the sampling rate is 62Msps. The purpose of downconversion is to convert the direct wave and echo real signals into IQ quadrature signals, so that subsequent decimation of the IQ signals will not cause spectral aliasing.

[0060] S5. Perform short-time 1PRT range-wise segmented pulse compression processing on the echo signal after carrier stripping and the local CA code of the direct wave signal. The specific steps include:

[0061] S51. After downsampling preprocessing, the echo signal sampling rate is 62MHz. In order to meet the requirement of the actual application scenario of the system that the monitoring distance is greater than 2km, the following calculation is used:

[0062]

[0063] Where c = 3.0*10 8 , f s =62MHz, so the effective pulse compression points should be greater than 414 points. The number of points of 1ms echo data is 62000. The 1ms echo data is divided into 50 segments, and the number of points of each 20us data segment is 1240. Therefore, the number of points calculated by FFT is 2048 points.

[0064] S52: The direct wave channel outputs a CA code cycle start pulse every 1ms. This pulse periodically divides the echo signal. When this pulse arrives, the 1ms echo signal and one period of the local CA code signal are synchronously read. The 1ms echo signal is divided into 50 segments. At the start of each segment, 2048 points of data are read sequentially. The local CA code signal is divided into 50 segments, each segment containing 1240 points, with the last 808 points padded with zeros. The read echo data for each segment and the direct wave CA code data are stored in ping-pong DRAM.

[0065] After stable tracking, the code NCO module outputs a start pulse at the 1ms start position of each CA code. The pulse compression module uses this pulse as the start signal for DRAM ping-pong storage. Each DRAM has 2048 points of storage space, and with a 20µs compression calculation, switching occurs once 2048 points of echo data are stored. The code NCO module generates a local CA code. After pulse compression is activated, the CA code is resampled and synchronously stored in DRAM with a 20µs cycle. The first 1240 points in DRAM are valid data, and the remaining 808 points in RAM are filled with zeros.

[0066] S53, the 20us echo data and direct wave CA code data read from the Ping-Pong DRAM are pulse compressed using a frequency domain method. The 20us pulse compression principle block diagram is shown in the figure. Figure 2 As shown in the figure, the echo signal is subjected to a 2048-point FFT calculation, and the direct wave CA code signal is subjected to a 2048-point FFT calculation and conjugated. The echo FFT calculation result and the conjugate result of the direct wave CA code FFT calculation are complex multiplied, and then an IFFT operation is performed to output the echo 20us pulse compression result data.

[0067] When a DRAM is fully written, the FFT module is started. The DRAM read and FFT operating clock is 124MHz. The FFT module directly uses the Xilinx IP core, and the RAM read address range is 0 to 2047, which is used as the index value of the FFT module input after delay. The FFT results of the direct wave and the echo are respectively multiplied by the conjugate of the FFT of the local CA code. After the complex multiplication results of the two are beat, they are used as the input of the subsequent IFFT data end. The index of the IFFT input data is delayed accordingly based on the front-end FFT output index and the number of delay cycles of the intermediate complex multiplication operation. The IFFT calculation results and the back-end DRAM read data are accumulated and cyclically stored in the DRAM. After each 1ms cycle, the DRAM is reset to ensure that the first accumulated DRAM output result is 0.

[0068] The S54 and FFT modules use a 214MHz clock. To save FPGA logic resources, the FFT module is time-division multiplexed within 20us, and the Ping-Pong DRAM is also multiplexed;

[0069] The time relationship of the signal pulse compression processing data flow is as follows Figure 5 As shown. The two-channel FFT module is time-division multiplexed within 20us, and the write of RAM1 to RAM4 needs to be multiplexed. In FPGA, the multiplexing of FFT modules is realized through state machine control. The block diagram of FFT multiplexing state machine is shown in Figure 6 shown.

[0070] S55, coherently accumulate the compression results of 50 adjacent 20us echo pulses to obtain the echo range pulse compression result of each 1ms;

[0071] After the IFFT result is accumulated 50 times, the result is multiplied by the coefficient and then accumulated with the data read from the back-end DRAM and stored in the DRAM in a circular manner.

[0072] S6. In order to remove the influence of the atmospheric phase at the transmitting end, the direct wave compensation phase is obtained in the direct wave channel and conjugate multiplied to compensate for the echo pulse compression result every 1ms. The schematic diagram of the echo pulse compression phase compensation process is shown as follows: Figure 7 As shown;

[0073] S7. In order to significantly reduce the amount of data transmitted between the end and the edge, a simulation demonstrates that 1000 PRTs are synthesized for the 1ms echo pulse compression data. That is, 1000 phase-compensated 1ms echo pulse compression results are coherently accumulated. After the accumulation, the first 800 points of data are taken to output the echo 1s pulse compression result. The principle block diagram of the echo 1s pulse compression implementation is shown in the figure. Figure 3 As shown;

[0074] After each 1000ms cycle, the DRAM is reset to ensure that the first accumulated DRAM output result is 0.

[0075] The entire echo pulse compression processing FPGA implementation block diagram is as follows Figure 8 shown.

[0076] S8. Quantify and package the echo 1s pulse compression result data and upload it through the Gigabit Ethernet port.

[0077] After the 1000ms calculation is complete, the results are written to DRAM accessible via the AXI bus, and a corresponding interrupt is sent to the software to initiate data reading. The calculation results and positioning results are packaged and transmitted via the network port. The data format is 32 bits for each I and Q channel, with a data size of 800*2*32 bits. The entire data package covers a length of 1 second.

[0078] The following is an example to illustrate the effect of the FPGA-based high sampling rate echo segmented pulse compression method of the present invention.

[0079] Figures 9 to 11 For echo pulse compression test results, the eight-satellite three-frequency direct wave antenna power is divided into two paths, one connected to the direct wave channel and the other to the echo channel test. Figure 9 This is the PRN21 satellite B3I frequency pulse pressure diagram. Figure 10 This is the pulse pressure diagram of the B2a frequency point of PRN22 satellite. Figure 11 This is the pulse compression diagram of the B2b frequency point of the PRN34 satellite. From the above three figures, it can be seen that the peak values ​​of the pulse compression results of the eight channels of the eight satellites all appear at the first point, and the peak values ​​of the pulse compression results of the three frequency points also appear at the first point, which is consistent with the theoretical pulse compression results.

[0080] By conducting an eight-satellite three-frequency direct wave power division test and collecting 600s of data, the peak point phase standard deviation of 600 sets of pulse compression results at the eight-satellite three-frequency points was obtained to verify the phase of the echo pulse compression results, as shown in Tables 1 to 3. It can be seen that the peak point phase standard deviation of 600 sets of pulse compression results at the eight-satellite three-frequency points is less than 1 degree, meeting the design requirements and demonstrating high processing efficiency and accuracy.

[0081] Table 1. Peak point phase standard deviation test results of eight-star 600s pulse compression results at frequency B3

[0082]

[0083]

[0084] Table 2B2a frequency point eight-star 600s pulse compression results peak point phase standard deviation test results

[0085]

[0086] Table 3 Test results of peak point phase standard deviation of eight-star 600s pulse compression results at B2b frequency

[0087]

[0088] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high sampling rate echo segmented pulse compression method based on FPGA, characterized in that: include: Step 1: Convert the received direct wave and echo RF signals into intermediate frequency analog signals, where the analog intermediate frequency is 91.48 MHz. Step 2: Using a 124MHz clock and a 14-bit quantized ADC, the Beidou direct wave and echo signals within a 40MHz bandwidth, including the main lobe and the first side lobe, are synchronously sampled at an intermediate frequency. The digital intermediate frequency after sampling is 32.52MHz. Step 3: downsample the sampled direct wave and echo digital real signals by a factor of 2 to convert them into complex signals; Step 4: Rapidly capture and track the direct wave signal processed in step 3, obtain the Doppler frequency of the direct wave signal by tracking the carrier loop, and use the Doppler frequency to synchronously perform carrier orthogonal down-conversion processing on the direct wave and echo signal; Step 5: Perform short-time 1PRT range-wise segmented pulse compression processing on the echo signal after carrier stripping and the local CA code of the direct wave signal; Step 6: Obtain the direct wave compensation phase in the direct wave channel, and perform conjugate multiplication to compensate for it in the echo pulse compression result of every 1ms; Step 7: Coherently accumulate the 1000 phase-compensated 1ms echo pulse compression results, and take the first 800 points of data to output the echo 1s pulse compression result; Step 8: quantize and package the echo 1s pulse compression result data and upload it through the Gigabit Ethernet port.

2. The method according to claim 1, wherein In step 2, the ADC performs synchronous sampling on the direct wave and the echo signal under the same rising edge triggering.

3. The method according to claim 1, wherein In step 3, the downsampling preprocessing is specifically as follows: S31, synchronously storing the direct wave and echo signal acquired in step 2 into a FIFO buffer with a bit width of twice the ADC bit width; the FIFO write clock is the ADC sampling clock, and the FIFO read clock is a working clock with the same frequency as the write clock; S32, the direct wave and echo signals read from the FIFO are averaged every 2048 points, the data of each point of the direct wave and echo signals are subtracted from the previous average value, and DC removal processing is performed on the direct wave and echo signals; S33, capturing the carrier of the direct wave, and using the carrier to synchronously perform lower sideband processing on the direct wave and echo signals to obtain direct wave and echo IQ signals with an intermediate frequency of 20 kHz; S34, performing low-pass filtering on the direct wave and echo IQ signals; S35, divide the 124 MHz by 2, and use the divided 62 MHz clock to perform 2-to-1 decimation on the direct wave and echo IQ signals after low-pass filtering. The decimated data is buffered in the FIFO. The write clock of the FIFO is 124 MHz before the frequency division, and the read clock of the FIFO is 62 MHz after the frequency division. S36: The extracted direct wave and echo signal enter the AGC module for automatic gain amplification and truncation processing.

4. The method according to claim 3, wherein In the S34, the low-pass filter is designed in MATLAB, using an FIR digital filter with a sampling rate of 124 MHz, a passband cutoff frequency of 20 MHz, and a stopband cutoff frequency of 25 MHz. The order of the low-pass filter is 63. The coefficients of the designed filter are quantized to 16 bits in MATLAB and then a coe coefficient file is output, which is loaded into the FIR IP core in the FPGA for use.

5. The method according to claim 1, wherein In step 3, the DDC module directly uses the sin and cos values ​​output by the DDS in the capture and tracking module to multiply them with the direct wave and echo respectively to obtain the direct wave and echo I and Q branch signals. After starting tracking, the two signals are stored in DRAM. After the above-mentioned 2x decimation, the sampling rate is 62Msps.

6. The method according to claim 1, wherein The step 5 specifically includes: S51. Calculate the number of effective pulse compression points N based on the monitoring distance L required in the actual application scenario of the system: Where c is the speed of light, t is the sampling time, and f s is the sampling rate of the echo signal after downsampling in step 3; S52. After stable tracking, the direct wave channel outputs a CA code period start pulse every 1ms. This pulse divides the echo signal periodically. When this pulse arrives, the 1ms echo signal and a period of local CA code signal are synchronously read; the 1ms echo signal is segmented and N segments are read sequentially from the starting position of each segment. fft Point data, the local CA code signal of each cycle is segmented and each segment of data is L*f s / c point, followed by N fft -L*f s / c point fills with zero; where N fft Take L*f upwards s / c is the value of the nearest integer power of 2; each echo data and direct wave CA code data read is stored in Ping-Pong DRAM; S53. When a DRAM is fully written, the FFT module is started; the DRAM reading and FFT working clock is 124MHz; the FFT module directly uses the Xilinx IP core, and the RAM reading address range is 0 to 2047, which is used as the index value of the FFT module input after delay; the FFT results of the direct wave and the echo wave are respectively multiplied by the conjugate of the FFT of the local CA code; the complex multiplication results of the two are beat and used as the input of the post-stage IFFT data end, and the index of the IFFT input data is delayed accordingly according to the front-end FFT output index and the delay cycle number of the intermediate complex multiplication operation; the calculation result of the IFFT and the accumulation of the back-end DRAM read data are cyclically stored in the DRAM; after each 1ms cycle, the DRAM is reset to ensure that the first accumulated DRAM output result is 0; Among them, the FFT module clock uses 214MHz; the FFT modules of the direct wave channel and the echo signal channel are time-division multiplexed within 20us; S54. Coherently accumulate the compression results of 50 adjacent 20 us echo pulses to obtain the echo distance pulse compression result of each 1 ms.

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