Multi-chip upgrading method and system, control device and storage medium

Abstract

The invention relates to the technical field of computers, particularly provides a multi-chip upgrading method and system, a control device and a storage medium, and aims to solve the technical problem of low upgrading efficiency for different chips in the prior art. In order to achieve the purpose, the multi-chip upgrading method comprises the steps that in response to a received preset request, a first chip obtains an upgrading file corresponding to a to-be-upgraded chip; and based on a preset transmission protocol, the first chip transmits the upgrading file to a corresponding to-be-upgraded chip, so that the to-be-upgraded chip is upgraded based on the received upgrading file. Through the application, the upgrading file of the to-be-upgraded chip can be transmitted to each to-be-upgraded chip through the preset transmission protocol by using the first chip, and different tools do not need to be used for upgrading different chips, so that the upgrading efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and specifically provides a multi-chip upgrade method, system, control device and storage medium. Background Art

[0002] Regional integration of automotive functions is a mainstream trend in the development of current automotive controllers, which is mainly to integrate different functions and systems within the vehicle to provide a more coordinated, intelligent and user-friendly automotive experience. This integration usually involves the integration of vehicle software, hardware, sensors and communication technologies.

[0003] The integration at the hardware level integrates chips of different types, architectures and performance into the same controller. Each chip runs different software, and the communication methods between and within these chips are also different. Every time developers and testers update the software, they need to use different tools to upgrade different chips (cores), which is cumbersome and time-consuming.

[0004] Accordingly, the art needs a new multi-chip upgrade method, system, control device and storage medium solution to solve the above problems. Summary of the invention

[0005] In order to overcome at least one of the above-mentioned defects, the present application is proposed to provide a multi-chip upgrade method, system, control device and storage medium that solve or at least partially solve the technical problem of low upgrade efficiency of different chips in the prior art.

[0006] In a first aspect, the present application provides a multi-chip upgrade method, the method comprising: in response to a received preset request, a first chip obtains an upgrade file corresponding to a chip to be upgraded; based on a preset transmission protocol, the first chip transmits the upgrade file to the corresponding chip to be upgraded, so that the chip to be upgraded is upgraded based on the received upgrade file.

[0007] Through the above technical solution, the first chip can be used to transmit the upgrade file of the chip to be upgraded to each chip to be upgraded using a preset transmission protocol, without using different tools to upgrade different chips, thereby improving the upgrade efficiency.

[0008] In a technical solution of the above-mentioned multi-chip upgrade method, the first chip includes at least a first core and a second core, wherein the performance of the first core is not weaker than the performance of the second core, and the first chip transmits the upgrade file to the corresponding chip to be upgraded based on a preset transmission protocol, including: based on the preset transmission protocol, the first chip transmits the second upgrade file to the second chip through the second core, wherein the second upgrade file is the upgrade file corresponding to the second chip in the upgrade file, and the performance of the first chip is not weaker than that of the second chip.

[0009] Through the above technical solution, the core with relatively weaker performance in the first chip is used to undertake data transmission with the chip with relatively weaker performance, thereby achieving the effect of reasonable configuration and utilization of chip resources.

[0010] In a technical solution of the above-mentioned multi-chip upgrade method, based on a preset transmission protocol, the first chip transmits the upgrade file to the corresponding chip to be upgraded, which also includes: based on the preset transmission protocol, the first chip transmits a third upgrade file to a third chip through the first core, wherein the third upgrade file is an upgrade file in the upgrade file corresponding to the third chip, and the performance of the third chip is not weaker than that of the first chip.

[0011] Through the above technical solution, the core with relatively strong performance in the first chip is used to undertake data transmission with the chip with relatively strong performance, thereby achieving the effect of reasonable configuration and utilization of chip resources.

[0012] In a technical solution of the above-mentioned multi-chip upgrade method, the upgrade file acquired by the first chip is stored in a preset unit, wherein the preset unit is communicatively connected with the first core.

[0013] Through the above technical solution, all the upgrade files are stored in the preset unit, and a communication connection is established with the preset unit through the first kernel with relatively strong performance, thereby ensuring the efficiency of extracting files.

[0014] In a technical solution of the above-mentioned multi-chip upgrade method, the first chip transmits the second upgrade file to the second chip through the second core, including: based on the preset transmission protocol, the first chip transmits the second upgrade file to the second core through the first core, so that the first chip transmits the second upgrade file to the second chip through the second core based on the preset transmission protocol.

[0015] In a technical solution of the above-mentioned multi-chip upgrade method, if the first chip is the chip to be upgraded, the method also includes: the first chip upgrades the first core based on the upgrade file corresponding to the first core, and / or, based on the preset transmission protocol, the first chip transmits the upgrade file corresponding to the second core to the second core through the first core, so that the first chip upgrades the second core based on the upgrade file received by the second core.

[0016] In a technical solution of the above-mentioned multi-chip upgrade method, based on a preset transmission protocol, the first chip transmits the upgrade file to the corresponding chip to be upgraded, so that before the chip to be upgraded is upgraded based on the received upgrade file, the method also includes: the first chip determines whether the current upgrade environment meets the preset upgrade conditions, and if so, executes subsequent steps.

[0017] Through the above technical solution, before executing the upgrade program, it is determined whether the current system environment is suitable for upgrading. The upgrade steps will only be executed if it is suitable for upgrading. By detecting the current upgrade environment, it is ensured that the upgrade process can be successfully executed.

[0018] In a second aspect, the present application provides a multi-chip upgrade system, the system comprising at least a first chip, wherein the first chip is configured to: obtain an upgrade file corresponding to the chip to be upgraded in response to a received preset request; and transmit the upgrade file to the corresponding chip to be upgraded based on a preset transmission protocol, so that the chip to be upgraded is upgraded based on the received upgrade file.

[0019] In a third aspect, a control device is provided, which includes a processor and a memory, wherein the memory is suitable for storing multiple program codes, and the program codes are suitable for being loaded and run by the processor to execute the multi-chip upgrade method described in any one of the technical solutions of the above-mentioned multi-chip upgrade method.

[0020] In a fourth aspect, a computer-readable storage medium is provided, which stores a plurality of program codes, wherein the program codes are suitable for being loaded and run by a processor to execute the multi-chip upgrade method described in any one of the technical solutions of the multi-chip upgrade method. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The disclosure of the present application will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present application. In addition, similar numbers in the drawings are used to represent similar components, among which:

[0022] Figure 1 It is a flowchart of the main steps of a multi-chip upgrade method according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of an application scenario of a multi-chip upgrade method according to an embodiment of the present application;

[0024] Figure 3 is a data interaction diagram of a multi-chip upgrade method according to an embodiment of the present application;

[0025] Figure 4 It is a schematic diagram of the main structure block diagram of a multi-chip upgrade system according to an embodiment of the present application.

[0026] Reference numerals list :

[0027] 11: first chip; 12: chip 1 to be upgraded; 13: chip 2 to be upgraded; 14: chip n to be upgraded. DETAILED DESCRIPTION

[0028] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the protection scope of the present application.

[0029] In the description of the present application, "module" and "processor" may include hardware, software or a combination of the two. A module may include hardware circuits, various suitable sensors, communication ports, memory, and may also include software parts, such as program code, or a combination of software and hardware. The processor may be a central processing unit, a microprocessor, an image processor, a digital signal processor or any other suitable processor. The processor has data and / or signal processing functions. The processor may be implemented in software, hardware or a combination of the two. Non-temporary computer-readable storage media include any suitable medium that can store program code, such as a disk, a hard disk, an optical disk, a flash memory, a read-only memory, a random access memory, etc. The term "A and / or B" means all possible combinations of A and B, such as only A, only B or A and B. The term "at least one A or B" or "at least one of A and B" has a similar meaning to "A and / or B" and may include only A, only B or A and B. The singular terms "one" and "the" may also include plural forms.

[0030] Please refer to the attached Figure 1 , Figure 1 FIG. 1 is a flow chart of the main steps of a multi-chip upgrade method according to an embodiment of the present application. Figure 1 As shown, the multi-chip upgrade method of the present application at least includes steps S1 and S2:

[0031] Step S1: In response to a received preset request, the first chip obtains an upgrade file corresponding to the chip to be upgraded;

[0032] Step S2: Based on a preset transmission protocol, the first chip transmits the upgrade file to the corresponding chip to be upgraded, so that the chip to be upgraded is upgraded based on the received upgrade file.

[0033] exist Figure 1 In the illustrated embodiment, the preset request refers to a chip upgrade request, or the preset request may also be a request containing information that the chip can be upgraded, that is, the preset request does not only refer to the request information actively sent by the chip, but may also be the inspection result generated after the first chip actively inspects the remaining chips. The first chip may be a chip to be upgraded, or a chip that does not need to be upgraded. As a chip that executes the upgrade proxy process, the first chip may be pre-specified by a technician as the first chip, or may be flexibly selected from a number of chips based on preset rules as the first chip. For example: based on preset rules, a chip whose performance meets certain requirements and has no upgrade requirements is selected as the first chip from among several chips to ensure its stability when "forwarding" the upgrade file; or, the first chip must be a chip to be upgraded to save resources of other chips that do not have upgrade requirements. As time goes by, each chip may be a chip to be upgraded, so the chip to be upgraded in this embodiment may change over time, and the first chip may also change accordingly unless it is a fixed chip pre-specified by a technician. The preset transmission protocol refers to a set of transmission protocols between the first chip and each chip to be upgraded. In some cases, the preset transmission protocol may also include transmission protocols between various parts inside the first chip, between the first chip and other external devices, cloud servers, etc.

[0034] In one embodiment, the first chip includes at least a first core and a second core, wherein the performance of the first core is not weaker than the performance of the second core; based on a preset transmission protocol, the first chip transmits the second upgrade file to the second chip through the second core, wherein the second upgrade file is an upgrade file corresponding to the second chip in the upgrade file, and the performance of the first chip is not weaker than the second chip. In this embodiment, the performance evaluation between the cores inside the chip and the performance evaluation of the chip as a whole, the specific evaluation method may include but is not limited to: running common running software to evaluate the performance according to the running score value; transmitting test files or running test programs to evaluate the performance according to the transmission time or running time; based on hardware parameters such as running memory size and cache size to evaluate the performance. Through such a setting, the performance of each core in the first chip and the performance of the first chip and each chip to be upgraded can be compared. When it is determined that there is such a second chip in the chip to be upgraded, the upgrade file is transmitted to the second chip through the second core in the first chip, which can not only enable the resource-constrained second chip to be successfully upgraded, but also make the resource allocation of the first chip more reasonable. It should be understood that this embodiment is an illustration of a scenario in which a second chip exists in the chip to be upgraded, and does not limit the implementation premise of the technical solution of the application itself to the requirement that the second chip must exist.

[0035] In one embodiment, based on a preset transmission protocol, the first chip transmits the third upgrade file to the third chip through the first kernel, wherein the third upgrade file is the upgrade file corresponding to the third chip in the upgrade file, and the performance of the third chip is not inferior to that of the first chip. In this embodiment, when it is determined that there is such a third chip in the chip to be upgraded, the upgrade file is transmitted to the third chip through the first kernel in the first chip, making full use of the performance resources of the first kernel, ensuring the transmission effect and thus improving the upgrade efficiency. It should be understood that this embodiment is an explanation of the scenario in which there is a third chip in the chip to be upgraded, and does not limit the implementation premise of the technical solution of the application itself to the existence of a third chip.

[0036] In one embodiment, the upgrade file obtained by the first chip is stored in a preset unit, wherein the preset unit is connected to the first kernel in communication. In this embodiment, the preset unit refers to a unit in a chip with a storage function, such as an eMMC storage, and its specific model is not limited here. The preset unit is connected to the first kernel in communication, and in some cases, the two can also establish a unique connection, that is, the first kernel exclusively occupies the preset unit. By establishing a communication connection, the first kernel can extract the upgrade file stored therein from the preset unit.

[0037] In one implementation of the above embodiment, the technical solution of the present application may further include: based on a preset transmission protocol, the first chip transmits the second upgrade file to the second core through the first core, so that the first chip transmits the second upgrade file to the second chip through the second core based on the preset transmission protocol. In this implementation, the first core needs to first extract the corresponding upgrade file from the preset unit.

[0038] In one embodiment, if the first chip is also a chip to be upgraded that needs to be upgraded, that is, the first kernel and / or the second kernel needs to be upgraded, the technical solution of the present application also includes: the first chip upgrades the first kernel based on the upgrade file corresponding to the first kernel, and / or, based on a preset transmission protocol, the first chip transmits the upgrade file corresponding to the second kernel to the second kernel through the first kernel, so that the first chip upgrades the second kernel based on the upgrade file received by the second kernel. In this embodiment, when the upgrade file of the second kernel is transmitted to the second kernel, the transmission protocol based on it can be the same as the transmission protocol when the second upgrade file is transmitted to the second kernel in the above embodiment, or it can be separated independently of each other, which can be flexibly set according to actual conditions, but it should be noted that when the same transmission protocol is used, the two transmission processes should be executed sequentially as much as possible to ensure the stability of the transmission process.

[0039] In one embodiment, before transferring the file to each chip, the technical solution of the present application may also include: the first chip determines whether the current upgrade environment meets the preset upgrade conditions, and if so, executes subsequent steps. In another embodiment, the first chip may also preferentially transfer the upgrade file to each chip to be upgraded, and then determine the current upgrade environment. If the upgrade conditions are met, the first chip issues an upgrade instruction to instruct each chip to be upgraded to upgrade. If the upgrade conditions are not met, the first chip issues a pause upgrade instruction or does not issue a signal with an indicative meaning, and then issues an upgrade instruction after the upgrade environment meets the conditions. The relevant user personal information that may be involved in each embodiment of the present application is strictly in accordance with the requirements of laws and regulations, follows the principles of legality, legitimacy, and necessity, and is based on the reasonable purpose of the business scenario to process personal information that users actively provide during the use of products / services or that is generated due to the use of products / services, as well as personal information obtained with user authorization.

[0040] The user personal information processed by this application will vary depending on the specific product / service scenario, and will be based on the specific scenario in which the user uses the product / service. It may involve the user's account information, device information, driving information, vehicle information or other related information. The applicant will treat the user's personal information and its processing with a high degree of diligence.

[0041] This application attaches great importance to the security of user personal information and has taken reasonable and feasible security protection measures that meet industry standards to protect user information and prevent personal information from being accessed, disclosed, used, modified, damaged or lost without authorization.

[0042] Please refer to the attached Figure 2 and attached Figure 3 ,in, Figure 2 is a schematic diagram of an application scenario of a multi-chip upgrade method according to an embodiment of the present application, Figure 3 FIG. 1 is a data interaction diagram of a multi-chip upgrade method according to an embodiment of the present application. Figure 2 As shown, the various parts in the application scenario can be described as:

[0043] The A core (first kernel) in SOC1 (first chip) has better performance and runs the non-real-time operating system GPOS. As an upgrade agent, it can obtain the upgrade package of each chip firmware through the network, and is responsible for distributing the upgraded firmware to each chip and controlling the upgrade process, and it exclusively occupies the eMMC of SOC1; the M core (second kernel) in SOC1 has poorer performance and runs the real-time operating system AUTOSAR. It is responsible for directly or indirectly processing various signals of vehicle sensors or actuators, and it exclusively occupies the Norflash and SRAM memory resources of SOC1, and can communicate with the A core through Ethernet; SOC2 (third chip) is an independent high-performance chip that runs the non-real-time operating system GPOS. It is mainly responsible for processing image processing and decision-making tasks that require a lot of computing power, and can communicate with SOC1 through Ethernet; MCU (second chip) is an independent low-cost chip that runs the real-time operating system RTOS. It is mainly responsible for collecting external signals and forwarding them to the M core of SOC1. Due to resource limitations, it uses the lower-cost SPI to communicate with the M core of SOC1.

[0044] exist Figure 2 On the basis of Figure 3 The data interaction shown can be described as:

[0045] 1. The upgrade application of GPOS1 receives the upgrade request and checks whether the current vehicle environment allows the upgrade. If so, it proceeds to the next step;

[0046] 2. The GPOS1 upgrade application initiates a firmware download request to the OTA background server via the HTTPS protocol;

[0047] 3. The GPOS1 upgrade application downloads the firmware upgrade package via the HTTPS protocol;

[0048] 4. The upgrade application of GPOS1 transfers the firmware of MCU to SRAM of SOC1 through DOIP protocol;

[0049] 5. The upgrade application of GPOS1 transfers the firmware of SOC2 to the eMMC of SOC2 through the NFS protocol;

[0050] 6. GPOS1 obtains the firmware file of SOC1 A core from the local eMMC and starts the firmware self-upgrade;

[0051] 7. After the firmware transfer of SOC2 is completed, GPOS2 starts the firmware self-upgrade;

[0052] 8. After the MCU firmware is completely transferred to the SRAM of SOC1, AUTOSAR transfers the RTOS firmware to the MCU via SPI;

[0053] 9.RTOS starts firmware upgrade;

[0054] 10. After the MCU is upgraded, the upgrade application of GPOS1 transfers the firmware of the M core to AUTOSAR through the DOIP protocol;

[0055] 11.SOC1 AUTOSAR starts M-core firmware upgrade.

[0056] exist Figure 2 and Figure 3 In one implementation shown, except for step 4 and step 10 which rely on the same DOIP channel and need to be executed sequentially, the remaining steps can be executed synchronously, and step 4, step 8 and step 9 provide a solution for upgrading resource-constrained chips in complex scenarios across chips and cores, thereby realizing firmware upgrades for the MCU.

[0057] So far, the multi-chip upgrade method of the present application has been fully described. It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effect of the present application, the different steps do not have to be executed in such an order, and they can be executed simultaneously (in parallel) or in other orders, and these changes are within the scope of protection of the present application.

[0058] Furthermore, the present application also provides a multi-chip upgrade system.

[0059] See attached Figure 4 , Figure 4 FIG. 1 is a main structural block diagram of a multi-chip upgrade system according to an embodiment of the present application. Figure 4As shown, the multi-chip upgrade system in the embodiment of the present application mainly includes a first chip 11. In some embodiments, the multi-chip upgrade system may also include a chip to be upgraded 1, a chip to be upgraded 2, and a chip to be upgraded n. In some embodiments, the first chip 11 may be configured to obtain an upgrade file corresponding to the chip to be upgraded in response to a received preset request; based on a preset transmission protocol, transmit the upgrade file to the corresponding chip to be upgraded, so that the chip to be upgraded is upgraded based on the received upgrade file.

[0060] The multi-chip upgrade system is used to perform Figure 1 The multi-chip upgrade method embodiment shown in the figure has similar technical principles, technical problems solved and technical effects produced. Technical personnel in this technical field can clearly understand that for the convenience and simplicity of description, the specific working process and related instructions of the multi-chip upgrade system can refer to the contents described in the embodiment of the multi-chip upgrade method, which will not be repeated here.

[0061] It is understood by those skilled in the art that all or part of the processes in the method for implementing the above-mentioned embodiment of the present application can also be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of each of the above-mentioned method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may include: any entity or device, medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory, random access memory, electric carrier signal, telecommunication signal and software distribution medium that can carry the computer program code. It should be noted that the content contained in the computer-readable storage medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable storage media do not include electric carrier signals and telecommunication signals.

[0062] Furthermore, the present application also provides a control device. In a control device embodiment according to the present application, the control device includes a processor and a memory, the memory can be configured to store a program for executing the multi-chip upgrade method of the above method embodiment, and the processor can be configured to execute the program in the memory, which includes but is not limited to the program for executing the multi-chip upgrade method of the above method embodiment. For ease of explanation, only the parts related to the embodiment of the present application are shown. For specific technical details not disclosed, please refer to the method part of the embodiment of the present application. The control device can be a control device device formed by various electronic devices.

[0063] Furthermore, the present application also provides a computer-readable storage medium. In a computer-readable storage medium embodiment according to the present application, the computer-readable storage medium can be configured to store a program for executing the multi-chip upgrade method of the above-mentioned method embodiment, and the program can be loaded and run by the processor to implement the above-mentioned multi-chip upgrade method. For ease of explanation, only the parts related to the embodiment of the present application are shown. For specific technical details not disclosed, please refer to the method part of the embodiment of the present application. The computer-readable storage medium can be a memory device formed by various electronic devices. Optionally, the computer-readable storage medium in the embodiment of the present application is a non-temporary computer-readable storage medium.

[0064] Further, it should be understood that since the setting of each module is only for illustrating the functional units of the device of the present application, the physical devices corresponding to these modules may be the processor itself, or a part of the software in the processor, a part of the hardware, or a part of the combination of software and hardware. Therefore, the number of each module in the figure is only schematic.

[0065] It is understood by those skilled in the art that each module in the device can be adaptively split or merged. Such splitting or merging of specific modules will not cause the technical solution to deviate from the principle of the present application, and therefore, the technical solutions after splitting or merging will fall within the protection scope of the present application.

[0066] So far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present application.

Claims

1. A multi-chip upgrade method, characterized in that: The method comprises: In response to the received preset request, the first chip obtains an upgrade file corresponding to the chip to be upgraded; Based on a preset transmission protocol, the first chip transmits the upgrade file to the corresponding chip to be upgraded, so that the chip to be upgraded is upgraded based on the received upgrade file.

2. The multi-chip upgrade method according to claim 1, characterized in that: The first chip includes at least a first core and a second core, wherein the performance of the first core is not weaker than the performance of the second core, and the first chip transmits the upgrade file to the corresponding chip to be upgraded based on the preset transmission protocol, comprising: Based on the preset transmission protocol, the first chip transmits the second upgrade file to the second chip through the second core, wherein the second upgrade file is the upgrade file corresponding to the second chip in the upgrade file, and the performance of the first chip is not weaker than that of the second chip.

3. The multi-chip upgrade method according to claim 2, characterized in that: The first chip transmitting the upgrade file to the corresponding chip to be upgraded based on the preset transmission protocol further includes: Based on the preset transmission protocol, the first chip transmits the third upgrade file to the third chip through the first kernel, wherein the third upgrade file is the upgrade file corresponding to the third chip in the upgrade files, and the performance of the third chip is not weaker than that of the first chip.

4. The multi-chip upgrade method according to claim 2, characterized in that: The upgrade file acquired by the first chip is stored in a preset unit, wherein the preset unit is in communication connection with the first core.

5. The multi-chip upgrade method according to claim 4, characterized in that: The first chip transmitting the second upgrade file to the second chip through the second core includes: Based on the preset transmission protocol, the first chip transmits the second upgrade file to the second core through the first core, so that the first chip transmits the second upgrade file to the second chip through the second core based on the preset transmission protocol.

6. The multi-chip upgrade method according to claim 4, characterized in that: If the first chip is the chip to be upgraded, the method further includes: The first chip upgrades the first kernel based on the upgrade file corresponding to the first kernel, and / or, Based on the preset transmission protocol, the first chip transmits the upgrade file corresponding to the second kernel to the second kernel through the first kernel, so that the first chip upgrades the second kernel based on the upgrade file received by the second kernel.

7. The multi-chip upgrade method according to claim 1, characterized in that: Based on the preset transmission protocol, before the first chip transmits the upgrade file to the corresponding chip to be upgraded so that the chip to be upgraded is upgraded based on the received upgrade file, the method further includes: The first chip determines whether the current upgrade environment meets the preset upgrade conditions, and if so, executes subsequent steps.

8. A multi-chip upgrade system, characterized in that: The system includes at least a first chip, wherein the first chip is configured to: obtain an upgrade file corresponding to the chip to be upgraded in response to a received preset request; and transmit the upgrade file to the corresponding chip to be upgraded based on a preset transmission protocol, so that the chip to be upgraded is upgraded based on the received upgrade file.

9. A control device, comprising a processor and a memory, wherein the memory is suitable for storing a plurality of program codes, characterized in that: The program code is suitable for being loaded and run by the processor to execute the multi-chip upgrading method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a plurality of program codes, characterized in that: The program code is suitable for being loaded and run by a processor to execute the multi-chip upgrading method according to any one of claims 1 to 7.

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