Inter-core-particle transmission method based on active interposer and interconnection structure

Abstract

The invention relates to the technical field of chips, in particular to an inter-core transmission method based on an active interposer and an interconnection structure, the inter-core transmission method based on the active interposer comprises the following steps: interacting a core logic of a functional core with a core interface, and sending a link layer data piece flit to the active interposer; analyzing the link layer data piece flit by a routing layer of the active intermediate layer, and determining a message type of the link layer data piece flit; if the message type is a data type, carrying out routing forwarding through a data plane; and if the message type is a configuration type or a message type, forwarding through a dedicated bus of a control plane. According to the technical scheme, the orthogonal architecture of combining the data plane with the control plane is adopted, the service data streams with different characteristics are separated, the interconnection architecture customization degree of respective communication networks is improved, and the efficiency is higher; meanwhile, mutual interference of configuration transmission, message transmission and data transmission is reduced, and high bandwidth of data communication and factuality of message communication are better guaranteed.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to an inter-chip transmission method and an interconnection structure based on an active intermediate layer. Background Art

[0002] "Chiplet" is also translated as "small chip". Chiplet technology uses multiple reusable prefabricated bare chips (die) through advanced packaging to form a chip system. The interconnection problem between chiplets can be divided into point-to-point connection between two chiplets and many-to-many interconnection between multiple chiplets when forming a system. The chiplet interface (die-to-dieinterface, D2D) technology is one of the basic key technologies of chiplet technology. In order to achieve reusability of chiplets, a unified interface standard needs to be designed to achieve interconnection and interoperability. The functions of chiplets vary and the bandwidth requirements vary. The design of chiplet interfaces needs to achieve high efficiency while ensuring versatility. The interconnection interface of chiplets should not only realize low-latency, high-bandwidth, low-power and high-reliability physical interfaces, but also include a unified interaction mechanism above the physical layer to ensure the interoperability of the interface. Therefore, the interface standard must be hierarchical. Generally speaking, it can be divided into three levels: transport layer, data link layer and physical layer. The existing D2D interface protocol stacks are all oriented to 2D or 2.5D packaging scenarios. The two chiplets are directly connected to each other, so the D2D interfaces of the two chiplets are symmetrical. The main consideration is the difference in electrical characteristics between D2D interconnection and traditional on-chip interconnection and circuit board-level interconnection. The focus is on improving the physical layer. The upper layer inherits the existing standard communication protocols, such as PCIe or AXI bus protocols, and then inserts an adaptation layer or link layer in between to complete the adaptation between the upper and lower layers.

[0003] There is also a packaging technology in the form of an active interposer in the prior art. The interposer silicon wafer is also a chip with circuits (transistors). It not only has the same interconnection density as the passive silicon interposer (2.5D packaging), but also can flexibly configure the connection relationship compared to other passive substrates (2D packaging). In traditional system design, a functional module may have multiple external system buses, such as connecting the high-speed AHB bus and the low-speed APB bus at the same time, but in the active interposer structure, these buses must be converged to the physical interface of the core particle-interposer, so supporting multi-protocol sharing of the physical layer interface is a necessary solution. At present, there is no specific interface protocol stack solution and transmission method for multi-protocol sharing on the active interposer. Summary of the invention

[0004] In order to solve the problems in the related art, the embodiments of the present disclosure provide an inter-chip transmission method and an interconnection structure based on an active interposer.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for inter-chip transmission based on an active interposer, comprising: The core logic of the functional core particle interacts with the core particle interface and sends the link layer data slice flit to the active interposer layer; The routing layer of the active intermediary layer parses the link layer data slice flit and determines the message type of the link layer data slice flit; If the message type is data, it is routed and forwarded through the data plane; If the message type is configuration or message, it is forwarded through the dedicated bus of the control plane.

[0006] In an implementation of the present disclosure, the routing layer of the active intermediary layer parses the link layer data slice flit, and determining the message type of the link layer data slice flit includes: Parse the service type Fmt field of the link layer data slice flit to determine the message type of the link layer data slice flit.

[0007] In an implementation of the present disclosure, if the message type is a data class, routing and forwarding through the data plane includes: Formatting the link layer data slice flit into a routing layer data packet; The routing layer data packet is forwarded through the on-chip network NoC of the data plane.

[0008] In one implementation of the present disclosure, formatting the link layer data slice flit into a routing layer data packet includes: If the link layer data fragment flit is a request message, the request message is parsed and at least a destination node field, a source node field, an exchange mode field, a packet length field and a location field are generated; If the request message is a write request, the above fields are spliced ​​onto the payload of the link layer data slice flit to obtain the routing layer data slice flit as the header slice, and then the corresponding data message transmitted in the same direction as the request message is used as the body slice to form a routing layer data packet with the header slice; If the request message is a read request, the header slice is used as a routing layer data packet; If the request message is a header flit of streaming data transmission, the source node field, the exchange mode field, the packet length field and the position field are spliced ​​to the payload of the link layer data slice flit to obtain the routing layer data slice flit as the header slice, and then the corresponding data message transmitted in the same direction as the request message is used as the body slice to form a routing layer data packet with the header slice; If the link layer data slice flit is a read response message, the read response message is parsed, and when the first read response message is received, at least a destination node field, a source node field, an exchange mode field, a packet length field and a location field are generated; the above fields are spliced ​​onto the payload of the link layer data slice flit to obtain a routing layer data slice flit as a header slice, and then subsequent data packets transmitted in the same direction as the read response message are used as body slices to form a routing layer data packet with the header slice.

[0009] In one implementation of the present disclosure, forwarding the routing layer data packet through the network on chip NoC of the data plane includes: If the exchange mode field is marked as streaming data transmission, circuit switching forwarding is adopted; If the exchange mode field is marked as address mapping data transmission, packet switching forwarding is adopted.

[0010] In an implementation of the present disclosure, if the message type is a configuration type or a message type, forwarding through a dedicated bus of the control plane includes: If the message type is configuration class, it is forwarded through the configuration management bus; If the message type is a message type, it is forwarded through the event forwarding unit and the corresponding bus.

[0011] In the second aspect, an active intermediary layer-based chip interconnection structure is provided in an embodiment of the present disclosure, including: an on-chip network set on the active intermediary layer, and a C2I interface between the chip and the active intermediary layer; the C2I interface between the chip and the active intermediary layer includes a chip side interface and an active intermediary layer side interface; the router of the on-chip network is connected to the active intermediary layer side interface through a network interface, and is connected to the chip through the chip layer interface; the functional unit on the active intermediary layer is directly connected to the router port.

[0012] In one implementation of the present disclosure, the on-chip network includes a data plane and a control plane; the data plane is used for data-type message transmission in the functional core particle, and the control plane is used for configuration-type or message-type message transmission in the functional core particle.

[0013] In an implementation of the present disclosure, the data plane and the control plane use different topology networks or the same topology network.

[0014] In an implementation of the present disclosure, the data plane adopts a ring topology network, and the control plane adopts a star topology network.

[0015] In an implementation of the present disclosure, the data plane adopts circuit switching and packet switching data transmission methods.

[0016] In an implementation of the present disclosure, the circuit switching routing table of the router in the data plane can be defined by programming of the control plane.

[0017] In one implementation of the present disclosure, the chip side interface includes the following protocol stack: physical layer, link layer, protocol adaptation layer and protocol layer; the active interposer side interface includes the following protocol stack: physical layer, link layer and routing layer.

[0018] In an implementation of the present disclosure, the protocol layer includes at least a data protocol, a configuration protocol, and a message protocol.

[0019] In an implementation of the present disclosure, the message format output by the protocol adaptation layer includes at least: a service type field, a transmission type field and a payload field.

[0020] In one implementation of the present disclosure, the link layer divides data, configuration and message into three virtual channels, corresponding to the transmission of corresponding link layer data slices flit, and can time-multiplex the underlying physical link; and / or, The link layer is also used to arbitrate link layer data slices flits of data class, configuration class and message class, among which the message class has the highest priority, and the priority decreases in the order of body slice of data class, configuration class and head slice of data class.

[0021] The technical effects provided by the embodiments of the present disclosure may include the following beneficial effects: According to the technical solution provided by the embodiment of the present disclosure, the inter-chiplet transmission method based on the active intermediary layer includes: the core logic of the functional chiplet interacts with the chiplet interface to send the link layer data slice flit to the active intermediary layer; the routing layer of the active intermediary layer parses the link layer data slice flit to determine the message type of the link layer data slice flit; if the message type is data type, routing forwarding is performed through the data plane; if the message type is configuration type or message type, forwarding is performed through the dedicated bus of the control plane. The above technical solution adopts an orthogonal architecture of the data plane combined with the control plane to separate business data flows with different characteristics, thereby improving the customization degree of the interconnection architecture of each communication network and being more efficient; at the same time, it reduces the mutual interference of configuration transmission, message transmission and data transmission, and better guarantees the high bandwidth of data communication and the factuality of message communication.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram showing an inter-chip interconnection structure based on an active interposer according to an embodiment of the present disclosure is shown.

[0024] Figure 2 A schematic diagram showing the structure of an on-chip network according to an embodiment of the present disclosure is shown.

[0025] Figure 3 A flow chart of an active interposer-based chiplet transmission method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0027] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0028] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] The existing D2D interface protocol stacks are all oriented to 2D or 2.5D packaging scenarios. The two chiplets are directly connected to each other, so the D2D interfaces of the two chiplets are symmetrical. The main consideration is the difference in electrical characteristics between D2D interconnection and traditional on-chip interconnection and circuit board-level interconnection. The focus is on improving the physical layer. The upper layer inherits the existing standard communication protocols, such as PCIe or AXI bus protocols, and then inserts an adaptation layer or link layer in between to complete the adaptation between the upper and lower layers.

[0030] The following disadvantages exist in the solution of integrated chip system based on active interposer: it ignores the difference in the division of roles between active interposer and functional core particles in this specific architecture: the interposer is the interconnection network core particle of the system, and the functional core particle is the implementation of various computing and storage functions of the system. The same design cannot be fully combined with their respective characteristics for optimization. For example, the datagram parsing of the active interposer needs to be parsed to the protocol layer to complete the data transmission. In this process, some redundant information irrelevant to the interconnection network task will be extracted, resulting in logic and delay overhead.

[0031] Figure 1 A schematic diagram showing an inter-chip interconnection structure based on an active interposer according to an embodiment of the present disclosure is shown. Figure 2 A schematic diagram showing the structure of an on-chip network according to an embodiment of the present disclosure is shown.

[0032] like Figure 1 , Figure 2 As shown, the chip-to-chip interconnection structure based on the active interposer includes: a network on chip (Network on Chip, abbreviated as NoC) set on the active interposer, and a C2I interface between the chip and the active interposer; the C2I interface between the chip and the active interposer includes a chip side interface and an active interposer side interface; the router R of the chip network is connected to the active interposer side interface through a network interface NI, and is connected to the chip through the chip layer interface; the functional unit on the active interposer is connected to the router port.

[0033] In the disclosed method, the nodes connected to the on-chip network include various C2I interfaces and functional units, such as memory, system IO interface, power supply and clock network and other intermediate layer peripherals. The router of the on-chip network is connected to the C2I interface through the network interface. When two functional core particles communicate, the message is sent to the active intermediate layer through the C2I interface. The router connected to the C2I interface in the active intermediate layer then routes the received message and transmits it to the destination node through the on-chip network. The router of the destination node then sends the received message to the destination functional core particle through the C2I interface. The on-chip network can also realize the communication between the functional core particles and the functional units on the active intermediate layer in a similar manner. At this time, the functional units on the active intermediate layer are directly connected to the on-chip network router port without passing through the C2I interface.

[0034] In one implementation of the present disclosure, the network on chip includes a data plane and a control plane; the data plane is used for data-type message transmission in the functional core particles, and the control plane is used for configuration-type or message-type message transmission in the functional core particles. Specifically, the data-type message refers to a communication task with a high transmission bandwidth requirement and a high duty cycle; the configuration-type message refers to a communication task with a low bandwidth requirement, a certain message length, and a very low duty cycle; the message-type message refers to a communication task with a high real-time requirement and a short message. Both the data plane and the control plane are connected to all nodes of the network on chip. Among them, the data plane and the control plane can adopt different topology networks or the same topology network.

[0035] In a specific embodiment of the present disclosure, Figure 2 As shown, the data plane adopts a ring topology network, and the control plane adopts a star topology network.

[0036] In one implementation of the present disclosure, the data plane adopts circuit switching and packet switching data transmission. Specifically, the router of the data plane supports two flow control mechanisms: circuit switching and packet switching. In circuit switching, the router does not examine the source address and destination address of the message, and forwards the message input from a certain input port to the set output port according to the routing table setting. In packet switching, the router determines which port the message is forwarded to based on the destination node ID in the message header.

[0037] In an implementation of the present disclosure, the circuit switching routing table of the router in the data plane can be defined by programming of the control plane.

[0038] Specifically, the control plane includes a central controller that can configure the circuit switching routing table of the data plane router through the APB bus to control the data plane routing. The central controller of the control plane can also read and write the configuration registers in the functional core grain through the APB bus and the network interface NI between the control plane and the functional core grain.

[0039] In one implementation of the present disclosure, the chip side interface includes the following protocol stack: physical layer, link layer, protocol adaptation layer and protocol layer; the active interposer side interface includes the following protocol stack: physical layer, link layer and routing layer.

[0040] Specifically, the protocol layer in the present disclosure adopts existing protocols, such as high-speed bus protocols such as AXI and AHB, low-speed peripheral bus protocols such as APB and AXI-Lite, and streaming data transmission protocols such as AXI-Stream. It can also adopt a customized private bus such as generating and sending a predefined operation instruction packet or a message packet indicating the occurrence of an event and related information.

[0041] The protocol adaptation layer in the present disclosure is used to format the bus protocol of the protocol layer to form a series of messages so that they can be transmitted in the link layer; for the receiving end, the messages from the link layer are restored to the corresponding data transmission protocol operations.

[0042] The routing layer in the present disclosure is used to route messages received from the link layer between networks composed of multiple core particles.

[0043] The link layer in the present disclosure is used to reliably transmit the messages packaged by the protocol adaptation layer and provide data verification and retransmission functions. In addition, the link layer also needs to implement the management of multiple physical layer channels, including but not limited to channel multiplexing, channel reorganization, power consumption management and other functions.

[0044] The physical layer in the present disclosure is used to convert link layer data flits into signals for transmission, mainly including the connection of chiplet external interface signals, data serial-to-parallel conversion, interface circuit driving, etc. In addition, the physical layer interface also supports link training, repair and other functions.

[0045] In an implementation of the present disclosure, the protocol layer includes at least a data protocol, a configuration protocol, and a message protocol.

[0046] Among them, data protocols mainly complete high-speed transmission, such as AXI bus, AHB bus, AXI-stream, Tile-link bus, etc. According to the characteristics of the data protocol (such as whether it contains address information), it can be further divided into streaming data transmission protocol and address mapping (memory-map) data transmission protocol.

[0047] Configuration protocols mainly complete low-speed access to configuration registers related to status and control in modules in the system, such as the APB bus and AXI-lite bus.

[0048] Message protocols are used for signal transmission such as interrupt signals or handshake signals between hardware, which have a small amount of information but high communication real-time requirements. For example, they can indicate whether an event has occurred and the parameters or ID information that mark the event type. They are commonly found in MCU, sensor, industrial control and other systems, such as the start signal of the sampling front end triggered by a hardware timer.

[0049] In one implementation of the present disclosure, one implementation of the protocol adaptation layer is that each of the two communicating parties has an adaptation module, each maintaining a state machine synchronized with each other, and the two parties maintain a determined initial state agreed upon in the initial state. The protocol adaptation layer provides transparent communication services for the protocol layers on both sides. When the active party (master) initiates communication, the protocol adaptation layer converts the signal information of the master bus into a data packet and sends it to the passive party (slave). Similarly, the slave's protocol adaptation layer translates the received data packet into an operation on the slave side bus (a set of signal changes); conversely, the signal fed back by the slave to the master is also converted into a data packet through the protocol adaptation layer, sent to the master's protocol adaptation layer module, and then converted into a signal response to the master bus. Each step of the operation of the two communicating parties corresponds to a message. If an operation that requires multiple cycles to complete, such as a string of data sent continuously, corresponds to multiple messages. While translating and forwarding the interactive data between the two parties, the protocol adaptation layer switches the state machine states of both parties according to the parsed message information and the current state machine state. The state transfer relationship between the two state machines is pre-designed collaboratively during the design phase. During the communication process, the protocol adaptation layer keeps each state machine in a matching state (i.e., keeps the state machines synchronized).

[0050] In the protocol layer adaptation layer state machine, a series of sub-state machines are included, each of which corresponds to a transaction. After the system receives the instruction of the upper computer protocol from the IDLE state, it enters the corresponding transaction mode (i.e., the entry state of the sub-state machine), and then exits the mode after the transaction is completed and returns to the IDLE state. For example, reading data is a protocol transaction, and its process goes through multiple steps such as issuing a read request (specifying the address and data length), returning the first data, returning the second data, etc. In the protocol adaptation layer of the present invention, it is decomposed into multiple sub-state machine states. In each state, both parties send and receive a specific string of messages to complete the state switching and promote the operation of the transaction state machine. When a data reading operation is completed, the communicating parties return to the IDLE state to prepare for the next transaction.

[0051] In one implementation of the present disclosure, the message format output by the protocol adaptation layer includes at least: a service type field, a transmission type field, and a payload field. The service type field indicates that the service type is specifically a data class, a configuration class, or a message class, and the transmission type field indicates the operation task corresponding to the message, such as an addressed read request, an addressed read response, an addressed write request, streaming data transmission, etc. The payload field indicates the main content and parameters of the transmission.

[0052] For messages generated by data protocols, at least the following transmission types and corresponding payload contents are supported: Transmission Type Load Read request flit with address Starting address and data length Read response flit with address Returned data Write request flit with address Starting address, data length Write data flit with address Data fields written Header flit for streaming data transmission Data stream length information Streaming data transmission data flit Data elements in a stream For messages generated by configuration protocols, at least the following transmission types and corresponding payload contents are supported: Transmission Type Load Configuration data read flit The address field of the target parameter to be read Configuration data read response flit The numeric field of the returned parameter Configuration data write request flit The address of the target parameter to be written Configuration data write data flit Write the value field of the target parameter For messages generated by message-type protocols, multiple transmission types can be optionally supported, and their payload includes at least a message ID field and a parameter field to transmit parameter information of the message.

[0053] At the data link layer, each protocol layer message is converted into a data fragment flit, or vice versa. In order to simplify the protocol logic, all flits are set to a fixed uniform length, such as 40 bits. When the total length of the valid field cannot fill the payload field of the flit, padding is required.

[0054] In one implementation of the present disclosure, the link layer divides data, configuration and message into three virtual channels, corresponding to the transmission of corresponding link layer data slices flit, and can time-multiplex the underlying physical link; and / or, The link layer is also used to arbitrate link layer data slices flits of data class, configuration class and message class, among which the message class has the highest priority, and the priority decreases in the order of body slice of data class, configuration class and head slice of data class.

[0055] In the disclosed method, the link layer is divided into three virtual channels: data, configuration, and message, and the underlying physical link is time-division multiplexed. In other words, the link layer receives messages from different protocols in parallel and generates flits. Each information class corresponds to an independent FIFO queue. At the transmitting end, the link layer arbitrates the flits of the three queues. The message class flits have the highest priority to ensure the real-time nature of the message class. At the same time, considering that the message class messages are short messages, the impact of occupying bandwidth on other channels is also relatively small. The priority of the configuration class flits is higher than the data class header, but lower than the data class body, so that the control information can be transmitted to various parts of the system in a timely manner, ensuring the response speed of the system. At the same time, it also avoids the system state switching during the data transmission process, resulting in incomplete data reception and abnormalities (that is, executing the control command after a complete message transmission is completed).

[0056] Figure 3 A flow chart of an active interposer-based chiplet transmission method according to an embodiment of the present disclosure is shown.

[0057] like Figure 3 As shown, the inter-chip transmission method based on the active interposer includes the following steps S310-S340: In step S310, the functional core logic interacts with the core interface to send a link layer data slice flit to the active interposer; In step S320, the routing layer of the active intermediary layer parses the link layer data slice flit to determine the message type of the link layer data slice flit; In step S330, if the message type is data class, routing forwarding is performed through the data plane; In step S340, if the message type is a configuration type or a message type, it is forwarded through the dedicated bus of the control plane.

[0058] In an implementation of the present disclosure, the routing layer of the active intermediary layer parses the link layer data slice flit, and determining the message type of the link layer data slice flit includes: Parse the service type Fmt field of the link layer data slice flit to determine the message type of the current data packet.

[0059] In an implementation of the present disclosure, if the message type is a data class, routing and forwarding through the data plane includes: Formatting the link layer data slice flit into a routing layer data packet; The routing layer data packet is forwarded through the on-chip network NoC of the data plane.

[0060] In one implementation of the present disclosure, formatting the link layer data slice flit into a routing layer data packet includes: If the link layer data fragment flit is a request message, the request message is parsed and at least a destination node field, a source node field, an exchange mode field, a packet length field and a location field are generated; If the request message is a write request, the above fields are spliced ​​onto the payload of the link layer data slice flit to obtain the routing layer data slice flit as the header slice, and then the corresponding data message transmitted in the same direction as the request message is used as the body slice to form a routing layer data packet with the header slice; If the request message is a read request, the header slice is used as a routing layer data packet; If the request message is a header flit of streaming data transmission, the source node field, the exchange mode field, the packet length field and the position field are spliced ​​to the payload of the link layer data slice flit to obtain the routing layer data slice flit as the header slice, and then the corresponding data message transmitted in the same direction as the request message is used as the body slice to form a routing layer data packet with the header slice; If the link layer data slice flit is a read response message, the read response message is parsed, and when the first read response message is received, at least a destination node field, a source node field, an exchange mode field, a packet length field and a location field are generated; the above fields are spliced ​​onto the payload of the link layer data slice flit to obtain a routing layer data slice flit as a header slice, and then subsequent data packets transmitted in the same direction as the read response message are used as body slices to form a routing layer data packet with the header slice.

[0061] In the disclosed method, the source node field is added by the routing layer interface unit connected to the functional core particle. Each node of the on-chip network can be pre-assigned an ID number during the system design or configuration stage, and the source ID of the data packet sent by the node can be obtained by directly querying the local register.

[0062] Other destination node fields, exchange mode fields, and packet length fields are obtained by parsing request messages (such as addressed data read requests, addressed data write requests, and header flits for streaming data transmission). Among them, the exchange mode field is an identification bit that marks whether it belongs to streaming transmission or addressed transmission, and is generated by parsing the transmission type field. If it is addressed transmission, parse the address fields of the read request and the write request, and then generate the destination node field based on the address conversion relationship stored locally on the network interface. For data messages containing data length, parse the data length field therein to generate a packet length field indicating the total number of flits contained in the message. For the header flit of streaming data transmission, the destination node field is not required, and the generation method of other header fields is the same as that of other transmission types described above.

[0063] Then, the routing layer re-encapsulates various request flits and the subsequent flits transmitted in the same direction to obtain routing layer data packets. The transmission type and payload of these flits are extracted as the payload of the routing layer flits, and the existing address fields are replaced with the destination address generated by the routing layer. A location field is added to each flit to mark the location of each routing layer flit in the routing layer data packet, indicating whether the corresponding flit is a header or a body. Therefore, the header field, location field and payload of the above request flit together constitute the header of the data packet, and the location fields and payloads of other flits constitute the body of the routing layer data packet.

[0064] The format of the router data header is as follows:

[0065] Among them, LOC is the location field and PAYLOAD is the payload field.

[0066] The above is a routing layer solution when the local node is the master end of the upper layer protocol and forwards data from the local link layer. It can be understood that if the local node is the master end of the upper layer protocol, for the routing layer data packets received by the routing layer from the remote node, the corresponding routing solution is to parse the routing layer data packets and decompose them into a string of routing layer flits. Each routing layer flit is then converted into a corresponding link layer flit by adding a service type field based on the flit payload, and then sending it to the link layer of the active intermediary layer for transmission to the functional core particle on the opposite side. If the destination node is a node of the active intermediary layer, it is directly sent by the routing layer to the protocol adaptation layer to interact with the SoC bus (such as the AHB bus).

[0067] For the local node which is the slave of the upper layer protocol, the received routing layer data packets from the remote end are decomposed into a string of routing layer flits, and each routing layer flit is then converted into the corresponding link layer flits by adding a service type field based on the flit payload. If the received routing layer data packet is an addressed read request, its destination node ID (DST_ID), source node ID (SRC_D) and packet length information are extracted and saved for use when the link layer of the local node returns the addressed read response flits. The routing layer solution for the message (read response flits) from the link layer of the local node is to package a group of addressed read response flits into a routing layer data packet and forward it through the data plane network. Specifically, the header field is generated. The header field is the same as the routing layer data packet format of the local node which is the master of the upper layer protocol, but the destination node ID value is filled with the previously saved SRC_ID value, the SRC_ID field is filled with the previously saved DST_ID value, and the packet length field is filled with the previously saved packet length value. The payload part of the header is the transfer type field and payload field of the first addressed read response flit. The subsequent addressed read response flits extract the transfer type field and payload field, add the location field, and form the body of the routing layer data packet. The value of the location field of each flit in the addressed read response data packet is the same as before.

[0068] In one implementation of the present disclosure, for configuration class message types, the link layer will send the flit received by the bottom layer to the control plane. The message sent from the control plane to the functional core particle is sent to the link layer of the C2I interface on the active interposer side through the on-chip bus and the protocol adaptation layer, and then sent to the functional core particle on the opposite side through the physical layer. The routing layer is not required in the functional core particle, and it is directly received by the link layer and uploaded to the protocol adaptation layer on this side to complete the communication. The message sent by the functional core particle to the control plane is sent to the link layer of the control plane through C2I in the form of a link layer flit. The destination of the read response flit of the configuration data is always the control unit in the control plane, so no routing is required, and it does not pass through the routing layer. It directly interacts with the configuration bus in the control plane through the protocol adaptation layer.

[0069] In one implementation of the present disclosure, for message-type packets, the link layer will match the flit received at the bottom layer to the corresponding virtual channel according to the service type and send it to the control plane. The control plane provides a dedicated high-real-time switching network for message transmission. The transmission of message-type protocols in the active intermediary layer adopts a routing layer protocol similar to the data-type protocol. The difference is that, first, the interface does not need to add a destination ID when forwarding a message message. The destination ID of the message message is obtained by the switching network based on the message ID and the source node ID, and is forwarded directly; second, the message message does not have an exchange mode identification field; third, the message always has only one flit and does not need to be packaged into a data packet. Therefore, the entry work of the routing layer is only to add the source node ID to the message protocol and extract the payload to form a routing flit; the exit work is to restore the message flit to a link layer flit (that is, add a service type field and a transmission type field).

[0070] In one implementation of the present disclosure, forwarding the routing layer data packet through the network on chip NoC of the data plane includes: If the exchange mode field is marked as streaming data transmission, circuit switching forwarding is adopted; If the exchange mode field is marked as address mapping data transmission, packet switching forwarding is adopted.

[0071] In the disclosed method, for the data transmission process of the circuit switching mode, the data is forwarded according to the pre-configured path. For the packet switching data, the head flit contains the routing information, and the head flit will enter the routing calculation module to calculate the route and forward it accordingly.

[0072] In an implementation of the present disclosure, if the message type is a configuration type or a message type, forwarding through a dedicated bus of the control plane includes: If the message type is configuration class, it is forwarded through the configuration management bus; If the message type is a message type, it is forwarded through the event forwarding unit and the corresponding bus.

[0073] In the disclosed method, the control plane includes a central control unit, which is connected to each functional unit and functional core of the active intermediary layer through the APB bus, and can read and write the configuration register through the APB bus. In the case where the configuration register is in the functional core, a protocol adapter from APB to C2I link layer is provided in the active intermediary layer NI corresponding to the functional core.

[0074] In the disclosed method, the control plane includes an event processing unit configuration, which is connected to each functional core particle and the peripherals on the active intermediary layer through a star connection, and is used to forward message-type messages.

[0075] The present disclosure also provides a specific inter-chip transmission method based on an active interposer, comprising the following steps: The core logic of the functional core particle interacts with the protocol layer of the interface, initiates communication (such as data access, interrupt information, etc.), is encapsulated by the link layer, and then enters the core particle standard interface of the active interposer layer through the physical layer interface; The information piece reaches the link layer through the physical layer of the standard interface. The link layer parses the corresponding communication type data packet and performs different routing; Data access packets are forwarded through the network on chip (NoC) of the data plane; Configuration and message packets are forwarded via the dedicated bus of the control plane; After forwarding, the data packet reaches the standard interface of the corresponding intermediate layer module or the destination core particle; The destination chip receives the forwarded data packet, which is decapsulated at the link layer and converted at the protocol adaptation layer before reaching the core logic of the destination chip.

[0076] The active interposer-based chip-to-chip transmission method and interconnect structure provided by the present disclosure achieve at least the following technical effects: (1) The solution proposed in this application adopts an orthogonal architecture that combines the data plane with the control plane, separates business data flows with different characteristics, improves the customization of the interconnection architecture of each communication network, and is more efficient; at the same time, it reduces the mutual interference between configuration transmission, message transmission and data transmission, and better guarantees the high bandwidth of data communication and the factuality of message communication.

[0077] (2) The solution proposed in this application enables the active intermediary layer to be reused among multiple applications. It places the definition of the connection relationship between the design core particles in the active intermediary layer as much as possible. For example, the destination node of the streaming transmission in the routing layer is defined by the circuit-switched router routing table, and the routing table can be programmed by the control plane. The routers in each intermediary layer support circuit switching and packet switching, so that they can connect functional core particles with different transmission requirements, with higher flexibility.

[0078] (3) It has higher efficiency when processing streaming data such as sensor data. The transmission protocol and circuit switching mode of streaming data take advantage of the large amount of address-free data communication, data flow path and traffic characteristics that are highly deterministic in systems such as industrial control that mainly collect and process sensor data streams. It simplifies the protocol, reduces the actions of message parsing and routing link establishment, and saves time and power consumption.

[0079] (4) It can better support real-time applications. The message protocols use dedicated communication networks and protocol message formats, avoiding delay disturbances and delay increases caused by other communication services interspersed in them.

[0080] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A chip-to-chip transmission method based on an active interposer, characterized in that: include: The core logic of the functional core particle interacts with the core particle interface and sends the link layer data slice flit to the active interposer layer; The routing layer of the active intermediary layer parses the link layer data slice flit and determines the message type of the link layer data slice flit; If the message type is data, it is routed and forwarded through the data plane; If the message type is configuration or message, it is forwarded through the dedicated bus of the control plane.

2. The method for inter-chip transmission based on active interposer according to claim 1, characterized in that: The routing layer of the active intermediary layer parses the link layer data slice flit, and determines the message type of the link layer data slice flit includes: Parse the service type Fmt field of the link layer data slice flit to determine the message type of the link layer data slice flit.

3. The method for inter-chip transmission based on active interposer according to claim 1, characterized in that: If the message type is data class, routing and forwarding through the data plane includes: Formatting the link layer data slice flit into a routing layer data packet; The routing layer data packet is forwarded through the on-chip network NoC of the data plane.

4. The method for inter-chip transmission based on active interposer according to claim 3, characterized in that: The formatting of the link layer data slice flit into a routing layer data packet comprises: If the link layer data fragment flit is a request message, the request message is parsed and at least a destination node field, a source node field, an exchange mode field, a packet length field and a location field are generated; If the request message is a write request, the above fields are spliced ​​onto the payload of the link layer data slice flit to obtain the routing layer data slice flit as the header slice, and then the corresponding data message transmitted in the same direction as the request message is used as the body slice to form a routing layer data packet with the header slice; If the request message is a read request, the header slice is used as a routing layer data packet; If the request message is a header flit of streaming data transmission, the source node field, the exchange mode field, the packet length field and the position field are spliced ​​to the payload of the link layer data slice flit to obtain the routing layer data slice flit as the header slice, and then the corresponding data message transmitted in the same direction as the request message is used as the body slice to form a routing layer data packet with the header slice; If the link layer data slice flit is a read response message, the read response message is parsed, and when the first read response message is received, at least a destination node field, a source node field, an exchange mode field, a packet length field and a location field are generated; the above fields are spliced ​​onto the payload of the link layer data slice flit to obtain a routing layer data slice flit as a header slice, and then subsequent data packets transmitted in the same direction as the read response message are used as body slices to form a routing layer data packet with the header slice.

5. The method for inter-chip transmission based on active interposer according to claim 4, characterized in that: The forwarding of the routing layer data packet through the on-chip network NoC of the data plane includes: If the exchange mode field is marked as streaming data transmission, circuit switching forwarding is adopted; If the exchange mode field is marked as address mapping data transmission, packet switching forwarding is adopted.

6. The method for inter-chip transmission based on active interposer according to claim 1, characterized in that: If the message type is a configuration type or a message type, forwarding through a dedicated bus of the control plane includes: If the message type is configuration class, it is forwarded through the configuration management bus; If the message type is a message type, it is forwarded through the event forwarding unit and the corresponding bus.

7. A core-to-chip interconnect structure based on an active interposer, characterized in that: include: An on-chip network is arranged on an active interposer, and a C2I interface between the core particle and the active interposer; the C2I interface between the core particle and the active interposer includes a core particle side interface and an active interposer side interface; a router of the on-chip network is connected to the active interposer side interface via a network interface, and is connected to the core particle via the core particle layer interface; and a functional unit on the active interposer is directly connected to a router port.

8. The chip-to-chip interconnect structure based on active interposer according to claim 7, characterized in that: The on-chip network includes a data plane and a control plane; the data plane is used for data-type message transmission in the functional core particle, and the control plane is used for configuration-type or message-type message transmission in the functional core particle.

9. The chip-to-chip interconnect structure based on active interposer according to claim 8, characterized in that: The data plane and the control plane use different topology networks or the same topology network.

10. The chip-to-chip interconnect structure based on active interposer according to claim 8, characterized in that: The data plane adopts a ring topology network, and the control plane adopts a star topology network.

11. The chip-to-chip interconnect structure based on active interposer according to claim 8, characterized in that: The data plane adopts circuit switching and packet switching data transmission modes.

12. The chip-to-chip interconnect structure based on active interposer according to claim 8, characterized in that: The circuit switching routing table of the router in the data plane can be defined programmatically by the control plane.

13. The chip-to-chip interconnect structure based on active interposer according to claim 7, characterized in that: The core particle side interface includes the following protocol stacks: physical layer, link layer, protocol adaptation layer and protocol layer; the active intermediary layer side interface includes the following protocol stacks: physical layer, link layer and routing layer.

14. The chip-to-chip interconnect structure based on active interposer according to claim 13, characterized in that: The protocol layer includes at least a data protocol, a configuration protocol and a message protocol.

15. The chip-to-chip interconnect structure based on active interposer according to claim 13, characterized in that: The message format output by the protocol adaptation layer includes at least: a service type field, a transmission type field and a load field.

16. The chip-to-chip interconnect structure based on active interposer according to claim 13, characterized in that: The link layer divides data, configuration and message into three virtual channels, corresponding to the transmission of corresponding link layer data slices flit, and can time-multiplex the underlying physical link; and / or, The link layer is also used to arbitrate link layer data slices flits of data class, configuration class and message class, among which the message class has the highest priority, and the priority decreases in the order of body slice of data class, configuration class and head slice of data class.

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