A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a plurality of data signal lines, a plurality of initialization signal lines and a plurality of pixel driving circuits. The pixel driving circuit comprises a driving transistor. The data signal line is used for providing a data signal for the gate of the driving transistor, and the initialization signal line is used for providing an initialization signal for the source of the driving transistor. The working stage of the display panel comprises a discharge stage, and in the discharge stage, the voltage difference between the gate of the driving transistor and the source of the driving transistor is greater than 0V. Thus, after the power-on inspection of the display panel, by setting the voltage difference between the gate of the driving transistor and the source of the driving transistor as a positive value, the discharge efficiency can be improved, the residual charge existing in the pixel driving circuit can be rapidly released in the discharge stage, and the horizontal stripe-shaped defects or flash screen defects caused by the residual charge in the pixel driving circuit and other phenomena can be avoided.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In existing technologies, after the display panel is manufactured, it needs to undergo a power-on test to check whether it can function properly. Furthermore, after the power-on test, a negative voltage is applied to the gate-source voltage Vgs of the driving transistor to discharge any residual power supply voltage. On one hand, applying a negative voltage to the gate-source voltage Vgs of the driving transistor for an extended period can degrade the electrical performance or shorten the lifespan of the light-emitting element, thus reducing its reliability. On the other hand, during the discharge phase, the negative gate-source voltage Vgs experiences voltage cancellation in different directions, resulting in slow discharge efficiency. This prevents residual charge in the pixel driving circuit from being released in time, potentially leading to horizontal stripe defects or screen flickering during power-on display. Summary of the Invention

[0003] The present invention provides a display panel and a display device. By setting the voltage difference between the gate and the source of the driving transistor in the discharge stage to a positive value, the discharge efficiency can be improved, and the residual charge in the pixel driving circuit can be quickly released in the discharge stage, avoiding phenomena such as horizontal stripe defects or screen flickering defects caused by residual charge in the pixel driving circuit.

[0004] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0005] Multiple data signal lines, multiple initialization signal lines, and multiple pixel driving circuits;

[0006] The pixel driving circuit includes a driving transistor;

[0007] The data signal line is used to provide a data signal to the gate of the driving transistor, and the initialization signal line is used to provide an initialization signal to the source of the driving transistor.

[0008] The operation of the display panel includes a discharge phase, in which the voltage difference between the gate and source of the driving transistor is greater than 0V.

[0009] Optionally, during the discharge phase, the voltage difference Vgs between the gate and source of the driving transistor satisfies: 2V≤Vgs≤8V.

[0010] Optionally, during the discharge phase, the data signal line provides a voltage of 5V to the gate of the driving transistor, and the initialization signal line provides an initialization signal of 0V to the source of the driving transistor.

[0011] Optionally, the display panel further includes a first power signal line, and the drain of the driving transistor is electrically connected to the first power signal line;

[0012] The working phase also includes a discharge holding phase;

[0013] The voltage at the gate of the driving transistor during the discharge holding phase is the same as the voltage at the gate of the driving transistor during the discharge phase, and the voltage at the source of the driving transistor during the discharge holding phase is the same as the voltage at the source of the driving transistor during the discharge phase.

[0014] During the discharge holding phase, the voltage at the drain of the driving transistor is 0V.

[0015] Optionally, the working phase may further include a discharge termination phase;

[0016] During the discharge termination phase, the voltages of the gate, source, and drain of the driving transistor are all 0V.

[0017] Optionally, the display panel further includes multiple scan signal lines, which are electrically connected to the pixel driving circuit and are used to provide scan signals to the pixel driving circuit.

[0018] The discharge termination phase includes a first sub-phase and a second sub-phase;

[0019] In the first sub-stage, the scan signal provided by the scan signal line is greater than 0V, and in the second sub-stage, the scan signal provided by the scan signal line is 0V.

[0020] Optionally, the display panel may also include multiple scan signal lines;

[0021] The pixel driving circuit also includes a data writing transistor, an initialization transistor, and a storage capacitor;

[0022] The data signal line is electrically connected to the source of the data writing transistor, and the drain of the data writing transistor is electrically connected to the gate of the driving transistor.

[0023] The initialization signal line is electrically connected to the source of the initialization transistor, and the drain of the initialization transistor is electrically connected to the source of the driving transistor.

[0024] The gate of the data writing transistor and the gate of the initialization transistor are both electrically connected to the scan signal line.

[0025] The first plate of the storage capacitor is electrically connected to the drain of the data writing transistor, and the second plate of the storage capacitor is electrically connected to the source of the driving transistor.

[0026] Optionally, the display panel further includes a first power signal line, a second power signal line, and a plurality of light-emitting elements;

[0027] Multiple scanning signal lines and multiple data signal lines are arranged in a cross-shaped mesh structure, and the pixel driving circuit and the light-emitting element are both located within the mesh of the mesh structure.

[0028] The first power signal line is electrically connected to the drain of the driving transistor, the anode of the light-emitting element is electrically connected to the source of the driving transistor, and the cathode of the light-emitting element is electrically connected to the second power signal line.

[0029] Optionally, the display panel further includes a gate driving circuit, which is disposed in the bezel area of ​​the display panel;

[0030] The gate drive circuit is electrically connected to the multiple scan signal lines and is used to provide scan signals to the multiple scan signal lines.

[0031] Secondly, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the first aspect of the present invention.

[0032] The display panel provided in this embodiment of the invention includes multiple data signal lines, multiple initialization signal lines, and multiple pixel driving circuits. Each pixel driving circuit includes a driving transistor. The data signal lines provide data signals to the gate of the driving transistor, and the initialization signal lines provide initialization signals to the source of the driving transistor. The operation of the display panel includes a discharge phase, during which the voltage difference between the gate and source of the driving transistor is greater than 0V. Thus, after powering on the display panel, by setting the voltage difference between the gate and source of the driving transistor to a positive value, discharge efficiency can be improved, allowing for the rapid release of residual charge in the pixel driving circuit during the discharge phase, avoiding horizontal stripe defects or flickering defects caused by residual charge in the pixel driving circuit. Furthermore, since the voltage difference between the gate and source of the driving transistor is positive, applying a positive voltage to the light-emitting element for a long time has a smaller impact on the performance and lifespan of the light-emitting element, thereby improving the reliability of the display panel. Attached Figure Description

[0033] Figure 1This is a timing diagram of a pixel driving circuit provided in the prior art;

[0034] Figure 2 This is a circuit diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0035] Figure 3 This is a timing diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0036] Figure 4 This is a timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0037] Figure 5 This is a timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be fully described below with reference to the accompanying drawings in the embodiments of this invention, through specific implementation methods. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort fall within the protection scope of this invention.

[0041] Figure 1 This is a timing diagram of a pixel driving circuit provided in the prior art. (Reference) Figure 1In the prior art, during the discharge process S1', a 0V data signal Data' (i.e., reduced from 2V in the display process to 0V in the discharge process) is provided to the pixel driving circuit via the data signal line, and an initialization signal Vref' (raised from 1V in the display process to 2V in the discharge process) is provided to the pixel driving circuit via the initialization signal line. At this time, in the pixel driving circuit, the gate voltage of the driving transistor is 0V, and the source voltage of the driving transistor is 2V, that is, during the discharge process S1', the gate-source voltage Vgs (the voltage difference between the gate and source of the driving transistor) is -2V. The inventors have found that, in the above solution, on the one hand, applying a negative voltage to the gate-source voltage Vgs of the driving transistor for a long time will reduce the electrical performance or shorten the lifespan of the light-emitting element, thereby reducing the reliability of the light-emitting element. On the other hand, during the discharge stage, the negative gate-source voltage Vgs experiences voltage cancellation in different directions during discharge, resulting in a slower discharge efficiency, such as... Figure 1 As shown, in the prior art, it takes nearly 1 second to complete the release of residual charge (the positive power supply voltage signal EVDD' drops from 22V to 0V. In addition, during the entire discharge process S1', the scan signal Scan' remains unchanged at 18V). The residual charge in the pixel driving circuit cannot be released in time, which can easily lead to horizontal stripe defects or screen flickering defects when the device is turned on and displayed.

[0042] Figure 2 This is a circuit diagram of a pixel driving circuit provided in an embodiment of the present invention. Figure 3 This is a timing diagram of a pixel driving circuit provided in an embodiment of the present invention. See also... Figure 2 and Figure 3 The display panel includes multiple data signal lines 10, multiple initialization signal lines 20, and multiple pixel driving circuits 30. Each pixel driving circuit 30 includes a driving transistor T1. The data signal lines 10 provide a data signal Data to the gate of the driving transistor T1, and the initialization signal lines 20 provide an initialization signal Vref to the source of the driving transistor T1. The operation of the display panel includes a discharge phase S1, during which the voltage difference between the gate and source of the driving transistor T1 is greater than 0V.

[0043] Specifically, such as Figure 2 and Figure 3As shown, the pixel driving circuit 30 includes a driving transistor T1, which is disposed between the first power signal line 40 and the second power signal line 50. Specifically, the drain of the driving transistor T1 is electrically connected to the first power signal line 40, the source of the driving transistor T1 is electrically connected to the anode of the light-emitting element 60, and the cathode of the light-emitting element 60 is electrically connected to the second power signal line 50. During the light-emitting phase, the driving transistor T1 generates a driving current under the influence of the positive power signal EVDD provided by the first power signal line 40 and the data signal Data provided by the data signal line 10, driving the light-emitting element 60 to emit light. During the discharge phase S1, the driving transistor T1 discharges the residual charge in the pixel driving circuit 30 (mainly the charge generated by the positive power signal EVDD).

[0044] For example, such as Figure 2 and Figure 3 As shown, in the discharge stage S1, the data signal Data provided by data signal line 10 to the gate of driving transistor T1 is set to 3V, and the initialization signal Vref provided by initialization signal line 20 to the source of driving transistor T1 is set to 0V. Therefore, the voltage difference between the gate and source of driving transistor T1 is 3V; in other words, the gate-source voltage Vgs of driving transistor T1 is 3V. Thus, after a power-on check of the display panel, since the gate-source voltage Vgs of driving transistor T1 is positive (3V), there is no voltage cancellation in different directions when discharging residual charge in the pixel driving circuit 30, thereby improving discharge efficiency. Figure 3 As shown, when the positive power supply signal EVDD drops from 22V to 0V (discharge stage S1), it takes less than 500ms, which is significantly shorter than the nearly 1s in the prior art. This greatly reduces the discharge time, enabling the rapid release of residual charge in the pixel driving circuit 30 during discharge stage S1, thus avoiding horizontal stripe defects or screen flickering caused by residual charge in the pixel driving circuit 30. Furthermore, since the voltage difference between the gate and source of the driving transistor T1 is positive, applying a positive voltage to the light-emitting element 60 for a long time has a smaller impact on the performance and lifespan of the light-emitting element 60, thereby improving the reliability of the display panel.

[0045] It should be noted that, Figure 3 The example provided is exemplified by using a data signal line 10 to provide a data signal Data of 3V to the gate of the driving transistor T1 and an initialization signal line 20 to provide an initialization signal Vref of 0V to the source of the driving transistor T1. However, this embodiment of the invention does not limit the scope of the invention. In other embodiments, the data signal Data and the initialization signal Vref can be other values, as long as the voltage difference between the gate and the source of the driving transistor T1 is greater than 0V.

[0046] In summary, the display panel provided in this embodiment of the invention includes multiple data signal lines, multiple initialization signal lines, and multiple pixel driving circuits. The pixel driving circuit includes a driving transistor. The data signal lines provide data signals to the gate of the driving transistor, and the initialization signal lines provide initialization signals to the source of the driving transistor. The operation of the display panel includes a discharge phase, during which the voltage difference between the gate and source of the driving transistor is greater than 0V. Thus, after powering on the display panel, by setting the voltage difference between the gate and source of the driving transistor to a positive value, the discharge efficiency can be improved, enabling the rapid release of residual charge in the pixel driving circuit during the discharge phase, avoiding phenomena such as horizontal stripe defects or screen flickering caused by residual charge in the pixel driving circuit. Furthermore, since the voltage difference between the gate and source of the driving transistor is positive, applying a positive voltage to the light-emitting element for a long time has a smaller impact on the performance and lifespan of the light-emitting element, thereby improving the reliability of the display panel.

[0047] Optionally, based on the above embodiments, Figure 4 This is a timing diagram of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 2 and Figure 4 During the discharge phase S1, the voltage difference Vgs between the gate and source of the driving transistor T1 satisfies: 2V≤Vgs≤8V.

[0048] Specifically, by setting the voltage difference Vgs between the gate and source of the driving transistor T1 to be greater than 0V, i.e., making the gate-source voltage Vgs of the driving transistor T1 positive, the discharge efficiency can be improved. Furthermore, the inventors discovered that when the gate-source voltage Vgs of the driving transistor T1 satisfies 2V≤Vgs≤8V, the improvement in discharge efficiency is more significant. Therefore, by adjusting the data signal Data provided by the data signal line 10 to the gate of the driving transistor T1, and the initialization signal Vref provided by the initialization signal line 20 to the source of the driving transistor T1, the gate-source voltage Vgs of the driving transistor T1 is made to satisfy 2V≤Vgs≤8V, thus ensuring the improvement in discharge efficiency and further avoiding phenomena such as horizontal stripe defects or screen flickering caused by residual charge in the pixel driving circuit 30.

[0049] It should be noted that the improvement in discharge efficiency is most significant when the voltage difference Vgs between the gate and source of driving transistor T1 is set to 5V. Figure 2 and Figure 4In the embodiment shown, during the discharge stage S1, the data signal line 10 provides a voltage of 5V to the gate of the driving transistor T1, and the initialization signal line 20 provides an initialization signal of 0V to the source of the driving transistor T1. That is, the gate-source voltage Vgs of the driving transistor T1 is 5V. At this time, the positive power supply signal EVDD drops the fastest, from 22V to 0V in only about 250ms. Compared with the nearly 1S discharge time in the prior art, the discharge time is greatly reduced, and the residual charge in the pixel driving circuit 30 is quickly released during the discharge stage S1, avoiding phenomena such as horizontal stripe defects or screen flickering defects caused by the residual charge in the pixel driving circuit 30.

[0050] Understandable, Figure 4 The example provided is exemplified by using a data signal line 10 to provide a data signal Data of 5V to the gate of the driving transistor T1 and an initialization signal line 20 to provide an initialization signal Vref of 0V to the source of the driving transistor T1. However, this embodiment of the invention does not limit the scope of the invention. In other embodiments, the data signal Data and the initialization signal Vref can be other values, as long as the voltage difference Vgs between the gate and the source of the driving transistor T1 is 5V.

[0051] Optionally, based on the above embodiments, see also... Figure 2 and Figure 4 The display panel also includes a first power signal line 40, through which the drain of the driving transistor T1 is electrically connected. During the light-emitting phase, the first power signal line 40 provides a positive power signal EVDD to the drain of the driving transistor T1. The operation of the display panel also includes a discharge holding phase S2, which is sequentially following and adjacent to the discharge phase S1. Specifically, the gate voltage of the driving transistor T1 in the discharge holding phase S2 is the same as that in the discharge phase S1, and the source voltage of the driving transistor T1 in the discharge holding phase S2 is also the same as that in the discharge phase S1. That is, in both the discharge phase S1 and the discharge holding phase S2, the data signal Data provided by the data signal line 10 to the gate of the driving transistor T1, and the initialization signal Vref provided by the initialization signal line 20 to the source of the driving transistor T1, remain unchanged. Furthermore, the residual charge generated by the positive power supply signal EVDD in the pixel driving circuit 30 is discharged through the discharge stage S1, and the residual charge in other parts (excluding the residual charge generated by the positive power supply signal EVDD) is discharged through the discharge holding stage S2, so as to further avoid phenomena such as horizontal stripe defects or screen flickering defects caused by residual charge in the pixel driving circuit 30.

[0052] It is understandable that during the discharge phase S1, the residual positive power supply signal EVDD drops from 22V to 0V, that is, the voltage at the drain of the driving transistor T1 drops from 22V to 0V. During the discharge holding phase S2, the voltage at the drain of the driving transistor T1 is 0V, that is, before the discharge holding phase S2, the residual charge generated by the positive power supply signal EVDD has been discharged.

[0053] Optionally, based on the above embodiments, Figure 5 This is a timing diagram of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 2 and Figure 5 The operation of the display panel also includes a discharge end stage S3. Discharge end stage S3 is sequentially located after and adjacent to the discharge holding stage S2. In discharge end stage S3, the voltages of the gate, source, and drain of the driving transistor T1 are all 0V. That is, the data signal line 10 provides the data signal Data to the gate of the driving transistor T1, the initialization signal line 20 provides the initialization signal Vref to the source of the driving transistor T1, and the residual charge generated by the positive power supply signal EVDD are all 0. This eliminates voltage after the entire discharge process is completed, ensuring the reliability of the entire discharge process.

[0054] Optionally, based on the above embodiments, see also... Figure 2 and Figure 5 The display panel also includes multiple scan signal lines 70, which are electrically connected to the pixel driving circuit 30 and are used to provide scan signals Scan to the pixel driving circuit 30. The discharge end stage S3 includes a first sub-stage S31 and a second sub-stage S32. In the first sub-stage S31, the scan signal Scan provided by the scan signal line 70 is greater than 0V, and in the second sub-stage S32, the scan signal Scan provided by the scan signal line 70 is 0V.

[0055] For details, see Figure 2 and Figure 5The scan signal line 70 is electrically connected to the pixel driving circuit 30 and is used to provide the pixel driving circuit 30 with a scan signal Scan. The scan signal Scan can control the writing of the data signal Data and the initialization signal Vref. For example, when the voltage of the scan signal Scan is greater than 0V, the data signal Data can be written to the gate of the driving transistor T1, and the initialization signal Vref can be written to the drain of the driving transistor T1. When the voltage of the scan signal Scan is equal to 0V, the data signal Data cannot be written to the gate of the driving transistor T1, and the initialization signal Vref cannot be written to the drain of the driving transistor T1. Furthermore, based on the above, the discharge end stage S3 is further configured to include a first sub-stage S31 and a second sub-stage S32. In this process, the first sub-stage S31 precedes the second sub-stage S32 in timing. In the first sub-stage S31, the scan signal Scan provided by the scan signal line 70 is greater than 0V. This means that in the first sub-stage S31, the data signal Data can be written to the gate of the driving transistor T1, and the initialization signal Vref can be written to the drain of the driving transistor T1. However, since both the data signal Data and the initialization signal Vref are 0, the voltage on the data signal line 10 and the initialization signal line 20 is eliminated through the first sub-stage S31. In the second sub-stage S31, the scan signal Scan provided by the scan signal line 70 is 0V. This means that the voltage on the scan signal line 70 is eliminated through the second sub-stage S31, further ensuring the reliability of the entire discharge process.

[0056] Optionally, based on the above embodiments, see also... Figure 2 The display panel further includes multiple scan signal lines 70. The pixel driving circuit 30 also includes a data writing transistor T2, an initialization transistor T3, and a storage capacitor C. Data signal line 10 is electrically connected to the source of data writing transistor T2, and the drain of data writing transistor T2 is electrically connected to the gate of driving transistor T1. Initialization signal line 20 is electrically connected to the source of initialization transistor T3, and the drain of initialization transistor T3 is electrically connected to the source of driving transistor T1. The gates of both data writing transistor T2 and initialization transistor T3 are electrically connected to scan signal lines 70. The first plate of storage capacitor C is electrically connected to the drain of data writing transistor T2, and the second plate of storage capacitor C is electrically connected to the source of driving transistor T1.

[0057] Specifically, such as Figure 2As shown, scan signal line 70 is electrically connected to the gate of data writing transistor T2, data signal line 10 is electrically connected to the source of data writing transistor T2, and the drain of data writing transistor T2 is electrically connected to the gate of driving transistor T1. Therefore, under the control of scan signal line 70, data writing transistor T2 is turned on, and the data signal provided by data signal line 10 is written to the gate of driving transistor T1. Initialization signal line 20 is electrically connected to the source of initialization transistor T3, the drain of initialization transistor T3 is electrically connected to the source of driving transistor T1, and the gate of initialization transistor T3 is electrically connected to scan signal line 70. Therefore, under the control of scan signal line 70, initialization transistor T3 is turned on, and the initialization signal provided by initialization signal line 20 is written to the drain of driving transistor T1. Thus, during the light-emitting stage, data writing transistor T2 is used to write data signals, and driving transistor T1 is used to generate driving current under the action of a positive power supply signal to drive the light-emitting element 60 to emit light. A storage capacitor C is positioned between the gate and source of the driving transistor T1 to store the data signal provided by the data signal line 10 and maintain a stable gate voltage of the driving transistor T1, ensuring the normal operation of the pixel driving circuit 30. During the initialization phase, the initialization transistor T3 provides an initialization signal to the anode of the light-emitting element 60 to reset the anode. During the discharge phase, the data writing transistor T2 provides a data signal to the gate of the driving transistor T1, and the initialization transistor T3 provides an initialization signal to the drain of the driving transistor T1 to discharge any residual charge in the pixel driving circuit 30.

[0058] Optional, Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also: Figure 2 and Figure 6 The display panel also includes a first power signal line 40, a second power signal line 50, and multiple light-emitting elements 60. Multiple scan signal lines 70 and multiple data signal lines 10 are arranged in a cross-shaped mesh structure, with the pixel driving circuit 30 and the light-emitting elements 60 located within the mesh. The first power signal line 40 is electrically connected to the drain of the driving transistor T1, the anode of the light-emitting element 60 is electrically connected to the source of the driving transistor T1, and the cathode of the light-emitting element 60 is electrically connected to the second power signal line 50.

[0059] Specifically, the first power signal line 40 provides a positive power signal to the drain of the driving transistor T1, and the second power signal line 50 provides a negative power signal to the cathode of the light-emitting element 60. Under the influence of the positive power signal, the negative power signal, and the data signal, the driving transistor T1 drives the light-emitting element 60 to emit light. Furthermore, multiple scan signal lines 70 and multiple data signal lines 10 are intersected to form a mesh structure. The pixel driving circuit 30 and the light-emitting element 60 are both located within the mesh of this structure, thus ensuring a simple wiring connection.

[0060] Optionally, based on the above embodiments, see also... Figure 6 The display panel also includes a gate driving circuit 80, which is disposed in the bezel area BB of the display panel. The gate driving circuit 80 is electrically connected to multiple scan signal lines 70 and is used to provide scan signals to the multiple scan signal lines 70.

[0061] Specifically, the display panel includes a display area AA and a bezel area BB. The display area AA contains multiple light-emitting elements 60 and corresponding pixel driving circuits 30. The light-emitting elements 60 and the pixel driving circuits 30 are electrically connected, and the pixel driving circuits 30 provide driving signals to the light-emitting elements 60 to achieve image display in the display area AA. The bezel area BB surrounds the display area AA. For example, the bezel area BB may include a left bezel area, a right bezel area, a top bezel area, and a bottom bezel area. The gate driving circuit 80 can be located in the left bezel area. The gate driving circuit 80 is electrically connected to multiple scan signal lines 70, and thus provides scan signals to the scan signal lines 70, ensuring a simple scan signal transmission method.

[0062] It should be noted that, Figure 6 The example provided is only exemplified by the fact that the gate driving circuit 80 can be located in the left frame area. However, the embodiments of the present invention do not limit this. In other embodiments, the gate driving circuit 80 can also be located in the right frame area, or simultaneously in the left frame area and the right frame area. Those skilled in the art can set it as needed.

[0063] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 7As shown, the display device includes the display panel 01 in the above embodiments. This display device includes the display panel 01 of any embodiment of the present invention; therefore, the display device provided by the embodiments of the present invention possesses the corresponding beneficial effects of the display panel 01 provided by the embodiments of the present invention, which will not be elaborated further here. For example, the display device can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device; the embodiments of the present invention do not limit this.

[0064] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes multiple data signal lines, multiple initialization signal lines, and multiple pixel driving circuits; The pixel driving circuit includes a driving transistor; The data signal line is used to provide a data signal to the gate of the driving transistor, and the initialization signal line is used to provide an initialization signal to the source of the driving transistor. The operation of the display panel includes a discharge phase, in which the voltage difference between the gate and source of the driving transistor is greater than 0V.

2. The display panel according to claim 1, characterized in that, During the discharge phase, the voltage difference Vgs between the gate and source of the driving transistor satisfies: 2V≤Vgs≤8V.

3. The display panel according to claim 2, characterized in that, During the discharge phase, the data signal line provides a voltage of 5V to the gate of the driving transistor, and the initialization signal line provides an initialization signal of 0V to the source of the driving transistor.

4. The display panel according to claim 1, characterized in that, The display panel further includes a first power signal line, and the drain of the driving transistor is electrically connected to the first power signal line; The working phase also includes a discharge holding phase; The voltage at the gate of the driving transistor during the discharge holding phase is the same as the voltage at the gate of the driving transistor during the discharge phase, and the voltage at the source of the driving transistor during the discharge holding phase is the same as the voltage at the source of the driving transistor during the discharge phase. During the discharge holding phase, the voltage at the drain of the driving transistor is 0V.

5. The display panel according to claim 4, characterized in that, The working phase also includes a discharge termination phase; During the discharge termination phase, the voltages of the gate, source, and drain of the driving transistor are all 0V.

6. The display panel according to claim 5, characterized in that, The display panel also includes multiple scanning signal lines, which are electrically connected to the pixel driving circuit and are used to provide scanning signals to the pixel driving circuit. The discharge termination phase includes a first sub-phase and a second sub-phase; In the first sub-stage, the scan signal provided by the scan signal line is greater than 0V, and in the second sub-stage, the scan signal provided by the scan signal line is 0V.

7. The display panel according to claim 1, characterized in that, The display panel also includes multiple scanning signal lines; The pixel driving circuit also includes a data writing transistor, an initialization transistor, and a storage capacitor; The data signal line is electrically connected to the source of the data writing transistor, and the drain of the data writing transistor is electrically connected to the gate of the driving transistor. The initialization signal line is electrically connected to the source of the initialization transistor, and the drain of the initialization transistor is electrically connected to the source of the driving transistor. The gate of the data writing transistor and the gate of the initialization transistor are both electrically connected to the scan signal line. The first plate of the storage capacitor is electrically connected to the drain of the data writing transistor, and the second plate of the storage capacitor is electrically connected to the source of the driving transistor.

8. The display panel according to claim 7, characterized in that, The display panel also includes a first power signal line, a second power signal line, and multiple light-emitting elements; Multiple scanning signal lines and multiple data signal lines are arranged in a cross pattern to form a mesh structure, and the pixel driving circuit and the light-emitting element are both located within the mesh of the mesh structure; The first power signal line is electrically connected to the drain of the driving transistor, the anode of the light-emitting element is electrically connected to the source of the driving transistor, and the cathode of the light-emitting element is electrically connected to the second power signal line.

9. The display panel according to claim 7, characterized in that, The display panel further includes a gate driving circuit, which is disposed in the bezel area of ​​the display panel; The gate drive circuit is electrically connected to the multiple scan signal lines and is used to provide scan signals to the multiple scan signal lines.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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