A low noise amplifier structure employing multiple inductive coupling and current reuse

Abstract

The application discloses a low-noise amplifier structure adopting multi-inductive coupling and current multiplexing, comprising a multi-inductive coupling network and a full nmos current multiplexing technology network, wherein the multi-inductive coupling network and the full nmos current multiplexing technology network are connected, the full nmos current multiplexing technology network is used for making multi-stage amplifiers flow through the same current and making the multi-stage amplifiers share the same power voltage, and the multi-inductive coupling network is used for realizing wideband maximum power transmission matching and noise coefficient matching at an input node, so that high power transmission and low noise coefficient are realized. By using the application, wideband input matching and noise matching can be realized simultaneously. The application can be widely applied to the field of radio frequency receiver front ends.

Description

Technical Field

[0001] This invention relates to the field of radio frequency receiver front-end, and more particularly to a low-noise amplifier structure employing multi-inductor coupling and current multiplexing. Background Technology

[0002] The rapid advancement of wireless communication technology has placed higher demands on receiver performance, particularly in signal amplification and sensitivity. In receiver architecture, the low-noise amplifier (LNA), as a key module after the antenna, is responsible for effectively amplifying weak radio frequency signals. The noise figure of the LNA is a crucial indicator of its performance; a high noise figure significantly reduces the receiver's ability to capture weak signals. Furthermore, traditional LNA designs often focus on optimal performance in specific frequency bands, leading to bandwidth becoming a major bottleneck when dealing with ultra-wideband signals, limiting its widespread application in broadband scenarios. In advanced processes, LNAs are also limited by power supply voltage. In advanced processes such as 65nm CMOS, transistor operating voltages are generally reduced to 1.2V or lower to pursue higher energy efficiency. However, current commercial systems widely use higher voltage power supplies, posing a challenge to the widespread application of LNAs. Therefore, how to overcome bandwidth limitations and adapt to different power supply voltage environments while maintaining a low noise figure has become a critical problem that urgently needs to be solved in the field of LNA design. Summary of the Invention

[0003] In view of this, in order to solve the technical problem that existing low-noise amplifiers cannot meet the bandwidth requirements of the scenario while maintaining a low noise figure, this invention proposes a low-noise amplifier structure employing multi-inductor coupling and current multiplexing, including a multi-inductor coupling network and a full NMOS current multiplexing network, wherein the multi-inductor coupling network and the full NMOS current multiplexing network are connected, wherein:

[0004] A multi-inductor coupled network is used to achieve broadband maximum power transfer matching and noise figure matching at the input node to achieve high power transfer and low noise figure. It includes an input transistor gate-end series inductor, an input transistor gate-end parallel inductor, an input transistor source-end series inductor, and an input transistor gate-source capacitance. The input transistor gate-end series inductor, the input transistor gate-end parallel inductor, and the input transistor source-end series inductor are coupled in pairs.

[0005] A full NMOS current multiplexing network is used to allow multiple amplifier stages to flow the same current and share the same power supply voltage. It includes a full NMOS cascode amplifier stage module, a full NMOS stack amplifier stage module, an inter-stage matching network, an output matching network, and a voltage biasing module. The full NMOS cascode amplifier stage module, the full NMOS stack amplifier stage module, the inter-stage matching network, and the output matching network are connected in sequence. The voltage biasing module is used to control the gate DC voltage and drain-source DC voltage of the transistors in the full NMOS cascode amplifier stage module and the full NMOS stack amplifier stage module.

[0006] In some embodiments, the NMOS transistor substrate and source terminal in the cascode amplification stage module are further connected to a breakdown resistor; the NMOS transistor substrate and source terminal in the stack structure amplification stage module are also connected to a breakdown resistor. This allows the DC potentials of the substrate and source terminal to be as close as possible, preventing the NMOS transistor from breaking down due to a large voltage difference between the substrate and source terminal.

[0007] Based on the above scheme, this invention provides a low-noise amplifier structure employing multi-inductor coupling and current multiplexing. This invention supports simultaneous wideband input matching and noise matching, supports the use of an all-NMOS LNA to adapt to the power supply voltage of commercial systems, improves the equivalent Q value of the inductors in the input matching network through multiple inductor couplings, increases the design freedom of the input matching network, changes the impedance required to achieve noise figure matching within the target wideband frequency range, and can simultaneously achieve wideband input matching and noise matching. Furthermore, by using all-NMOS current multiplexing technology to adapt to the power supply voltage of commercial systems, it reduces the sensitivity requirements and power supply voltage limitations of high-performance receivers. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the framework of a low-noise amplifier structure employing multi-inductor coupling and current multiplexing according to the present invention;

[0009] Figure 2 This is a schematic diagram of the cascode amplification stage module and the multi-inductor coupling network in a specific embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of the stack structure amplification stage module and inter-stage matching network in a specific embodiment of the present invention;

[0011] Figure 4 This is a simulation curve of the S11 parameter of the low-noise amplifier structure according to a specific embodiment of the present invention;

[0012] Figure 5This is a simulation curve of the S22 parameter of the low-noise amplifier structure according to a specific embodiment of the present invention;

[0013] Figure 6 This is a simulation curve of the S21 parameter of the low-noise amplifier structure in a specific embodiment of the present invention;

[0014] Figure 7 This is a simulation curve of the noise figure of the low-noise amplifier structure according to a specific embodiment of the present invention;

[0015] Figure 8 This is a simulation curve of the K-parameter stability factor of the low-noise amplifier structure in a specific embodiment of the present invention.

[0016] Reference numerals: M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; L1, first inductor; L2, second inductor; L3, third inductor; L4, fourth inductor; L5, fifth inductor; L6, sixth inductor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; C7, seventh capacitor; C8, eighth capacitor. Detailed Implementation

[0017] To increase the bandwidth of LNAs, previous researchers have introduced various topologies, including dual-cavity transformers, high-order matching networks, and pole-tuning techniques. However, most reported LNAs tend to use multiple cascaded resonant cavities with different resonant frequencies to extend bandwidth, which may reduce the frequency response factor (NF). To adapt advanced LNAs to higher voltage power supplies, LDOs or DC-DC circuits are generally used to reduce the voltage. DC-DC circuits can achieve 95% efficiency, but residual ripple in DC-DC circuits can affect the RF signal-to-noise ratio (SNR) through their harmonic terms, degrading performance. LDOs can suppress ripple, but their lower efficiency leads to energy waste. In summary, existing LNAs still cannot meet practical needs.

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0020] It should be understood that the terms "system," "apparatus," "unit," and / or "module" used in this application are a method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0021] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. An element defined by the phrase "comprising an..." does not exclude the presence of other identical elements in the process, method, product, or apparatus that includes the element.

[0022] In the description of the embodiments of this application, "a plurality of" refers to two or more. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0023] Furthermore, flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, the steps can be processed in reverse order or simultaneously. Additionally, other operations can be added to these processes, or one or more steps can be removed from them.

[0024] Reference Figure 1 and Figure 2 This is a schematic diagram of an optional example of the low-noise amplifier structure employing multi-inductor coupling and current multiplexing proposed in this invention. The LNA proposed in this embodiment may include, but is not limited to, the following structures:

[0025] A multi-inductor coupling network includes a first inductor, a second inductor, a third inductor, and a first capacitor. A first terminal of the first inductor is connected to a second terminal of the second inductor. A first terminal of the second inductor is connected to a first terminal of the first capacitor. The second terminal of the first inductor and the first terminal of the third inductor are respectively connected to the full NMOS current multiplexing network.

[0026] The first terminal of the first inductor is also connected to the cascode amplifier stage module; the second terminal of the first capacitor is grounded; and the second terminal of the third inductor is grounded.

[0027] The full NMOS current multiplexing technology network includes a cascode amplification stage module, a stack structure amplification stage module, an interstage matching network, an output matching network, and a voltage bias module. The cascode amplification stage module, the stack structure amplification stage module, the interstage matching network, and the output matching network are connected in sequence. The voltage bias module is used to control the gate DC voltage and drain-source DC voltage of the transistors in the cascode amplification stage module and the stack structure amplification stage module. The cascode amplification stage module is also connected to a multi-inductor coupling network.

[0028] The transistors used in both the cascode amplification stage module and the stack structure amplification stage module are NMOS transistors.

[0029] The aforementioned all-NMOS cascode amplification stage module, all-NMOS stack amplification stage module, inter-stage matching network, output matching network, and voltage biasing module collectively implement the all-NMOS current multiplexing technology network. The sequential connection of the all-NMOS cascode amplification stage module, inter-stage matching network, all-NMOS stack amplification stage module, and output matching network provides a DC path from power to ground for the LNA. The transistor dimensions and voltage control module of the all-NMOS cascode amplification stage module and the all-NMOS stack amplification stage module achieve a reasonable DC voltage distribution for the LNA transistors, reducing the breakdown risk of the transistors in the LNA using all-NMOS current multiplexing technology. The all-NMOS stack amplification stage module can also control the gate-source voltage of the transistors in this stage, further reducing the transistor breakdown risk. The interstage matching network provides a suitable AC ground for both the all-NMOS stack amplifier stage module and the all-NMOS cascode amplifier stage module, without affecting the transmission of DC signals. This allows DC current supplied by the same power supply voltage to flow through both the all-NMOS cascode amplifier stage module and the all-NMOS stack amplifier stage module simultaneously, thus achieving current multiplexing.

[0030] In some embodiments, the cascode amplification stage module includes a first NMOS transistor, a second NMOS transistor, a second capacitor, a first resistor, and a second resistor, wherein:

[0031] The gate of the first NMOS transistor is connected to the second terminal of the first inductor, the source of the first NMOS transistor is connected to the first terminal of the third inductor, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the second NMOS transistor, the first terminal of the second resistor and the first terminal of the second capacitor are connected, and the first terminal of the first resistor is connected to the first terminal of the first inductor.

[0032] Wherein, the second end of the first resistor is connected to the VG1 signal terminal, the second end of the second resistor is connected to the VG2 signal terminal, and the first end of the first resistor serves as the input terminal of the overall LNA.

[0033] The active NMOS transistor connected in cascode is used to amplify the input signal and output it to the next stage of amplified signal. It shares the same current with the amplification stage of the all-NMOS stack structure. By using transistors with similar dimensions to the amplification stage of the all-NMOS stack structure, the drain-source voltage of the transistor is reasonably distributed, reducing the risk of transistor breakdown.

[0034] The connection resistance between the substrate and the source of the NMOS transistor is used to make the DC potentials of the substrate and the source as close as possible, preventing the NMOS transistor from breaking down due to a large voltage difference between the substrate and the source.

[0035] In some embodiments, refer to Figure 3 The interstage matching network includes a fourth inductor, a fifth inductor, a sixth inductor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The stack structure amplification stage module includes a third transistor, a fourth transistor, a third resistor, a fourth resistor, a seventh capacitor, and an eighth capacitor, wherein:

[0036] The first terminal of the fourth inductor, the first terminal of the third capacitor, the first terminal of the third resistor, and the gate of the third transistor are connected. The second terminal of the third resistor is connected to the VG3 signal terminal. The second terminal of the fourth inductor, the second terminal of the third capacitor, and the first terminal of the fourth capacitor are connected. The second terminal of the fifth inductor, the second terminal of the sixth inductor, the first terminal of the fifth capacitor, and the first terminal of the sixth capacitor are connected. The first terminal of the sixth inductor and the second terminal of the fifth capacitor are connected and connected to the front-end module. The second terminal of the sixth capacitor is grounded. The source of the third transistor is connected to the first terminal of the fifth inductor. The drain of the third transistor, the second terminal of the eighth capacitor, and the source of the fourth transistor are connected. The gate of the fourth transistor, the first terminal of the eighth capacitor, the first terminal of the seventh capacitor, and the first terminal of the fourth resistor are connected. The second terminal of the fourth resistor is connected to the VG4 signal terminal. The second terminal of the seventh capacitor is grounded. The drain of the fourth transistor is connected to the next module.

[0037] The stacked active NMOS transistors are used to amplify the input signal from the upper amplifier and output the amplified signal. They are used to control the gate-source voltage of the NMOS transistors to prevent the transistor from breaking down due to a large gate-source voltage difference. They share the same current with the full NMOS cascode structure amplifier stage. By using transistors with similar dimensions to the full NMOS cascode structure amplifier stage, the drain-source voltage of the transistors can be reasonably distributed, reducing the risk of transistor breakdown.

[0038] The connection resistance between the substrate and the source of the NMOS transistor is used to make the DC potentials of the substrate and the source as close as possible, preventing the NMOS transistor from breaking down due to a large voltage difference between the substrate and the source.

[0039] The series inductance at the drain end of the output transistor of the all-NMOS cascode structure amplifier stage module and the series inductance at the source end of the input transistor of the all-NMOS stack structure amplifier stage module are connected to the AC-to-ground capacitor at the node. This is used to provide the AC ground for the inter-stage matching network at this node, without interfering with the DC current flowing from the later stage to the earlier stage, thus realizing DC current multiplexing.

[0040] The input transistors of the all-NMOS stack structure amplifier stage module have a gate-parallel inductor, a gate-parallel capacitor, and a source-series inductor. The output transistors of the all-NMOS cascode structure amplifier stage module have a drain-series inductor and a parallel capacitor. Together with the aforementioned AC-to-ground capacitor, they achieve interstage conjugate matching and avoid power reflection.

[0041] Similarly, in this embodiment, the substrate and source of the NMOS transistor are connected to a resistor to make the DC potentials of the substrate and source as close as possible, preventing the NMOS transistor from breaking down due to a large voltage difference between the substrate and source.

[0042] In some embodiments, the voltage biasing module specifically includes:

[0043] The drain power supply voltage of the output stage NMOS transistor serves as the sole power supply for the current-reused LNA. The DC current flowing out of this power supply passes through both the cascode amplification stage module and the stack structure amplification stage module to achieve current reuse.

[0044] The gate bias voltage of an nmos transistor sets an appropriate DC voltage at the gate of each stage of the transistor, making the drain-source voltage of each transistor approximately equal and reducing the risk of breakdown of transistors that reuse DC current.

[0045] Based on the above scheme, the coupling between the series inductance at the gate end and the series inductance at the source end of the input transistor improves the Q value of the series inductance at the gate end, the coupling between the parallel inductance at the gate end and the series inductance at the source end of the input transistor improves the Q value of the parallel inductance at the gate end, and the coupling between the parallel inductance at the gate end and the series inductance at the gate end of the input transistor improves the Q value of the parallel inductance at the gate end, reduces the signal leakage caused by the parasitic resistance of the parallel inductance at the gate end, and improves the noise figure. The coupling between the parallel inductance at the gate end and the series inductance at the gate end of the input transistor changes the real and imaginary impedances of the parallel inductance at the gate end, making the impedance required to achieve noise figure matching within the target broadband frequency range close to the impedance required to achieve conjugate matching.

[0046] Figure 4 The figure shown is a simulation curve of the S11 parameter of the low-noise amplifier provided in a specific embodiment of the present invention. (Refer to...) Figure 4 As can be seen, the input matching curve of S11 is below -10dB in the frequency range of 9.4GHz-15GHz. The results show that the low-noise amplifier provided in the specific embodiment of the present invention has good input matching in the frequency range of 9.4GHz-15GHz.

[0047] Figure 5 The figure shown is a simulation curve of the S22 parameter of the low-noise amplifier provided in a specific embodiment of the present invention. (Refer to...) Figure 5 As can be seen, the input matching curve of S22 is below -10dB in the frequency range of 11GHz-13.5GHz. The results show that the low-noise amplifier provided in the specific embodiment of the present invention has good output matching in the frequency range of 11GHz-13.5GHz.

[0048] Figure 6 The figure shown is a simulation curve of the S21 parameter of the low-noise amplifier provided in a specific embodiment of the present invention. (Refer to...) Figure 6 As can be seen, the S21 gain curve has only 2dB of ripple in the frequency range of 10GHz-14GHz. The results show that the low-noise amplifier provided in the specific embodiment of the present invention has a flat gain curve in the frequency range of 10GHz-14GHz.

[0049] Figure 7 The figure shown is a simulation curve of the noise figure of the low-noise amplifier provided in a specific embodiment of the present invention. (Refer to...) Figure 7 As can be seen, the noise figure simulation curve is below 2dB in the frequency range of 9.5GHz-15GHz. The results show that the low-noise amplifier provided by the specific embodiment of the present invention has good noise figure matching and low noise figure in the frequency range of 9.5GHz-15GHz.

[0050] Figure 8 The figure shown is a simulation curve of the K-parameter stability factor of the low-noise amplifier provided in a specific embodiment of the present invention. (Refer to...) Figure 8 As can be seen, the simulated stability factor curves for the K-parameter are generally above 10 in the frequency range of 9GHz-15GHz, which is much greater than 1. The results show that the low-noise amplifier provided in the specific embodiment of this invention has good stability in the frequency range of 9GHz-15GHz.

[0051] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. An LNA employing multi-inductor coupling and current multiplexing, characterized in that, This includes a multi-inductively coupled network and a full NMOS current multiplexing network, which are connected, wherein: A multi-inductor coupling network includes a first inductor, a second inductor, a third inductor, and a first capacitor. A first terminal of the first inductor is connected to a second terminal of the second inductor. A first terminal of the second inductor is connected to a first terminal of the first capacitor. The second terminal of the first inductor and the first terminal of the third inductor are respectively connected to the full NMOS current multiplexing network. The full NMOS current multiplexing technology network includes a cascode amplification stage module, a stack structure amplification stage module, an interstage matching network, an output matching network, and a voltage bias module. The cascode amplification stage module, the stack structure amplification stage module, the interstage matching network, and the output matching network are connected in sequence. The voltage bias module is used to control the gate DC voltage and drain-source DC voltage of the transistors in the cascode amplification stage module and the stack structure amplification stage module. The transistors used in both the cascode amplification stage module and the stack structure amplification stage module are NMOS transistors. The cascode amplification stage module includes a first NMOS transistor, a second NMOS transistor, a second capacitor, a first resistor, and a second resistor, wherein: The gate of the first nmos transistor is connected to the second terminal of the first inductor, the source of the first nmos transistor is connected to the first terminal of the third inductor, the drain of the first nmos transistor is connected to the source of the second nmos transistor, the gate of the second nmos transistor, the first terminal of the second resistor and the first terminal of the second capacitor are connected, and the first terminal of the first resistor is connected to the first terminal of the first inductor. The interstage matching network includes a fourth inductor, a fifth inductor, a sixth inductor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor, wherein: The first end of the fourth inductor is connected to the first end of the third capacitor, the second end of the fourth inductor, the second end of the third capacitor and the first end of the fourth capacitor are connected, the second end of the fifth inductor, the second end of the sixth inductor, the first end of the fifth capacitor and the first end of the sixth capacitor are connected, and the first end of the sixth inductor and the second end of the fifth capacitor are connected. The stack structure amplification stage module includes a third transistor, a fourth transistor, a third resistor, a fourth resistor, a seventh capacitor, and an eighth capacitor, wherein: The gate of the third transistor, the first terminal of the fourth inductor, and the first terminal of the third resistor are connected. The source of the third transistor is connected to the first terminal of the fifth inductor. The drain of the third transistor, the second terminal of the eighth capacitor, and the source of the fourth transistor are connected. The gate of the fourth transistor, the first terminal of the eighth capacitor, the first terminal of the seventh capacitor, and the first terminal of the fourth resistor are connected.

2. The LNA employing multi-inductive coupling and current multiplexing according to claim 1, characterized in that, The nmos transistor substrate and source terminal in the cascode amplification stage module are also connected to a breakdown resistor.

3. The LNA employing multi-inductor coupling and current multiplexing according to claim 1, characterized in that, The NMOS transistor substrate and source terminal in the stack structure amplification stage module are also connected to a breakdown resistor.

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