A variable gain amplifier and radio frequency front end

Abstract

The embodiments of the present disclosure provide a variable gain amplifier and a radio frequency front end, wherein the variable gain amplifier comprises: a variable gain module and a compensation module; the variable gain module comprises a main transistor pair and a cross-coupled transistor pair; the compensation module comprises a turned-off first transistor and a turned-off second transistor; wherein, when the phase of the attenuation state of the variable gain module lags behind the phase of the reference state, the input end and the output end of the first transistor are respectively connected to the input end and the output end of one of the main transistor pair, and the input end and the output end of the second transistor are respectively connected to the input end and the output end of the other of the main transistor pair; or, when the phase of the attenuation state of the variable gain module leads the phase of the reference state, the input end and the output end of the first transistor are respectively connected to the input end and the output end of one of the cross-coupled transistor pair, and the input end and the output end of the second transistor are respectively connected to the input end and the output end of the other of the cross-coupled transistor pair.

Description

Technical Field

[0001] The present disclosure relates to the field of communications, and in particular to a variable gain amplifier and a radio frequency front end. Background Art

[0002] Phased array technology is widely used in millimeter wave communications, radar and other fields. The phased array system contains a large number of transceiver components, and the performance of the transceiver components will directly affect the performance of the phased array system. The transceiver components of the phased array system include both the transmit link and the receive link, which are mainly used to amplify the signal and control the phase and amplitude changes of the signal. In traditional transceiver components, both the transmit link and the receive link include variable gain modules for adjusting the phase or amplitude.

[0003] In order to adapt to high-frequency scenarios such as millimeter-wave communications and high-performance radar applications, the variable gain module needs to have a smaller phase offset. Summary of the invention

[0004] The embodiments of the present disclosure provide a variable gain amplifier and a radio frequency front end, which can compensate for the phase shift caused by the different parasitic capacitances of the variable gain module under different gains.

[0005] An embodiment of the present disclosure provides a variable gain amplifier, comprising: a variable gain module, configured to perform gain adjustment based on a received gain control signal; the variable gain module comprises a main transistor pair and a cross-coupled transistor pair; a compensation module, comprising a turned-off first transistor and a turned-off second transistor; wherein, when the phase of the attenuation state of the variable gain module lags behind the phase of the reference state, the input end and the output end of the first transistor are respectively connected to the input end and the output end of one of the main transistor pair, and the input end and the output end of the second transistor are respectively connected to the input end and the output end of the other of the main transistor pair; or, when the phase of the attenuation state of the variable gain module leads the phase of the reference state, the input end and the output end of the first transistor are respectively connected to the input end and the output end of one of the cross-coupled transistor pair, and the input end and the output end of the second transistor are respectively connected to the input end and the output end of the other of the cross-coupled transistor pair.

[0006] In the scheme disclosed in the present invention, the variable gain amplifier includes a variable gain module and a compensation module. The variable gain module is configured to adjust the gain based on the received gain control signal, and includes a main transistor pair and a cross-coupled transistor pair; the compensation module includes a first transistor that is turned off and a second transistor that is turned off. The variable gain module includes an attenuation state and a reference state. The reference state is a state in which the gain of the variable gain module is maximum, and the attenuation state is a state in which the gain of the variable gain module is not maximum. When the gain of the variable gain module changes, its parasitic capacitance is different, resulting in a phase shift.

[0007] When the attenuation state phase of the variable gain module leads the reference state phase, the input and output ends of the first transistor are respectively connected to the input and output ends of one of the main transistor pair, and the input and output ends of the second transistor are respectively connected to the input and output ends of the other of the main transistor pair; at this time, the parasitic capacitance of the turned-off first transistor and the turned-off second transistor can compensate for the parasitic capacitance of the cross-coupled transistor pair, thereby reducing the parasitic capacitance difference between the cross-coupled transistor pair and the main transistor pair, thereby compensating for the phase shift.

[0008] When the attenuation state phase of the variable gain module lags behind the reference state phase, the input and output ends of the first transistor are respectively connected to the input and output ends of one of the cross-coupled transistor pair, and the input and output ends of the second transistor are respectively connected to the input and output ends of the other of the cross-coupled transistor pair; at this time, the parasitic capacitance of the turned-off first transistor and the turned-off second transistor can compensate for the parasitic capacitance of the main transistor pair, thereby reducing the parasitic capacitance difference between the cross-coupled transistor pair and the main transistor pair, thereby compensating for the phase shift.

[0009] In some embodiments, the variable gain module has multiple attenuation states, each attenuation state has a phase difference with a reference state; if the median of the multiple phase differences is positive, the phase of the variable gain module is advanced; or, if the median of the multiple phase differences is negative, the phase of the variable gain module is delayed. The phase advance or phase lag of the median of the phase difference is compensated, and all attenuation states can be compensated by a first transistor and a second transistor, which saves the number of first transistors and second transistors, and the circuit is simple and small in area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of the structure of a transceiver component in the related art is shown;

[0011] Figure 2A The invention shows a block diagram of a variable gain amplifier provided by an embodiment of the present invention. Figure 1 ;

[0012] Figure 2B A second block diagram of a variable gain amplifier provided by an embodiment of the present disclosure is shown;

[0013] Figure 3A The structure of the variable gain amplifier provided in the first embodiment of the present disclosure is shown. Figure 1 ;

[0014] Figure 3B A second structural diagram of a variable gain amplifier provided in the second embodiment of the present disclosure is shown;

[0015] Figure 3C Shows Figure 3B Equivalent circuit diagram of the structure shown;

[0016] Figure 4A A third structural diagram of a variable gain amplifier provided in the third embodiment of the present disclosure is shown;

[0017] Figure 4B A fourth structural diagram of a variable gain amplifier provided in a fourth embodiment of the present disclosure is shown;

[0018] Figure 5A A fifth structural diagram of a variable gain amplifier provided in a fifth embodiment of the present disclosure is shown;

[0019] Figure 5B A sixth structural diagram of a variable gain amplifier provided in a sixth embodiment of the present disclosure is shown;

[0020] Fig. 6A A seventh structural diagram of a variable gain amplifier provided in a seventh embodiment of the present disclosure is shown;

[0021] Figure 6B FIG. 8 shows a structural schematic diagram of a variable gain amplifier provided by an eighth embodiment of the present disclosure;

[0022] Fig. 7A A ninth structural diagram of a variable gain amplifier provided by a ninth embodiment of the present disclosure is shown;

[0023] Figure 7B A structural schematic diagram 10 of a variable gain amplifier provided by Embodiment 10 of the present disclosure is shown;

[0024] Fig. 8A A structural schematic diagram eleven of a variable gain amplifier provided in the eleventh embodiment of the present disclosure is shown;

[0025] Figure 8B A structural schematic diagram 12 of a variable gain amplifier provided in a 12th embodiment of the present disclosure is shown;

[0026] Fig.9A A schematic diagram showing the variation of parasitic phase modulation with frequency when the compensation module is not used provided in the third embodiment of the present disclosure;

[0027] Fig. 9B A schematic diagram showing the variation of parasitic phase modulation with frequency when using a compensation module provided in the third embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0034] In the related art, each antenna unit in the phased array circuit is equipped with a transceiver component, and multiple transceiver components are synthesized to obtain a phased array. Figure 1 FIG. 1 shows a schematic diagram of the structure of a transceiver component and an antenna in the related art. Figure 1 As shown, the transceiver assembly includes a transmission link and a receiving link; the transmission link and the receiving link are switched through the transceiver channel switches 101 and 108. The transmission link includes a power amplifier 102, a phase shifter 103 and a variable gain amplifier 104; the receiving link includes a low noise amplifier 105, a phase shifter 106 and a variable gain amplifier 107. Among them, the phase shifters 103 and 106 are respectively used to realize the phase control of the transmission link and the receiving link, the variable gain amplifiers 104 and 107 are respectively used to realize the amplitude control of the transmission link and the receiving link, the power amplifier 102 is used to realize the signal amplification of the transmission link, and the low noise amplifier 105 is used to realize the signal amplification of the receiving link.

[0035] Since the parasitic capacitance of the transistor in the variable gain amplifier has different capacitance values ​​under different bias currents, the output phase of the variable gain amplifier will change with the change of the bias current. How to achieve a relatively small phase offset under different gains is an urgent problem to be solved.

[0036] In this regard, the present disclosure proposes the following implementation modes.

[0037] Figure 2A The invention shows a block diagram of a variable gain amplifier provided by an embodiment of the present invention. Figure 1 , Figure 2B FIG2 shows a block diagram of a variable gain amplifier provided by an embodiment of the present disclosure. Figure 2A and Figure 2B As shown, the variable gain amplifier includes: a variable gain module 210, which is configured to perform gain adjustment based on a received gain control signal; the variable gain module 210 includes a main transistor pair 211, 212 and a cross-coupled transistor pair 213, 214; a compensation module 220, including a turned-off first transistor M1 and a turned-off second transistor M2; wherein the input end of the main transistor 211 is connected to the input end of the cross-coupled transistor 213, the output end of the main transistor 211 is connected to the output end of the cross-coupled transistor 214, the input end of the main transistor 212 is connected to the input end of the cross-coupled transistor 214, and the main transistor 212 is connected to the output end of the cross-coupled transistor 213 to form a cross-coupling relationship.

[0038] It should be noted that Figure 2A The diagram shows the connection between the compensation module 220 and the variable gain module 210 when the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state; Figure 2B It illustrates the connection mode between the compensation module 220 and the variable gain module 210 when the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state.

[0039] In some embodiments, the variable gain amplifier is a current canceling variable gain amplifier (VGA), which includes a main transistor pair 211, 212 and a cross-coupled transistor pair 213, 214, and the cross-coupled transistor pair 213, 214 is used to cancel the current flowing through the main transistor pair 211, 212, thereby reducing the current cancellation and providing a dynamically adjustable gain. The parasitic phase modulation of the variable gain amplifier at low frequencies is small.

[0040] In some embodiments, the gain of the variable gain module 210 has multiple gears, the reference state is the state in which the gain of the variable gain module 210 is the maximum, and the attenuation state is the state in which the gain of the variable gain module 210 is not the maximum. The variable gain module 210 can have multiple attenuation states, and the gain of the variable gain module 210 is different in different attenuation states, and the attenuation state includes a state in which the gain is 0. When the gain is different, the variable gain module 210 is in different states (including different attenuation states, reference states), the states of the transistors in the variable gain module 210 are different (for example, the number of turn-offs of the array transistors is different, or the channel conduction current of the voltage-controlled transistor is different), and the parasitic capacitance of the transistors is different, resulting in different phases.

[0041] like Figure 2A As shown, when the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state, the parasitic capacitance of the main transistor pair 211, 212 is greater than the parasitic capacitance of the cross-coupled transistor pair 213, 214. The input terminal and the output terminal of the first transistor M1 are respectively connected to the input terminal and the output terminal of one of the cross-coupled transistor pairs 213, and the input terminal and the output terminal of the second transistor M2 are respectively connected to the input terminal and the output terminal of the other cross-coupled transistor pair 214; at this time, the turned-off first transistor M1 and the turned-off second transistor M2 have parasitic capacitance, which can compensate for the parasitic capacitance of the cross-coupled transistor pair 213, 214, thereby reducing the parasitic capacitance difference between the cross-coupled transistor pair 213, 214 and the main transistor pair 211, 212, thereby compensating for the phase shift.

[0042] like Figure 2BAs shown, when the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state, the parasitic capacitance of the main transistor pair 211, 212 is smaller than the parasitic capacitance of the cross-coupled transistor pair 213, 214. The input terminal and the output terminal of the first transistor M1 are respectively connected to the input terminal and the output terminal of one of the main transistor pairs 211, and the input terminal and the output terminal of the second transistor M2 are respectively connected to the input terminal and the output terminal of the other of the main transistor pair 212; at this time, the turned-off first transistor M1 and the turned-off second transistor M2 have parasitic capacitance, which can compensate for the parasitic capacitance of the main transistor pair 211, 212, thereby reducing the parasitic capacitance difference between the cross-coupled transistor pair 213, 214 and the main transistor pair 211, 212, thereby compensating for the phase shift.

[0043] Therefore, the compensation module is used to realize the compensation of the phase lag or phase advance of the variable gain module, so that the phase offset of the variable gain amplifier can be reduced or even eliminated. The circuit is simple, easy to realize, and occupies a small area.

[0044] In some embodiments, the size of the first transistor M1 and the second transistor M2 is proportional to the phase difference between the reference state and the attenuation state. The size mentioned here may be the channel width-to-length ratio of the transistor, or may simply be the channel length of the transistor. When there are multiple first transistors or multiple second transistors, the size of the first transistor M1 is the equivalent size of the multiple first transistors, and the size of the second transistor M2 is the equivalent size of the multiple second transistors. In some embodiments, when the phase difference between the reference state and the attenuation state is large, the size of the first transistor M1 and the second transistor M2 can be set larger, so that the equivalent capacitance of the first transistor M1 and the second transistor M2 is larger, and can be adapted to the larger phase difference between the reference state and the attenuation state. Similarly, when the phase difference between the reference state and the attenuation state is small, the size of the first transistor M1 and the second transistor M2 can be set smaller, so that the equivalent capacitance of the first transistor M1 and the second transistor M2 is smaller, and can be adapted to the smaller phase difference between the reference state and the attenuation state.

[0045] In other embodiments, when the phase difference between the reference state and the attenuation state is large and the size of a single first transistor M1 and a single second transistor M2 cannot meet the requirement of the phase difference, the number of first transistors M1 and second transistors M2 can be increased, but the number of first transistors M1 and second transistors M2 is fixed.

[0046] In some embodiments, the transistor types of the first transistor M1 and the second transistor M2 are the same as the transistor types of the cross-coupled transistor pair and the main transistor pair. For example, these transistors are NMOS transistors, PMOS transistors, NPN transistors, or PNP transistors at the same time, so that the PVT (Process, Voltage, Temperature) parameters of the first transistor M1, the second transistor M2, the cross-coupled transistor pair, and the main transistor pair are consistent, thereby ensuring the consistency of the process angle under the PVT parameters. Avoid the situation where the device performance is affected by different PVT parameters or different process angles.

[0047] In addition, if the PVT parameters of the transistors in the compensation module and the transistors in the variable gain module are consistent, the influence of the PVT parameters on the equivalent capacitance of the transistors in the compensation module and the parasitic capacitance of the transistors in the variable gain module can be consistent, so a better compensation effect can be achieved when the PVT parameters are consistent.

[0048] It should be noted that Figure 2A and Figure 2B The first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 in the illustrated variable gain amplifier are only used to illustrate the inclusion relationship, and are not used to limit the connection relationship between the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214. The specific connection relationship will be described in detail later.

[0049] Figure 3A The structure of a variable gain amplifier provided by the embodiment of the present disclosure is shown. Figure 1 , Figure 3B FIG2 shows a structural schematic diagram of a variable gain amplifier provided by an embodiment of the present disclosure. It should be noted that: Figure 3A for Figure 2A A refinement of the block diagram shown, Figure 3B for Figure 2B The structural refinement of the block diagram shown, namely Figure 3A The diagram shows a situation where the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state. Figure 3B The diagram shows the situation where the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state. Figure 2A , Figure 2B , Figure 3A and Figure 3BAs shown, the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 are all array transistors. The array transistor includes N transistors, where N is an integer greater than or equal to 2, wherein the transistors in the array transistor are digitally controlled transistors, and the control signals of their control terminals (gates or bases) are digital signals. That is to say, the transistors in the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 are arranged in an array, and the input terminals of the transistors in the array transistors are connected together, and the output terminals of the transistors in the array transistors are connected together, so as to control and adjust the current of the array transistors through control signals. Here, Figure 3A and Figure 3B The following description is made by taking as an example that all transistors in the array transistor are NMOS transistors.

[0050] The first master transistor unit 211 includes N first master transistors M 2P The second master transistor unit 212 includes N second master transistors M 2N The first cross-coupled transistor unit 213 includes N first cross-coupled transistors M 3P The second cross-coupled transistor unit 214 includes N second cross-coupled transistors M 3N . N first master transistors M 2P The input end is connected to N first cross-coupled transistors M 3P The input terminal, N second master transistors M 2N The input end of the transistor M is connected to N second cross-coupled transistors M 3N N first main transistors M 2P The output end of the transistor M is connected to N second cross-coupled transistors 3N The output terminal, N second master transistors M 2N The output end of the transistor M is connected to N first cross-coupled transistors 3P The output terminal.

[0051] The first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 operate in parallel, and the N transistors in the first main transistor unit 211 operate in parallel, the N transistors in the second main transistor unit 212 operate in parallel, the N transistors in the first cross-coupled transistor unit 213 operate in parallel, and the N transistors in the second cross-coupled transistor unit 214 operate in parallel.

[0052] In some embodiments, the transistors in the main transistor pair and the cross-coupled transistors are all common-gate transistors; the control ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are the gates of the transistors, and the control ends of the first main transistor unit 211 and the second main transistor unit 212 are controlled by a first gain control signal, and the control ends of the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are controlled by a second gain control signal, and the first gain control signal and the second gain control signal are synchronous inverted signals.

[0053] The first gain control signal includes N first control signals Va1-VaN (for clarity, Figure 3A and Figure 3B Only Va1 is shown in FIG. 1 ), each first control signal controls a first main transistor M 2P and a second master transistor M 2N For example, the first control signal Va1 controls the first first main transistor M 2P and the first second master transistor M 2N , the first control signal VaN controls the Nth first main transistor M 2P and the Nth second master transistor M 2N The second gain control signal includes N second control signals Vb1-VbN (for clarity, Figure 3A and Figure 3B Only Vb1 is shown in FIG. 1 ), each second control signal controls a first cross-coupled transistor M 3P and a second cross-coupled transistor M 3N For example, the second control signal Vb1 controls the first first cross-coupled transistor M 3P and the first second cross-coupled transistor M 3N , the second control signal VbN controls the Nth first cross-coupled transistor M 3P and the Nth second cross-coupled transistor M 3N .

[0054] Here, the first control signal and the second control signal can specifically be digital voltage signals. In addition, the first control signal and the second control signal are synchronous inverted signals, and the effective numbers of the first control signal Va1-VaN and the second control signal Vb1-VbN are complementary, so that the conduction numbers of the main transistor and the cross-coupled transistor are complementary, and different gain states are achieved. Among them, the first control signal or the second control signal is effective means that the control signal can control the conduction of the corresponding transistor. "Complementary effective numbers" means that the sum of the effective numbers of the control signals is a fixed value, and the sum of the effective numbers in the first control signal Va1-VaN and the effective numbers in the second control signal Vb1-VbN is the fixed value. For example, the fixed value is N. If n first control signals are valid, then Nn second control signals are valid.

[0055] In some embodiments, the input ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are the sources of the transistors, and the output ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are the drains of the transistors.

[0056] In some embodiments, the input terminals of the first main transistor unit 211 and the first cross-coupled transistor unit 213 receive a positive input signal Vin+, and the input terminals of the second main transistor unit 212 and the second cross-coupled transistor unit 214 receive a negative input signal Vin-. The positive input signal Vin+ and the negative input signal Vin- are differential input signals. The output terminals of the first main transistor unit 211 and the second cross-coupled transistor unit 214 output a positive output signal Vout+, and the output terminals of the second main transistor unit 212 and the first cross-coupled transistor unit 213 output a negative output signal Vout-. The positive output signal Vout+ and the negative output signal Vout- are differential input signals.

[0057] like Figure 3A and Figure 3B As shown, the first transistor M1 and the second transistor M2 are both NMOS transistors, the input terminals of the first transistor M1 and the second transistor M2 are the sources of the transistors, and the output terminals of the first transistor M1 and the second transistor M2 are the drains of the transistors. The control terminals of the first transistor M1 and the second transistor M2 are both grounded. Thus, the first transistor M1 and the second transistor M2 can constitute a turned-off first transistor M1 and a turned-off second transistor M2.

[0058] In other embodiments, the transistors in the variable gain module 210 may all be PMOS transistors, the first transistor M1 and the second transistor M2 may also both be PMOS transistors, and the control terminals of the first transistor M1 and the second transistor M2 are both connected to the power supply voltage VDD.

[0059] Combination Figure 3A and Figure 3B As shown, during circuit design, the variable gain module is simulated to obtain the phase of the variable gain module in the reference state and the attenuation state in the target frequency band. The reference state and different attenuation states correspond to different gains.

[0060] The reference state is: the transistors in the first main transistor unit 211 and the second main transistor unit 212 are all turned on, and the transistors in the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are all turned off. At this time, the gain of the variable gain module is in the first gain state.

[0061] The variable gain block has N attenuation states, where:

[0062] The first decay state is: N first main transistors M 2P , N second master transistors M 2N The transistors in each of the N first cross-coupled transistors M are turned off, and the rest are turned on. 3P , N second cross-coupled transistors M 3N One of the transistors in each of the two transistors is turned on, and the rest are turned off; at this time, the gain of the variable gain module is in the second gain state;

[0063] The second decay state is: N first main transistors M 2P , N second master transistors M 2N Two transistors in each of the N first cross-coupled transistors M are turned off and the rest are turned on. 3P , N second cross-coupled transistors M 3N Two transistors in each of the two transistors are turned on, and the rest are turned off; at this time, the gain of the variable gain module is in the third gain state;

[0064] Similarly, the N-1th decay state: N first main transistors M 2P , N second master transistors M 2N The transistors in each of the N-1 transistors are turned off, and the rest are turned on, and the N first cross-coupled transistors M 3P , N second cross-coupled transistors M 3N N-1 transistors in each are turned on, and the rest are turned off; at this time, the gain of the variable gain module is in the Nth gain state.

[0065] Nth decay state: N first master transistors M 2P, N second master transistors M 2N All transistors in the N first cross-coupled transistors M are turned off. 3P , N second cross-coupled transistors M 3N All transistors in are turned on; at this time, the gain of the variable gain module is in the N+1th gain state.

[0066] Because the number of transistors turned off in the N attenuation states and the reference state is different, resulting in a change in the equivalent capacitance of the turned-off transistors, the N attenuation states and the reference state have N+1 different phases respectively.

[0067] Compare N attenuation states with the reference state in turn to obtain N phase differences, sort the N phase differences in order of magnitude, and the median is the phase difference in the middle position among the multiple phase differences sorted in order of magnitude. If the median of the N phase differences is positive, it means that the phase of the attenuation state is ahead of the phase of the reference state, that is, the phase of the variable gain module is ahead, then use Figure 3A The compensation module 220 shown; if the median of the N phase differences is negative, it means that the phase of the attenuation state lags behind the phase of the reference state, that is, the phase lag of the variable gain module, then use Figure 3B The compensation module 220 is shown.

[0068] The variable gain amplifier provided in the embodiment of the present disclosure can compensate for the phase advance or phase lag of the median of the phase difference. All attenuation states can be compensated by a first transistor and a second transistor, thereby saving the number of transistors included in the compensation module and thus saving device area.

[0069] like Figure 3A As shown, when the phase of the attenuation state of the variable gain module 210 leads the phase of the reference state, the first transistor M1 and the second transistor M2 are respectively connected in parallel to the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214, and the gates of the first transistor M1 and the second transistor M2 are grounded; at this time, the parasitic capacitance of the turned-off first transistor M1 and the turned-off second transistor M2 can compensate for the parasitic capacitance of the cross-coupled transistor pair, thereby reducing the parasitic capacitance difference between the cross-coupled transistor pair and the main transistor pair, thereby compensating for the phase shift.

[0070] like Figure 3BAs shown, when the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state, the first transistor M1 and the second transistor M2 are respectively connected in parallel to the first main transistor unit 211 and the second main transistor unit 212, and the gates of the first transistor M1 and the second transistor M2 are grounded; at this time, the parasitic capacitance of the turned-off first transistor M1 and the turned-off second transistor M2 can compensate for the parasitic capacitance of the main transistor pair, thereby reducing the parasitic capacitance difference between the cross-coupled transistor pair and the main transistor pair, thereby compensating for the phase shift.

[0071] Therefore, the compensation module is used to achieve compensation for the phase lag or phase advance of the variable gain module, so that the phase offset of the variable gain amplifier can be reduced or even eliminated.

[0072] Figure 3C Shows Figure 3B Here, the equivalent capacitance of the transistor turned off in the array transistor is Cds. For example, X first main transistors M are turned off in the first main transistor unit 211. 2P , which turns off the X first master transistors M 2P The equivalent capacitance is Cds1, and X second main transistors M in the second main transistor unit 212 are turned off. 2N , which turns off the X second master transistors M 2N The equivalent capacitance is Cds1; NX first cross-coupled transistors M in the first cross-coupled transistor unit 213 are turned off. 3P , which turns off the NX first cross-coupled transistors M 3P The equivalent capacitance is Cds2, and Nx second cross-coupled transistors M in the second cross-coupled transistor unit 214 are turned off. 3N , which turns off the NX second cross-coupled transistors M 3N The equivalent capacitance of the first transistor M1 and the second transistor M2 is Ccomp. Thus, Ccomp can compensate for Cds1 of the main transistor pair, so that Cds1+Ccomp=Cds2, thereby reducing the parasitic capacitance difference between the cross-coupled transistor pair and the main transistor pair, thereby compensating for the phase shift.

[0073] Figure 4A FIG3 shows a structural schematic diagram of a variable gain amplifier provided by an embodiment of the present disclosure. Figure 4B FIG4 shows a structural diagram of a variable gain amplifier provided by an embodiment of the present disclosure. It should be noted that: Figure 4A for Figure 2A A refinement of the block diagram shown, Figure 4B for Figure 2BThe structural refinement of the block diagram shown, namely Figure 4A The diagram shows a situation where the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state. Figure 4B The diagram shows the situation where the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state. Figure 2A , Figure 2B , Figure 4A and Figure 4B As shown, the variable gain module 210 also includes a third transistor M3 and a fourth transistor M4 with a common source; the input ends of the first main transistor unit 211 and the first cross-coupled transistor unit 213 are connected to the drain of the third transistor M3, the source of the third transistor M3 is grounded, and the gate of the third transistor M3 receives the positive input signal Vin+; the input ends of the second main transistor unit 212 and the second cross-coupled transistor unit 214 are connected to the drain of the fourth transistor M4, the source of the fourth transistor M4 is grounded, and the gate of the fourth transistor M4 receives the negative input signal Vin-. Among them, the positive input signal Vin+ and the negative input signal Vin- are differential input signals. Here, the third transistor M3 and the fourth transistor M4 are used as input differential pairs, which can provide transconductance for the gain of the variable gain module.

[0074] It should be noted that Figure 4A and Figure 4B The structures of the main transistor pair, the cross-coupled transistor pair and the compensation module 220 are shown in FIG. Figure 3A and Figure 3B The structures of the main transistor pair, the cross-coupled transistor pair and the compensation module 220 are shown to be the same. Figure 4A and Figure 4B The specific connection relationship between the main transistor pair, the cross-coupled transistor pair and the compensation module 220 can be referred to Figure 3A and Figure 3B description and understand.

[0075] Figure 5A FIG5 shows a structural schematic diagram of a variable gain amplifier provided by an embodiment of the present disclosure. Figure 5B FIG6 shows a structural diagram of a variable gain amplifier provided by an embodiment of the present disclosure. It should be noted that: Figure 5A for Figure 2A A refinement of the block diagram shown, Figure 5B for Figure 2B The structural refinement of the block diagram shown, namely Figure 5A The diagram shows a situation where the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state. Figure 5B The diagram shows the situation where the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state. Figure 2A , Figure 2B , Figure 5A and Figure 5B As shown, the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are all array transistors. The array transistor includes N transistors, where N is an integer greater than or equal to 2. Here, Figure 5A and Figure 5B The following description is made by taking the example that all transistors in the array transistor are NPN transistors.

[0076] The first master transistor unit 211 includes N first master transistors Q 1P The second master transistor unit 212 includes N second master transistors Q 1N The first cross-coupled transistor unit 213 includes N first cross-coupled transistors Q 2P The second cross-coupled transistor unit 214 includes N second cross-coupled transistors Q 2N . N first master transistors Q 1P The input end is connected to N first cross-coupled transistors Q 2P The input terminal of N second main transistors Q 1N The input terminal is connected to N second cross-coupled transistors Q 2N N first main transistors Q 1P The output end of the transistor is connected to N second cross-coupled transistors Q 2N The output terminal of N second main transistors Q 1N The output end is connected to N first cross-coupled transistors Q 2P The output terminal.

[0077] In some embodiments, the transistors in the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 are all common-base transistors, and the control ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 are the bases of the transistors, and the control ends of the first main transistor unit 211 and the second main transistor unit 212 are controlled by a first gain control signal, and the control ends of the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are controlled by a second gain control signal, and the first gain control signal and the second gain control signal are synchronous inverted signals.

[0078] The first gain control signal includes N first control signals Va1-VaN (for clarity, Figure 5A and Figure 5B Only Va1 is shown in FIG. 1 ), each first control signal controls a first main transistor Q 1P and a second main transistor Q1N The second gain control signal includes N second control signals Vb1-VbN (for clarity, Figure 5A and Figure 5B Only Vb1 is shown in FIG. 1 ), each second control signal controls a first cross-coupled transistor Q 2P and a second cross-coupled transistor Q 2N Here, the first control signal and the second control signal may be digital voltage signals. Furthermore, the effective numbers of the first control signals Va1-VaN and the second control signals Vb1-VbN are opposite, so that the conduction numbers of the main transistor and the cross-coupled transistor are complementary to achieve different gain states.

[0079] In some embodiments, the input ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are emitters of the transistors, and the output ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are collectors of the transistors.

[0080] like Figure 5A and Figure 5B As shown, the first transistor M1 and the second transistor M2 are both NPN transistors, the input ends of the first transistor M1 and the second transistor M2 are emitters of the transistors, and the output ends of the first transistor M1 and the second transistor M2 are collectors of the transistors.

[0081] The control terminals of the first transistor M1 and the second transistor M2 are both grounded, so that the first transistor M1 and the second transistor M2 may constitute a turned-off first transistor M1 and a turned-off second transistor M2.

[0082] In some other embodiments, the transistors in the variable gain module 210 may all be PNP transistors, the first transistor M1 and the second transistor M2 may also both be PNP transistors, and the control terminals of the first transistor and the second transistor are both connected to the power supply voltage VDD.

[0083] Figure 5A and Figure 5B The simulation process of the variable gain module can be referred to Figure 3A and Figure 3B You can understand it through the description, so I won’t go into details here.

[0084] Fig. 6A FIG7 shows a structural schematic diagram of a variable gain amplifier provided by an embodiment of the present disclosure. Figure 6B FIG8 shows a structural diagram of a variable gain amplifier provided by an embodiment of the present disclosure. It should be noted that: Fig. 6A for Figure 2AA refinement of the block diagram shown, Figure 6B for Figure 2B The structural refinement of the block diagram shown, namely Fig. 6A The diagram shows a situation where the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state. Figure 6B The diagram shows the situation where the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state. Figure 2A , Figure 2B , Fig. 6A and Figure 6B As shown, the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are all array transistors. The array transistor includes N transistors, where N is an integer greater than or equal to 2. Here, Fig. 6A and Figure 6B The following description is made by taking as an example that all transistors in the array transistor are NMOS transistors.

[0085] The first master transistor unit 211 includes N first master transistors M 2P’ The second master transistor unit 212 includes N second master transistors M 2N’ The first cross-coupled transistor unit 213 includes N first cross-coupled transistors M 3P’ The second cross-coupled transistor unit 214 includes N second cross-coupled transistors M 3N’ .

[0086] In some embodiments, the first main transistor unit 211 further includes N capacitors C1, each capacitor C1 is disposed at a position corresponding to the first main transistor M. 2P’ The second main transistor unit 212 also includes N capacitors C2, each capacitor C2 is provided at a corresponding second main transistor M 2N’ The first cross-coupled transistor unit 213 also includes N capacitors C3, each capacitor C3 is provided at a corresponding first cross-coupled transistor M 3P’ The second cross-coupled transistor unit 214 also includes N capacitors C4, each capacitor C4 is provided at a corresponding second cross-coupled transistor M 3N’ The gate of the transistor; wherein the capacitors C1-C4 are filter capacitors. Here, the capacitors C1-C4 can also be used to isolate DC signals.

[0087] In some embodiments, the transistors in the main transistor pair and the cross-coupled transistors are all common source transistors, and the sources of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are all grounded, which can increase the gain and reduce the parasitic phase shift.

[0088] In some embodiments, the input ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are the gates of the transistors, and the output ends of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are the drains of the transistors.

[0089] In some embodiments, the compensation module 220 further includes capacitors C5-C6 and resistors R1-R2, the gate of the first transistor M1 is connected to the positive input signal Vin+ through the capacitor C5, the gate of the first transistor M1 is grounded through the resistor R1, the gate of the second transistor M2 is connected to the negative input signal Vin+ through the capacitor C6, and the gate of the second transistor M2 is grounded through the resistor R2. Among them, the capacitors C5-C6 are filter capacitors, and the resistors R1-R2 are filter resistors. The capacitors C5-C6 and the resistors R1-R2 constitute a filter network of the compensation module 220. Here, the capacitors C5-C6 can also be used to isolate DC signals, and the resistors R1-R2 can also be used to isolate AC signals.

[0090] Fig. 6A and Figure 6B The simulation process of the variable gain module can be referred to Figure 3A and Figure 3B You can understand it through the description, so I won’t go into details here.

[0091] like Fig. 6A and Figure 6B As shown, the first transistor M1 and the second transistor M2 are both NMOS transistors, the input terminals of the first transistor M1 and the second transistor M2 are the gates of the transistors, and the output terminals of the first transistor M1 and the second transistor M2 are the drains of the transistors.

[0092] Fig. 7A FIG9 shows a structural diagram of a variable gain amplifier provided by an embodiment of the present disclosure. Figure 7B FIG10 shows a structural diagram of a variable gain amplifier provided by an embodiment of the present disclosure. It should be noted that: Fig. 7A for Figure 2A A refinement of the block diagram shown, Figure 7B for Figure 2B The structural refinement of the block diagram shown, namely Fig. 7A The diagram shows a situation where the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state. Figure 7B The diagram shows the situation where the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state. Figure 2A , Figure 2B , Fig. 7A and Figure 7BAs shown, the input terminals of the first main transistor unit 211 and the second cross-coupled transistor unit 214 receive a positive input signal Vin+, and the input terminals of the second main transistor unit 212 and the first cross-coupled transistor unit 213 receive a negative input signal Vin-. The positive input signal Vin+ and the negative input signal Vin- are differential input signals.

[0093] In some embodiments, the variable gain module 210 further includes a third transistor M3' and a fourth transistor M4' with a common source; the output ends of the first main transistor unit 211 and the first cross-coupled transistor unit 213 are connected to the source of the third transistor M3', the drain of the third transistor M3' is used to output a positive output signal Vout+, and the gate of the third transistor M3' receives a first control signal Vx; the output ends of the second main transistor unit 212 and the second cross-coupled transistor unit 214 are connected to the source of the fourth transistor M4', the drain of the fourth transistor M4' is used to output a negative output signal Vout-, and the gate of the fourth transistor M4' receives a second control signal Vy. Wherein, the positive output signal Vout+ and the negative output signal Vout- are differential input signals. Here, the control signal Vx and the control signal Vy can specifically be voltage signals. In addition, the first control signal Vx and the second control signal Vy are synchronous inverted signals.

[0094] It should be noted that Fig. 7A and Figure 7B The structures of the main transistor pair, the cross-coupled transistor pair and the compensation module 220 are shown in FIG. Fig. 6A and Figure 6B The structures of the main transistor pair, the cross-coupled transistor pair and the compensation module 220 are shown to be the same. Fig. 7A and Figure 7B The specific connection relationship between the main transistor pair, the cross-coupled transistor pair and the compensation module 220 can be referred to Fig. 6A and Figure 6B description and understand.

[0095] Fig. 8A FIG11 shows a structural schematic diagram of a variable gain amplifier provided by an embodiment of the present disclosure. Figure 8B FIG. 12 shows a structural schematic diagram of a variable gain amplifier provided by an embodiment of the present disclosure. It should be noted that: Fig. 8A for Figure 2A A refinement of the block diagram shown, Figure 8B for Figure 2B The structural refinement of the block diagram shown, namely Fig. 8A The diagram shows a situation where the phase of the attenuation state of the variable gain module 210 is ahead of the phase of the reference state. Figure 8B The diagram shows the situation where the phase of the attenuation state of the variable gain module 210 lags behind the phase of the reference state. Figure 2A , Figure 2B , Fig. 8A and Figure 8B As shown, the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213 and the second cross-coupled transistor unit 214 are all voltage-controlled transistors, and the control terminals of the voltage-controlled transistors receive analog voltages. Fig. 8A and Figure 8B The following description is given by taking the voltage-controlled transistor as an NMOS transistor as an example.

[0096] In some embodiments, the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 are common source transistors, that is, the sources of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 are all grounded. In this way, the gain can be improved and the parasitic phase shift can be reduced.

[0097] In some embodiments, the gates of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 serve as both input terminals and control terminals, and the drains of the first main transistor unit 211, the second main transistor unit 212, the first cross-coupled transistor unit 213, and the second cross-coupled transistor unit 214 serve as output terminals.

[0098] In some embodiments, the first main transistor unit 211 further includes a resistor R3, and the gate of the first main transistor unit 211 receives the first control signal Va through the resistor R3; the second main transistor unit 212 further includes a resistor R4, and the gate of the second main transistor unit 212 receives the first control signal Va through the resistor R4; the first cross-coupled transistor unit 213 further includes a resistor R5, and the gate of the first cross-coupled transistor unit 213 receives the second control signal Vb through the resistor R5; the second cross-coupled transistor unit 214 further includes a resistor R6, and the gate of the second cross-coupled transistor unit 214 receives the second control signal Vb through the resistor R6; wherein the resistors R3-R6 are filter resistors. Here, the resistors R3-R6 can also be used to isolate AC signals.

[0099] In some embodiments, the compensation module 220 further includes resistors R7-R8, the gate of the first transistor M1 is grounded through the resistor R7, and the gate of the second transistor M2 is grounded through the resistor R8. The resistors R7-R8 are filter resistors. Here, the resistors R7-R8 can also be used to isolate AC signals.

[0100] like Fig. 8A and Figure 8BAs shown, the first transistor M1 and the second transistor M2 are both NMOS transistors, the gates of the first transistor M1 and the second transistor M2 are input terminals, and the drains of the first transistor M1 and the second transistor M2 are output terminals.

[0101] Fig.9A FIG. 1 shows a schematic diagram of parasitic phase modulation changing with frequency when the compensation module is not used in an embodiment of the present disclosure. Fig. 9B The figure shows the parasitic phase modulation changing with frequency when the compensation module is used in the embodiment of the present disclosure. It should be noted that: Fig.9A Shows Figure 4A Schematic diagram of the parasitic phase modulation of the variable gain module (excluding the variable gain amplifier of the compensation module) changing with frequency. Fig. 9B Shows Figure 4A FIG. 1 is a schematic diagram showing the variation of parasitic phase modulation of a variable gain amplifier including a compensation module with frequency. The parasitic phase modulation here refers to the phase difference between the attenuation state and the reference state. Fig.9A and Fig. 9B The horizontal axis is frequency, and the unit of frequency is GHz. The vertical axis is parasitic phase modulation, and the unit of parasitic phase modulation is deg (degree). Fig.9A and Fig. 9B A 3-bit variable gain module is used as an example for explanation. The 3-bit variable gain module has 8 states, namely, a reference state and 7 attenuation states. Fig.9A The parasitic phase modulation of the seven attenuation states shown is greater than 0 degrees, and the maximum is close to 35 degrees, that is, the phase of the variable gain amplifier in the attenuation state is ahead of the phase of the reference state. After using the compensation module, Fig. 9B The parasitic phase modulation of the seven attenuation states shown is in the range of 2deg to -4deg, which greatly improves the phase lead of the variable gain amplifier, thereby reducing the parasitic phase modulation of the variable gain amplifier. Fig.9A and Fig. 9B As shown, according to the difference in the parasitic phase modulation changes with frequency before and after compensation, it can be obtained that after setting the compensation module, the parasitic phase modulation is less than 5deg in the broadband, which is greatly improved compared to the maximum parasitic phase modulation of 35deg before compensation.

[0102] The present solution also provides a radio frequency front end, which includes any of the above variable gain amplifiers to adjust the gain of the signal. The radio frequency front end can be a phased array chip, a power amplifier, a radio frequency transceiver, a phase shifter or a radar sensing chip.

[0103] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0104] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A variable gain amplifier, characterized in that: include: a variable gain module configured to perform gain adjustment based on a received gain control signal; The variable gain module includes a main transistor pair and a cross-coupled transistor pair; wherein the cross-coupled transistor pair is used to offset the current flowing through the main transistor pair to provide a variable gain; The compensation module includes a turned-off first transistor and a turned-off second transistor; wherein, When the phase of the attenuation state of the variable gain module lags behind the phase of the reference state, the input terminal and the output terminal of the first transistor are respectively connected to the input terminal and the output terminal of one of the main transistor pair, and the input terminal and the output terminal of the second transistor are respectively connected to the input terminal and the output terminal of the other of the main transistor pair; or, When the phase of the attenuation state of the variable gain module leads the phase of the reference state, the input end and the output end of the first transistor are respectively connected to the input end and the output end of one of the cross-coupled transistor pair, and the input end and the output end of the second transistor are respectively connected to the input end and the output end of the other of the cross-coupled transistor pair.

2. The variable gain amplifier according to claim 1, characterized in that: The sizes of the first transistor and the second transistor are proportional to the phase difference between the reference state and the decay state.

3. The variable gain amplifier according to claim 1 or 2, characterized in that: The variable gain module has a plurality of attenuation states, each of the attenuation states having a phase difference with the reference state; If the median of the plurality of phase differences is positive, the phase of the variable gain module is advanced; or, If the median of the multiple phase differences is negative, the phase of the variable gain module is delayed.

4. The variable gain amplifier according to claim 1, characterized in that: The first transistor and the second transistor are one of the following: The first transistor and the second transistor are both NMOS transistors, and control terminals of the first transistor and the second transistor are both grounded; The first transistor and the second transistor are both PMOS transistors, and control terminals of the first transistor and the second transistor are both connected to a power supply voltage VDD; The first transistor and the second transistor are both NPN transistors, and the control terminals of the first transistor and the second transistor are both grounded; or, The first transistor and the second transistor are both PNP transistors, and control terminals of the first transistor and the second transistor are both connected to a power supply voltage VDD.

5. The variable gain amplifier according to claim 1, characterized in that: The first transistor, the second transistor, the main transistor pair, and the cross-coupled transistor pair are of the same transistor type.

6. The variable gain amplifier according to claim 1, characterized in that: The master transistor pair includes a first master transistor unit and a second master transistor unit; The cross-coupled transistor pair includes a first cross-coupling unit and a second cross-coupling unit; An input terminal of the first main transistor unit is connected to an input terminal of the first cross-coupled transistor unit, and an input terminal of the second main transistor unit is connected to an input terminal of the second cross-coupled transistor unit; The output end of the first main transistor unit is connected to the output end of the second cross-coupled transistor unit, and the output end of the second main transistor unit is connected to the output end of the first cross-coupled transistor unit.

7. The variable gain amplifier according to claim 6, characterized in that: The first main transistor unit, the second main transistor unit, the first cross-coupled transistor unit, and the second cross-coupled transistor unit are all array transistors, or are all voltage-controlled transistors.

8. The variable gain amplifier according to claim 6, characterized in that: The transistors in the main transistor pair and the cross-coupled transistors are all common-gate transistors; the input ends of the first main transistor unit, the second main transistor unit, the first cross-coupled transistor unit, and the second cross-coupled transistor unit are the sources of the transistors, and the output ends are the drains of the transistors.

9. The variable gain amplifier according to claim 8, characterized in that: The variable gain module further includes a third transistor and a fourth transistor having a common source; The input terminals of the first main transistor unit and the first cross-coupled transistor unit are connected to the drain of the third transistor, the source of the third transistor is grounded, and the gate of the third transistor receives a positive input signal; Input terminals of the second main transistor unit and the second cross-coupled transistor unit are connected to the drain of the fourth transistor, the source of the fourth transistor is grounded, and the gate of the fourth transistor receives a negative input signal.

10. The variable gain amplifier according to claim 6, characterized in that: The transistors in the main transistor pair and the cross-coupled transistors are all common source transistors, the input ends of the first main transistor unit, the second main transistor unit, the first cross-coupled transistor unit, and the second cross-coupled transistor unit are the gates of the transistors, and the output ends are the drains of the transistors.

11. The variable gain amplifier according to claim 10, characterized in that: The variable gain module further includes a third transistor and a fourth transistor having a common gate; The output terminals of the first main transistor unit and the first cross-coupled transistor unit are connected to the source of the third transistor, the drain of the third transistor is used to output a positive output signal, and the gate of the third transistor receives a first control signal; The output terminals of the second main transistor unit and the second cross-coupled transistor unit are connected to the source of the fourth transistor, the drain of the fourth transistor is used to output a negative output signal, and the gate of the fourth transistor receives a second control signal.

12. The variable gain amplifier according to claim 6, characterized in that: The transistors in the main transistor pair and the cross-coupled transistors are all common-base transistors, the input ends of the first main transistor unit, the second main transistor unit, the first cross-coupled transistor unit, and the second cross-coupled transistor unit are emitters of transistors, and the output ends are collectors of transistors.

13. A radio frequency front end, characterized in that: Comprising a variable gain amplifier as claimed in any one of claims 1-12.

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