A current comparator with variable input current

Abstract

The present invention belongs to the field of mobile communications and provides a current comparator with a variable input current, comprising: an input current compensation part, a current mirror part, and an improved SR stage part connected in sequence; the input current compensation part comprises: a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the improved SR stage part comprises: a plurality of trimming position correction circuits; the present invention solves the defects of traditional current comparators requiring multiple different current comparators and complex control logic by adding an input current compensation part and designing a multi-stage trimming position correction circuit, thereby achieving an expansion of the input current range.

Description

Technical Field

[0001] The present invention relates to the field of mobile communications, and in particular to a current comparator with variable input current. Background Art

[0002] In high-speed, high-precision, current-steering digital-to-analog converters, current comparators are required for current steering calibration. When zero-drift calibration of current source gain models is performed, the input current to be calibrated must vary significantly, typically by a factor of four. Commonly used current comparators are modified from strong ARM voltage comparators.

[0003] like Figure 1 As shown, since the SR stage requires a better operating point and needs to limit the amplitude of the input current, relying on traditional current comparators requires multiple different current comparators and complex control logic. Summary of the Invention

[0004] In order to overcome the shortcomings of the existing technology, the purpose of the present invention is to provide a current comparator with variable input current. By adding an input current compensation part and designing a multi-stage TRIMMING bit correction circuit, the defects of traditional current comparators requiring multiple different current comparators and complex control logic are solved, thereby achieving the expansion of the input current range.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A current comparator with variable input current includes: an input current compensation part, a current mirror part, and an improved SR stage part connected in sequence; the input current compensation part includes: a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the improved SR stage part includes: a plurality of trimming position correction circuits;

[0007] The gate of the first PMOS transistor, the drain of the first PMOS transistor, the source of the second PMOS transistor, and the source of the third PMOS transistor are connected in pairs; the gate of the second PMOS transistor and the gate of the third PMOS transistor are both connected to an external low-level terminal; the source of the first PMOS transistor is connected to an external high-voltage terminal; the substrate of the second PMOS transistor and the substrate of the third PMOS transistor are connected; the drain of the second PMOS transistor is connected to the first current input terminal of the current mirror part; the drain of the third PMOS transistor is connected to the second current input terminal of the current mirror part; all the trimming position correction circuits are connected in parallel;

[0008] The first PMOS tube is used for; the second PMOS tube is used for; the third PMOS tube is used for; the current mirror part is used for; the improved SR stage part is used for; the TRIMMING position correction circuit is used for.

[0009] The present invention discloses the following technical effects:

[0010] The present invention provides a current comparator with variable input current. By adding an input current compensation part and designing a multi-stage TRIMMING bit correction circuit, the defects of traditional current comparators requiring multiple different current comparators and complex control logic are solved, and the input current range is expanded. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 A circuit diagram of a commonly used current comparator provided in an embodiment of the present invention;

[0013] Figure 2 A circuit diagram of a current comparator with variable input current provided by an embodiment of the present invention;

[0014] Figure 3 A detailed circuit diagram of a current comparator provided in an embodiment of the present invention;

[0015] Figure 4 A circuit effect diagram provided by an embodiment of the present invention;

[0016] Description of reference numerals:

[0017] M1-first PMOS tube, M2-second PMOS tube, M3-third PMOS tube. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] The purpose of the present invention is to provide a current comparator with variable input current. By adding an input current compensation part and designing a multi-stage TRIMMING bit correction circuit, the defects of traditional current comparators requiring multiple different current comparators and complex control logic are solved, thereby expanding the input current range.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Figure 2 The current comparator circuit diagram with variable input current provided by the embodiment of the present invention is as follows: Figure 2 As shown, the present invention provides a current comparator with variable input current, comprising: an input current compensation part, a current mirror part, and an improved SR stage part connected in sequence; the input current compensation part comprises: a first PMOS transistor M1, a second PMOS transistor M2, and a third PMOS transistor M3; the improved SR stage part comprises: a plurality of TRIMMING position correction circuits;

[0022] The gate of the first PMOS transistor M1, the drain of the first PMOS transistor M1, the source of the second PMOS transistor M2, and the source of the third PMOS transistor M3 are connected in pairs; the gate of the second PMOS transistor M2 and the gate of the third PMOS transistor M3 are both connected to the external low-level terminal; the source of the first PMOS transistor M1 is connected to the external high voltage terminal; the substrate of the second PMOS transistor M2 and the substrate of the third PMOS transistor M3 are connected; the drain of the second PMOS transistor M2 is connected to the first current input terminal of the current mirror part; the drain of the third PMOS transistor M3 is connected to the second current input terminal of the current mirror part; all trimming position correction circuits are connected in parallel;

[0023] The first PMOS transistor M1 is used to provide a current path from the power supply to the input stage; the second PMOS transistor M2 is used to isolate the positive input voltage from the common-mode voltage; the third PMOS transistor M3 is used to isolate the negative input voltage from the common-mode voltage; the current mirror part is used to mirror the first-stage current to the SR stage; the improved SR stage part is used to compare the mirrored SR stage current and output the comparison result; the trimming position correction circuit is used to control the impact of power supply voltage changes on the operating point.

[0024] refer to Figure 3In the figure, M4 to M11 are all NMOS transistors; I_cal, I_mir_c, I_dio_c, I_ref, I_mir_r, I_dio_r, I_chg_c, and I_chg_r are all currents in their respective circuits; clk is the clock signal; cmp_out is the comparator output; enn is the enable input voltage; vdd is a high level; cmp_speed <2> cmp_speed <0> The added TRIMMING bit is used to cope with the impact of changes in the power supply voltage Vdd; v2_c, v2_r, vdd, vb2, and v1 are all voltages of the corresponding circuits. The traditional comparator does not include the input current compensation part (M1, M2, M3). Its working principle is that the first stage is a diode-connected NMOS (M6, M7) used to convert the input current into a voltage. M8 and M9 are current mirrors, mirroring the current flowing through M6 and M7 to the SR stage. M4, M5, M10, and M11 are common-gate stages to ensure the accuracy of the current mirror and ensure:

[0025] I_cal=I_mir_c=I_dio_c

[0026] I_ref=I_mir_r=I_dio_r

[0027] The SR stage gives a comparison result by comparing the two input currents (I_mir_c and I_mir_r). This has strict requirements on the range of input current. If the current is too large, the SR stage common-mode voltage is too low and cannot be reset, and the second comparison result cannot be output normally. If the current is too small, the SR stage common-mode voltage is too high and no comparison result is generated.

[0028] Furthermore, this embodiment adds an input current compensation circuit (M1, M2, M3) to ensure that the comparator can work properly. Since the working state of the SR stage is related to the common mode current, for the convenience of analysis, it is assumed that:

[0029] I_cal=I_ref

[0030] but:

[0031] I_chg_c=I_chg_r

[0032] I_dio_c=I_cal+I_chg_c=I_ref+I_chg_r=I_dio_r

[0033] I_mir_c=I_dio_c=I_dio_r=I_mir_r

[0034] Therefore, only the single-sided circuit is analyzed. The compensation circuit consists of a PMOS transistor (M1) connected in diode form and two PMOS transistors (M2 and M3) with their gates grounded. M1 operates in the saturation region, while M2 and M3 operate in the linear region (low impedance). These two transistors will be ignored in the subsequent analysis.

[0035] The impedance of M2 and M3 is expressed as R on , which is not discussed in the subsequent analysis due to its low impedance:

[0036]

[0037] Therefore, without considering the input current, the current in the first stage is determined by the diode-connected PMOS and NMOS:

[0038]

[0039] I_dio_c=I_chg_c+I_cal

[0040]

[0041] Among them, μ p and μ n is the carrier mobility; C ox is the channel charge density; V THP and V THN is the gate voltage of the MOS tube; W and L are the width and length of the MOS tube.

[0042] refer to Figure 4 By adjusting the size of the MOS tube, the comparator can still work normally even when there is no current input. Without considering the impedance RON of M2 and M3, v2_c = v1,

[0043]

[0044] I_dio_c=I_chg_c+I_cal

[0045] When I_cal increases by ΔI in When v1 increases, I_chg_c decreases by ΔI chg , then the current flowing through M6 becomes

[0046] I_dio_c=I_chg_c+I_cal+ΔI in -ΔI chg

[0047] Furthermore, to offset the impact of power supply voltage fluctuations on the SR stage's operating state, a TIMMING stage is added to ensure normal operation of the comparator under different power supply voltages. By compensating for the input stage and increasing the trimming bit of the SR stage, the current comparator's input current range is expanded while maintaining a small footprint and without adding additional digital control.

[0048] The beneficial effects of the present invention are as follows:

[0049] The present invention solves the defects of traditional current comparators requiring multiple different current comparators and complex control logic by adding an input current compensation part and designing a multi-level TRIMMING bit correction circuit, thereby expanding the input current range.

[0050] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0051] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A current comparator with a variable input current, characterized in that: include: The input current compensation part, the current mirror part and the improved SR stage part are connected in sequence; The input current compensation part includes: a first PMOS transistor, a second PMOS transistor and a third PMOS transistor; the improved SR stage part includes: a plurality of trimming position correction circuits; the current mirror part includes: NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, NMOS transistor M11; The gate of the first PMOS tube, the drain of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected in pairs; the gate of the second PMOS tube and the gate of the third PMOS tube are both connected to the external low-level end; the source of the first PMOS tube is connected to the external high voltage end; the substrate of the second PMOS tube and the substrate of the third PMOS tube are connected; the drain of the second PMOS tube is connected to the first current input end of the current mirror part; the drain of the third PMOS tube is connected to the second current input end of the current mirror part; all the trimming position correction circuits are connected in parallel; the NMOS tube M4 is connected to the NMOS tube M6; the NMOS tube M5 is connected to the NMOS transistor M7; the NMOS transistors M6 and M7 are connected in a diode manner; the gate of the NMOS transistor M6 is connected to the gate of the NMOS transistor M8; the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M9; the NMOS transistors M8 and M9 form a current mirror; the NMOS transistor M8 is connected to the NMOS transistor M10; the NMOS transistor M9 is connected to the NMOS transistor M11; the NMOS transistors M4, M5, M10, and M11 are connected in a common gate manner; each of the trimming position correction circuits is connected to the NMOS transistor M10 and the NMOS transistor M11; The first PMOS transistor is used to provide a current path from the power supply to the input stage; the second PMOS transistor is used to isolate the positive input voltage from the common-mode voltage; the third PMOS transistor is used to isolate the negative input voltage from the common-mode voltage; the current mirror part is used to mirror the first-stage current to the SR stage through the NMOS transistor M8 and the NMOS transistor M9; the improved SR stage part is used to output a comparison result by comparing the magnitudes of the two input currents; the trimming position correction circuit is used to control the impact of power supply voltage changes on the operating point.

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