Anti-backflow system applied to load switch

Abstract

The invention relates to an anti-backflow system applied to a load switch, which comprises a voltage detection module, a voltage selection module and a load switch, and is characterized in that the voltage detection module is a P input comparator circuit, the in-phase input end of the voltage detection module is connected with a VOUT signal, the inverted input end of the voltage detection module is connected with a VIN signal, and the output end of the voltage detection module is connected with the load switch; the voltage selection module is connected with a VOUT signal and a VIN signal, and the voltage selection module is connected with the output end of the voltage detection module and is connected with a VMAX signal; the load switch is a PMOS power tube, the grid electrode is connected with the FLAG signal, the source electrode is connected with the VIN signal, the drain electrode is connected with the VOUT signal, and the substrate end is connected with the VMAX signal. By adopting the anti-backflow system applied to the load switch and the voltage negative feedback principle, the VGS of the load switch tube is reduced in advance, conditions are created for reverse rapid turn-off of subsequent current, meanwhile, the load switch tube is prevented from being directly and completely turned off in advance, and the supply demand of output current in the whole process is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, in particular to the field of battery power supply systems, and specifically refers to an anti-backflow system applied to a load switch. Background Art

[0002] As the demand for battery capacity in portable electronic devices such as smartphones grows, more and more battery-powered systems are beginning to use integrated load switches to optimize the total power consumption of the power management system, effectively reducing standby power consumption and extending battery life by shutting down unused subsystems. Or by making reasonable choices for different power inputs, the power distribution of the entire power supply system can be adjusted to achieve efficient use of power. By integrating a variety of protection functions, load switches can ensure that the load is not damaged by overload, ensuring that the system works safely and reliably and that it interacts with the microprocessor in real time to transmit information.

[0003] In the design of switch paths, it is often necessary to consider the situation where the output voltage is higher than the input voltage. At this time, it is usually necessary to block the switch path to prevent the current from the output end to the input end (reverse current blocking). For example, in the design of a charging chip, if the voltage of the charging battery is higher than the voltage of the charging power supply, it is necessary to shut down the switch path to prevent the battery voltage from being discharged; if the input is short-circuited, it is even more important to prevent the large current from directly discharging the battery to the ground and damaging the battery. For another example, in the design of a switch selector used for switching multiple power inputs, in order to prevent mutual charging and discharging between power supply voltages of different potentials, it is necessary to embed a reverse current blocking protection function in the switch design.

[0004] At present, the method used is to use back-to-back PMOS tubes as switching devices, which naturally have the function of reverse current blocking in the shutdown mode. However, its disadvantage is that it occupies a large area, and more than twice the tube area is required to achieve the same on-resistance. Another method is to use NMOS tubes as switching devices, and the substrate is connected to the ground, which blocks the parasitic PN junction, but a charge pump needs to be added to drive the NMOS tube, which greatly increases the complexity of the circuit. In addition, due to the gate capacitance C of the power tube GS The gate capacitance of the power tube needs to be discharged to the turn-off threshold voltage when it is turned off. This process greatly limits the turn-off speed of the switching device. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a backflow prevention system for load switches which has the advantages of simple structure, high safety, fast shutdown and a wide range of applications.

[0006] In order to achieve the above object, the anti-backflow system applied to the load switch of the present invention is as follows:

[0007] The anti-backflow system applied to the load switch has the following main features: the system comprises a voltage detection module, a voltage selection module and a load switch; the voltage detection module is a P-input comparator circuit; the in-phase input terminal of the voltage detection module is connected to a VOUT signal, the inverting input terminal is connected to a VIN signal, the output terminal is connected to the load switch; the voltage selection module is connected to the VOUT signal and the VIN signal, the voltage selection module is connected to the output terminal of the voltage detection module, and is also connected to a VMAX signal; the load switch is a PMOS power tube, the gate is connected to a FLAG signal, the source is connected to a VIN signal, the drain is connected to a VOUT signal, and the substrate terminal is connected to a VMAX signal.

[0008] Preferably, the voltage detection module includes a first input pair of tubes MP1, a second input pair of tubes MP2 and an inverter I2. The first input pair of tubes MP1 and the second input pair of tubes MP2 form a 1:1 current mirror circuit. The drain of the first input pair of tubes MP1 is connected to a VOUT signal, the drain of the second input pair of tubes MP2 is connected to a VIN signal, the first input pair of tubes MP1 is connected to a gate of the second input pair of tubes MP2, the input end of the inverter I2 is connected to a source of the second input pair of tubes MP2, and the output of the inverter I2 is a FLAG signal.

[0009] Preferably, when the voltage value of the VOUT signal of the system is higher than the voltage value of the VIN signal, the first input pair of tubes MP1 is turned off, the second input pair of tubes MP2 is turned on, and the FLAG signal output after passing through the inverter I2 is a low level; when the voltage value of the VOUT signal is lower than the voltage value of the VIN signal, the first input pair of tubes MP1 is turned on, the second input pair of tubes MP2 is turned off, and the FLAG signal output after passing through the inverter I2 is a high level.

[0010] Preferably, the voltage selection module includes a third PMOS switch tube PM3, a fourth PMOS switch tube PM4 and a dead time logic circuit, the gate of the third PMOS switch tube PM3 and the gate of the fourth PMOS switch tube PM4 are connected to the dead time logic circuit, the drain of the third PMOS switch tube PM3 is connected to the VOUT signal, the drain of the fourth PMOS switch tube PM4 is connected to the VIN signal, the midpoint of the third PMOS switch tube PM3 and the fourth PMOS switch tube PM4 is the output end, and the VMAX signal is output.

[0011] Preferably, when the voltage detection module outputs a low level, the fourth PMOS switch tube PM4 is turned on, and the voltage value of the output VMAX signal is the voltage value of the VIN signal; when the voltage detection module outputs a high level, the third PMOS switch tube PM3 is turned on, and the voltage value of the output VMAX signal is the voltage value of the VOUT signal.

[0012] Preferably, the system also includes a voltage negative feedback module, the non-inverting input terminal of the voltage negative feedback module is connected to the drain of the load switch, the inverting input terminal is connected to the VIN signal, and the output terminal is connected to the gate of the load switch; when it is detected that the voltage difference between the VOUT signal and the signal VIN is within a preset voltage difference value, the gate of the load switch tube is raised through feedback to stabilize the voltage difference between the VOUT signal and the VIN signal at a voltage difference setting value; when the voltage value of the VOUT signal is close to the voltage value of the VIN signal, the gate voltage value of the load switch tube increases and approaches the voltage value of the VIN signal; if the VOUT signal is greater than the VIN signal, when reverse current occurs, the gate voltage is pulled up to the VIN signal in a short time.

[0013] Preferably, the voltage negative feedback module includes a sixth MOS tube MP6, a seventh MOS tube MP7, a fourth MOS tube MN4, a fifth MOS tube MN5 and a second resistor R2, the sixth MOS tube MP6 and the seventh MOS tube MP7 are an input pair, the gates of the sixth MOS tube MP6 and the seventh MOS tube MP7 are connected, the drain of the sixth MOS tube MP6 is connected to the VOUT signal, the drain of the seventh MOS tube MP7 is connected to the VIN signal through the second resistor R2, the source of the sixth MOS tube MP6 is connected to the drain of the fourth MOS tube MN4, the source of the seventh MOS tube MP7 is connected to the drain of the fifth MOS tube MN5, the fourth MOS tube MN4 and the fifth MOS tube MN5 are 1:1 mirror current mirrors, the gates of the fourth MOS tube MN4 and the fifth MOS tube are both connected to the bias voltage VB, and the middle point of the seventh MOS tube MP7 and the fifth MOS tube MN5 is an output end, which is connected to the gate of the load switch.

[0014] The anti-backflow system applied to the load switch of the present invention adopts the voltage negative feedback principle. When the input-output voltage difference or the output current is reduced to a certain set value, the gate of the load switch tube begins to be lifted, so that the load switch tube is switched from the linear region to the saturation region, and then to the cut-off region, and the on-resistance of the load switch tube is dynamically adjusted, so that the VGS of the load switch tube is reduced in advance, creating conditions for the subsequent reverse rapid shutdown of the current, while avoiding directly shutting down the load switch tube completely in advance, thereby ensuring the supply demand of the output current in the whole process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1The figure is a schematic diagram of the circuit structure of the anti-backflow system applied to a load switch of the present invention.

[0016] Figure 2 The circuit diagram of the voltage detection module of the anti-backflow system applied to the load switch of the present invention is shown in FIG.

[0017] Figure 3 The circuit diagram of the voltage selection module of the anti-backflow system applied to the load switch of the present invention is shown in FIG.

[0018] Figure 4 The circuit diagram of the voltage negative feedback module of the anti-backflow system applied to the load switch of the present invention is shown in FIG.

[0019] Figure 5 (a) is a schematic diagram of the voltage curve of a common switching tube.

[0020] Figure 5 (b) is a schematic diagram of a voltage curve of the anti-backflow system applied to a load switch of the present invention. DETAILED DESCRIPTION

[0021] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0022] The anti-backflow system applied to a load switch of the present invention comprises a voltage detection module, a voltage selection module and a load switch, wherein the voltage detection module is a P-input comparator circuit, the in-phase input terminal of the voltage detection module is connected to a VOUT signal, the inverting input terminal is connected to a VIN signal, the output terminal is connected to the load switch, the voltage selection module is connected to the VOUT signal and the VIN signal, the voltage selection module is connected to the output terminal of the voltage detection module, and is also connected to a VMAX signal; the load switch is a PMOS power tube, the gate is connected to a FLAG signal, the source is connected to a VIN signal, the drain is connected to a VOUT signal, and the substrate terminal is connected to a VMAX signal.

[0023] As a preferred embodiment of the present invention, the voltage detection module includes a first input pair of tubes MP1, a second input pair of tubes MP2 and an inverter I2. The first input pair of tubes MP1 and the second input pair of tubes MP2 form a 1:1 current mirror circuit. The drain of the first input pair of tubes MP1 is connected to the VOUT signal, the drain of the second input pair of tubes MP2 is connected to the VIN signal, the first input pair of tubes MP1 is connected to the gate of the second input pair of tubes MP2, the input end of the inverter I2 is connected to the source of the second input pair of tubes MP2, and the output of the inverter I2 is a FLAG signal.

[0024] As a preferred embodiment of the present invention, when the voltage value of the VOUT signal of the system is higher than the voltage value of the VIN signal, the first input pair of tubes MP1 is turned off, the second input pair of tubes MP2 is turned on, and the FLAG signal output after passing through the inverter I2 is a low level; when the voltage value of the VOUT signal is lower than the voltage value of the VIN signal, the first input pair of tubes MP1 is turned on, the second input pair of tubes MP2 is turned off, and the FLAG signal output after passing through the inverter I2 is a high level.

[0025] As a preferred embodiment of the present invention, the voltage selection module includes a third PMOS switch tube PM3, a fourth PMOS switch tube PM4 and a dead time logic circuit, the gate of the third PMOS switch tube PM3 and the gate of the fourth PMOS switch tube PM4 are connected to the dead time logic circuit, the drain of the third PMOS switch tube PM3 is connected to the VOUT signal, the drain of the fourth PMOS switch tube PM4 is connected to the VIN signal, the midpoint of the third PMOS switch tube PM3 and the fourth PMOS switch tube PM4 is the output end, and the VMAX signal is output.

[0026] As a preferred embodiment of the present invention, when the voltage detection module outputs a low level, the fourth PMOS switch tube PM4 is turned on, and the voltage value of the output VMAX signal is the voltage value of the VIN signal; when the voltage detection module outputs a high level, the third PMOS switch tube PM3 is turned on, and the voltage value of the output VMAX signal is the voltage value of the VOUT signal.

[0027] As a preferred embodiment of the present invention, the system also includes a voltage negative feedback module, the non-inverting input terminal of the voltage negative feedback module is connected to the drain of the load switch, the inverting input terminal is connected to the VIN signal, and the output terminal is connected to the gate of the load switch; when it is detected that the voltage difference between the VOUT signal and the signal VIN is within a preset voltage difference value, the gate of the load switch tube is raised by feedback, and the voltage difference between the VOUT signal and the VIN signal is stabilized at a voltage difference setting value; when the voltage value of the VOUT signal is close to the voltage value of the VIN signal, the gate voltage value of the load switch tube increases and approaches the voltage value of the VIN signal; if the VOUT signal is greater than the VIN signal, when reverse current occurs, the gate voltage is pulled up to the VIN signal in a short time.

[0028] As a preferred embodiment of the present invention, the voltage negative feedback module includes a sixth MOS transistor MP6, a seventh MOS transistor MP7, a fourth MOS transistor MN4, a fifth MOS transistor MN5 and a second resistor R2, the sixth MOS transistor MP6 and the seventh MOS transistor MP7 are an input pair, the gates of the sixth MOS transistor MP6 and the seventh MOS transistor MP7 are connected, the drain of the sixth MOS transistor MP6 is connected to the VOUT signal, the drain of the seventh MOS transistor MP7 is connected to the VIN signal through the second resistor R2, the source of the sixth MOS transistor MP6 is connected to the drain of the fourth MOS transistor MN4, the source of the seventh MOS transistor MP7 is connected to the drain of the fifth MOS transistor MN5, the fourth MOS transistor MN4 and the fifth MOS transistor MN5 are 1:1 mirror current mirrors, the gates of the fourth MOS transistor MN4 and the fifth MOS transistor are both connected to the bias voltage VB, and the middle point of the seventh MOS transistor MP7 and the fifth MOS transistor MN5 is an output end, which is connected to the gate of the load switch.

[0029] In a specific embodiment of the present invention, a PMOS tube is used as a switch device, and the input and output voltages are compared in real time, and the higher value is used as the power supply of the switch control circuit and the substrate potential of the switch, and when the output is higher than the input, the output tube is turned off to block the reverse current path. At the same time, a negative feedback loop is used to change the on-resistance of the PMOS tube when the current is small, so that when a reverse current occurs, the current path can be cut off more quickly to prevent device damage.

[0030] Figure 1 The invention discloses a load switch backflow prevention circuit, which is composed of a voltage detection module, a voltage selection module, a load switch and a negative feedback module.

[0031] The voltage detection module is a P-input comparator circuit. One of its implementation circuits consists of Figure 2 As shown, MP1 and MP2 are input pair tubes, MN1 and MN2 are 1:1 current mirror circuits. When VOUT is higher than VIN, MP1 is turned off, MP2 is turned on, and after passing through inverter I2, FLAG outputs a low level; when VOUT is lower than VIN, MP1 is turned on, MP2 is turned off, and after passing through inverter I2, FLAG outputs a high level.

[0032] The voltage selection module consists of two PMOS switches and a dead time logic circuit. Its implementation circuit is as follows: Figure 3When the comparator output FLAG is low, the PMOS switch PM4 connected to the VIN end is turned on, and VMAX = VIN; when the comparator output FLAG is high, the PMOS switch PM3 connected to the VOUT end is turned on, and VMAX = VOUT; the inverter I5, the NOR gates I3 and I4 generate dead time to prevent the two switches from being turned on at the same time and generating a large current path.

[0033] The load switch tube uses a PMOS power tube, with its source connected to VIN, drain connected to VOUT, and substrate connected to VMAX, which can prevent conduction through the substrate parasitic diode when VOUT is greater than VIN; at the same time, the gate of the PMOS power tube is connected to the FLAG signal. When it is detected that VOUT is greater than VIN, the load switch tube is immediately turned off to prevent VOUT from flowing back to VIN through the channel of the tube.

[0034] Since the load switch tube is generally required to have a very small on-resistance in applications, the tube size is designed to be large, and the gate of the PMOS power tube has a large parasitic capacitance. Therefore, when the load switch tube is turned off, the gate of the tube must be pulled up from 0V to VIN before the tube can be completely turned off. The turn-off time at this time is calculated as follows:

[0035] toff=VIN×Cg / Id.

[0036] Wherein Cg is the gate parasitic capacitance of the load switch tube, and Id is the pull-up driving current of the inverter I2.

[0037] It takes some time for the tube to turn off. During this shutdown process, some reverse current will still flow from VOUT to VIN, causing bad consequences.

[0038] Therefore, further, the present invention adds a voltage feedback loop. When it is detected that VOUT is close to a certain set voltage difference value of VIN, the gate of the load switch tube is raised through feedback, and the voltage difference between VOUT and VIN is stabilized at a relatively low voltage difference setting value. As VOUT further approaches VIN, the load current is further reduced, and the gate voltage of the load switch tube is further raised to approach VIN. When VOUT is greater than VIN and reverse current occurs, since the gate voltage of the load switch has been raised to close to VIN in advance through the feedback loop, it only takes a short time to pull the gate voltage up to VIN, which greatly shortens the original toff time of pulling the gate from 0V to VIN, thereby achieving the purpose of quickly shutting down the load switch tube.

[0039] The voltage negative feedback module includes an operational amplifier and a VIN voltage difference generating circuit. A specific implementation circuit is as follows: Figure 4As shown: It consists of MOS tubes MP6, MP7, MN4, MN5 and resistor R2. MP6 and MP7 are the input pair of the op amp, VOUT is connected to the drain of MP6, VIN is connected to the drain of MP7 after the voltage drop of R2, MN4 and MN5 are 1:1 mirror current mirrors, and the bias voltage VB is connected to the gates of MN4 and MN5. VB can be Figure 2 The output Vg is connected to the gate of the load switch tube, and the VGS of the load switch tube is controlled to realize feedback regulation.

[0040] The voltage drop of VIN through R2 is ΔU (ΔU=R2×IB_MN5), which is 15mV to 25mV in actual process. It is necessary to ensure that this value is as small as possible to minimize the loss of the load switch tube. But it cannot be too small, otherwise it will be covered by the offset error of the input tube, resulting in the loop still not working when VOUT is greater than VIN.

[0041] The working process of the voltage negative feedback module is as follows: When the forward load current is very large, VIN is obtained after the on-resistance voltage drop of the load switch tube. VOUT is less than VIN-ΔU, the op amp is in an open-loop state, Vg outputs a low level, and controls the load switch tube to be in the linear region, that is, the through switch state. When the forward load current decreases slowly, the difference between VOUT and VIN is also decreasing, until the difference between VOUT and VIN-ΔU is within VDDA / Aop (where VDDA is the module power supply voltage and Aop is the open-loop gain of the op amp), the op amp is in a closed-loop state, Vg outputs an intermediate voltage, controls the load switch tube to be in the saturation region, and maintains the VOUT value at VIN-ΔU through the feedback loop. When the forward load current further decreases to 0 and reverse current begins to appear, the VOUT voltage is greater than the VIN voltage, which triggers the FLAG output of the voltage detection module to be low, pulls PM5 up to VMAX, and the load switch tube is quickly turned off.

[0042] The curves of VIN, VOUT, and Vg voltage changing with load current IOUT are as follows: Figure 5 shown. Figure 5 (a) is the voltage-current curve realized by a common load switch chip. It can be seen that as the load current IOUT changes from large to small, the load switch tube always works in the linear region, and the Vg voltage is always 0 voltage; when the load current IOUT decreases to 0 and reverse current appears, the voltage detection module pulls Vg from 0 voltage to VIN. After Vg is pulled up to VIN, the load switch tube is completely turned off. This process requires the parasitic capacitance of the gate of the load switch tube to be charged from 0 to VIN. By the time the load switch tube is completely turned off, the reverse current has already flowed in for a period of toff time.

[0043] Figure 5(b) is the voltage-current curve of the circuit of the present invention. It can be seen that as the load current IOUT changes from large to small, the load switch tube initially works in the linear region, and the Vg voltage is 0 voltage. When the load current IOUT decreases to the preset value ΔU / Rdson, the voltage feedback loop starts to work, the load switch tube starts to work in the adjustment region, and the Vg voltage starts to rise. As IOUT further decreases to 0, when reverse current is about to appear, Vg is pulled up from VIN-ΔU voltage to VIN through the voltage detection module. After Vg is pulled up to VIN, the load switch tube is completely turned off. This process requires a process in which the parasitic capacitance of the gate of the load switch tube is charged from VIN-ΔU to VIN. Compared with the ordinary switch tube solution, the turn-off time is greatly reduced.

[0044] For example, in the design of VIN=5V, ΔU=15mV, the turn-off time of the present invention is reduced to 15mV / 5V=3 / 1000 of the original time, which shows the significant improvement effect of the present invention.

[0045] The present invention can realize faster cutting off of the current path, prevent the backflow phenomenon of the voltage at both ends of the load switch, has a simple circuit design, and a small static current, and can be widely used in the anti-backflow design of the load switch.

[0046] The technical solution of the present invention is a closed-loop system with negative feedback characteristics, which can turn off the load switch tube more quickly. The turn-off speed of the load switch tube is a particularly important parameter and an important indicator for measuring the performance of the load switch chip. Through negative feedback regulation, when the output current is reduced to zero, the VGS voltage of the switch tube will be gradually reduced. The specific implementation scheme of this embodiment can be found in the relevant description of the above embodiment, which will not be repeated here.

[0047] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0048] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0049] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0050] The anti-backflow system applied to the load switch of the present invention adopts the voltage negative feedback principle. When the input-output voltage difference or the output current is reduced to a certain set value, the gate of the load switch tube begins to be lifted, so that the load switch tube is switched from the linear region to the saturation region, and then to the cut-off region, and the on-resistance of the load switch tube is dynamically adjusted, so that the VGS of the load switch tube is reduced in advance, creating conditions for the subsequent reverse rapid shutdown of the current, while avoiding directly shutting down the load switch tube completely in advance, thereby ensuring the supply demand of the output current in the whole process.

[0051] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A backflow prevention system applied to a load switch, characterized in that: The system includes a voltage detection module, a voltage selection module and a load switch. The voltage detection module is a P-input comparator circuit. The in-phase input terminal of the voltage detection module is connected to the VOUT signal, the inverting input terminal is connected to the VIN signal, and the output terminal is connected to the load switch. The voltage selection module is connected to the VOUT signal and the VIN signal. The voltage selection module is connected to the output terminal of the voltage detection module and is also connected to the VMAX signal. The load switch is a PMOS power tube, the gate is connected to the FLAG signal, the source is connected to the VIN signal, the drain is connected to the VOUT signal, and the substrate terminal is connected to the VMAX signal.

2. The backflow prevention system for load switch according to claim 1, characterized in that: The voltage detection module includes a first input pair of tubes MP1, a second input pair of tubes MP2 and an inverter I2. The first input pair of tubes MP1 and the second input pair of tubes MP2 form a 1:1 current mirror circuit. The drain of the first input pair of tubes MP1 is connected to a VOUT signal, the drain of the second input pair of tubes MP2 is connected to a VIN signal, the first input pair of tubes MP1 is connected to a gate of the second input pair of tubes MP2, the input end of the inverter I2 is connected to a source of the second input pair of tubes MP2, and the output of the inverter I2 is a FLAG signal.

3. The anti-backflow system for load switch according to claim 2, characterized in that: In the described system, when the voltage value of the VOUT signal is higher than the voltage value of the VIN signal, the first input pair of tubes MP1 is turned off, the second input pair of tubes MP2 is turned on, and the FLAG signal output after passing through the inverter I2 is a low level; when the voltage value of the VOUT signal is lower than the voltage value of the VIN signal, the first input pair of tubes MP1 is turned on, the second input pair of tubes MP2 is turned off, and the FLAG signal output after passing through the inverter I2 is a high level.

4. The backflow prevention system for load switch according to claim 1, characterized in that: The voltage selection module includes a third PMOS switch tube PM3, a fourth PMOS switch tube PM4 and a dead time logic circuit. The gate of the third PMOS switch tube PM3 and the gate of the fourth PMOS switch tube PM4 are connected to the dead time logic circuit. The drain of the third PMOS switch tube PM3 is connected to the VOUT signal, and the drain of the fourth PMOS switch tube PM4 is connected to the VIN signal. The midpoint of the third PMOS switch tube PM3 and the fourth PMOS switch tube PM4 is the output end, and the VMAX signal is output.

5. The backflow prevention system for load switch according to claim 4, characterized in that: When the voltage detection module outputs a low level, the fourth PMOS switch tube PM4 is turned on, and the voltage value of the output VMAX signal is the voltage value of the VIN signal; when the voltage detection module outputs a high level, the third PMOS switch tube PM3 is turned on, and the voltage value of the output VMAX signal is the voltage value of the VOUT signal.

6. The backflow prevention system for load switch according to claim 1, characterized in that: The system further comprises a voltage negative feedback module, wherein the non-inverting input terminal of the voltage negative feedback module is connected to the drain of the load switch, the inverting input terminal is connected to the VIN signal, and the output terminal is connected to the gate of the load switch; when it is detected that the voltage difference between the VOUT signal and the signal VIN is within a preset voltage difference value, the gate of the load switch tube is raised by feedback to stabilize the voltage difference between the VOUT signal and the VIN signal at a voltage difference setting value; when the voltage value of the VOUT signal is close to the voltage value of the VIN signal, the gate voltage value of the load switch tube increases and approaches the voltage value of the VIN signal; If the VOUT signal is greater than the VIN signal, when reverse current occurs, the gate voltage is pulled up to the VIN signal in a short time.

7. The backflow prevention system for load switch according to claim 6, characterized in that: The voltage negative feedback module includes a sixth MOS tube MP6, a seventh MOS tube MP7, a fourth MOS tube MN4, a fifth MOS tube MN5 and a second resistor R2. The sixth MOS tube MP6 and the seventh MOS tube MP7 are an input pair. The gates of the sixth MOS tube MP6 and the seventh MOS tube MP7 are connected. The drain of the sixth MOS tube MP6 is connected to the VOUT signal. The drain of the seventh MOS tube MP7 is connected to the VIN signal through the second resistor R2. The source of the sixth MOS tube MP6 is connected to the drain of the fourth MOS tube MN4. The source of the seventh MOS tube MP7 is connected to the drain of the fifth MOS tube MN5. The fourth MOS tube MN4 and the fifth MOS tube MN5 are 1:1 mirror current mirrors. The gates of the fourth MOS tube MN4 and the fifth MOS tube are both connected to the bias voltage VB. The middle point of the seventh MOS tube MP7 and the fifth MOS tube MN5 is an output end, which is connected to the gate of the load switch.

Images