Ultra-wideband digital phase-locked loop synchronizing signal adjusting method

Abstract

The invention discloses an ultra-wideband digital phase-locked loop synchronizing signal adjusting method, which relates to the technical field of time service, and comprises the following steps: receiving a standard pulse per second signal emitted by a GPS satellite by using a main control chip of a main base station, detecting a rising edge of the standard pulse per second signal, and when the rising edge of the standard pulse per second signal is detected, adjusting the synchronizing signal of the ultra-wideband digital phase-locked loop according to the rising edge of the standard pulse per second signal; generating an ultra-wideband synchronization signal of a preset period by using the ultra-wideband chip; respectively calculating periodic data of the standard pulse per second signal and the ultra-wideband synchronization signal by using a phase detector, and calculating phase difference data between the standard pulse per second signal and the ultra-wideband synchronization signal based on the obtained periodic data; and dynamically adjusting the period of the ultra-wideband synchronization signal based on the phase difference data. According to the technical scheme, the constant phase difference between the synchronization signal of the main base station and the GPS pulse per second can be kept, and the synchronization stability is enhanced.

Description

Technical Field

[0001] The invention belongs to the technical field of time service, and in particular relates to an ultra-wideband digital phase-locked loop synchronization signal adjustment method. Background Art

[0002] Today's society is gradually entering the era of "Internet of Everything". Low-cost precision clock synchronization has become an important supporting technology for wireless cluster network applications such as drone cluster flight control, Internet of Vehicles data synchronization, wireless sensor network positioning, distributed multiple input multiple output (MIMO) communication, and low-orbit satellite cluster collaboration. Clock synchronization is a basic service for information communication, and related research has always been in a booming trend. The performance of clock synchronization directly plays a decisive role in the comprehensive performance of distributed collaborative systems such as indoor positioning, multi-base radar detection, and smart grids. With the advent of the Internet of Things era, high-precision wireless time and frequency synchronization technology applied to wireless sensor networks has become one of the most popular research issues in the field of PNT (positioning, navigation and timing). At present, high-precision wireless time and frequency synchronization technology still relies heavily on the assistance of the satellite positioning system (GPS), such as satellite time service solutions based on pseudo-range information and carrier phase analysis, collaborative positioning, etc. This GPS-based solution has matured in terms of technical path, stable performance, and has been widely used within the industry. However, the GPS-based wireless clock synchronization solution has its inherent defects, that is, it cannot provide clock synchronization services when GPS is degraded or GPS signals cannot be received. This means that this solution is not suitable for indoor, underground, mines or other scenarios where there is no GPS coverage or GPS signals cannot be received.

[0003] In order to effectively solve the above-mentioned problems, some non-GPS-assisted clock synchronization methods have been proposed in recent years, such as clock synchronization methods based on WIFI networks and Bluetooth, which have successfully achieved microsecond-level synchronization accuracy. However, compared with the 10-20ns accuracy that GPS can achieve, these non-GPS-assisted methods are not high enough in clock synchronization performance, and the synchronization accuracy is relatively poor, which makes it difficult to meet the needs of high-precision synchronization for positioning, radar detection, etc.

[0004] At the same time, the main control chip of the main base station has an inherent time delay when processing GPS second pulse interruption events, resulting in the synchronization signal generated by the main base station not being strictly synchronized with the standard second pulse. When the synchronization signal distributed by the main base station is distributed to the slave base station after a fixed time delay, the phase difference of the synchronization signal received by the slave base station compared to the standard second pulse will show a further increasing trend, that is, the synchronization signal of the main base station cannot achieve accurate synchronization with the standard second pulse. Summary of the invention

[0005] The purpose of the present invention is to provide a method for adjusting a synchronization signal of an ultra-wideband digital phase-locked loop to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above object, the present invention provides an ultra-wideband digital phase-locked loop synchronization signal adjustment method, comprising: The main control chip of the main base station receives the standard second pulse signal transmitted by the GPS satellite, and detects the rising edge of the standard second pulse signal. When the rising edge of the standard second pulse signal is detected, the ultra-wideband chip is used to generate an ultra-wideband synchronization signal of a preset period; Calculate the period data of the standard second pulse signal and the ultra-wideband synchronization signal respectively by using a phase detector, and calculate the phase difference data between the standard second pulse signal and the ultra-wideband synchronization signal based on the obtained period data; The period of the ultra-wideband synchronization signal is dynamically adjusted based on the phase difference data.

[0007] Optionally, the using a phase detector to respectively calculate the period data of the standard second pulse signal and the ultra-wideband synchronization signal specifically includes: Based on the SPI protocol, a first phase detection channel and a second phase detection channel are configured on the main control chip, the first phase detection channel is used to calculate the period data of the standard second pulse signal, and the second phase detection channel is used to calculate the period data of the ultra-wideband synchronization signal.

[0008] Optionally, the dynamically adjusting the period of the ultra-wideband synchronization signal based on the phase difference data specifically includes: Abnormal data elimination and filtering are performed on the phase difference data to obtain preprocessed phase difference data, and the period of the ultra-wideband synchronization signal is dynamically adjusted based on the preprocessed phase difference data.

[0009] Optionally, the dynamically adjusting the period of the ultra-wideband synchronization signal based on the preprocessed phase difference data specifically includes: The pre-processed phase difference data is judged based on the preset demarcation threshold. When the phase difference data is greater than the preset demarcation threshold, the system feedback coarse adjustment is performed; when the phase difference data is less than the preset demarcation threshold, the system PID feedback fine adjustment is performed.

[0010] Optionally, the process of performing system feedback coarse adjustment specifically includes: A compensation value is calculated based on the phase difference data, and a count value compensation is performed on a delayed transceiver register inside the ultra-wideband chip based on the compensation value, thereby completing a system feedback coarse adjustment.

[0011] Optionally, the compensation value is calculated based on the phase difference data, and the specific calculation formula is: , In the formula, is the count value required to be compensated inside the ultra-wideband chip, is the operating frequency of the ultra-wideband chip, is the phase difference, It is the original counter count value of the ultra-wideband chip.

[0012] Optionally, the process of fine-tuning the system PID feedback specifically includes: The phase difference data is converted into an operating frequency variation based on a PID fine-tuning formula, and the counting frequency and cycle of the ultra-wideband chip are adjusted based on the operating frequency variation to complete system PID feedback fine-tuning.

[0013] Optionally, the phase difference data is converted into an operating frequency variation based on a PID fine-tuning formula, and a specific calculation formula is: , In the formula, is the change in operating frequency that needs to be adjusted inside the ultra-wideband chip. is the original counter count value of the UWB chip, is the compensation count value after coarse adjustment. If the phase difference entering the control system does not need to be processed by coarse adjustment, then Can be 0, The control output is the time difference of discrete time points.

[0014] The technical effects of the present invention are: The present invention can ensure that after receiving the GPS signal, the main base station can distribute the synchronization signal to the slave base station with extremely high accuracy, ensure its time synchronization accuracy within 15ns, maintain a constant phase difference between the main base station synchronization signal and the GPS second pulse, and enhance synchronization stability; by combining the phase detection tracking of the digital phase-locked loop with the high-precision time resolution of the UWB synchronization signal, the robustness and stability of the wireless timing system in multipath propagation and interference environments are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 Schematic diagram of the basic principle of a digital phase-locked loop (DPLL) in an embodiment of the present invention; Figure 2 It is a schematic diagram of a wireless timing system in an embodiment of the present invention; Figure 3 Schematic diagram of GPS_1PPS and UWB synchronization signal SYNC_1PPS in an embodiment of the present invention; Figure 4 is a flowchart of program filtering in an embodiment of the present invention; Figure 5 The figure is a flowchart of synchronization signal adjustment in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0018] It should be understood that the terms described in the present invention are only for describing special embodiments and are not intended to limit the present invention. In addition, for the numerical range in the present invention, it should be understood that each intermediate value between the upper and lower limits of the scope is also specifically disclosed. Each smaller range between the intermediate value in any stated value or stated range and any other stated value or intermediate value in the described range is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded in the scope.

[0019] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to those skilled in the art. The present application description and examples are exemplary only.

[0020] The words “include,” “including,” “have,” “contain,” etc. used in this article are open-ended terms, meaning including but not limited to.

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] like Figure 1 - Figure 5As shown, in this embodiment, a method for adjusting an ultra-wideband digital phase-locked loop synchronization signal is provided, comprising: using a main control chip of a main base station to receive a standard second pulse signal transmitted by a GPS satellite, and detecting a rising edge of the standard second pulse signal; after detecting the rising edge of the standard second pulse signal, using an ultra-wideband chip to generate an ultra-wideband synchronization signal of a preset period; using a phase detector to respectively calculate the period data of the standard second pulse signal and the ultra-wideband synchronization signal, and calculating the phase difference data between the standard second pulse signal and the ultra-wideband synchronization signal based on the obtained period data; and dynamically adjusting the period of the ultra-wideband synchronization signal based on the phase difference data.

[0023] This embodiment proposes a digital phase-locked loop (DPLL) wireless timing solution based on ultra-wideband technology. The core goal of this solution is to ensure that the master base station can distribute the synchronization signal to the slave base station with extremely high accuracy after receiving the GPS signal, ensuring that its time synchronization accuracy is within 15ns. By combining the phase detection tracking of DPLL with the high-precision time resolution of ultra-wideband (UWB) synchronization signals, this solution effectively improves the robustness and stability of the wireless timing system in multipath propagation and interference environments. In addition, the adaptive characteristics of DPLL enable the system to adjust phase tracking in real time, further enhancing the timing accuracy and reliability.

[0024] This embodiment innovatively combines UWB technology with DPLL technology to construct a new type of wireless timing system. The high time resolution and superior anti-interference ability of ultra-wideband signals effectively improve the performance of the system in complex electromagnetic environments and significantly enhance the accuracy and reliability of time synchronization. At the same time, this embodiment applies the PID algorithm to the phase tracking of DPLL, which can achieve more accurate and stable phase adjustment. It helps to optimize the system response speed and steady-state error and improve the timing accuracy.

[0025] This embodiment uses UWB technology and combines TDC to perform high-precision time measurement, which significantly improves the accuracy of clock synchronization. Secondly, this embodiment solves the clock synchronization problem when GPS signals are unavailable, broadening the application scenarios. At the same time, this embodiment can optimize the main base station synchronization signal, maintain a constant phase difference between the main base station synchronization signal and the GPS second pulse, and enhance synchronization stability.

[0026] The specific contents of this embodiment are as follows: Based on the principle and composition of DPLL, this embodiment uses the standard second pulse provided by GPS as a reference for clock synchronization. To achieve high-precision phase comparison, this embodiment introduces a time-to-digital converter (TDC) module of model TDC7201 as a phase detector (PD). Triggered by the interrupt signal of the standard second pulse, the main control chip STM32H750 drives the ultra-wideband UWB to generate a 1-second synchronization signal with the same period as the standard second pulse through the serial peripheral interface (SPI) protocol.

[0027] The phase detector calculates the phase difference between the synchronization signal and the standard second pulse in real time and feeds the phase difference value back to the main control chip. The main control chip then filters the feedback phase difference to reduce the impact of noise and improve the stability of the system. The phase difference value after filtering will serve as a key reference for adjusting the synchronization signal period of the UWB module, thereby achieving accurate clock synchronization.

[0028] This embodiment effectively utilizes the feedback mechanism and phase comparison principle of DPLL to gradually approach and converge the phase difference between the synchronization signal distributed by the master base station and the standard GPS second pulse to within the allowable error range.

[0029] The hardware platform in this embodiment is mainly the main base station, which is divided into four functional modules: GPS module, main control chip, UWB chip and time digital converter (TDC). Among them, the function of the GPS module is to transmit the standard time second pulse signal. The main control chip is responsible for receiving this second pulse signal and using the SPI protocol to drive the UWB chip and TDC. The main control chip is also responsible for processing the phase difference data calculated by TDC. When the main control chip receives an interrupt trigger signal, the UWB module will generate a synchronization signal with a period of 1 second. The task of the TDC module is to accurately calculate the phase difference between the GPS second pulse signal and the synchronization signal generated by the UWB module, and return this calculation result to the main control chip.

[0030] In the main base station, the main control chip is STM32H750. STM32H750 is a high-performance microcontroller (MCU) produced by STMicroelectronics (ST), belonging to the STM32H7 series, using a 32-bit ARMCortex-M7 core, and operating at a frequency of up to 480 MHz. The chip's processing power and operating frequency can meet the requirements of a nanosecond-level clock synchronization working environment.

[0031] The main base station uses a UWB communication chip to send a UWB synchronization signal. The UWB communication chips in this embodiment all use DW1000 chips, which are UWB wireless transceiver chips launched by Decawave and are widely used in fields such as high-precision positioning.

[0032] The TDC module uses TDC7201, a high-precision time-to-digital converter (TDC) produced by Texas Instruments. TDC7201 has a resolution of 55ps and a standard deviation of 35ps, and can provide picosecond-level measurement accuracy. It supports independent measurement mode and combined measurement mode. The built-in self-calibration time base can compensate for time and temperature deviations to ensure measurement accuracy.

[0033] The technical solution and working principle of this implementation: Principle of digital phase-locked loop: Digital phase-locked loop (DPLL) is a phase-locked loop circuit based on digital signal processing technology. It aims to accurately track and control the frequency and phase of the input signal by performing a series of processing on the input signal, including sampling, digital filtering, phase detection and adjustment.

[0034] The basic structure of DPLL is similar to that of a traditional phase-locked loop, and is mainly composed of a phase detector, a low-pass filter, a control voltage generator, and an oscillator. The phase detector receives input signals and feedback signals, and outputs an error signal; the low-pass filter filters the error signal to generate a control voltage; the control voltage generator converts the control voltage into an oscillator control signal, thereby adjusting the oscillator frequency and phase.

[0035] Digital phase-locked loop wireless timing solution based on ultra-wideband technology: This embodiment is based on the principle of digital phase-locked loop and proposes a digital phase-locked loop wireless timing solution using ultra-wideband technology. The solution uses the second pulse generated by GPS as the reference signal in the digital phase-locked loop and uses TDC as a phase detector to calculate the phase difference between the reference second pulse and the UWB synchronization signal.

[0036] In this embodiment, the main control chip filters and processes the phase difference data, and uses the processed data as the control factor of the UWB module synchronization signal. By adjusting the period of the UWB synchronization signal, the phase difference between it and the reference pulse converges to a preset range, thereby achieving a high-precision wireless timing function. The system schematic diagram of this solution is shown in FIG. Figure 2 shown.

[0037] The specific workflow of this embodiment is as follows: (1) The master base station sends a synchronization signal: The master control chip of the master base station receives the GPS second pulse signal GPS_1PPS. After the master control chip detects the rising edge of GPS_1PPS, it controls the DW1000 chip to start the UWB transmission function and send a UWB synchronization signal SYNC_1PPS with a period of 1 second for the slave base station to receive.

[0038] (2) Configure TDC module: TDC7201 is a dual-channel time TDC device, which is marked as TDC1 and TDC2 in this embodiment. TDC1 is mainly used to measure the period of the standard second pulse GPS_1PPS, while TDC2 is used to measure the period of SYNC_1PPS generated by the DW1000 chip. The main control chip drives and enables TDC7201 through the SPI protocol, thereby calculating and storing the period data of GPS_1PPS and SYNC_1PPS in TDC1 and TDC2, so that the main control chip can perform subsequent data reading and processing.

[0039] (3) Data reading and processing of the main control chip: After TDC7201 successfully completes the calculation of the GPS_1PPS and SYNC_1PPS cycles, the main control chip reads these two values ​​from TDC7201 in real time through the SPI protocol. Based on the value of GPS_1PPS, the main control chip calculates the difference between it and SYNC_1PPS, which is recorded as In order to effectively reduce noise interference and improve the robustness of the system, it is necessary to This study uses an improved filtering algorithm to obtain the average difference after denoising. .Should Will be used as a regulatory factor for SYNC_1PPS, according to The SYNC_1PPS period is dynamically adjusted according to the size of the SYNC_1PPS, thereby optimizing and improving the system time synchronization accuracy.

[0040] Figure 3 middle The time difference is obtained by reading the standard second pulse GPS_1PPS and the UWB synchronization signal SYNC_1PPS from the main control chip. The calculation formula is: , In the formula, is the period of GPS_1PPS, is the period of SYNC_1PPS, It is the phase difference between SYNC_1PPS and GPS_1PPS, that is, the time difference.

[0041] Get the time difference in the main control chip After that, the data is preprocessed. First, the acquired information is judged and eliminated for abnormal values. Specifically, the main control chip groups the time differences according to the order of acquisition time, and uses Rhineda The criterion is used to identify and remove outliers. The specific judgment basis of this criterion follows the following algorithm rules: There are n groups in each group The values ​​are recorded as If the residual error of a measured value is considered to be greater than three times the standard deviation, the outlier is identified and removed. The calculation formula is as follows: , when

[0042] Then the jth data is an outlier and needs to be removed.

[0043] The main control chip follows After removing the abnormal data items in principle, the retained valid data needs to be further filtered. This embodiment combines the two widely used digital filtering technologies, sliding average filtering and average filtering, to improve the filtering effect and real-time performance of time difference data. The specific implementation steps are as follows: First, a data queue with a fixed length of N is constructed to store continuously collected time difference signals. Whenever a new time difference signal is collected, it will be added to the end of the queue, and the head data of the queue will be removed accordingly. This mechanism ensures the constancy of the queue length and realizes real-time update and processing of data.

[0044] Next, the processing results of the data in the current queue are calculated and output. This process not only maintains the stability of the queue length, but also ensures the real-time responsiveness of the output data, so that the filtered time difference data can quickly reflect the latest signal changes.

[0045] On this basis, each time difference data entering the queue is tested for extreme values. If a time difference data is determined to be the maximum or minimum value in the queue, the data will be directly eliminated to avoid the potential impact of abnormal values ​​on the filtering results. Then, we perform arithmetic averaging on the remaining data, and the result is the time difference data after optimized filtering.

[0046] By combining the real-time update characteristics of the sliding average filter with the robustness of the average value filter to outliers, the method proposed in this embodiment not only significantly improves the filtering accuracy of the time difference data, but also effectively reduces the interference of outliers on the filtering results, providing a more reliable data basis for subsequent data processing and analysis. Figure 4 shown.

[0047] (4) System feedback coarse adjustment: In this embodiment, GPS_1PPS and SYNC_1PPS are both clock signals with a period of 1 second. After the system is filtered, the phase difference between the two, i.e. the time difference , must be maintained within a range of less than 1 second. In order to clearly distinguish the adjustment process, this embodiment sets 1 millisecond as the demarcation threshold between coarse adjustment and fine adjustment. Specifically, when the time difference When it exceeds 1 millisecond, the system will automatically enter the coarse adjustment stage.

[0048] The core of the coarse adjustment mechanism is to detect the phase difference (i.e. the time difference) ), the count value of the delayed transmit and receive register inside the DW1000 module is compensated. This compensation operation is intended to adjust the count time, thereby achieving the regulation of the phase of the transmitted synchronous timing pulse. The calculation of the compensation value follows the following formula: , The formula is transformed into: , In the formula, is the operating frequency of DW1000, is the phase difference, It is the original counter count value of DW1000.

[0049] Using the above-mentioned calculation formula, the phase difference between GPS_1PPS and SYNC_1PPS can be calculated as , effectively converted into the count value required for compensation inside the DW1000 This process achieves the preliminary tracking of the phase of GPS_1PPS by SYNC_1PPS. The conversion formula maps the phase difference in the time domain to the compensation value in the DW1000 counter domain, and then achieves the purpose of sync pulse phase alignment by adjusting the delay transmit and receive register of DW1000.

[0050] (5) System PID feedback fine-tuning: PID control is a regulation method widely used in automatic control systems. By setting appropriate proportional (P), integral (I) and differential (D) parameters, it can accurately control the output and make the system reach a stable state.

[0051] The output signal of the PID control method and system can be expressed as the following mathematical formula: , in, is the control signal; is the system error, that is, the difference between the set value and the actual value. are the proportional, integral and differential coefficients respectively.

[0052] When the PID algorithm is executed on a computer, the integral term and the differential term need to be discretized, namely: , In the formula, k represents the time series.

[0053] This embodiment uses the traditional PID control model to fine-tune the system. When it is less than 1 millisecond, the synchronization signal SYNC_1PPS needs to be fine-tuned with PID. If the phase of the GPS_1PPS signal is ahead of the SYNC_1PPS signal, the period of the SYNC_1PPS signal needs to be increased, that is, the counting frequency needs to be increased to achieve phase adjustment while maintaining the same counting value. Conversely, if the phase of the GPS_1PPS signal lags behind the SYNC_1PPS signal, the period of the SYNC_1PPS signal needs to be reduced or the counting frequency needs to be lowered accordingly.

[0054] Assume there is a fixed sampling period , then the discrete time point can be expressed as ,in is a discrete time index (e.g. =0,1,2,…). At discrete time points Phase difference It can be expressed as .

[0055] The PID fine-tuning formula is as follows: , in The control output is the time difference of discrete time points.

[0056] Combined equation (7), Substitution Then the operating frequency of DW1000 that needs to be changed is: , In the formula, is the original counter value of DW1000, is the compensation count value after coarse adjustment. No rough adjustment is required. Can be 0.

[0057] According to formulas (10) and (11), appropriate proportional, integral and differential coefficients are set to effectively convert the phase difference between GPS_1PPS and SYNC_1PPS into , which is converted into the change in operating frequency that needs to be adjusted inside DW1000 Through precise control , to achieve accurate tracking and synchronization of the phase of the SYNC_1PPS signal relative to the GPS_1PPS signal. This process ensures that the SYNC_1PPS signal can closely follow the phase changes of the GPS_1PPS signal, thus meeting the requirements of fine time synchronization.

[0058] This embodiment relates to a digital phase-locked loop (DPLL) wireless timing system based on ultra-wideband (UWB) technology, the design of which relies on the UWB communication principle and uses a high-performance UWB communication chip as a core component. Compared with the traditional synchronous timing solution, this embodiment utilizes the strong anti-multipath interference capability and high time resolution characteristics of UWB technology in indoor environments, and innovatively develops an indoor timing solution. This solution adjusts and tracks the standard clock by integrating DPLL, and uses a specific algorithm to eliminate and filter possible errors in actual operation, thereby generating a synchronous timing signal with high resolution and significant anti-multipath interference capability. This embodiment ensures that the synchronous timing signal distributed by the master base station has extremely high accuracy, and its distribution error is controlled within 15 nanoseconds, thereby effectively ensuring that the slave base station can receive a highly accurate time synchronization signal. This technical implementation relies on a precise time synchronization mechanism and an optimized signal distribution strategy, ensuring the accuracy and consistency of time information in the entire communication network, and providing a reliable and accurate time reference for the slave base station.

[0059] The above is only a preferred specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for adjusting a synchronization signal of an ultra-wideband digital phase-locked loop, characterized in that: include: The main control chip of the main base station receives the standard second pulse signal transmitted by the GPS satellite, and detects the rising edge of the standard second pulse signal. When the rising edge of the standard second pulse signal is detected, the ultra-wideband chip is used to generate an ultra-wideband synchronization signal of a preset period; Calculating the period data of the standard second pulse signal and the ultra-wideband synchronization signal respectively by using a phase detector; Calculate the phase difference data between the standard second pulse signal and the ultra-wideband synchronization signal based on the obtained periodic data; The period of the ultra-wideband synchronization signal is dynamically adjusted based on the phase difference data.

2. The method for adjusting the synchronization signal of an ultra-wideband digital phase-locked loop according to claim 1, characterized in that: The method of calculating the period data of the standard second pulse signal and the ultra-wideband synchronization signal respectively by using a phase detector specifically includes: Based on the SPI protocol, a first phase detection channel and a second phase detection channel are configured on the main control chip, the first phase detection channel is used to calculate the period data of the standard second pulse signal, and the second phase detection channel is used to calculate the period data of the ultra-wideband synchronization signal.

3. The method for adjusting the synchronization signal of an ultra-wideband digital phase-locked loop according to claim 1, characterized in that: The dynamically adjusting the period of the ultra-wideband synchronization signal based on the phase difference data specifically includes: Abnormal data elimination and filtering are performed on the phase difference data to obtain preprocessed phase difference data, and the period of the ultra-wideband synchronization signal is dynamically adjusted based on the preprocessed phase difference data.

4. The method for adjusting the synchronization signal of an ultra-wideband digital phase-locked loop according to claim 3, characterized in that: The dynamically adjusting the period of the ultra-wideband synchronization signal based on the preprocessed phase difference data specifically includes: The pre-processed phase difference data is judged based on the preset demarcation threshold. When the phase difference data is greater than the preset demarcation threshold, the system feedback coarse adjustment is performed; when the phase difference data is less than the preset demarcation threshold, the system PID feedback fine adjustment is performed.

5. The method for adjusting the synchronization signal of an ultra-wideband digital phase-locked loop according to claim 4, characterized in that: The process of performing system feedback coarse adjustment specifically includes: A compensation value is calculated based on the phase difference data, and a count value compensation is performed on a delayed transceiver register inside the ultra-wideband chip based on the compensation value, thereby completing a system feedback coarse adjustment.

6. The method for adjusting the synchronization signal of an ultra-wideband digital phase-locked loop according to claim 5, characterized in that: The compensation value is calculated based on the phase difference data, and the specific calculation formula is: ， In the formula, is the count value required to be compensated inside the ultra-wideband chip, is the operating frequency of the ultra-wideband chip, is the phase difference, It is the original counter count value of the UWB chip.

7. The method for adjusting the synchronization signal of an ultra-wideband digital phase-locked loop according to claim 4, characterized in that: The process of fine-tuning the system PID feedback specifically includes: The phase difference data is converted into an operating frequency variation based on a PID fine-tuning formula, and the counting frequency and cycle of the ultra-wideband chip are adjusted based on the operating frequency variation to complete system PID feedback fine-tuning.

8. The method for adjusting the synchronization signal of an ultra-wideband digital phase-locked loop according to claim 7, characterized in that: The phase difference data is converted into the operating frequency variation based on the PID fine adjustment formula, and the specific calculation formula is: ， In the formula, is the change in operating frequency that needs to be adjusted inside the ultra-wideband chip. is the original counter count value of the UWB chip, is the compensation count value after coarse adjustment. If the phase difference entering the control system does not need to be processed by coarse adjustment, then Can be 0, The control output is the time difference of discrete time points.

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