Transistor manufacturing method, display device, and display device manufacturing method

Abstract

The invention provides a manufacturing method of a transistor, a display device and a manufacturing method of the display device. The manufacturing method of the transistor includes: providing a preliminary polysilicon layer including an upper surface on which a protrusion is formed; providing a sacrificial layer on the upper surface of the preliminary polycrystalline silicon layer; providing argon (Ar) ions in an upper portion of the sacrificial layer to dope the sacrificial layer and the preliminary polysilicon layer; providing an etchant to an upper portion of the doped sacrificial layer; and removing the sacrificial layer and etching the protrusion to form a polysilicon layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0097174 filed in the Korean Intellectual Property Office on July 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a method for manufacturing a transistor including a polysilicon layer, a display device including a transistor including a polysilicon layer, and a method for manufacturing the display device. Background Art

[0004] The display device provides various functions for allowing communication with a user, such as displaying an image to provide information to the user or sensing a user input.

[0005] The display device may include a transistor including a semiconductor pattern and a gate constituting a source, a drain and a channel. Recent display devices have used a polysilicon (p-Si) layer in the semiconductor pattern to improve the performance of the transistor. The polysilicon layer can be formed by crystallizing amorphous silicon (a-Si), and in order to make the transistor formed by the polysilicon layer show excellent performance, it is desirable to control the crystallization quality and surface quality of the polysilicon layer.

[0006] It should be understood that this background technology section is intended to provide a useful background for understanding the technology to some extent. However, this background technology section may also include ideas, concepts or cognitions that were not known or clear to those skilled in the relevant art before the corresponding effective application date of the subject matter disclosed in this article. Summary of the invention

[0007] The present disclosure provides a method for manufacturing a transistor including a polysilicon layer whose surface has improved surface quality.

[0008] The present disclosure also provides a display device including a transistor having a polysilicon layer having excellent surface quality, and a method for manufacturing the display device.

[0009] An embodiment provides a method for manufacturing a transistor, wherein the method may include: providing a preliminary polysilicon layer including an upper surface on which a protrusion is formed; providing a sacrificial layer on the upper surface of the preliminary polysilicon layer; providing argon (Ar) ions in an upper portion of the sacrificial layer to dope the sacrificial layer and the preliminary polysilicon layer; providing an etchant to the upper portion of the doped sacrificial layer; and removing the sacrificial layer and etching the protrusion to form a polysilicon layer.

[0010] In an embodiment, the surface roughness of the upper surface of the polysilicon layer may be less than about 50% of the surface roughness of the upper surface of the preliminary polysilicon layer.

[0011] In an embodiment, the preliminary polysilicon layer may be formed in an operation of performing crystallization by providing an excimer laser to an amorphous silicon layer.

[0012] In an embodiment, the sacrificial layer may include silicon oxide (SiO x ).

[0013] In an embodiment, the average thickness of the sacrificial layer may be about to about within the range.

[0014] In an embodiment, providing the argon ions may include providing the argon ions in an ion implantation apparatus with an acceleration voltage in a range of about 5 keV to about 80 keV and a dose in a range of about 1.0E15 to about 1.0E20.

[0015] In one embodiment, the etchant may include hydrogen fluoride (HF) and ammonium fluoride (NH 4 F) of an acidic solution.

[0016] In an embodiment, a ratio of an etch rate of the doped sacrificial layer to an etch rate of the doped preliminary polysilicon layer may be less than about 5.0.

[0017] In an embodiment, a display device may include a base layer, a circuit layer disposed on the base layer and including a transistor and a plurality of insulating layers, and a display layer disposed on the circuit layer and including a light-emitting element electrically connected to the transistor, wherein the transistor includes a polycrystalline silicon layer containing argon (Ar).

[0018] In embodiments, the transistor may include a semiconductor pattern including a source, a channel, and a drain, and a gate disposed to overlap the semiconductor pattern, wherein the semiconductor pattern may be a polysilicon layer including argon.

[0019] In an embodiment, the circuit layer may include a gate insulating layer disposed between the semiconductor pattern and the gate, the gate may be disposed on an upper side of the semiconductor pattern via the gate insulating layer disposed between the gate and the semiconductor pattern, and at least a portion of the semiconductor pattern adjacent to the gate insulating layer may contain argon.

[0020] In an embodiment, the surface roughness of the polysilicon layer may be about 10 nm or less.

[0021] In an embodiment, a method for manufacturing a display device may include: providing a base layer; forming a circuit layer including multiple transistors and multiple insulating layers on the base layer; and providing a display layer on the circuit layer, wherein forming the circuit layer may include: forming an amorphous silicon layer on the base layer; crystallizing the amorphous silicon layer into a preliminary polycrystalline silicon layer; providing a sacrificial layer on the preliminary polycrystalline silicon layer; doping the sacrificial layer and the preliminary polycrystalline silicon layer with argon; providing an etchant on the doped sacrificial layer and the doped preliminary polycrystalline silicon layer; and removing the sacrificial layer and reducing the surface roughness of the preliminary polycrystalline silicon layer to form a polycrystalline silicon layer.

[0022] In an embodiment, at least one of the plurality of transistors may include a polysilicon layer.

[0023] In an embodiment, forming the circuit layer may also include manufacturing a transistor including a polysilicon layer by: providing a gate insulating layer on the polysilicon layer; forming a gate overlapping the polysilicon layer on the gate insulating layer; and forming the polysilicon layer into a semiconductor pattern divided into a source, a channel, and a drain.

[0024] In an embodiment, crystallizing the amorphous silicon layer may include providing an excimer laser to the amorphous silicon layer.

[0025] In an embodiment, the sacrificial layer may include silicon oxide (SiO x ).

[0026] In an embodiment, the average thickness of the sacrificial layer may be about to about within the range.

[0027] In an embodiment, doping the sacrificial layer may include providing argon ions in an ion implantation apparatus with an acceleration voltage in a range of about 5 keV to about 80 keV and a dose in a range of about 1.0E15 to about 1.0E20.

[0028] In one embodiment, the etchant may include hydrogen fluoride (HF) and ammonium fluoride (NH 4 F) of an acidic solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the specification. The accompanying drawings illustrate embodiments and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0030] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0031] Figure 2 is an exploded schematic perspective view of a display device according to an embodiment;

[0032] Figure 3 is shown with Figure 2 A schematic cross-sectional view of a portion corresponding to line II';

[0033] Figure 4 is a schematic plan view of a display panel according to an embodiment;

[0034] Figure 5 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0035] Fig. 6A is a schematic cross-sectional view of a portion of a display module according to an embodiment;

[0036] Figure 6B is a schematic cross-sectional view showing a portion of a transistor according to an embodiment;

[0037] Figure 7 is a flow chart of a method for manufacturing a transistor according to an embodiment;

[0038] FIG. 8A to FIG. 8G Each is a schematic diagram illustrating the operation of a method for manufacturing a transistor according to an embodiment;

[0039] Fig. 9 is a schematic cross-sectional view showing a portion of a polysilicon layer according to an embodiment;

[0040] Fig. 10A is a schematic diagram showing a plan image of a preliminary polysilicon layer according to an embodiment;

[0041] Fig. 10B is a schematic diagram showing a planar image of a polysilicon layer according to an embodiment;

[0042] FIG. 11A to FIG. 11D Each is a schematic diagram showing a simulation result of argon doping according to an embodiment;

[0043] Fig. 12A is a view showing a schematic cross-sectional image of a preliminary polysilicon layer according to an embodiment; and

[0044] Fig. 12B is a view showing a schematic cross-sectional image of a polysilicon layer according to an embodiment. DETAILED DESCRIPTION

[0045] The present disclosure can be modified in many alternative forms, and therefore only certain specific embodiments are disclosed in the drawings and described in detail. However, it should be understood that these embodiments are not intended to limit the present disclosure to the specific forms disclosed, but the present disclosure is intended to cover all modifications, equivalents and substitutes.

[0046] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or".

[0048] In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of" is intended to include "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0049] In the specification, when an element (or region, layer, part, etc.) is referred to as being "on," "connected to" or "coupled to" another element, it means that the element may be directly disposed on, connected / coupled to the other element, or a third element may be disposed therebetween.

[0050] The same reference numerals refer to the same elements. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the elements may be exaggerated.

[0051] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and a second element may also be referred to as a first element in a similar manner.

[0052] In addition, terms such as "below", "lower", "above", "upper" and the like are used to describe the relationship of elements shown in the drawings. These terms are used as relative concepts and are described with reference to the directions indicated in the drawings.

[0053] It should be understood that the terms “includes,” “comprising,” and “having” are intended to specify the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof in the present disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

[0054] In the present disclosure, "directly disposed" may mean that there is no added layer, film, region, plate or the like between one part of a layer, film, region, plate or the like and the other part. For example, "directly disposed" may mean that there is no additional component such as a bonding component disposed between two layers or two components.

[0055] The term "overlap" or "overlapped" means that a first object may be located above or below, or to the side of, a second object, and vice versa. Additionally, the term "overlap" may include layer, stack, facing or facing, extending over, covering or partially covering, or any other suitable term as would be apparent and understood by one of ordinary skill in the art.

[0056] As used herein, "about" or "approximately" or "substantially" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0057] Unless otherwise defined or implied, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined as such herein.

[0058] Figure 1 is a schematic perspective view of a display device ELD according to an embodiment; Figure 2 is an exploded schematic perspective view of a display device ELD according to an embodiment; Figure 3 is a schematic cross-sectional view of a display device ELD according to an embodiment; Figure 3 is with Figure 2 The line II' corresponds to the cross-sectional view.

[0059] Reference Figure 1The display device ELD may be a device that is activated in response to an electrical signal and displays an image. For example, the display device ELD may be a large device such as a television or an external billboard, or may be a small or medium-sized device such as a monitor, a mobile phone, a tablet computer, a navigation system unit, or a game console. However, the embodiments of the display device ELD are merely examples, and the display device ELD is not limited to any one of them without departing from the present disclosure.

[0060] The display device ELD may be rigid or flexible. "Flexible" means having the property of being able to bend. For example, the flexible display device ELD may include a bendable device, a rollable device, or a foldable device.

[0061] exist Figure 1 The first direction axis DR1 to the third direction axis DR3 are shown in the following drawings, and the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 described in the specification are relative concepts and can be converted into different directions. In addition, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 can be described as the first direction DR1, the second direction DR2, and the third direction DR3, and can be represented by the same reference numerals. In the specification, the first direction axis DR1 and the second direction axis DR2 are perpendicular to each other, and the third direction axis DR3 can be a normal direction relative to a plane defined by the first direction axis DR1 and the second direction axis DR2.

[0062] The thickness direction of the display device ELD may be a direction parallel to the third directional axis DR3 which is a normal direction relative to a plane defined by the first directional axis DR1 and the second directional axis DR2. In the specification, the front surface (or upper surface) and the rear surface (or lower surface) of the member constituting the display device ELD may be defined based on the third directional axis DR3. The front surface (or upper surface) and the rear surface (or lower surface) of the member constituting the display device ELD may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The spacing distance between the front surface and the rear surface defined in the third direction DR3 may correspond to the thickness of the member.

[0063] In the specification, "in a plan view" may be defined as a state observed in the third direction DR3. In the specification, "in a cross-sectional view" may be defined as a state observed in the first direction DR1 or the second direction DR2. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be converted into different directions.

[0064] The display device ELD according to the embodiment may display an image IM through the active area AA-ED. The active area AA-ED may include a plane defined by the first direction DR1 and the second direction DR2. The active area AA-ED may also include a bent surface bent from at least one side of the plane defined by the first direction DR1 and the second direction DR2. The surface on which the image IM is displayed may correspond to the front surface of the display device ELD. The image IM may include both a moving image and a still image.

[0065] The peripheral area NAA-ED is adjacent to the active area AA-ED. The peripheral area NAA-ED may surround the active area AA-ED. Accordingly, the shape of the active area AA-ED may be substantially defined by the peripheral area NAA-ED. However, this is merely an example shown, and the peripheral area NAA-ED may be disposed adjacent to only one side of the active area AA-ED, or may be omitted. The display device ELD according to the embodiment may include active areas of various shapes, and is not limited to any one embodiment.

[0066] The display device ELD may have a rectangular shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 crossing the first direction DR1 in a plan view. However, the embodiment is not limited thereto, and the display device ELD may have various shapes in a plan view, such as a circular shape and other polygonal shapes.

[0067] The display device ELD may sense external input applied from the outside. The external input may include various forms of input such as force, pressure, temperature, light, and the like.

[0068] Reference Figures 1 to 3 , the display device ELD according to the embodiment may include a display module DM. The display module DM may be a component configured to generate an image and sense an input applied from the outside. The display module DM according to the embodiment may include a display panel DP and an input sensor ISP disposed on the display panel DP. The display module DM of the embodiment may also include an optical layer AF disposed on the input sensor ISP. The display panel DP according to the embodiment may include a thin film transistor manufactured by the manufacturing method of the transistor according to the embodiment.

[0069] The display device ELD of the embodiment may include a window module WM provided in an upper portion of the display module DM. The display device ELD may further include an electronic module EM, a power module PSM, a case EDC, and the like.

[0070] An active area AA and a peripheral area NAA may be defined in the display module DM according to the embodiment. The active area AA may be an area activated in response to an electrical signal. The peripheral area NAA may be an area located adjacent to at least one side of the active area AA.

[0071] The active area AA may correspond to Figure 1 The peripheral area NAA may be disposed to surround the active area AA. However, the embodiment is not limited thereto, and the peripheral area NAA may be disposed to surround the active area AA. Figure 2 Unlike those shown in the examples above, in an embodiment, a portion of the peripheral area NAA may be omitted. The peripheral area NAA may correspond to Figure 1 The peripheral area NAA-ED of the display device ELD shown in FIG.

[0072] The display module DM according to the embodiment may include a peripheral area NAA disposed on at least one side of the active area AA, and in the peripheral area NAA, a pad PD is disposed therein (see Figure 4 ) may also be referred to as a pad area. The pad area may be a part of the peripheral area NAA. In the pad area, a driving circuit, a driving line, or the like for driving the active area AA may be provided. The driving circuit, the driving line, or the like may be electrically connected to the thin film transistor manufactured by the manufacturing method of the transistor according to the embodiment.

[0073] The window module WM may be disposed on the display module DM to protect the display module DM from external impact or scratches. The window module WM may cover the entire outer side of the display module DM. The front surface of the window module WM may correspond to the upper surface of the display device ELD described above.

[0074] In an embodiment, the window module WM may include a base substrate WP. The base substrate WP may include an optically transparent insulating material. The base substrate WP may include at least one of a glass substrate and a synthetic resin film. The base substrate WP may have a single-layer structure or a multi-layer structure in which a plurality of films are coupled. The window module WM may further include a functional layer such as an anti-fingerprint layer, a phase control layer, or a hard coating layer disposed on the base substrate WP.

[0075] The window module WM may further include an adhesive layer AP. The base substrate WP and the display module DM may be coupled to each other through the adhesive layer AP. However, the embodiment is not limited thereto, and the adhesive layer AP may be omitted, and the window module WM may be directly disposed on the display module DM.

[0076] The window module WM may be divided into a transmissive portion TA and a frame portion BZA. The transmissive portion TA may be a portion corresponding to the active area AA of the display module DM, and the frame portion BZA may be a portion corresponding to the peripheral area NAA of the display module DM. The frame portion BZA may define the shape of the transmissive portion TA. The frame portion BZA may be adjacent to the transmissive portion TA and may surround the transmissive portion TA. However, the embodiments are not limited to what is shown, and the frame portion BZA may be disposed adjacent to only one side of the transmissive portion TA, or a portion of the frame portion BZA may be omitted.

[0077] The window module WM may further include a frame pattern BZP arranged to correspond to the frame portion BZA. The frame pattern BZP may be a color layer formed on one surface of the base substrate WP. The frame pattern BZP may include a material having a color. For example, the frame pattern BZP may include a colored organic film. The frame pattern BZP may have a single-layer or multi-layer structure. The frame portion BZA of the window module WM in which the frame pattern BZP is placed may have a lower light transmittance than the transmission portion TA.

[0078] The display module DM may further include a main circuit board MCB, a flexible circuit film FCB, a data driver, a sensor control circuit T-IC, and a main controller MC.

[0079] The main circuit board MCB may be electrically connected to the display module DM through a flexible circuit film FCB. The main circuit board MCB may be electrically connected to the electronic module EM through a connector.

[0080] The flexible circuit film FCB may be connected to each of the display panel DP and the input sensor ISP to connect the display panel DP and the input sensor ISP to the main circuit board MCB. The input sensor ISP may be electrically connected to the display panel DP to be electrically connected to the main circuit board MCB through the flexible circuit film FCB. However, the embodiment is not limited thereto, and the input sensor ISP may be electrically connected to the main circuit board MCB through an additional flexible circuit film, or the flexible circuit film FCB may be omitted and the main circuit board MCB may be directly connected to the display panel DP.

[0081] Each of the data driver, the sensor control circuit T-IC, and the main controller MC may be provided in the form of an integrated chip. The data driver may be mounted on the display module DM, and the sensor control circuit T-IC and the main controller MC may be mounted on the main circuit board MCB. However, the embodiment is not limited thereto. For example, the data driver may be mounted on a flexible circuit film FCB.

[0082] The main controller MC may control the overall operation of the display device ELD. For example, the main controller MC may control the operation of the display panel DP and the input sensor ISP. The main controller MC may control the operation of the electronic module EM. The main controller MC may include at least one microprocessor.

[0083] The data driver may include a driving circuit for driving pixels of the display panel DP. The data driver may receive image data and control signals from the main controller MC. For example, the control signal may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, a data enable signal, and the like.

[0084] The sensor control circuit T-IC may provide an electrical signal for driving the input sensor ISP to the input sensor ISP. The sensor control circuit T-IC may receive a control signal such as a clock signal from the main controller MC.

[0085] The electronic module EM may include various functional modules desired for driving the display device ELD. For example, the electronic module EM may include a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, and the like. The electronic module EM may be mounted on the main circuit board MCB, or may be electrically connected to the main circuit board MCB via a separate flexible circuit board.

[0086] The power module PSM may be electrically connected to the electronic module EM. The power module PSM may supply power desired for overall operation of the display device ELD. For example, the power module PSM may include a typical battery device.

[0087] The window module WM and the housing EDC may be coupled to each other to configure the appearance of the display device ELD. The window module WM and the housing EDC may be coupled to each other to form an internal space for accommodating components of the display device ELD. In the internal space, a display module DM, a flexible circuit film FCB, a main circuit board MCB, an electronic module EM, a power module PSM, and the like may be accommodated. A portion of the display module DM may be bent so that the flexible circuit film FCB and the main circuit board MCB face the rear surface of the display module DM and are stored in the housing EDC.

[0088] The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a frame and / or a plate composed of a combination of glass, plastic, or metal. The housing EDC may protect the display module DM and the like housed in the housing EDC by absorbing an impact applied from the outside or preventing foreign matter / moisture and the like from penetrating from the outside.

[0089] In the display device ELD of the embodiment, the display panel DP may be a component that substantially generates an image. The display panel DP may be a light-emitting display panel, and for example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, a quantum dot display panel, a micro LED display panel, or a nano LED display panel. The display panel DP may be referred to as a display layer.

[0090] Reference Figure 3 , the display panel DP may include a base layer BS, a circuit layer DP-CL, a display layer DP-ED and an encapsulation layer TFE.

[0091] The base layer BS may be a member that provides a base surface on which the circuit layer DP-CL is disposed. The base layer BS may be a rigid substrate, or a flexible substrate that can be bent, folded, curled, etc. The base layer BS may be a glass substrate, a metal substrate, a polymer substrate, or the like. However, the embodiment is not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0092] The base layer BS may have a multi-layer structure. For example, the base layer BS may include a first synthetic resin layer, an intermediate layer of a multi-layer or single-layer structure, and a second synthetic resin layer disposed on the intermediate layer. The intermediate layer may be referred to as a base barrier layer. The intermediate layer may include silicon oxide (SiO x ) layer and an amorphous silicon (a-Si) layer disposed above the silicon oxide layer, but the embodiment is not particularly limited thereto. For example, the intermediate layer may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an amorphous silicon layer.

[0093] Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin. Each of the first synthetic resin layer and the second synthetic resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a carbamate-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In the specification, a "~"-based resin means a functional group containing "~".

[0094] The circuit layer DP-CL may be disposed on the base layer BS. The circuit layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, and the like. An insulating layer, a semiconductor layer, and a conductive layer are formed on the base layer BS by coating, deposition, or a similar process, and thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by performing multiple photolithography processes. Thereafter, a semiconductor pattern, a conductive pattern, and a signal line included in the circuit layer DP-CL may be formed. The circuit layer DP-CL may include an inorganic insulating layer and an organic insulating layer as an insulating layer. At least one of the semiconductor patterns included in the circuit layer DP-CL may be manufactured by a manufacturing method of a transistor according to an embodiment.

[0095] The display layer DP-ED may be disposed on the circuit layer DP-CL. The display layer DP-ED may include a light emitting element. For example, the display layer DP-ED may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED or a nano LED. The light emitting element of the display layer DP-ED may be electrically connected to a driving element of the circuit layer DP-CL to display an image by generating light in response to a signal provided by the driving element.

[0096] The encapsulation layer TFE may be disposed on the display layer DP-ED. The encapsulation layer TFE may protect the display layer DP-ED from foreign substances such as moisture, oxygen, and dust particles. The encapsulation layer TFE may seal the light emitting element of the display layer DP-ED. The encapsulation layer TFE may include at least one thin film for improving the optical efficiency of the display layer DP-ED or protecting the display layer DP-ED.

[0097] The input sensor ISP may be provided on the display panel DP. The input sensor ISP may sense an external input applied from the outside. The external input may be a user input. The user input may include various forms of external inputs, such as a part of the user's body, light, heat, a pen, pressure, or the like. The input sensor ISP may sense the external input and provide an input signal including information about the external input so that the display panel DP can generate an image IM corresponding to the external input. The input sensor ISP may be driven in various ways such as a capacitive manner, a resistive film manner, an infrared light manner, a sound wave manner, or a pressure manner, but is not limited to any one of them. In an embodiment, the input sensor ISP is described as being driven in a capacitive manner.

[0098] The input sensor ISP may be formed on the display panel DP by a continuous process. The input sensor ISP may be described as being directly disposed on the display panel DP. Directly disposed may mean that a third element is not disposed between the input sensor ISP and the display panel DP. For example, a separate adhesive member may not be disposed between the input sensor ISP and the display panel DP.

[0099] The optical layer AF may be provided on the input sensor ISP. The optical layer AF may be a reflection reducing layer that reduces the reflectivity of external light incident from the outside of the display module DM. The optical layer AF may be formed on the input sensor ISP by a continuous process. For example, the optical layer AF may include a polarizing film having a phase retarder and / or a polarizer, a multilayer reflective layer that destructively interferes with the reflected light, or a color filter arranged to correspond to the pixel arrangement and emission color of the display panel DP. For example, in the case where the optical layer AF includes a color filter, the color filter may be arranged in consideration of the emission color of the pixels included in the display panel DP. In an embodiment, the optical layer AF may be omitted.

[0100] Figure 4 is a schematic plan view of a display panel DP according to an embodiment. Figure 4In the display panel DP, a display area DA and a non-display area NDA around the display area DA may be defined. The display area DA and the non-display area NDA may be distinguished by whether pixels PX are disposed therein. The pixels PX may be disposed in the display area DA, and the pixels PX may not be disposed in the non-display area NDA. In the non-display area NDA, a scan driver SDV, a data driver, and a light emitting driver EDV may be disposed. The data driver may be a part of a circuit configured in a driver chip DIC.

[0101] The display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, data lines DL1 to DLn, first and second control lines CSL1 and CSL2, driving voltage lines PL, a scan driver SDV, a data driver, an emission driver EDV, a driving chip DIC, and pads PD. Here, m and n may be natural numbers of 2 or more.

[0102] The pixels PX may be connected to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0103] Initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, and black scan lines GBL1 to GBLm may extend in a first direction DR1 to be electrically connected to a scan driver SDV. Data lines DL1 to DLn may extend in a second direction DR2 to be electrically connected to a drive chip DIC. Light emission control lines ECL1 to ECLm may extend in a first direction DR1 to be electrically connected to a light emission driver EDV.

[0104] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be disposed at different layers. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0105] The first control line CSL1 may be connected to the scan driver SDV. The second control line CSL2 may be connected to the light emitting driver EDV.

[0106] The driving chip DIC, the driving voltage line PL, the first control line CSL1 and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a pad for connecting the flexible circuit film FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX via the driving voltage line PL, the first control line CSL1 and the second control line CSL2.

[0107] Figure 5 is a schematic diagram of an equivalent circuit of a pixel PXij according to an embodiment.

[0108] Figure 5 The pixel PX (see Figure 4 ) is an equivalent circuit of a pixel PXij among the pixels PX. Since each of the pixels PX may have the same circuit structure, by providing a description of the circuit structure of the pixel PXij, a detailed description of the rest of the pixels PX will be omitted.

[0109] Reference Figure 4 and Figure 5 , the pixel PXij may be connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1 to ECLm, the first and second drive voltage lines VL1 and VL2, and the first and second initialization voltage lines VL3 and VL4. Here, i may be an integer from 1 to n, and j may be an integer from 1 to m.

[0110] The pixel PXij may include a light emitting element LD and a pixel circuit PDC. The light emitting element LD may be a light emitting diode. As an example, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer, but the embodiment is not limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element LD in response to the data signal Di. The light emitting element LD may emit light at a predetermined or selected brightness corresponding to the amount of current provided from the pixel circuit PDC.

[0111] The pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. However, the configuration of the pixel circuit PDC is not limited to Figure 5 The embodiment shown in . Figure 5 The pixel circuit PDC shown in FIG. 1 is only an example, and the configuration of the pixel circuit PDC may be modified and implemented.

[0112] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor including a polysilicon layer. In an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be manufactured by the transistor manufacturing method of the embodiment, and at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a polysilicon layer including argon (Ar).

[0113] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be a transistor having a low temperature polysilicon (LTPS) semiconductor layer. The polysilicon layer may be crystallized by providing an excimer laser to the amorphous silicon layer.

[0114] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 are oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0115] Specifically, the first transistor T1 that directly affects the brightness of the light-emitting element LD can be configured to include a semiconductor layer made of polycrystalline silicon (which may be referred to as polycrystalline silicon) with high reliability, by which a high-resolution display device can be implemented. Since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not large even when the driving time is long. For example, since there is no significant change in the color of the image due to the voltage drop even during low-frequency driving, low-frequency driving is possible. Since oxide semiconductors have the advantage of low leakage current as described above, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be used as an oxide semiconductor to prevent leakage current that may flow into the gate electrode and reduce power consumption at the same time.

[0116] Some of the first to seventh transistors T1 to T7 may be P-type transistors, and the others may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each be a P-type transistor, and the third transistor T3 and the fourth transistor T4 may each be an N-type transistor.

[0117] The configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 5 The embodiment shown in . Figure 5 The pixel circuit PDC shown in is only an example, and the configuration of the pixel circuit PDC may be modified and implemented. For example, all of the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. In another embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may each be a P-type transistor, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may each be an N-type transistor.

[0118] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a signal similar to that input to the display device ELD (see Figure 1 )’s image signal corresponding to the voltage level.

[0119] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. The first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0120] The first transistor T1 may be connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the light emitting element LD. The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or, referred to as an anode) of the light emitting element LD via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 may receive a data signal Di transmitted by the i-th data line DLi and supply a driving current to the light emitting element LD according to a switching operation of the second transistor T2.

[0121] The second transistor T2 may be connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 may be turned on in response to the j-th write scan signal GWj received through the j-th write scan line GWLj and transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst may be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst may be connected to the first node N1.

[0122] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the jth compensation scan line GCLj. The third transistor T3 may be turned on in response to the jth compensation scan signal GCj received through the jth compensation scan line GCLj, and may diode-connect the first transistor T1 by connecting the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other. One end of the third capacitor Nbst may be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst may be connected to the first node N1.

[0123] The fourth transistor T4 may be connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line GILj. The fourth transistor T4 may be turned on in response to the jth initialization scan signal GIj received through the jth initialization scan line GILj. The turned-on fourth transistor T4 may transmit the first initialization voltage VINT to the first node N1 and initialize the potential of the third electrode of the first transistor T1 (e.g., the potential of the first node N1).

[0124] The fifth transistor T5 may include a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light emitting element LD via the second node N2, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj.

[0125] The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on in response to the jth emission control signal EMj received through the jth emission control line ECLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be compensated by the diode-connected first transistor T1 and transmitted to the light emitting element LD through the sixth transistor T6.

[0126] The seventh transistor T7 may include a first electrode connected to a second initialization voltage line VL4 to which a second initialization voltage VAINT is transmitted, a second electrode connected to a second electrode of the sixth transistor T6 via a second node N2, and a third electrode (e.g., a gate electrode) connected to a j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to a voltage level of the first initialization voltage VINT.

[0127] One end of the first capacitor Cst may be connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst may be connected to the first driving voltage line VL1. The cathode of the light emitting element LD may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0128] Fig. 6A is a schematic cross-sectional view of a portion of a display module DM according to an embodiment. Fig. 6A A pixel PX is provided therein (see Figure 4 ) in a portion of the light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA.

[0129] Figure 6B is a schematic cross-sectional view showing a portion of a transistor TR according to the embodiment. Figure 6B It is shown Fig. 6A A cross-sectional view of an enlarged area XX'.

[0130] The display module DM may include a display panel DP and an input sensor ISP, and the display panel DP may include a base layer BS, a circuit layer DP-CL, a display layer DP-ED, and an encapsulation layer TFE. Figure 4 ) may have an equivalent circuit including a transistor, a capacitor, and a light-emitting element, and the equivalent circuit diagram of a pixel may be modified into various forms. Fig. 6A The pixel PX (see Figure 4 ) in the transistor TR and the light emitting element LD.

[0131] The display panel DP according to the embodiment may include an insulating layer, a transistor, a conductive pattern, a signal line, and the like.

[0132] The inorganic film, the organic film, the semiconductor layer and the conductive layer may be formed by coating, deposition or the like. Thereafter, the inorganic film, the organic film, the semiconductor layer and the conductive layer may be selectively patterned by photolithography. In this way, a circuit layer DP-CL including an insulating layer formed from an inorganic film and an organic film, a transistor including a semiconductor pattern formed from a semiconductor layer, and a conductive pattern and a signal line formed from a conductive layer may be formed.

[0133] Thereafter, a display layer DP-ED including a light emitting element LD including a conductive pattern and the like may be formed on the circuit layer DP-CL, and an encapsulation layer TFE covering the display layer DP-ED may be formed.

[0134] Reference Fig. 6A The circuit layer DP-CL may include a shielding electrode BML, a buffer layer BFL, insulating layers IOL1, IOL2, IOL3 and IOL4 each including an inorganic film and insulating layers OML1 and OML2 each including an organic film, a transistor TR, connection electrodes CNE1, CNE2 and a signal line SCL, etc.

[0135] The shielding electrode BML may be disposed on the base layer BS. The shielding electrode BML may overlap the transistor TR. In an embodiment, the shielding electrode BML may also be disposed in a lower portion of the signal line SCL. The shielding electrode BML may block light incident from the lower portion of the display panel DP to the transistor TR or the signal line SCL so as to protect semiconductor patterns or conductive patterns such as the transistor TR and the signal line SCL. The shielding electrode BML may include a conductive material. In an embodiment, the shielding electrode BML may be connected to a driving voltage line PL (see Figure 4 ) to be applied with a voltage. When a voltage is applied to the shielding electrode BML, a threshold voltage of the transistor TR disposed on the shielding electrode BML may be maintained. However, the embodiment is not limited thereto, and the shielding electrode BML may be a floating electrode. In an embodiment, the shielding electrode BML may be omitted.

[0136] The buffer layer BFL may be disposed on the base layer BS to cover the shielding electrode BML. The buffer layer BFL may improve the coupling force between the semiconductor pattern or the conductive pattern disposed on the buffer layer BFL and the base layer BS. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BS into the semiconductor pattern or the conductive pattern.

[0137] The buffer layer BFL may be an inorganic film. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked with each other.

[0138] The transistor TR may include a source SE, a channel AC, a drain DE, and a gate GT. The source SE, the channel AC, and the drain DE of the transistor TR may constitute a semiconductor pattern SP.

[0139] In an embodiment, the semiconductor pattern SP of the transistor TR may include polycrystalline silicon (p-Si). The semiconductor pattern SP of the transistor TR may be a polycrystalline silicon layer including polycrystalline silicon. In an embodiment, the semiconductor pattern SP may be a polycrystalline silicon layer including crystals crystallized from amorphous silicon (also referred to as amorphous silicon (a-Si)). The source SE, the channel AC, the drain DE, and the like formed as the semiconductor pattern SP may be a polycrystalline silicon layer.

[0140] In an embodiment, the semiconductor pattern SP may include argon (Ar). Figure 6B , argon (Ar) may be included near the upper surface of the semiconductor pattern SP. For example, in an embodiment, argon (Ar) may be included near the first insulating layer IOL1. However, the embodiment is not limited thereto, and in an embodiment, the distribution of argon (Ar) included in the transistor TR may be random.

[0141] In cross section, the source SE and the drain DE of the transistor TR may extend in opposite directions from the channel AC. Fig. 6A A portion of a signal line SCL formed of a semiconductor pattern is shown. Although not separately shown, the signal line SCL may be connected to a drain DE of the transistor TR.

[0142] The semiconductor pattern may include a plurality of regions distinguished according to the size of the conductivity. In the semiconductor pattern, a region doped with a dopant or a region in which a metal oxide is reduced may have a high conductivity and may substantially serve as a source electrode and a drain electrode of the transistor TR. In the semiconductor pattern, a region having a high conductivity may correspond to a source electrode SE and a drain electrode DE of the transistor TR. A region that is not doped or doped to a low concentration, or has a low conductivity due to non-reduction of the metal oxide, may correspond to a channel AC (or an active portion) of the transistor TR.

[0143] The first insulating layer IOL1 may be disposed on the buffer layer BFL while covering the semiconductor pattern of the transistor TR. The first insulating layer IOL1 may be referred to as a gate insulating layer. The gate GT of the transistor TR may be disposed on the first insulating layer IOL1. The gate GT may overlap the semiconductor pattern SP via the first insulating layer IOL1 as a gate insulating layer disposed between the gate GT and the semiconductor pattern SP. The gate GT may overlap the channel AC of the transistor TR. In an embodiment, the gate GT may be used as a mask in a process of doping the semiconductor pattern of the transistor TR.

[0144] The gate GT may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), or the like, but is not particularly limited thereto.

[0145] The first insulating layer 101 may include an inorganic film. The first insulating layer 101 may also be referred to as a first inorganic film. For example, the first insulating layer 101 may be an inorganic film including at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer 101 may have a single-layer or multi-layer structure. The first insulating layer 101 may have a structure in which inorganic films are stacked on each other.

[0146] In an embodiment, the first insulating layer IOL1 may include an organic film in addition to the inorganic film. In the case where the first insulating layer IOL1 includes a structure in which the inorganic film and the organic film are stacked on each other, the first insulating layer IOL1 may further include a buffer inorganic film disposed between the inorganic film and the organic film adjacent to each other.

[0147] The multilayer structure described with reference to the first insulating layer IOL1 can also be introduced into the second insulating layer IOL2, the third insulating layer IOL3 and the fourth insulating layer IOL4 to be described below. Accordingly, the stacking structure of the insulating layers of the above-mentioned multilayer structure, the configuration of the buffer inorganic film in the multilayer structure and the like can be equally applied to the second insulating layer IOL2, the third insulating layer IOL3 and the fourth insulating layer IOL4.

[0148] The second insulating layer IOL2 may be disposed on the first insulating layer IOL1 and may cover the gate GT. The second insulating layer IOL2 may overlap with the pixel in common. The second insulating layer IOL2 may include an inorganic film. The second insulating layer IOL2 may also be referred to as a second inorganic film. For example, the second insulating layer IOL2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating layer IOL2 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In an embodiment, the second insulating layer IOL2 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0149] The third insulating layer IOL3 may be disposed on the second insulating layer IOL2. The third insulating layer IOL3 may include an inorganic film. The third insulating layer IOL3 may also be referred to as a third inorganic film. The third insulating layer IOL3 may have a single-layer or multi-layer structure. For example, the third insulating layer IOL3 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0150] The first connection electrode CNE1 may be disposed on the third insulating layer IOL3. The first connection electrode CNE1 may be connected to the signal line SCL via a first contact hole CH-1 passing through the first insulating layer IOL1, the second insulating layer IOL2, and the third insulating layer IOL3.

[0151] The fourth insulating layer IOL4 may be disposed on the third insulating layer IOL3. The fourth insulating layer IOL4 may include an inorganic film, and the fourth insulating layer IOL4 may also be referred to as a fourth inorganic film. The fourth insulating layer IOL4 may be a single silicon oxide layer.

[0152] The fifth insulating layer OML1 may be disposed on the fourth insulating layer IOL4. The fifth insulating layer OML1 may include an organic film. The fifth insulating layer OML1 may be referred to as a first organic film. The first organic film may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin.

[0153] The second link electrode CNE2 may be disposed on the fifth insulating layer OML1. The second link electrode CNE2 may be connected to the first link electrode CNE1 via a second contact hole CH-2 passing through the fourth insulating layer IOL4 and the fifth insulating layer OML1.

[0154] The sixth insulating layer OML2 may be disposed on the fifth insulating layer OML1 and may cover the second connection electrode CNE2. The sixth insulating layer OML2 may include an organic film. The sixth insulating layer OML2 may be referred to as a second organic film. The second organic film may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin.

[0155] Although in Fig. 6A Although not shown in the figure, the circuit layer may further include a plurality of transistors, and may further include a plurality of signal lines electrically connected to the plurality of transistors. The plurality of signal lines may extend and be connected to the pads PD of the non-display area NDA (see Figure 4 ).

[0156] The display layer DP-ED may be disposed on the circuit layer DP-CL. The display layer DP-ED may include a pixel defining layer PDL and a light emitting element LD. The light emitting element LD may include a first electrode AE, a light emitting layer EL, and a second electrode CE.

[0157] The first electrode AE ​​may be disposed on the sixth insulating layer OML2. The first electrode AE ​​may be connected to the second connection electrode CNE2 via the third contact hole CH-3 passing through the sixth insulating layer OML2. The first electrode AE ​​may be electrically connected to the drain DE of the transistor TR via the first and second connection electrodes CNE1 and CNE2.

[0158] The first electrode AE ​​may be referred to as a pixel electrode. The first electrode AE ​​may be formed of a metal material, a metal alloy, or a conductive compound. The first electrode AE ​​may be an anode or a cathode. The first electrode AE ​​may be a transmissive electrode, a transflective electrode, or a reflective electrode. In the case where the first electrode AE ​​is a transmissive electrode, the first electrode AE ​​may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. In the case where the first electrode AE ​​is a transflective electrode or a reflective electrode, the first electrode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The first electrode AE ​​may also be a double-layer structure including a compound of the above-mentioned metal materials, such as LiF / Ca or LiF / Al. In another embodiment, the first electrode AE ​​may have a multilayer structure including a reflective film or a transflective film formed of the above-mentioned material, and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or the like. For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO. The embodiment is not limited thereto, and the first electrode AE ​​may include any one of the above-mentioned metal materials, a combination of two or more selected from the above-mentioned metal materials, an oxide of any one of the above-mentioned metal materials, or the like.

[0159] The pixel defining layer PDL may be disposed on the sixth insulating layer OML2. In an embodiment, the pixel defining layer PDL may be formed of a polymer resin. For example, the pixel defining layer PDL may be formed by including a polyacrylate-based resin or a polyimide-based resin. In addition to the polymer resin, the pixel defining layer PDL may be formed by also including an inorganic substance. The pixel defining layer PDL may be formed by including a light absorbing material, or may be formed by including a black pigment or a black dye. A black pixel defining layer may be realized by forming a pixel defining layer PDL including a black pigment or a black dye. In the case of forming the pixel defining layer PDL, carbon black and the like may be used as the black pigment or the black dye, but the embodiment is not limited thereto.

[0160] The pixel defining layer PDL may be formed of an inorganic material. For example, the pixel defining layer PDL may be formed by including silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0161] A pixel opening PX-OP exposing a portion of the first electrode AE ​​may be defined on the pixel defining layer PDL. In the display module DM of the embodiment, the light-emitting area PXA may be distinguished by the pixel defining layer PDL. The display module DM may include the light-emitting area PXA and the non-light-emitting area NPXA, and the non-light-emitting area NPXA may be a portion overlapping with the pixel defining layer PDL. In the pixel opening PX-OP, a portion corresponding to the exposed first electrode AE ​​may be defined as the light-emitting area PXA.

[0162] In the light emitting element LD, the light emitting layer EL may be disposed on the first electrode AE. In an embodiment, the light emitting layer EL may emit light of at least one color of blue, red, and green. In an embodiment, the light emitting layer EL may be disposed over the entire display area DA (see Figure 4 ) provides blue light.

[0163] The second electrode CE may be disposed on the light emitting layer EL. The second electrode CE may have a single body shape and may be commonly disposed in the pixel PX (see Figure 4 ). The second electrode CE may be referred to as a common electrode. The second electrode CE may be a cathode or an anode. For example, when the first electrode AE ​​is an anode, the second electrode CE may be a cathode, and when the first electrode AE ​​is a cathode, the second electrode CE may be an anode.

[0164] The second electrode CE may be a transmissive electrode, a transflective electrode or a reflective electrode. In the case where the second electrode CE is a transmissive electrode, the second electrode CE may be formed of a transparent metal oxide (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or the like). The second electrode CE may be formed by including Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The first electrode AE ​​may also be a double-layer structure including a compound of the above-mentioned metal materials, such as LiF / Ca or LiF / Al.

[0165] Although not shown, the hole control layer may be disposed between the first electrode AE ​​and the light emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. The electron control layer may be disposed between the light emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer may be commonly formed in the pixel PX (see FIG. 1 ) using an open mask. Figure 4 )middle.

[0166] The encapsulation layer TFE may be disposed on the display layer DP-ED. The encapsulation layer TFE may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked on each other. However, the layers constituting the encapsulation layer TFE are not limited thereto.

[0167] The inorganic layers IL1 and IL2 may protect the display layer DP-ED from moisture and oxygen, and the organic layer OL may protect the display layer DP-ED from foreign substances such as dust particles. The inorganic layers IL1 and IL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic layer OL may include an acrylic organic material. However, the types of materials constituting the inorganic layers IL1 and IL2 and the organic layer OL are not limited thereto.

[0168] The input sensor ISP may be disposed on the packaging layer TFE. In an embodiment, the input sensor ISP may include a sensor insulating layer ISL and a sensor conductive layer MTL. The sensor insulating layer ISL may include a sensor base layer ISL-B and interlayer insulating layers ISL-C and ISL-T.

[0169] exist Fig. 6A, the input sensor ISP is shown as a multilayer structure including a first sensor conductive layer MTL1 and a second sensor conductive layer MTL2. The second sensor conductive layer MTL2 may be connected to the first sensor conductive layer MTL1 via a contact hole CNT. However, the embodiment is not limited thereto, and the input sensor ISP may include a single-layer sensor conductive layer. At least one of the interlayer insulating layers ISL-C and ISL-T may be omitted.

[0170] In an embodiment, the sensor base layer ISL-B may be directly disposed on the encapsulation layer TFE. For example, the sensor base layer ISL-B may be directly disposed on the second inorganic layer IL2 of the encapsulation layer TFE.

[0171] Reference Fig. 6A , the display module DM according to the embodiment may include an optical layer AF. In the embodiment, the optical layer AF may be directly disposed on the interlayer insulating layer ISL-T. However, the embodiment is not limited thereto, and an adhesive layer and the like may be further included between the optical layer AF and the input sensor ISP. The optical layer AF may be a reflection reduction layer that reduces external light. In the embodiment, the optical layer AF may be omitted.

[0172] The transistor TR included in the display module DM described above can be manufactured by the transistor manufacturing method of the embodiment. The transistor TR manufactured by the transistor manufacturing method according to the embodiment exhibits excellent mobility and reliability properties, and can improve the reliability and display quality of the display device according to the embodiment including the transistor.

[0173] Figure 7 is a flow chart of a method for manufacturing a transistor according to an embodiment. FIG. 8A to FIG. 8G Each is a schematic diagram illustrating the operation of the method of manufacturing the transistor according to the embodiment.

[0174] Reference Figures 7 to 8G The manufacturing method of the transistor of the embodiment may include: providing a preliminary polysilicon layer (S200); providing a sacrificial layer on the upper surface of the preliminary polysilicon layer (S300); providing argon (Ar) ions to dope the sacrificial layer and the preliminary polysilicon layer (S400); providing an etchant to the upper portion of the sacrificial layer (S500); and removing the sacrificial layer and etching the protrusion to form a polysilicon layer (S600). The preliminary polysilicon layer may be formed in an operation of performing crystallization by providing an excimer laser to the amorphous silicon layer. Therefore, the manufacturing method of the transistor of the embodiment may include: before the operation of providing the preliminary polysilicon layer (S200), performing an operation of crystallization (S100) by providing an excimer laser to the amorphous silicon layer.

[0175] The operation of performing crystallization (S100) by providing an excimer laser to the amorphous silicon layer may correspond to an excimer laser annealing (ELA) process operation. Amorphous silicon may be crystallized by heat provided from laser energy in the ELA process operation.

[0176] In the specification, the preliminary polysilicon layer may include polysilicon and refers to the state of the layer after the amorphous silicon layer is crystallized. The preliminary polysilicon layer is described as being distinguished from the polysilicon layer, and the preliminary polysilicon layer may correspond to the polysilicon layer before the operation of providing the etchant, and may be different in surface properties from the polysilicon layer formed by surface treatment with the etchant. For example, in the specification, the preliminary polysilicon layer may refer to the state before the protrusion on the surface is etched. The preliminary polysilicon layer and the polysilicon layer may have the same crystallization properties, other physical properties, and similar properties.

[0177] exist Fig. 8A 200. The operation of providing the preliminary polysilicon layer P-PT (S200) is shown in FIG. The protrusion EP may be disposed on the upper surface US-PSL of the preliminary polysilicon layer P-PT. The protrusion EP may be a portion formed by protruding from the upper surface US-PSL. In the preliminary polysilicon layer P-PT, the base portion BP may be a silicon layer including crystals.

[0178] exist Fig. 8A In the embodiment of the present invention, the protrusions EP are shown to be formed in a similar shape and a similar size and arranged at regular intervals, but the embodiment is not limited thereto. The protrusions EP may each have a random shape, a random size, and a random arrangement property. The protrusions EP may be generated in an operation of performing crystallization (S100) by providing an excimer laser to the amorphous silicon layer. The protrusions EP may be generated during a phase change operation of silicon in an operation of performing crystallization by providing an excimer laser to the amorphous silicon layer. For example, the protrusions EP may be generated in a portion corresponding to a boundary between formed crystals.

[0179] Fig. 10A is a schematic diagram showing a plane image of a preliminary polysilicon layer P-PT according to an embodiment. Fig. 10A An image of the preliminary polysilicon layer P-PT taken with a scanning electron microscope (SEM) is shown. Fig. 10A In the image of , the relatively bright portion may correspond to the protrusion EP, and the relatively dark and flat portion may correspond to the base portion BP. Fig. 10A Corresponds to Fig. 8A A plan image of the preliminary polysilicon layer P-PT is shown in FIG.

[0180] Reference Fig. 10A In an image of FIG. 1 , the protrusion EP may be randomly generated and may be formed at a boundary between crystals formed with the base portion BP which may correspond to a relatively flat plane.

[0181] The protrusion EP formed by the protrusion may deteriorate the properties of transistors and the like including the polysilicon layer. The surface of the polysilicon layer becomes uneven due to the protrusion EP, which leads to an increase in surface roughness, and accordingly, there may be a problem that the reliability of the transistor formed by including the polysilicon layer may be deteriorated and electrical properties such as low-frequency properties may be deteriorated. Accordingly, it is desirable to effectively remove the protrusion EP while minimizing the influence on the base portion BP.

[0182] Figure 8B 2 is a view illustrating an operation of providing a sacrificial layer on an upper surface of a preliminary polysilicon layer (S300). The sacrificial layer SL may be provided on the preliminary polysilicon layer P-PT having the protrusion EP formed thereon.

[0183] The sacrificial layer SL may include silicon oxide (SiO x For example, the sacrificial layer SL may include silicon dioxide (SiO 2 ) to form.

[0184] The sacrificial layer SL may be provided with a thickness sufficient to cover the protrusion EP. The average thickness t of the sacrificial layer SL is SL Can be about to about For example, the average thickness of the sacrificial layer SL is SL Can be about The average thickness may correspond to an average value of the thickness of the sacrificial layer SL provided on the base portion BP of the preliminary polysilicon layer P-PT and the thickness of the entire sacrificial layer SL provided on the protrusion EP.

[0185] The average thickness of the sacrificial layer SL is t SL Less than In the case of an average thickness t of the sacrificial layer SL, the coating uniformity of the sacrificial layer SL may not be ensured, and thus the etching quality may be deteriorated during a subsequent etching process using an etchant. SL Greater than In this case, there may be a problem of deterioration of processability such as an increase in tracking time.

[0186] Figure 8C 1 is a view showing an operation of providing argon ions to dope the sacrificial layer and the preliminary polysilicon layer (S400). Argon (Ar) ions may be provided from an upper portion of the sacrificial layer SL. The sacrificial layer SL and the preliminary polysilicon layer P-PT may be doped with the provided argon (Ar) ions. In the preliminary polysilicon layer P-PT, the protrusion EP (see Figure 8B ) portion may be doped. Argon is an inert ion that can minimize changes in properties of the doping element even after doping.

[0187] The operation of providing argon ions to dope the sacrificial layer and the preliminary polysilicon layer (S400) may be performed using an ion implantation device. The operation of providing argon ions to dope the sacrificial layer and the preliminary polysilicon layer (S400) may include providing argon ions by optimizing an acceleration voltage and a dose in the ion implantation device. The acceleration voltage and dose corresponding to the doping conditions may vary according to the thickness of the provided sacrificial layer SL, the thickness of the generated protrusion EP, and the like.

[0188] In an embodiment, the sacrificial layer SL is provided to be approximately to about In the case of a thickness of , argon ions can be provided to the preliminary polysilicon layer P-PT using an ion implantation device with an acceleration voltage of about 5 keV to about 80 keV and a dose of about 1.0E15 to about 1.0E20 in the operation of providing argon ions to dope the sacrificial layer and the preliminary polysilicon layer (S400).

[0189] Argon has a relatively large atomic weight among inert ions, so that in the case of using argon ions, damage may propagate in a region adjacent to the provided surface compared to the case of doping with ions having a relatively small atomic weight. Accordingly, in the case of argon ions, shallow doping may occur in a region adjacent to the surface in which doping is achieved or in a protruding portion.

[0190] The atomic weight of argon is about 38, and compared to doping performed using, for example, boron (B) (whose atomic weight is about 10.8) or phosphorus (P) (whose atomic weight is about 30.9) having an atomic weight smaller than argon, argon doping promotes energy transfer in the lateral direction in a region closer to the surface or a region adjacent to a portion where the provided ions reach.

[0191] Accordingly, argon (Ar) may be doped on the sacrificial layer SL and the protrusion EP of the preliminary polysilicon layer P-PT. Argon may be doped in a portion adjacent to an upper surface of the base portion BP of the preliminary polysilicon layer P-PT.

[0192] FIG. 11A to FIG. 11D Each is a schematic diagram showing a simulation result of argon doping according to an embodiment. FIG. 11A to FIG. 11D The simulation results shown in are derived using a simulation program called Stopping and Range of Ions in Materials (SRIM).

[0193] FIG. 11A to FIG. 11D They are the results that can be derived by changing the accelerating voltage. FIG. 11A to FIG. 11D are the results of simulations that can be performed by adjusting the acceleration voltage to 10keV, 20keV, 30keV, and 40keV, respectively. The silicon dioxide layer can be used as a sacrificial layer SL (see Figure 8C ).

[0194] FIG. 11A to FIG. 11D The peak in the graph shown in may correspond to the doping amount of argon. FIG. 11A to FIG. 11D The doping amount of argon according to the thickness can be shown in FIG. FIG. 11A to FIG. 11D The upper surface of the sacrificial layer SL may correspond to the FIG. 1 is a diagram showing an increase in the doping amount of argon in thickness of a stacked structure of a preliminary polysilicon layer P-PT and a buffer layer BFL arranged in a downward direction. FIG. 11A to FIG. 11D The buffer layer BFL indicated as different regions in the figure may correspond to Fig. 6A Buffer layer BFL.

[0195] Reference FIG. 11A to FIG. 11D It can be seen that the doping amount of argon can increase with the increase of the acceleration voltage, and as the acceleration voltage increases, argon can be doped deeper in the thickness direction from the surface. For example, when the thickness of the sacrificial layer SL is about And when the acceleration voltage is about 20 keV or more, argon may be doped on the preliminary polysilicon layer P-PT. FIG. 11A to FIG. 11D , the thickness of the sacrificial layer SL is about And in the case where the acceleration voltage is about 20keV to about 40keV, the preliminary polysilicon layer P-PT may be sufficiently doped. Specifically, in the case where the acceleration voltage is about 30keV, the doping amount may be increased on the upper surface of the preliminary polysilicon layer P-PT.

[0196] For example, from FIG. 11A to FIG. 11D It can be seen from the simulation results that the argon doping process conditions should be adjusted according to the thickness of the sacrificial layer SL. For example, the acceleration voltage can be controlled according to the thickness of the sacrificial layer SL during argon doping to effectively dope the upper surface of the preliminary polysilicon layer.

[0197] exist Figure 8C , the preliminary polysilicon layer P-PT is shown as including a doped protrusion D-EP and a doped base portion D-BP, and including an undoped base portion ND-BP on the lower side of the doped base portion D-BP. However, this is only an example, and the embodiments of the present disclosure are not limited thereto. Argon may also be doped in the undoped base portion ND-BP indicated as a different region, and a portion of the undoped region may also be included in the portion indicated as the doped base portion D-BP.

[0198] Fig.8D FIG. 4 shows an example after the operation of providing an etchant to the upper portion of the sacrificial layer (S500). The sacrificial layer SL (see FIG. 4 ) may be doped with an etchant. Figure 8C ) is provided with an etchant ETH on the upper part.

[0199] In an embodiment, the etchant ETH may be an acidic solution. The etchant ETH may be a buffered oxide etchant (BOE). In an embodiment, the etchant ETH may include hydrogen fluoride (HF) and ammonium fluoride (NH 4 F) can be diluted and used with HF and NH 4 F.

[0200] A portion of the sacrificial layer SL and a portion of the preliminary polysilicon layer P-PT may be etched by the etchant ETH. In an embodiment, the sacrificial layer SL doped with argon and the doped protrusion D-EP may be etched by the etchant ETH.

[0201] Polysilicon doped with argon may have an increased etch rate compared to undoped polysilicon. Silicon oxide or the like used as a sacrificial layer may also have an increased etch rate during argon doping.

[0202] The rate of increase in etching rate due to argon doping may be greater in the case of polysilicon than in the case of silicon oxide. For example, in the case where the silicon oxide layer and the polysilicon layer are equally doped with argon, the ratio of the etching rate of the silicon oxide layer to the etching rate of the polysilicon layer may be reduced compared to before doping. Accordingly, the etching rate of the polysilicon layer may be increased due to argon doping compared to before doping.

[0203] In an embodiment, after argon doping, a ratio of an etching rate of the doped sacrificial layer to an etching rate of the doped preliminary polysilicon layer (sacrificial layer etching rate / preliminary polysilicon layer etching rate) may be less than about 5.0. For example, a ratio of an etching rate of the doped sacrificial layer to an etching rate of the doped preliminary polysilicon layer may be about 3.0 or less, but the embodiment is not limited thereto. The ratio of the etching rates may vary according to the doping conditions of argon, the thickness of the sacrificial layer, and the like.

[0204] Table 1 below shows a comparison of etching rates according to argon doping. In Table 1, the comparative example may correspond to a case where an etchant is provided to each of the sacrificial layer and the preliminary polysilicon layer, and the example may correspond to a case where an etchant is provided after each of the sacrificial layer and the preliminary polysilicon layer is doped with argon. The argon doping conditions in the example are an acceleration voltage of about 10 keV and a dose of about 1.0E16.

[0205] The etchant used in the comparative example and the example may correspond to hydrogen fluoride (HF) having a concentration of about 0.95% and ammonium fluoride (NH 2) having a concentration of about 10%. 4 In Table 1, the etch rate of the sacrificial layer and the etch rate of the preliminary polysilicon layer may correspond to the thickness etched in each layer for a predetermined or selected time. In Table 1, the etch rate ratio may correspond to the ratio of the etch rate of the sacrificial layer to the etch rate of the preliminary polysilicon layer (sacrificial layer etch rate / preliminary polysilicon layer etch rate).

[0206] [Table 1]

[0207]

[0208] Referring to Table 1, the etching rate of the example in which both the sacrificial layer and the polysilicon layer may be doped with argon may be increased compared to the comparative example. However, it can be seen that the etching rate ratio of the example doped with argon may be reduced compared to the comparative example in which etching is performed without argon doping.

[0209] For example, the degree of increase in etching rate due to argon doping may be greater in the preliminary polysilicon layer than in the sacrificial layer, and accordingly, the relative etching rate of the preliminary polysilicon layer of the example doped with argon may be increased compared to the comparative example. Accordingly, the protruding portion protruding in the example may be more easily etched than in the comparative example.

[0210] Fig.8D The sacrificial layer SL is shown in FIG. 1 , wherein the sacrificial layer SL is removed by the provided etchant ETH (see FIG. 1 ). Figure 8C ) and the remaining sacrificial layer region R-SL in which etching is being performed. After the sacrificial layer SL is partially removed by the etchant ETH (see Figure 8C ) and the upper portion EP-T of the doped protrusion D-EP is exposed, etching may start from the exposed upper portion EP-T. Referring to the results in Table 1, the doped protrusion D-EP portion may be etched at a faster rate than before doping, and accordingly, the doped protrusion D-EP portion may be selectively etched. For example, the base portion BP (see Figure 8B ) compared to the protruding doped protrusion D-EP portion, and accordingly, during etching, the base portion BP (see Figure 8B ) while minimizing the reduction in thickness and effectively reducing the protrusion EP (see Figure 8B ) thickness.

[0211] FIG. 8E to FIG. 8G An operation of removing the sacrificial layer and etching the protrusion to form a polysilicon layer ( S600 ) is shown. FIG. 8E to FIG. 8G Changes according to etching progress are sequentially shown.

[0212] Fig. 8E The thickness of the doped protrusion D-EPa is shown in FIG. Fig.8D The thickness of the doped protrusion D-EPa shown in FIG. 1 can be reduced and the thickness of the remaining sacrificial layer region R-SL can also be reduced. For example, as described with reference to Table 1, etc., as the etching rate of the doped preliminary polysilicon layer increases, the etching of the doped protrusion D-EPa can continue while the remaining sacrificial layer region R-SL still exists, thereby minimizing the base portion BP (see FIG. Figure 8B ) thickness variation.

[0213] Fig.8F It is shown that the remaining sacrificial layer region R-SL (see Fig. 8E ) and then the doped protrusion D-EPb is additionally etched. Fig.8F As shown in FIG. 1 , however, in addition to the doped protrusion D-EPb, a portion of the doped base portion D-BP may be additionally etched.

[0214] Figure 8G The final polysilicon layer PT is shown after the etching process. Fig. 9 is a schematic cross-sectional view showing a portion of a polysilicon layer PT according to an embodiment. Specifically, Fig. 9 Shows Figure 8G The enlarged area YY'.

[0215] Reference Figure 8G and Fig. 9 The polysilicon layer PT may include a protrusion region F-EP partially protruding from the upper surface US-PSL of the base portion BP. The protrusion region F-EP in the polysilicon layer PT may be formed by removing the protrusion EP in the preliminary polysilicon layer by etching (see Fig. 8A ) after the remainder.

[0216] and including from Fig. 8A Compared with the preliminary polysilicon layer P-PT of the protrusion EP protruding from the upper surface US-PSL shown in FIG, the surface roughness of the polysilicon layer PT including the protrusion area F-EP after the etching process can be significantly reduced. EP-P (See Fig. 8A ) compared to the thickness t of the protruding area F-EP EP-F Can be significantly reduced.

[0217] The surface roughness at the upper surface of the polysilicon layer PT may be less than about 10 nm.The surface roughness of the upper surface of the polysilicon layer PT may be a root mean square (RMS) value of the thickness of the protrusion region F-EP.

[0218] The surface roughness at the upper surface of the polysilicon layer PT may be less than about 50% of the surface roughness at the upper surface of the preliminary polysilicon layer P-PT. For example, in an embodiment, the surface roughness at the upper surface of the preliminary polysilicon layer P-PT may have an RMS value of about 11 nm to about 14 nm, and the surface roughness at the upper surface of the polysilicon layer PT may have an RMS value of about 2 nm to about 5 nm. However, the embodiment is not limited thereto, and the values ​​of the surface roughness of the polysilicon layer before and after etching may vary according to the thickness of the sacrificial layer, the doping amount of argon, and the like.

[0219] Fig. 10B is a schematic diagram showing a plan image of a polysilicon layer PT according to an embodiment. Fig. 10B Shown in Fig. 10A The conditions of the preliminary planar image of the polysilicon layer are the same as those of the image of the polysilicon layer PT taken with a scanning electron microscope (SEM). Fig. 10B In the image of , a relatively bright portion may correspond to a portion corresponding to a boundary of the crystal. The protrusion region F-EP may be positioned at the boundary of the crystal as a relatively bright portion. Fig. 10B In the figure, the relatively dark and flat portion may correspond to the base portion BP (see Figure 8G ).For example, Fig. 10B Corresponds to Figure 8G A plan image of the polysilicon layer PT shown in FIG.

[0220] Reference Fig. 10B From the image, we can see that the thickness of the protrusion EP part is Fig. 10A can be reduced compared to the image.

[0221] Return to reference Figure 8G and Fig. 9 The polysilicon layer PT may contain argon (Ar). The polysilicon layer PT may contain argon (Ar) near the upper surface US-PSL of the polysilicon layer PT.

[0222] Fig. 12A is a view showing a schematic cross-sectional image of a preliminary polysilicon layer according to an embodiment, and Fig. 12B is a view showing a schematic cross-sectional image of a polysilicon layer according to an embodiment. Fig. 12A and Fig. 12B is a transmission electron microscope (TEM) image. Fig. 12A and Fig. 12B The thickness of each section is indicated in the images shown in .

[0223] Reference Fig. 12A and Fig. 12B , the protrusion EP formed on the surface of the preliminary polysilicon layer P-PT may have a reduced thickness after the argon doping and etching processes, and thus may be changed into a flat state like the protrusion region F-EP.

[0224] Reference Fig. 12A , in the portion where the protrusion EP is formed, the thickness of the preliminary polysilicon layer P-PT is shown to be about And refer to Fig. 12B Even in the portion including the protruding portion region F-EP, the thickness of the polysilicon layer PT is shown to be about For example, see Fig. 12A and Fig. 12B, it can be seen that, in the case where etching is performed with an etchant after argon doping, the protrusion EP portion can be selectively etched, thereby improving the surface physical properties of the polysilicon layer.

[0225] Reference Figures 7 to 12B The manufacturing method of the transistor described may correspond to forming a semiconductor pattern SP of the transistor (see Fig. 6A ) operation. Figures 7 to 12B The transistor TR manufactured by the manufacturing method of the transistor described in Fig. 6A ) can exhibit excellent surface properties, high reliability and improved electrical properties.

[0226] For example, by referring to Figures 7 to 12B The transistor manufacturing method described herein may include manufacturing a polysilicon layer in Fig. 6A In the semiconductor pattern SP of the transistor TR shown in FIG. 1 , the argon (Ar) provided in the doping operation may be kept in contact with the upper surface US-PSL (see FIG. 1 ) of the semiconductor pattern SP. Figure 6B ) are adjacent.

[0227] The manufacturing method of the display device of the embodiment may correspond to the following steps: Figure 3 and Fig. 6A The manufacturing method of the display device ELD of the display module DM shown in the etc. Figures 3 to 9 The method for manufacturing the display device of the embodiment may include: providing a base layer BS; forming a circuit layer DP-CL; and providing a display layer DP-ED.

[0228] The operation of forming the circuit layer DP-CL may be an operation of providing the circuit layer DP-CL including the transistors TR and the insulating layers IOL1 to IOL4 , OML1 , and OML2 on the base layer BS. The display layer DP-ED may be provided on the circuit layer DP-CL.

[0229] The operation of forming the circuit layer DP-CL may include: forming an amorphous silicon layer on a base layer; crystallizing the amorphous silicon layer into a preliminary polycrystalline silicon layer; providing a sacrificial layer on the preliminary polycrystalline silicon layer; doping the sacrificial layer and the preliminary polycrystalline silicon layer with argon; providing an etchant on the doped sacrificial layer and the doped preliminary polycrystalline silicon layer; and removing the sacrificial layer and reducing the surface roughness of the preliminary polycrystalline silicon layer to form a polycrystalline silicon layer.

[0230] The operation of forming the circuit layer DP-CL may include the operation of the method of manufacturing the transistor according to the above-described embodiments.

[0231] The operation of crystallizing the amorphous silicon layer into the preliminary polysilicon layer may include providing an excimer laser to the amorphous silicon layer. The preliminary polysilicon layer P-PT may include a protrusion EP formed on an upper surface thereof.

[0232] In the operation of providing the sacrificial layer on the preliminary polysilicon layer, the sacrificial layer SL may be provided by covering the protrusion EP. The sacrificial layer SL may include silicon oxide. The average thickness of the provided sacrificial layer SL may be about to about

[0233] Argon ions may be provided from an upper portion of the sacrificial layer SL to the sacrificial layer SL and the preliminary polysilicon layer P-PT to dope the sacrificial layer SL and the preliminary polysilicon layer P-PT. The operation of doping the sacrificial layer and the preliminary polysilicon layer with argon may include: using an ion implantation device to provide argon ions with an acceleration voltage of about 5keV to about 80keV and a dose of about 1.0E15 to about 1.0E20.

[0234] The etchant provided in the operation of providing the etchant on the doped sacrificial layer and the doped preliminary polysilicon layer may be an acidic solution. The etchant provided may contain HF and NH 4 F.

[0235] After providing the etchant, the polysilicon layer PT may be formed by removing the sacrificial layer SL and etching the protrusion EP of the preliminary polysilicon layer P-PT. The thickness of the protrusion EP may be reduced in the operation of forming the polysilicon layer PT, thereby reducing the surface roughness of the polysilicon layer PT.

[0236] In the case of the method for manufacturing the display device of the embodiment, at least one of the transistors of the display device may include a polysilicon layer PT.

[0237] In the manufacturing method of the display device of the embodiment, the operation of forming the circuit layer may include a transistor manufacturing operation, including: providing a gate insulating layer IOL1 on the polysilicon layer, forming a gate GT overlapping the polysilicon layer on the gate insulating layer, and forming the polysilicon layer into a semiconductor pattern SP divided into a source SE, a channel AC and a drain DE.

[0238] In the display device manufactured by the manufacturing method of the display device of the embodiment, at least one of the plurality of transistors may include a polysilicon layer formed by performing an etching process after argon doping to reduce the thickness of the protrusion. For example, the manufacturing method of the display device according to the embodiment can provide a display device with improved reliability and improved display quality by allowing the polysilicon layer included in the transistor to have improved surface properties while maintaining excellent mobility properties and physical properties.

[0239] The manufacturing method of the transistor of the embodiment and the manufacturing method of the display device of the embodiment may include: providing argon ions from the upper portion of the sacrificial layer to dope the preliminary polysilicon layer on which the sacrificial layer and the protrusion are formed; providing an etchant to the upper portion of the doped sacrificial layer; and removing the sacrificial layer and etching the protrusion to form a polysilicon layer to reduce the thickness of the protrusion on the upper surface of the polysilicon layer, and thereby can exhibit improved surface properties while maintaining the excellent physical properties of the polysilicon layer.

[0240] The display device of the embodiment may include a transistor manufactured by the method for manufacturing a transistor of the embodiment, and thus may exhibit excellent transistor performance, and may exhibit improved display quality.

[0241] The method for manufacturing a transistor of an embodiment can provide a transistor with excellent properties by providing argon (Ar) ions in an upper portion of a sacrificial layer to dope the sacrificial layer and polysilicon, and providing an etchant to the upper portion of the doped sacrificial layer to effectively remove a protrusion in the upper portion of the polysilicon.

[0242] The manufacturing method of the display device of the embodiment can provide a display device with excellent reliability and display quality by providing argon (Ar) ions in the upper portion of the sacrificial layer during the operation of forming the circuit layer to dope the sacrificial layer and polysilicon, and forming a transistor including a polysilicon layer formed by providing an etchant to the upper portion of the doped sacrificial layer to effectively remove a protrusion in the upper portion of the polysilicon.

[0243] The display device of the embodiment may exhibit excellent reliability and display quality by including a transistor including a semiconductor pattern having excellent surface properties.

[0244] Embodiments have been disclosed herein, and although terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Accordingly, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a transistor, the method comprising: providing a preliminary polysilicon layer including an upper surface having a protrusion formed on the upper surface; providing a sacrificial layer on the upper surface of the preliminary polysilicon layer; providing argon ions in an upper portion of the sacrificial layer to dope the sacrificial layer and the preliminary polysilicon layer; providing an etchant to an upper portion of the doped sacrificial layer; as well as The sacrificial layer is removed and the protrusion is etched to form a polysilicon layer.

2. The method for manufacturing a transistor according to claim 1, wherein: The surface roughness of the upper surface of the polysilicon layer is less than 50% of the surface roughness of the upper surface of the preliminary polysilicon layer.

3. The method for manufacturing a transistor according to claim 1, wherein: The preliminary polysilicon layer is formed in an operation of performing crystallization by supplying excimer laser to the amorphous silicon layer.

4. The method for manufacturing a transistor according to claim 1, wherein: The sacrificial layer includes silicon oxide.

5. The method for manufacturing a transistor according to claim 4, wherein: The average thickness of the sacrificial layer is to within the range.

6. The method for manufacturing a transistor according to claim 5, wherein: Providing the argon ions comprises: The argon ions are provided in an ion implantation apparatus with an acceleration voltage in the range of 5 keV to 80 keV and a dose in the range of 1.0E15 to 1.0E20.

7. The method for manufacturing a transistor according to claim 1, wherein: The etchant is an acidic solution containing hydrogen fluoride and ammonium fluoride.

8. The method for manufacturing a transistor according to claim 1, wherein: A ratio of an etching rate of the doped sacrificial layer to an etching rate of the doped preliminary polysilicon layer is less than 5.

0.

9. A display device, comprising: Base layer; a circuit layer, the circuit layer being disposed on the base layer and comprising transistors and a plurality of insulating layers; as well as a display layer disposed on the circuit layer and including a light emitting element electrically connected to the transistor, Wherein, the transistor includes a polysilicon layer containing argon.

10. The display device according to claim 9, wherein: The transistor comprises: a semiconductor pattern, the semiconductor pattern comprising a source electrode, a channel electrode, and a drain electrode; and a gate, the gate being arranged to overlap with the semiconductor pattern, Wherein, the semiconductor pattern is the polysilicon layer containing the argon.

11. The display device according to claim 10, wherein: The circuit layer includes a gate insulating layer disposed between the semiconductor pattern and the gate. The gate is disposed on an upper side of the semiconductor pattern via the gate insulating layer disposed between the gate and the semiconductor pattern, and At least a portion of the semiconductor pattern adjacent to the gate insulating layer includes the argon.

12. The display device according to claim 9, wherein: The surface roughness of the polysilicon layer is 10 nm or less.

13. A method for manufacturing a display device, the method comprising: Provides a base layer; forming a circuit layer including a plurality of transistors and a plurality of insulating layers on the base layer; as well as providing a display layer on the circuit layer, Wherein, forming the circuit layer comprises: forming an amorphous silicon layer on the base layer; crystallizing the amorphous silicon layer into a preliminary polycrystalline silicon layer; providing a sacrificial layer on the preliminary polysilicon layer; doping the sacrificial layer and the preliminary polysilicon layer with argon; providing an etchant on the doped sacrificial layer and the doped preliminary polysilicon layer; and The sacrificial layer is removed and the surface roughness of the preliminary polysilicon layer is reduced to form a polysilicon layer.

14. The method for manufacturing a display device according to claim 13, wherein: At least one of the plurality of transistors includes the polysilicon layer.

15. The method for manufacturing a display device according to claim 14, wherein: Forming the circuit layer further includes: A transistor including the polysilicon layer is manufactured by: providing a gate insulating layer on the polysilicon layer; forming a gate on the gate insulating layer so as to overlap with the polysilicon layer; and The polysilicon layer is formed into a semiconductor pattern divided into a source, a channel, and a drain.

16. The method for manufacturing a display device according to claim 13, wherein: Crystallizing the amorphous silicon layer includes: Excimer laser is provided to the amorphous silicon layer.

17. The method for manufacturing a display device according to claim 13, wherein: The sacrificial layer includes silicon oxide.

18. The method for manufacturing a display device according to claim 17, wherein: The average thickness of the sacrificial layer is to within the range.

19. The method for manufacturing a display device according to claim 18, wherein: Doping the sacrificial layer comprises: Argon ions are provided in an ion implantation apparatus with an acceleration voltage in the range of 5 keV to 80 keV and a dose in the range of 1.0E15 to 1.0E20.

20. The method for manufacturing a display device according to claim 13, wherein: The etchant is an acidic solution containing hydrogen fluoride and ammonium fluoride.

Images