Display substrate and display device

Abstract

A display substrate and a display device relate to the technical field of display. The display substrate comprises a plurality of sub-pixels, and each sub-pixel comprises a thin film transistor. The display substrate comprises a substrate, a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer, the first conductive layer, the semiconductor layer, the first insulating layer and the second conductive layer are sequentially stacked on one side of the substrate, the first conductive layer is close to the substrate and comprises a data line, and the semiconductor layer comprises a plurality of semiconductor patterns located at different sub-pixels. The semiconductor pattern comprises a source electrode connection region, a first conductor region and a channel region which are arranged along a first direction and are connected in sequence, and the second conductive layer comprises a first switching pattern and a grid electrode; wherein the first insulating layer is provided with a first via hole, the first via hole exposes a part of the data line, the source electrode connecting area and the first conductor area, the data line and the source electrode connecting area are in lap joint with the first switching pattern through the first via hole, and the orthographic projection of the first switching pattern and the orthographic projection of the first conductor area on the substrate are not overlapped.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Electronic paper mostly uses electrophoresis display (EPD) technology as the display panel. Electronic paper display not only has the advantages of being comfortable to read, ultra-thin, light, and bendable, but also can refresh the displayed content and consumes less power than LCD displays. Summary of the invention

[0003] The present disclosure provides a display substrate, comprising a display area and a non-display area surrounding the display area, wherein the display area comprises a plurality of sub-pixels, and the sub-pixels comprise thin film transistors;

[0004] The display substrate comprises: a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer which are sequentially stacked, the first conductive layer being arranged close to the substrate, the first conductive layer comprising a data line, the semiconductor layer comprising a plurality of semiconductor patterns located in different sub-pixels, the semiconductor patterns comprising a source connection region, a first conductorization region and a channel region of the thin film transistor, the source connection region, the first conductorization region and the channel region being arranged along a first direction and sequentially connected, the second conductive layer comprising a first transfer pattern, a scan line and a gate of the thin film transistor;

[0005] A first via is provided on the first insulating layer, and the first via exposes a portion of the data line, the source connection area and the first conductor area. The data line and the source connection area are respectively overlapped with the first transfer pattern through the first via, and the first transfer pattern and the first conductor area have no overlap in their orthographic projection on the substrate.

[0006] In some embodiments, the semiconductor pattern further includes:

[0007] The second conductor region is connected between the first conductor region and the channel region, the thickness of the first conductor region is less than the thickness of the second conductor region, the thickness of the first conductor region is less than or equal to the thickness of the source connection region, and the thickness of the second conductor region is less than or equal to the thickness of the channel region.

[0008] In some embodiments, the semiconductor pattern further includes:

[0009] The drain connection region, the third conductor region and the fourth conductor region of the thin film transistor, the channel region, the fourth conductor region, the third conductor region and the drain connection region are arranged along the first direction and connected in sequence, and the thickness of the third conductor region is less than the thickness of the fourth conductor region;

[0010] The second conductive layer also includes a second transfer pattern, which is located on a side of the gate away from the first transfer pattern. A second via is also provided on the first insulating layer, and the second via exposes the drain connection area and the third conductor area. The second transfer pattern is overlapped with the drain connection area through the second via, and the orthographic projections of the second transfer pattern and the third conductor area on the substrate do not overlap.

[0011] In some embodiments, the sub-pixel further includes a common electrode and a first pixel electrode, the second transfer pattern overlaps with an orthographic projection of the common electrode on the substrate, and the second transfer pattern constitutes the first pixel electrode.

[0012] In some embodiments, the sub-pixel further includes a common electrode and a first pixel electrode, and the second transfer pattern has no overlap with an orthographic projection of the common electrode on the substrate;

[0013] The semiconductor pattern further includes: a fifth conductor region, located at a side of the drain connection region away from the channel region and connected to the drain connection region, the fifth conductor region overlaps with the positive projection of the common electrode on the substrate, and the fifth conductor region constitutes the first pixel electrode.

[0014] In some embodiments, the sub-pixel further includes a first common electrode, a first pixel electrode, a second common electrode, and a second pixel electrode, the first pixel electrode is located in the semiconductor layer or the second conductive layer, the first common electrode and the first pixel electrode are arranged in different layers and their orthographic projections on the substrate overlap, and the display substrate further includes:

[0015] a third conductive layer, disposed on a side of the second conductive layer away from the substrate, comprising the second common electrode; and

[0016] A transparent conductive layer is arranged on the side of the third conductive layer away from the substrate, including the second pixel electrode, the second pixel electrode and the second common electrode have overlapping positive projections on the substrate, the second pixel electrode is connected to the first pixel electrode through a via hole, and the first pixel electrode is also connected to the drain connection area of ​​the thin film transistor.

[0017] In some embodiments, the first pixel electrode includes a plurality of sub-electrodes, the plurality of sub-electrodes are arranged along a second direction and connected in sequence, the second direction intersects with the first direction, and different sub-electrodes have different widths along the first direction.

[0018] In some embodiments, along the second direction and in a direction away from the channel region, the widths of the plurality of sub-electrodes along the first direction increase sequentially.

[0019] In some embodiments, in an orthographic projection on the substrate, the plurality of sub-electrodes are substantially aligned away from edges of the channel region.

[0020] In some embodiments, the first common electrode is located in the first conductive layer, and the first common electrode is located between two adjacent data lines;

[0021] The second conductive layer also includes a third transfer pattern, which is located on a side of the first transfer pattern and the gate away from the scanning line. The second common electrode and the first common electrode are respectively connected to the third transfer pattern through vias, and the third transfer pattern has no overlap with the orthographic projection of the first pixel electrode on the substrate.

[0022] In some embodiments, the plurality of sub-electrodes include a first sub-electrode, a second sub-electrode, and a third sub-electrode connected in sequence, the first sub-electrode being connected to a drain connection region of the thin film transistor and being located on a side of the drain connection region away from the channel region;

[0023] In the orthographic projection on the substrate, the second sub-electrode and the third switching pattern are arranged along the first direction, the first common electrode overlaps with the second sub-electrode and the third sub-electrode respectively, and the first common electrode does not overlap with the first sub-electrode.

[0024] In some embodiments, the third conductive layer further comprises:

[0025] A fourth transfer pattern, wherein the fourth transfer pattern and the second common electrode are separated from each other, the second sub-electrode and the second pixel electrode are respectively connected to the fourth transfer pattern through vias, and in the orthographic projection on the substrate, the fourth transfer pattern is located in the area of ​​the second sub-electrode.

[0026] In some embodiments, the first common electrode is located in the third conductive layer, and the first common electrode and the second common electrode share the same electrode;

[0027] The second conductive layer further includes a second transfer pattern, the second transfer pattern is located at a side of the gate away from the first transfer pattern, and the second transfer pattern is used to connect the first pixel electrode and the second pixel electrode;

[0028] In an orthographic projection on the substrate, the same electrode covers the first transfer pattern and the gate and has no overlap with the second transfer pattern.

[0029] In some embodiments, the first pixel electrode is located in the semiconductor layer, the plurality of sub-electrodes include a fourth sub-electrode and a fifth sub-electrode connected in sequence, the fourth sub-electrode is connected to the drain connection region of the thin film transistor, and is located on a side of the drain connection region away from the channel region;

[0030] In the orthographic projection on the substrate, the second switching pattern is located within the range of the fourth sub-electrode, and the same electrode overlaps with the edge of the fourth sub-electrode close to the channel region and the fifth sub-electrode respectively.

[0031] In some embodiments, the display substrate further comprises:

[0032] a second insulating layer, disposed between the second conductive layer and the third conductive layer; and

[0033] An organic insulating layer is disposed between the second insulating layer and the third conductive layer, wherein the organic insulating layer and the orthographic projection of the first pixel electrode on the substrate at least partially do not overlap.

[0034] In some embodiments, in the orthographic projection on the substrate, the first pixel electrode and the second pixel electrode have no overlap with the scan line, respectively, the first pixel electrode is located in the region of the second pixel electrode, and the gap width between the second pixel electrodes of two adjacent sub-pixels is greater than or equal to 5 microns and less than or equal to 15 microns.

[0035] In some embodiments, in the orthographic projection on the substrate, the first common electrode and the second common electrode have no overlap with the data line respectively, the second common electrode has an overlapping area with the scan line, and the width of the overlapping area along the first direction is smaller than the width of the non-overlapping area along the first direction.

[0036] The present disclosure provides a display device, comprising: an opposing substrate, an electrophoretic solution, and a display substrate as described in any embodiment, wherein the electrophoretic solution is located between the opposing substrate and the display substrate, and the second conductive layer is located on a side of the substrate close to the electrophoretic solution.

[0037] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0039] Figure 1 A schematic diagram of the structure of a first display substrate example is shown;

[0040] Figure 2 A schematic diagram of the structure of a display substrate after the first conductive layer is prepared in the first example is shown;

[0041] Figure 3 A schematic diagram of the structure of a display substrate after the semiconductor layer is prepared in the first example is shown;

[0042] Figure 4 A schematic diagram of the structure of a display substrate after the first insulating layer is prepared in the first example is shown;

[0043] Figure 5 A schematic diagram of the structure of the display substrate after the second conductive layer is prepared in the first example is shown;

[0044] Figure 6 A schematic diagram of the structure of a display substrate in which an organic insulating layer is prepared in the first example is shown;

[0045] Figure 7 A schematic diagram of the structure of the display substrate after the second insulating layer is prepared in the first example is shown;

[0046] Figure 8 A schematic diagram of the structure of the display substrate after the third conductive layer is prepared in the first example is shown;

[0047] Fig. 9 A schematic diagram of the structure of the display substrate after the third insulating layer is prepared in the first example is shown;

[0048] Fig.10 A schematic diagram of the structure of a display substrate in which the transparent conductive layer is prepared in the first example is shown;

[0049] Fig.11A schematic structural diagram of a second display substrate example is shown;

[0050] Fig.12 A schematic diagram of the structure of a display substrate after the first conductive layer is prepared in the second example is shown;

[0051] Fig.13 A schematic diagram of the structure of a display substrate after the semiconductor layer is prepared in the second example is shown;

[0052] Fig.14 A schematic diagram of the structure of a display substrate after the first insulating layer is prepared in the second example is shown;

[0053] Fig.15 A schematic diagram of the structure of a display substrate after the second conductive layer is prepared in the second example is shown;

[0054] Fig.16 A schematic diagram of the structure of a display substrate after the organic insulating layer is prepared in the second example is shown;

[0055] Fig.17 A schematic diagram of the structure of a display substrate after the second insulating layer is prepared in the second example is shown;

[0056] Fig.18 A schematic diagram of the structure of a display substrate after the third conductive layer is prepared in the second example is shown;

[0057] Fig.19 A schematic diagram of the structure of a display substrate after the third insulating layer is prepared in the second example is shown;

[0058] Fig. 20 A schematic diagram of the structure of a display substrate in which a transparent conductive layer is prepared in a second example is shown;

[0059] Fig.21 A schematic structural diagram of a third display substrate example is shown;

[0060] Fig. 22 A schematic diagram of the structure of a display substrate after the first conductive layer is prepared in the third example is shown;

[0061] Fig.23 A schematic diagram of the structure of a display substrate after the semiconductor layer is prepared in the third example is shown;

[0062] Fig.24 A schematic diagram of the structure of a display substrate after the first insulating layer is prepared in the third example is shown;

[0063] Fig.25 A schematic diagram of the structure of a display substrate after the second conductive layer is prepared in the third example is shown;

[0064] Fig.26A schematic diagram of the structure of a display substrate after the organic insulating layer is prepared in the third example is shown;

[0065] Fig. 27 A schematic diagram of the structure of a display substrate after the preparation of the third conductive layer is shown in the third example;

[0066] Fig.28 A schematic diagram of the structure of a display substrate after the preparation of the third insulating layer is shown in the third example;

[0067] Fig.29 A schematic diagram of the structure of a display substrate in which the transparent conductive layer is prepared in the third example is shown;

[0068] Fig.30 A bar graph showing the electric field strength in the channel region as a function of the doping concentration in the first conductive region;

[0069] Fig.31 A schematic diagram of a cross-sectional structure of a display device is exemplarily shown;

[0070] Fig.32 A schematic diagram of a connection structure of a display device is exemplarily shown. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0072] In related technologies, electronic paper mainly uses the following two methods to achieve full-color display: the first is color printed electronic paper technology, which is electronic paper with a color filter, and uses the color mixing principle to convert black and white electronic paper into full-color electronic paper; the second method is color electronic paper technology. Color electronic paper is composed of ink particles of four colors (such as yellow, cyan, magenta and white). By applying an electric field and using the principle of positive and negative attraction, the ink particles of the corresponding color are pushed to the display side. After the particles of different colors are mixed, they present a variety of colors.

[0073] In order to drive the electronic paper to display full color, a higher driving voltage needs to be provided, for example, VGH ≥ 28 V, VGL ≤ -28 V. However, the highest operating voltage of the display substrate in the related art cannot meet the driving requirements of color electronic paper. Therefore, it is urgent to develop a high-voltage display substrate.

[0074] The present disclosure provides a display substrate, such as Figure 1 , Fig.11 or Fig.21 As shown, the display substrate includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a plurality of sub-pixels PX. The sub-pixels PX include thin film transistors.

[0075] It should be noted that in Figures 1 to 29 In FIG. 1 , FIG. a exemplarily shows a schematic diagram of a planar structure of a sub-pixel PX in a display substrate, FIG. b exemplarily shows a schematic diagram of a cross-sectional structure along the AA' position in FIG. a, and FIG. c exemplarily shows a schematic diagram of a cross-sectional structure along the BB' and CC' positions in FIG. a. Figures 1 to 10 In FIG. 4 , FIG. d exemplarily shows a planar structural diagram of four sub-pixels PX in a display substrate.

[0076] like Figure 1 , Fig.11 or Fig.21 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a semiconductor layer ACT, a first insulating layer GI and a second conductive layer M2 stacked in sequence on one side of the substrate 10, the first conductive layer M1 is arranged close to the substrate 10, the first conductive layer M1 includes a data line DL, the semiconductor layer ACT includes a plurality of semiconductor patterns located at different sub-pixels PX, the semiconductor pattern includes a source connection area S, a first conductor area DT1 and a channel area CH of a thin film transistor, the source connection area S, the first conductor area DT1 and the channel area CH are arranged along a first direction f1 and are connected in sequence, and the second conductive layer M2 includes a first transfer pattern ZJ1, a scan line GL and a gate G of the thin film transistor.

[0077] Among them, a first via hole H1 is set on the first insulating layer GI, and the first via hole H1 exposes a portion of the data line DL, the source connection area S and the first conductor area DT1. The data line DL and the source connection area S are respectively overlapped with the first transfer pattern ZJ1 through the first via hole H1, and the first transfer pattern ZJ1 and the first conductor area DT1 have no overlap in their orthographic projections on the substrate 10.

[0078] In the present disclosure, the first conductor area DT1 is exposed at the position of the first via H1, and the first transfer pattern ZJ1 has no overlap with the orthographic projection of the first conductor area DT1 on the substrate 10, that is, the first transfer pattern ZJ1 does not cover the first conductor area DT1, that is, the first transfer pattern ZJ1 realizes the connection between the data line DL and the source connection area S by semi-covering or semi-overlapping the first via H1. By adjusting the doping concentration of the first conductor area DT1 exposed by the first via H1, the resistance of the first via H1 can be adjusted, and then the voltage division size of the first via H1 can be adjusted, which is beneficial to the improvement of the voltage resistance of the thin film transistor.

[0079] Reference Fig.30The bar graph shows the electric field strength of the channel region CH as a function of the doping concentration of the first conductive region DT1. Fig.30 As shown, as the doping concentration of the first conductive area DT1 decreases, the electric field strength of the channel area CH decreases. This is because as the doping concentration of the first conductive area DT1 decreases, the resistance and voltage division of the first via H1 increase, so the electric field strength of the channel area CH decreases, thereby improving the withstand voltage capability of the thin film transistor.

[0080] In the present disclosure, a thin film transistor refers to an element including at least three terminals, namely, a gate G, a drain and a source. A thin film transistor has a channel region CH between a drain (drain terminal, a drain region or a drain) and a source (source terminal, a source region or a source), and current can flow through the drain, the channel region CH and the source. In the present disclosure, the channel region CH refers to a region where current mainly flows.

[0081] In the present disclosure, when using thin film transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in the present disclosure, the "source" and "drain" can be interchanged.

[0082] Exemplarily, the material of the active layer 12 includes oxide semiconductor materials such as IGZO, and may also include materials such as amorphous silicon or low-temperature polysilicon, which is not limited in the present disclosure.

[0083] In some embodiments, the channel region CH of the thin film transistor includes a semiconductor material M1OaNb, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents an oxygen element, and N represents a nitrogen element, that is, the semiconductor material is a metal oxide material or a metal nitride oxide material. Suitable metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb and Cd-Sn-O. The material of the channel CH may be in an amorphous, partially crystalline, single crystal or polycrystalline state, and may also be a single layer or multi-layer structure.

[0084] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride or a combination thereof. In one example, the material of the channel region CH includes indium gallium zinc oxide (IGZO).

[0085] For example, refer to Figure 2 , Fig.12 or Fig. 22 As shown, the data line DL includes a first line segment XD1 extending along the second direction f2, and a second line segment XD2 extending along the first direction f1. Figure 1 , Fig.11 or Fig.21 As shown, the second line segment XD2 is connected to the side of the first line segment XD1 close to the channel region CH, the second line segment XD2 is exposed at the first via H1, the second line segment XD2 overlaps with the orthographic projection of the source connection region S on the substrate 10, and the first transfer pattern ZJ1 realizes the connection between the second line segment XD2 and the source connection region S by half-overlapping the first via H1. The source connection region S is arranged close to the intersection of the first line segment XD1 and the scan line GL.

[0086] Exemplarily, the first direction f1 is parallel to the extending direction of the scan line GL.

[0087] For example, Figure 1 , Fig.11 or Fig.21 As shown, the sub-pixel PX further includes a pixel electrode EP1 / EP2, a gate G of the thin film transistor is connected to the scan line GL, a source connection area S is connected to the data line DL through a first transfer pattern ZJ1, a drain connection area D is connected to the pixel electrode EP1 / EP2, and the pixel electrode EP1 / EP2 is used to drive the target particles to move. The target particles may be electrophoretic particles, such as two-color particles, three-color particles or four-color particles, etc.; or they may be liquid crystal molecules.

[0088] In the present disclosure, the movement of target particles may refer to the target particles moving up and down (such as moving in a direction perpendicular to the substrate 10) or left and right (such as moving in a direction parallel to the substrate 10) between two substrates or plates, or the target particles deflecting up and down, left and right, or forward and backward between two substrates or plates.

[0089] Since the source connection area S and the first conductive area DT1 will be overetched during the process of forming the first via hole H1, Figure 1 , Fig.11 or Fig.21 As shown, the thickness of the source connection region S and the first conductive region DT1 are both smaller than the thickness of the channel region CH.

[0090] For example, Figure 1 , Fig.11 or Fig.21 As shown, the thickness of the first conductive region DT1 is less than or equal to the thickness of the source connection region S.

[0091] In some embodiments, Figure 1 , Fig.11 or Fig.21 As shown, the semiconductor pattern further includes: a second conductive region DT2 connected between the first conductive region DT1 and the channel region CH, the thickness of the first conductive region DT1 is less than the thickness of the second conductive region DT2, and the thickness of the second conductive region DT2 is less than or equal to the thickness of the channel region CH.

[0092] In some embodiments, Figure 1 or Fig.21 As shown, the semiconductor pattern also includes: a drain connection area D, a third conductor area DT3 and a fourth conductor area DT4 of the thin film transistor, the channel area CH, the fourth conductor area DT4, the third conductor area DT3 and the drain connection area D are arranged along the first direction f1 and connected in sequence, and the thickness of the third conductor area DT3 is less than the thickness of the fourth conductor area DT4. The second conductive layer M2 also includes a second transfer pattern ZJ2, the second transfer pattern ZJ2 is located on the side of the gate G away from the first transfer pattern ZJ1, and a second via hole H2 is further provided on the first insulating layer GI, the second via hole H2 exposes the drain connection area D and the third conductor area DT3, the second transfer pattern ZJ2 is overlapped with the drain connection area D through the second via hole H2, and the orthographic projections of the second transfer pattern ZJ2 and the third conductor area DT3 on the substrate 10 do not overlap.

[0093] In the present embodiment, the third conductive area DT3 is exposed at the position of the second via H2, and the second transfer pattern ZJ2 has no overlap with the orthographic projection of the third conductive area DT3 on the substrate 10, that is, the second transfer pattern ZJ2 does not cover the third conductive area DT3, that is, the second transfer pattern ZJ2 is connected to the drain connection area D by semi-covering or semi-overlapping the second via H2. By adjusting the doping concentration of the third conductive area DT3 exposed by the second via H2, the resistance of the second via H2 can be adjusted, and then the voltage division size of the second via H2 can be adjusted, so that the voltage resistance of the thin film transistor can be further improved.

[0094] Exemplarily, the thickness of the third conductor region DT3 is less than or equal to the thickness of the drain connection region D. The thickness of the drain connection region D and the third conductor region DT3 are both less than the thickness of the channel region CH. The thickness of the fourth conductor region DT4 is less than or equal to the thickness of the channel region CH.

[0095] Exemplarily, the thickness of the drain connection region D is substantially equal to the thickness of the source connection region S, the thickness of the third conductor region DT3 is substantially equal to the thickness of the first conductor region DT1, and the thickness of the fourth conductor region DT4 is substantially equal to the thickness of the second conductor region DT2.

[0096] In specific implementation, after forming the second conductive layer M2, the second conductive layer M2 can be used as a mask to perform secondary etching on the first insulating layer GI, and then the second conductive layer M2 can be used as a mask to perform conductorization on the semiconductor material in the exposed area (such as the first conductorization area DT1, the second conductorization area DT2, the third conductorization area DT3 and the fourth conductorization area DT4) in the semiconductor layer ACT by using a self-alignment process. The conductorization process can, for example, use dry etching equipment or ion implantation equipment to inject plasma (such as plasma containing at least one element of helium, oxygen, nitrogen, chlorine, hydrogen, boron and phosphorus) into the semiconductor material, or use an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductorization. Among them, the use of dry etching equipment to conduct the semiconductor material can be performed simultaneously with the secondary etching process of the first insulating layer GI, thereby simplifying the process.

[0097] In a specific implementation, after forming the second conductive layer M2, the first insulating layer GI may not be etched for the second time, and the second conductive layer M2 may be directly used as a mask to conduct the semiconductor material in the exposed area (such as the first conductive area DT1, the second conductive area DT2, the third conductive area DT3 and the fourth conductive area DT4) in the semiconductor layer ACT through a self-alignment process. The conduction process may, for example, use dry etching equipment or ion implantation equipment to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron and phosphorus) into the semiconductor material, or may use an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conduction.

[0098] For example, when the first insulating layer GI is etched twice, Figure 1 , Fig.11 or Fig.21 As shown, the second conductor area DT2 and the first insulating layer GI have no overlap in orthographic projection on the substrate 10, the thickness of the first conductor area DT1 is less than the thickness of the source connection area S and the second conductor area DT2, and the thickness of the second conductor area DT2 is less than the thickness of the channel area CH. The fourth conductor area DT4 and the first insulating layer GI have no overlap in orthographic projection on the substrate 10, the thickness of the third conductor area DT3 is less than the thickness of the drain connection area D and the fourth conductor area DT4, and the thickness of the fourth conductor area DT4 is less than the thickness of the channel area CH.

[0099] Exemplarily, without performing secondary etching on the first insulating layer GI, the first insulating layer GI covers the surface of the second conductive region DT2 away from the substrate 10, the thickness of the second conductive region DT2 is substantially equal to the thickness of the channel region CH, and the thickness of the first conductive region DT1 is substantially equal to the thickness of the source connection region S. The first insulating layer GI covers the surface of the fourth conductive region DT4 away from the substrate 10, the thickness of the fourth conductive region DT4 is substantially equal to the thickness of the channel region CH, and the thickness of the third conductive region DT3 is substantially equal to the thickness of the drain connection region D.

[0100] Exemplarily, the pixel electrodes EP1 / EP2 of different sub-pixels PX are arranged separately from each other. The pixel electrode EP1 / EP2 may include a first pixel electrode EP1 and a second pixel electrode EP2. The first pixel electrode EP1 and the second pixel electrode EP2 are arranged in different layers and connected through a via.

[0101] Exemplarily, the sub-pixel PX may further include a common electrode EC1 / EC2, and the orthographic projections of the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 on the substrate 10 overlap with each other to form a storage capacitor. The common electrodes EC1 / EC2 of different sub-pixels PX may be connected to each other. The common electrode EC1 / EC2 may include a first common electrode EC1, and may also include a second common electrode EC2. The first common electrode EC1 and the second common electrode EC2 may be arranged in the same layer and connected to each other, or may be arranged in different layers and connected through vias.

[0102] In some embodiments, Figure 1 As shown, the second transfer pattern ZJ2 overlaps with the orthographic projection of the common electrode EC1 / EC2 on the substrate 10 , and the second transfer pattern ZJ2 constitutes the first pixel electrode EP1 .

[0103] In some embodiments, Fig.21 As shown, the second transfer pattern ZJ2 has no overlap with the orthographic projection of the common electrode EC1 / EC2 on the substrate 10. The semiconductor pattern further includes: a fifth conductor region DT5, which is located on the side of the drain connection region D away from the channel region CH and connected to the drain connection region D. The fifth conductor region DT5 overlaps with the orthographic projection of the common electrode EC1 / EC2 on the substrate 10, and the fifth conductor region DT5 constitutes the first pixel electrode EP1. The second transfer pattern ZJ2 serves to connect the first pixel electrode EP1 and the second pixel electrode EP2.

[0104] In some embodiments, Figure 1 , Fig.11 or Fig.21As shown, the sub-pixel PX further includes a first common electrode EC1, a first pixel electrode EP1, a second common electrode EC2, and a second pixel electrode EP2. The first pixel electrode EP1 is located on the semiconductor layer ACT (eg, Fig.11 and Fig.21 as shown) or the second conductive layer M2 (as shown Figure 1 shown).

[0105] The first common electrode EC1 and the first pixel electrode EP1 are disposed in different layers and their projections on the substrate 10 overlap, forming a first storage capacitor Cst1. The second common electrode EC2 and the second pixel electrode EP2 are disposed in different layers and their projections on the substrate 10 overlap, forming a second storage capacitor Cst2.

[0106] like Figure 1 As shown, the first pixel electrode EP1 is located in the second conductive layer M2 , the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2 , and the first pixel electrode EP1 is connected to the drain connection region D through the second via hole H2 .

[0107] like Fig.21 As shown, the first pixel electrode EP1 is located in the semiconductor layer ACT, that is, in the fifth conductive region DT5 of the semiconductor layer ACT. The fifth conductive region DT5 is located on a side of the drain connection region D away from the channel region CH and is connected to the drain connection region D.

[0108] like Fig.11 As shown, the first pixel electrode EP1 is located in the semiconductor layer ACT. The semiconductor pattern further includes a sixth conductive region DT6. The sixth conductive region DT6 is located on a side of the drain connection region D away from the channel region CH and connected to the drain connection region D. The sixth conductive region DT6 constitutes the first pixel electrode EP1.

[0109] For example, Figure 1 , Fig.11 or Fig.21 As shown, the display substrate also includes: a third conductive layer M3, which is arranged on the side of the second conductive layer M2 away from the substrate 10, including a second common electrode EC2; and a transparent conductive layer TD, which is arranged on the side of the third conductive layer M3 away from the substrate 10, including a second pixel electrode EP2, the second pixel electrode EP2 overlaps with the second common electrode EC2 in their positive projections on the substrate 10, the second pixel electrode EP2 is connected to the first pixel electrode EP1 through a via, and the first pixel electrode EP1 is also connected to the drain connection area D of the thin film transistor.

[0110] Exemplarily, the first common electrode EC1 is located on the first conductive layer M1 (eg Figure 1 and Fig.11 as shown) or the third conductive layer M3 (as shown Fig.21shown).

[0111] In some embodiments, Figure 1 , Fig.11 or Fig.21 As shown, the first pixel electrode EP1 includes a plurality of sub-electrodes 11, which are arranged along a second direction f2 and connected in sequence. The second direction f2 intersects with the first direction f1, and different sub-electrodes 11 have different widths along the first direction f1.

[0112] Exemplarily, the second direction f2 is parallel to the extending direction of the data line DL. The first direction f1 is, for example, perpendicular to the second direction f2.

[0113] For example, Figure 1 , Fig.11 or Fig.21 As shown, along the second direction f2 and in a direction away from the channel region CH, the widths of the plurality of sub-electrodes 11 along the first direction f1 increase sequentially.

[0114] For example, Figure 1 , Fig.11 or Fig.21 As shown, in the orthographic projection on the substrate 10, the edges of the plurality of sub-electrodes 11 away from the channel region CH or the data line DL (the lower edges of the sub-electrodes 11 as shown in the figure) are roughly aligned.

[0115] For example, Figure 1 , Fig.11 or Fig.21 As shown, a plurality of sub-electrodes connected in sequence form a stepped structure.

[0116] For example, Figure 1 or Fig.11 As shown, the plurality of sub-electrodes 11 include a first sub-electrode 111, a second sub-electrode 112, and a third sub-electrode 113 connected in sequence, the first sub-electrode 111 is connected to the drain connection region D of the thin film transistor, and is located on the side of the drain connection region D away from the channel region CH. The first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 are arranged in sequence along the second direction f2 and away from the channel region CH, and the widths of the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 along the first direction f1 increase in sequence. Moreover, the edges of the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 away from the channel region CH or the data line DL are roughly aligned, and the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 form a three-level stepped structure.

[0117] For example, Fig.21As shown, the plurality of sub-electrodes 11 include a fourth sub-electrode 114 and a fifth sub-electrode 115 connected in sequence, and the fourth sub-electrode 114 is connected to the drain connection region D of the thin film transistor and is located on the side of the drain connection region D away from the channel region CH. The fourth sub-electrode 114 and the fifth sub-electrode 115 are arranged in sequence along the second direction f2 and in a direction away from the channel region CH, and the widths of the fourth sub-electrode 114 and the fifth sub-electrode 115 along the first direction f1 are increased in sequence. Moreover, the edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH or the data line DL are roughly aligned, and the fourth sub-electrode 114 and the fifth sub-electrode 115 form a two-level stepped structure.

[0118] In some embodiments, Figure 1 or Fig.11 As shown, the first common electrode EC1 is located on the first conductive layer M1. The first common electrode EC1 is, for example, located between two adjacent data lines DL.

[0119] like Figure 1 As shown, the first common electrode EC1 is located in the first conductive layer M1, and the first pixel electrode EP1 is located in the second conductive layer M2, that is, the two plates of the first storage capacitor Cst1 are respectively located in the first conductive layer M1 and the second conductive layer M2.

[0120] like Fig.11 As shown, the first common electrode EC1 is located on the first conductive layer M1, and the first pixel electrode EP1 is located on the semiconductor layer ACT, that is, the two plates of the first storage capacitor Cst1 are respectively located on the first conductive layer M1 and the semiconductor layer ACT. Figure 1 Compared with the embodiment of the present invention, the first insulating layer GI is reduced between the two plates of the first storage capacitor Cst1, which is beneficial to increase the capacitance of the first storage capacitor Cst1 or reduce the areas of the first pixel electrode EP1 and the first common electrode EC1, thereby facilitating the improvement of pixel density.

[0121] For example, Figure 1 or Fig.11 As shown, the second conductive layer M2 also includes a third transfer pattern ZJ3, which is located on the side of the first transfer pattern ZJ1 and the gate G away from the scanning line GL, and the second common electrode EC2 and the first common electrode EC1 are respectively connected to the third transfer pattern ZJ3 through vias, and the third transfer pattern ZJ3 has no overlap with the orthographic projection of the first pixel electrode EP1 on the substrate 10.

[0122] like Figure 1 or Fig.11 As shown, the first common electrode EC1 is connected to the third transfer pattern ZJ3 through the via hole H3, and the second common electrode EC2 is connected to the third transfer pattern ZJ3 through the via hole RH1.

[0123] For example, Figure 1 or Fig.11 As shown, in the orthographic projection on the substrate 10, the second sub-electrode 112 and the third transfer pattern ZJ3 are arranged along the first direction f1, the first common electrode EC1 overlaps with the second sub-electrode 112 and the third sub-electrode 113 respectively, and the first common electrode EC1 does not overlap with the first sub-electrode 111. The first common electrode EC1 is located on the side of the first transfer pattern ZJ1 and the gate G away from the scan line GL.

[0124] For example, Figure 1 or Fig.11 As shown, in the orthographic projection on the substrate 10, the gate G and the third transfer pattern ZJ3 are located on the same side of the second transfer pattern ZJ2 (i.e., the first pixel electrode EP1), and the first transfer pattern ZJ1 and the first sub-electrode 111 are located on opposite sides of the gate G in the first direction f1. The edge of the first transfer pattern ZJ1 close to the scan line GL is roughly aligned with the edge of the first sub-electrode 111 close to the scan line GL, and the width of the first transfer pattern ZJ1 in the second direction f2 is smaller than the width of the first sub-electrode 111 in the second direction f2.

[0125] For example, Figure 1 As shown, in the orthographic projection on the substrate 10, the edge of the first transfer pattern ZJ1 away from the scan line GL is aligned with the edge of the gate G away from the scan line GL. The edge of the third transfer pattern ZJ3 close to the second sub-electrode 112 is roughly aligned with the edge of the gate G close to the first transfer pattern ZJ1. The edge of the third transfer pattern ZJ3 close to the data line DL is aligned with the edge of the third sub-electrode 113 close to the data line DL, and is located on the side of the first common electrode EC1 close to the data line DL. The edge of the third transfer pattern ZJ3 close to the scan line GL is roughly aligned with the edge of the second sub-electrode 112 close to the scan line GL, and is located on the side of the first common electrode EC1 close to the scan line GL.

[0126] For example, Figure 1 or Fig.11 As shown, the width of the third switching pattern ZJ3 in the second direction f2 is smaller than the width of the second sub-electrode 112 in the second direction f2. The width of the second sub-electrode 112 in the second direction f2 is larger than the width of the first sub-electrode 111 and the third sub-electrode 113 in the second direction f2.

[0127] For example, Figure 1 or Fig.11 As shown, in the first direction f1, the width of the first common electrode EC1 is greater than the width of the second sub-electrode 112 and smaller than the width of the third sub-electrode 113. In the orthographic projection on the substrate 10, the third sub-electrode 113 covers the first common electrode EC1 in the first direction f1.

[0128] For example, Figure 1 or Fig.11 As shown, the third conductive layer M3 also includes: a fourth transfer pattern ZJ4, the fourth transfer pattern ZJ4 and the second common electrode EC2 are separated from each other, the second sub-electrode 112 and the second pixel electrode EP2 are respectively connected to the fourth transfer pattern ZJ4 through vias, and in the orthographic projection on the substrate 10, the fourth transfer pattern ZJ4 is located in the area of ​​the second sub-electrode 112.

[0129] like Figure 1 or Fig.11 As shown, the second sub-electrode 112 is connected to the fourth transfer pattern ZJ4 through the via hole RH2, and the second pixel electrode EP2 is connected to the fourth transfer pattern ZJ4 through the via hole H4.

[0130] For example, Figure 1 As shown, the edge of the fourth transfer pattern ZJ4 away from the scan line GL is aligned with the edge of the third transfer pattern ZJ3 away from the scan line GL, and in the second direction f2, the width of the fourth transfer pattern ZJ4 is less than the width of the third transfer pattern ZJ3. The fourth transfer pattern ZJ4 is located in the gap where the second common electrode EC2 is away from the third transfer pattern ZJ3, and the second common electrode EC2 is arranged on three sides of the fourth transfer pattern ZJ4, such as the left side, the right side and the top side as shown in the figure. The shape of the fourth transfer pattern ZJ4 is, for example, a square. The width of the second common electrode EC2 in the first direction f1 is greater than the width of the first pixel electrode EP1 and the first common electrode EC1 in the first direction f1, and the second common electrode EC2 covers the first pixel electrode EP1 and the first common electrode EC1 in the first direction f1. In the orthographic projection on the substrate 10, the second common electrode EC2 is roughly aligned with the edges of the data line DL that are close to each other.

[0131] For example, Figure 1 As shown, the gap between the fourth transfer pattern ZJ4 and the second common electrode EC2 is substantially equal to the gap between the third transfer pattern ZJ3 and the first pixel electrode EP1.

[0132] In some embodiments, Fig.21 As shown, the first common electrode EC1 is located in the third conductive layer M3, and the first common electrode EC1 and the second common electrode EC2 share the same electrode EC. This embodiment can significantly reduce the number of vias, thereby increasing the facing area between the electrodes, thereby increasing the storage capacitor, which is beneficial to improving the pixel density and can more flexibly adjust the size of the storage capacitor according to actual needs.

[0133] For example, Fig.21As shown, the second conductive layer M2 further includes a second transfer pattern ZJ2, which is located on the side of the gate G away from the first transfer pattern ZJ1, and is used to connect the first pixel electrode EP1 and the second pixel electrode EP2. In the orthographic projection on the substrate 10, the same electrode EC covers the first transfer pattern ZJ1 and the gate G, and has no overlap with the second transfer pattern ZJ2. The second transfer pattern ZJ2 is located in the notch of the same electrode EC, and the same electrode EC is located on both sides of the second transfer pattern ZJ2, as shown in FIG. Fig.21 Top and right sides shown.

[0134] like Fig.21 As shown, the second transfer pattern ZJ2 is connected to the first pixel electrode EP1 through the second via hole H2, and the second transfer pattern ZJ2 is connected to the second pixel electrode EP2 through the via hole H5. The centers of the second via hole H2 and the via hole H5 do not coincide, and the orthographic projections of the second via hole H2 and the via hole H5 on the substrate 10 partially overlap.

[0135] For example, Fig.21 As shown, the first pixel electrode EP1 is located on the semiconductor layer ACT.

[0136] For example, Fig.21 As shown, in the orthographic projection on the substrate 10 , the second switching pattern ZJ2 is located within the range of the fourth sub-electrode 114 , and the same electrode EC overlaps with the edge of the fourth sub-electrode 114 close to the channel region CH and the fifth sub-electrode 115 .

[0137] For example, Fig.21 As shown, the edge of the gate electrode G away from the scan line GL is aligned with the edge of the second switching pattern ZJ2 away from the scan line GL. The edges of the same electrode EC and the data line DL close to each other are roughly aligned.

[0138] For example, Fig. 27 As shown, the same electrode EC includes a first sub-common electrode EC11 and a second sub-common electrode EC12 arranged and sequentially connected along the second direction f2. In the first direction f1, the width of the first sub-common electrode EC11 is smaller than the width of the second sub-common electrode EC12. The boundary line between the first sub-common electrode EC11 and the second sub-common electrode EC12 is roughly aligned with the edge of the gate G away from the scanning line GL. The first sub-common electrode EC11 is located on the side of the second transfer pattern ZJ2 close to the gate G.

[0139] For example, Fig.21As shown, the display substrate also includes: a second insulating layer PVX1, arranged between the second conductive layer M2 and the third conductive layer M3; and an organic insulating layer RS, arranged between the second insulating layer PVX1 and the third conductive layer M3, and the organic insulating layer RS ​​and the orthographic projection of the first pixel electrode EP1 on the substrate 10 have at least partial non-overlap.

[0140] By removing the organic insulating layer RS ​​above the first pixel electrode EP1 and reducing the distance between the first pixel electrode EP1 and the first common electrode EC1, a first storage capacitor Cst1 with a larger capacitance can be formed or the areas of the first pixel electrode EP1 and the first common electrode EC1 can be reduced, which is beneficial to improving the pixel density.

[0141] In some embodiments, Figure 1 , Fig.11 or Fig.21 As shown, in the orthographic projection on the substrate 10, the first pixel electrode EP1 and the second pixel electrode EP2 have no overlap with the scanning line GL respectively, the first pixel electrode EP1 is located in the area of ​​the second pixel electrode EP2, and the gap width w1 between the second pixel electrodes EP2 located in two adjacent sub-pixels PX is greater than or equal to 5 microns and less than or equal to 15 microns.

[0142] For example, Figure 1 , Fig.11 or Fig.21 As shown, in the orthographic projection on the substrate 10 , the first pixel electrode EP1 has no overlap with the data line DL and the scanning line GL, and in the first direction f1 , the second pixel electrode EP2 at least partially covers the data line DL.

[0143] In some embodiments, Figure 1 , Fig.11 or Fig.21 As shown, in the orthographic projection on the substrate 10, the first common electrode EC1 and the second common electrode EC2 have no overlap with the data line DL respectively, the second common electrode EC2 has an overlapping area with the scan line GL, and the width of the overlapping area along the first direction f1 is smaller than the width of the non-overlapping area along the first direction f1.

[0144] By shrinking the width of the second common electrode EC2 in the overlapping area, the parasitic capacitance between the second common electrode EC2 and the scan line GL can be reduced, thereby improving signal stability.

[0145] For example, Figure 1 , Fig.11 or Fig.21 As shown, in the orthographic projection on the substrate 10 , the first common electrode EC1 has no overlap with the scan line GL and the data line DL.

[0146] For example, Figure 1 As shown, the width w2 of the overlapped area of ​​the second common electrode EC2 and the scan line GL along the first direction f1 is greater than or equal to one times the width of the scan line GL, and less than or equal to two times the width of the scan line GL. The width of the scan line GL is the width of the scan line GL along the second direction f2.

[0147] Exemplarily, the first conductive layer M1 , the second conductive layer M2 , and the third conductive layer M3 are all metal layers.

[0148] Exemplarily, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 can each independently adopt any one or more metal materials such as copper, molybdenum, aluminum, titanium, silver, nickel, niobium, etc., and the structure of each conductive layer can be a single layer or a stacked layer.

[0149] In some embodiments, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 may include at least one of copper or copper alloy, molybdenum-niobium alloy, molybdenum-nickel alloy and molybdenum-nickel-titanium alloy, for example, copper / molybdenum-niobium, molybdenum-niobium / copper, copper / molybdenum-nickel-titanium, molybdenum-nickel-titanium / copper, molybdenum-nickel / copper, copper / molybdenum-nickel, molybdenum-niobium / copper / molybdenum-nickel-titanium, molybdenum-niobium / copper / molybdenum-niobium, molybdenum-nickel / copper / molybdenum-nickel-titanium and the like.

[0150] For example, the transparent conductive layer TD may be made of a transparent conductive material, such as metal oxides such as ITO, IZO, IGZO, IGO, and ZTO. The use of metal oxides may improve the oxidation resistance of the transparent conductive layer TD.

[0151] To meet the driving requirements of color electronic paper, illustratively, in each sub-pixel PX, the storage capacitance formed by the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 is greater than or equal to 1.0 pF and less than or equal to 2.0 pF, such as 1.2 pF.

[0152] Exemplarily, the storage capacitor includes a first storage capacitor Cst1 formed by the first common electrode EC1 and the first pixel electrode EP1, and a second storage capacitor Cst2 formed by the second common electrode EC2 and the second pixel electrode EP2. Since the first common electrode EC1 is connected to the second common electrode EC2 and the second pixel electrode EP2 is connected to the second pixel electrode EP2, the first storage capacitor Cst1 is connected to the second storage capacitor Cst2 in parallel. Therefore, in each sub-pixel PX, the storage capacitor formed by the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 is the sum of the capacitance values ​​of the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0153] For example, Figure 1As shown in the figure d in FIG. 1 , the data line DL extends along the row direction (i.e., the second direction f2), the scan line GL extends along the column direction (i.e., the first direction f1), the sub-pixels PX in the same column are connected to the same scan line GL, the sub-pixels PX in two adjacent columns are connected to different scan lines GL, and two columns of sub-pixels PX are arranged between the two adjacent scan lines GL. The sub-pixels PX in the same row are connected to two data lines DL, and the two data lines DL are arranged on both sides of the sub-pixels PX in the row, and the two adjacent sub-pixels PX in the same row are connected to different data lines DL.

[0154] Combine the following Figures 1 to 29 The technical solution provided by the present disclosure is exemplified.

[0155] In a first exemplary embodiment, Figure 1 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2 and a transparent conductive layer TD which are sequentially stacked on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0156] like Figure 1 As shown, the first conductive layer M1 includes a data line DL and a first common electrode EC1, the semiconductor layer ACT includes a semiconductor pattern, the semiconductor pattern includes a source connection area S, a first conductive area DT1, a second conductive area DT2, a channel area CH, a fourth conductive area DT4, a third conductive area DT3 and a drain connection area D arranged along a first direction f1 and connected in sequence, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1, a second transfer pattern ZJ2 and a third transfer pattern ZJ3, the third conductive layer M3 includes a second common electrode EC2 and a fourth transfer pattern ZJ4, and the transparent conductive layer TD includes a second pixel electrode EP2.

[0157] like Figure 1 As shown, the first transfer pattern ZJ1 connects the data line DL and the source connection area S through a first via H1 half-overlappingly arranged on the first insulating layer GI, and the second transfer pattern ZJ2 is connected to the drain connection area D through a second via H2 half-overlappingly arranged on the first insulating layer GI, and the second transfer pattern ZJ2 serves as the first pixel electrode EP1.

[0158] like Figure 1As shown, the first common electrode EC1 is connected to the second common electrode EC2 through the third transfer pattern ZJ3. Specifically, the first common electrode EC1 is connected to the third transfer pattern ZJ3 through vias set on the first insulating layer GI and the buffer layer BF, and the second common electrode EC2 is connected to the third transfer pattern ZJ3 through vias set on the second insulating layer PVX1 and the organic insulating layer RS.

[0159] like Figure 1 As shown, the first pixel electrode EP1 is connected to the second pixel electrode EP2 through the fourth transfer pattern ZJ4. Specifically, the first pixel electrode EP1 is connected to the fourth transfer pattern ZJ4 through vias set on the second insulating layer PVX1 and the organic insulating layer RS, and the second pixel electrode EP2 is connected to the fourth transfer pattern ZJ4 through vias set on the third insulating layer PVX2.

[0160] like Figure 1 As shown, the first common electrode EC1 and the first pixel electrode EP1 constitute two plates of the first storage capacitor Cst1, and the dielectric layer between the two plates includes a first insulating layer GI and a buffer layer BF. The second common electrode EC2 and the second pixel electrode EP2 constitute two plates of the second storage capacitor Cst2, and the dielectric layer between the two plates includes a third insulating layer PVX2. After testing, the technical solution provided in this embodiment is applied to a display substrate of 300PPI, and the storage capacitance of each sub-pixel PX can reach 1.2pF.

[0161] Reference Figures 2 to 10 The display substrate provided in this embodiment can be prepared by the following steps:

[0162] Step 11: Form a patterned first conductive layer M1 on the substrate 10, such as Figure 2 As shown, the first conductive layer M1 includes the data line DL and the first common electrode EC1, and may also include a shielding pattern (not shown in the figure), and the orthographic projection of the shielding pattern on the substrate 10 covers the channel region CH.

[0163] Step 12: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in FIG. Figure 3 The semiconductor layer ACT is a transparent material, and includes semiconductor patterns located in different sub-pixels PX, and the semiconductor patterns include a source connection area S, a first conductor area DT1, a second conductor area DT2, a channel area CH, a fourth conductor area DT4, a third conductor area DT3 and a drain connection area D arranged along a first direction f1 and connected in sequence.

[0164] Step 13: Form a patterned first insulating layer GI on the side of the semiconductor layer ACT facing away from the substrate 10, such as Figure 4As shown, a first via hole H1, a second via hole H2 and a third via hole H3 are provided on the first insulating layer GI. In the orthographic projection on the substrate 10, the first via hole H1 and the second via hole H2 are located on both sides of the channel region CH. The first via hole H1 exposes a portion of the data line DL, the source connection region S and the first conductor region DT1. The second via hole H2 exposes the drain connection region D and the third conductor region DT3. The third via hole H3 is located in the region of the first common electrode EC1.

[0165] Step 14: Form a patterned second conductive layer M2 on the side of the first insulating layer GI facing away from the substrate 10, such as Figure 5 As shown, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1, a second transfer pattern ZJ2 (i.e., a first pixel electrode EP1) and a third transfer pattern ZJ3. The gate G is connected to one side of the scan line GL, and the gate G overlaps with the channel region CH. The first transfer pattern ZJ1 half covers the first via hole H1 and is respectively connected to the data line DL and the source connection region S. The second transfer pattern ZJ2 half covers the second via hole H2 and is connected to the drain connection region D. The third transfer pattern ZJ3 fully covers the third via hole H3 and is connected to the first common electrode EC1.

[0166] After forming the second conductive layer M2, the first insulating layer GI can be etched twice using the second conductive layer M2 as a mask, and then the semiconductor material in the exposed area (such as the first conductive area DT1, the second conductive area DT2, the third conductive area DT3 and the fourth conductive area DT4) in the semiconductor layer ACT can be conductorized using a self-alignment process using the second conductive layer M2 as a mask. The conductorization process can, for example, use dry etching equipment or ion implantation equipment to inject plasma (such as plasma containing at least one element of helium, oxygen, nitrogen, chlorine, hydrogen, boron and phosphorus) into the semiconductor material, or use an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductorization. Among them, the use of dry etching equipment to conduct the semiconductor material can be carried out simultaneously with the secondary etching process of the first insulating layer GI, thereby simplifying the process.

[0167] Step 15: Deposit a second insulating material on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer, and then apply an organic insulating material to form an organic insulating material layer. Then, pattern the organic insulating material layer to form an organic insulating layer RS, such as Figure 6As shown, two organic vias are provided on the organic insulating layer RS, namely a first organic via RH1 and a second organic via RH2. The first organic via RH1 is located in the area of ​​the third transfer pattern ZJ3. The first organic via RH1 and the third via H3 are arranged along the second direction f2. The second organic via RH2 is located in the area of ​​the first pixel electrode EP1, such as in the area of ​​the second sub-electrode 112.

[0168] For example, Figure 6 As shown, the third via H3 and the first organic via RH1 are arranged along the second direction f2, and the first organic via RH1 and the second organic via RH2 are arranged along the first direction f1. The first organic via RH1 and the second organic via RH2 have the same shape and size.

[0169] Step 16: Patterning the second insulating material layer to form a second insulating layer PVX1, such as Figure 7 As shown, two via holes are disposed on the second insulating layer PVX1, namely, via hole PH1 and via hole PH2. The via hole PH1 is disposed in the first organic via hole RH1, and the via hole PH2 is disposed in the second organic via hole RH2.

[0170] For example, Figure 7 As shown, the via hole PH1 is centrally disposed in the first organic via hole RH1 , and the via hole PH2 is centrally disposed in the second organic via hole RH2 , and the via hole PH1 and the via hole PH2 are arranged along the first direction f1 .

[0171] Step 17: forming a patterned third conductive layer M3 on the side of the organic insulating layer RS ​​facing away from the substrate 10, such as Figure 8 As shown, the third conductive layer M3 includes a second common electrode EC2 and a fourth transfer pattern ZJ4 separated from each other, the second common electrode EC2 covers the via hole RH1 on the third transfer pattern ZJ3, is connected to the third transfer pattern ZJ3, and further connected to the first common electrode EC1. The fourth transfer pattern ZJ4 covers the via hole RH2 on the first pixel electrode EP1 and is connected to the first pixel electrode EP1.

[0172] Step 18: Form a patterned third insulating layer PVX2 on the side of the third conductive layer M3 facing away from the substrate 10, such as Fig. 9 As shown, a via H4 is provided on the third insulating layer PVX2 , and the via H4 is located in the region of the second organic via hole RH2 , and is used to expose the fourth transfer pattern ZJ4 .

[0173] Step 19: Form a patterned transparent conductive layer TD on the side of the third insulating layer PVX2 facing away from the substrate 10, such as Fig.10As shown, the transparent conductive layer TD includes a second pixel electrode EP2 located in a different sub-pixel PX. The second pixel electrode EP2 covers the via hole H4 located on the fourth transfer pattern ZJ4 and is connected to the fourth transfer pattern ZJ4 and further connected to the first pixel electrode EP1.

[0174] In a second exemplary embodiment, Fig.11 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2 and a transparent conductive layer TD which are sequentially stacked on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0175] like Fig.11 As shown, the first conductive layer M1 includes a data line DL and a first common electrode EC1, the semiconductor layer ACT includes a semiconductor pattern, the semiconductor pattern includes a source connection area S, a first conductive area DT1, a second conductive area DT2, a channel area CH, a drain connection area D and a sixth conductive area DT6 (i.e., a first pixel electrode EP1) arranged along a first direction f1 and connected in sequence, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a third transfer pattern ZJ3, the third conductive layer M3 includes a second common electrode EC2 and a fourth transfer pattern ZJ4, and the transparent conductive layer TD includes a second pixel electrode EP2.

[0176] like Fig.11 As shown, the first transfer pattern ZJ1 connects the data line DL and the source connection region S through a first via hole H1 half-overlappingly disposed on the first insulating layer GI.

[0177] like Fig.11 As shown, the first common electrode EC1 is connected to the second common electrode EC2 through the third transfer pattern ZJ3. Specifically, the first common electrode EC1 is connected to the third transfer pattern ZJ3 through vias set on the first insulating layer GI and the buffer layer BF, and the second common electrode EC2 is connected to the third transfer pattern ZJ3 through vias set on the second insulating layer PVX1 and the organic insulating layer RS.

[0178] like Fig.11 As shown, the first pixel electrode EP1 is connected to the second pixel electrode EP2 through the fourth transfer pattern ZJ4. Specifically, the first pixel electrode EP1 is connected to the fourth transfer pattern ZJ4 through vias set on the second insulating layer PVX1 and the organic insulating layer RS, and the second pixel electrode EP2 is connected to the fourth transfer pattern ZJ4 through vias set on the third insulating layer PVX2.

[0179] like Fig.11As shown, the first common electrode EC1 and the first pixel electrode EP1 form two plates of the first storage capacitor Cst1, and the dielectric layer between the two plates includes a buffer layer BF. The second common electrode EC2 and the second pixel electrode EP2 form two plates of the second storage capacitor Cst2, and the dielectric layer between the two plates includes a third insulating layer PVX2.

[0180] Reference Figures 12 to 20 The display substrate provided in this embodiment can be prepared by the following steps:

[0181] Step 21: Form a patterned first conductive layer M1 on the substrate 10, such as Fig.12 As shown, the first conductive layer M1 includes the data line DL and the first common electrode EC1, and may also include a shielding pattern (not shown in the figure), and the orthographic projection of the shielding pattern on the substrate 10 covers the channel region CH.

[0182] Step 22: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, such as Fig.13 As shown. The semiconductor layer ACT is a transparent material, including semiconductor patterns located in different sub-pixels PX, the semiconductor patterns overlap with the orthographic projection of the data line DL on the substrate 10, and the semiconductor patterns include a source connection area S, a first conductor area DT1, a second conductor area DT2, a channel area CH, a drain connection area D and a sixth conductor area DT6 arranged along a first direction f1 and connected in sequence, and the sixth conductor area DT6 constitutes a first pixel electrode EP1 and overlaps with the first common electrode EC1.

[0183] Step 23: Form a patterned first insulating layer GI on the side of the semiconductor layer ACT facing away from the substrate 10, such as Fig.14 As shown, a first via hole H1 and a third via hole H3 are provided on the first insulating layer GI. The first via hole H1 exposes a portion of the data line DL, the source connection region S and the first conductive region DT1 , and the third via hole H3 is located in the region of the first common electrode EC1 .

[0184] Step 24: Form a patterned second conductive layer M2 on the side of the first insulating layer GI facing away from the substrate 10, such as Fig.15 As shown, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a third transfer pattern ZJ3. The gate G is connected to one side of the scan line GL, and the gate G overlaps with the channel region CH. The first transfer pattern ZJ1 half covers the first via hole H1 and is respectively connected to the data line DL and the source connection region S. The third transfer pattern ZJ3 fully covers the third via hole H3 and is connected to the first common electrode EC1.

[0185] After forming the second conductive layer M2, the first insulating layer GI can be etched twice using the second conductive layer M2 as a mask, and then the semiconductor material in the exposed area (such as the first conductive area DT1, the second conductive area DT2, the area between the channel area CH and the drain connection area D, and the sixth conductive area DT6) in the semiconductor layer ACT can be conductively processed using a self-aligned process. The conductive process can, for example, use dry etching equipment or ion implantation equipment to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or use an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductive processing. The use of dry etching equipment to conductively process the semiconductor material can be performed simultaneously with the secondary etching process of the first insulating layer GI, thereby simplifying the process.

[0186] Step 25: Deposit a second insulating material on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer, and then apply an organic insulating material to form an organic insulating material layer. Then, pattern the organic insulating material layer to form an organic insulating layer RS, such as Fig.16 As shown, two organic vias are provided on the organic insulating layer RS, namely a first organic via RH1 and a second organic via RH2. The first organic via RH1 is located in the area of ​​the third transfer pattern ZJ3. The first organic via RH1 and the third via H3 are arranged along the second direction f2. The second organic via RH2 is located in the area of ​​the first pixel electrode EP1, such as in the area of ​​the second sub-electrode 112.

[0187] Step 26: Patterning the second insulating material layer to form a second insulating layer PVX1, such as Fig.17 As shown, two via holes are disposed on the second insulating layer PVX1, namely, via hole PH1 and via hole PH2. The via hole PH1 is disposed in the first organic via hole RH1, and the via hole PH2 is disposed in the second organic via hole RH2.

[0188] For example, Fig.17 As shown, the via hole PH1 is centrally disposed in the first organic via hole RH1 , and the via hole PH2 is centrally disposed in the second organic via hole RH2 , and the via hole PH1 and the via hole PH2 are arranged along the first direction f1 .

[0189] Step 27: Form a patterned third conductive layer M3 on the side of the organic insulating layer RS ​​facing away from the substrate 10, such as Fig.18As shown, the third conductive layer M3 includes a second common electrode EC2 and a fourth transfer pattern ZJ4 separated from each other, the second common electrode EC2 covers the via hole RH1 on the third transfer pattern ZJ3, is connected to the third transfer pattern ZJ3, and further connected to the first common electrode EC1. The fourth transfer pattern ZJ4 covers the via hole RH2 on the first pixel electrode EP1 and is connected to the first pixel electrode EP1.

[0190] Step 28: Form a patterned third insulating layer PVX2 on the side of the third conductive layer M3 facing away from the substrate 10, such as Fig.19 As shown, a via H4 is provided on the third insulating layer PVX2 , and the via H4 is located in the region of the second organic via hole RH2 , and is used to expose the fourth transfer pattern ZJ4 .

[0191] Step 29: Form a patterned transparent conductive layer TD on the side of the third insulating layer PVX2 facing away from the substrate 10, such as Fig. 20 As shown, the transparent conductive layer TD includes a second pixel electrode EP2 located in a different sub-pixel PX. The second pixel electrode EP2 covers a via hole located on the fourth transfer pattern ZJ4 and is connected to the fourth transfer pattern ZJ4 and further connected to the first pixel electrode EP1.

[0192] In a third exemplary embodiment, Fig.21 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2 and a transparent conductive layer TD which are sequentially stacked on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0193] like Fig.21 As shown, the first conductive layer M1 includes a data line DL, the semiconductor layer ACT includes a semiconductor pattern, the semiconductor pattern includes a source connection area S, a first conductive area DT1, a second conductive area DT2, a channel area CH, a fourth conductive area DT4, a third conductive area DT3, a drain connection area D and a fifth conductive area DT5 (i.e., a first pixel electrode EP1) arranged along a first direction f1 and connected in sequence, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a second transfer pattern ZJ2, the third conductive layer M3 includes a common electrode EC, i.e., a first common electrode EC1 and a second common electrode EC2, and the transparent conductive layer TD includes a second pixel electrode EP2.

[0194] like Fig.21 As shown, the first transfer pattern ZJ1 connects the data line DL and the source connection region S through a first via hole H1 half-overlappingly disposed on the first insulating layer GI.

[0195] like Fig.21 As shown, the first pixel electrode EP1 and the drain connection area D are arranged in the same layer and are connected to each other, and the second pixel electrode EP2 is connected to the drain connection area D through the second transfer pattern ZJ2. Specifically, the second transfer pattern ZJ2 is connected to the drain connection area D through a second via H2 half-overlappingly arranged on the first insulating layer GI, and the second pixel electrode EP2 is connected to the second transfer pattern ZJ2 through vias arranged on the second insulating layer PVX1, the organic insulating layer RS ​​and the third insulating layer PVX2.

[0196] like Fig.21 As shown, the first common electrode EC1 and the first pixel electrode EP1 constitute two plates of the first storage capacitor Cst1, and the organic insulating layer RS ​​above the first pixel electrode EP1 is removed so that the dielectric layer between the two plates is thinned to become the second insulating layer PVX1. The second common electrode EC2 and the second pixel electrode EP2 constitute two plates of the second storage capacitor Cst2, and the dielectric layer between the two plates includes the third insulating layer PVX2.

[0197] Reference Figure 22 to Figure 29 The display substrate provided in this embodiment can be prepared by the following steps:

[0198] Step 31: Form a patterned first conductive layer M1 on the substrate 10, such as Fig. 22 As shown, the first conductive layer M1 includes the data line DL, and may also include a shielding pattern (not shown in the figure), and the orthographic projection of the shielding pattern on the substrate 10 covers the channel region CH.

[0199] Step 32: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, such as Fig.23 As shown. The semiconductor layer ACT is a transparent material, including semiconductor patterns located in different sub-pixels PX, the semiconductor patterns overlap with the orthographic projection of the data line DL on the substrate 10, and the semiconductor patterns include a source connection area S, a first conductor area DT1, a second conductor area DT2, a channel area CH, a fourth conductor area DT4, a third conductor area DT3, a drain connection area D and a fifth conductor area DT5 (i.e., a first pixel electrode EP1) arranged along a first direction f1 and connected in sequence, and the fifth conductor area DT5 constitutes the first pixel electrode EP1 and overlaps with the first common electrode EC1.

[0200] Step 33: Form a patterned first insulating layer GI on the side of the semiconductor layer ACT facing away from the substrate 10, such as Fig.24As shown, a first via hole H1 and a second via hole H2 are provided on the first insulating layer GI. The first via hole H1 and the second via hole H2 are located on both sides of the channel region CH. The first via hole H1 exposes a portion of the data line DL, the source connection region S and the first conductor region DT1, and the second via hole H2 exposes the drain connection region D.

[0201] Step 34: Form a patterned second conductive layer M2 on the side of the first insulating layer GI facing away from the substrate 10, such as Fig.25 As shown, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a second transfer pattern ZJ2. The gate G is connected to one side of the scan line GL, and the gate G overlaps with the channel region CH. The first transfer pattern ZJ1 half covers the first via hole H1 and is respectively connected to the data line DL and the source connection region S. The second transfer pattern ZJ2 half covers the second via hole H2 and is connected to the drain connection region D.

[0202] After forming the second conductive layer M2, the first insulating layer GI can be etched twice using the second conductive layer M2 as a mask, and then the semiconductor material in the exposed area (such as the first conductive area DT1, the second conductive area DT2, the third conductive area DT3, the fourth conductive area DT4, and the fifth conductive area DT5) in the semiconductor layer ACT can be conductorized using a self-alignment process using the second conductive layer M2 as a mask. The conductorization process can, for example, use dry etching equipment or ion implantation equipment to inject plasma (such as plasma containing at least one element of helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or use an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductorization. Among them, the use of dry etching equipment to conduct the semiconductor material can be performed simultaneously with the secondary etching process of the first insulating layer GI, thereby simplifying the process.

[0203] Step 35: Deposit a second insulating material on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer, and then apply an organic insulating material to form an organic insulating material layer. Then, pattern the organic insulating material layer to form an organic insulating layer RS, such as Fig.26 As shown, an opening RH3 is provided on the organic insulating layer RS, and the opening RH3 is used to expose the first pixel electrode EP1 and the second transfer pattern ZJ2 thereon.

[0204] Step 36: forming a patterned third conductive layer M3 on the side of the organic insulating layer RS ​​facing away from the substrate 10, such as Fig. 27 As shown, the third conductive layer M3 includes a common electrode EC of the first common electrode EC1 and the second common electrode EC2 , and the common electrode EC has no overlap with the second switching pattern ZJ2 .

[0205] Step 37: Form a patterned third insulating layer PVX2 on the side of the third conductive layer M3 facing away from the substrate 10, such as Fig.28 As shown, a via hole H5 is provided on the third insulating layer PVX2 , and the via hole H5 penetrates the second insulating layer PVX1 to expose the second transfer pattern ZJ2 .

[0206] Step 38: Form a patterned transparent conductive layer TD on the side of the third insulating layer PVX2 facing away from the substrate 10, such as Fig.29 As shown, the transparent conductive layer TD includes a second pixel electrode EP2 located in a different sub-pixel PX. The second pixel electrode EP2 covers a via hole located on the second switching pattern ZJ2 and is connected to the second switching pattern ZJ2 and further connected to the first pixel electrode EP1.

[0207] The present disclosure provides a display device, such as Fig.31 As shown, the display device includes an opposing substrate 171, an electrophoretic solution 172, and a display substrate 173 provided in any embodiment, the electrophoretic solution 172 is located between the opposing substrate 171 and the display substrate 173, and the second conductive layer M2 is located on a side of the substrate 10 close to the electrophoretic solution.

[0208] The electrophoretic solution 172 includes target particles LZ. The target particles may be electrophoretic particles, such as two-color particles, three-color particles, or four-color particles, etc., or may be liquid crystal molecules.

[0209] Those skilled in the art can understand that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate 173 .

[0210] The display device provided by the present disclosure can be: electronic paper, electronic price tags, electronic work badges, display modules, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, car display devices, smart watches, fitness wristbands, personal digital assistants, and any other products or components with display functions.

[0211] Exemplarily, the counter substrate 171 includes: a counter substrate 1711 , and a counter electrode 1712 disposed on a side of the counter substrate 1711 close to the electrophoretic solution 172 , and the counter electrode 1712 and the pixel electrodes EP1 / EP2 together form an electric field for driving the target particles LZ to move.

[0212] Exemplarily, the electrophoretic solution 172 may be an electronic paper film.

[0213] For example, Fig.32 As shown, the display device may further include a driving chip IC bound to the non-display area NA of the display substrate 173 , and the driving chip IC is connected to the driving circuit board 182 via the flexible circuit board 181 .

[0214] In the process of displaying the picture, the driving chip IC can be started through the driving circuit board 182. The driving chip IC inputs the scanning signal to the scanning line GL and the data signal to the data line DL, turns on the thin film transistor, and the pixel electrode EP1 / EP2 of the sub-pixel PX obtains the voltage required for the picture, and forms a voltage difference with the upper opposing electrode 1712, thereby separating the white particles and the black particles in the electrophoretic solution 172, and then forming different display grayscale states.

[0215] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0216] In the present disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0217] In this specification, "electrically connected" and "coupled" include the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0218] In the present disclosure, "plurality" means two or more, and "at least one" means one or more, unless otherwise clearly and specifically defined. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0219] The use of "for" or "configured to" in this disclosure is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0220] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0221] As used in the present disclosure, "parallel", "perpendicular", "equal", and "level" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 10° or 5°.

[0222] "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equals is less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein the acceptable deviation range of approximate flush can be, for example, the distance between the two flushes is less than or equal to 5% of either one.

[0223] It should be understood that when a layer or an element is referred to as being disposed on one side of another layer or substrate, the layer or element may be directly disposed on the other layer or substrate, or an intervening layer may be present between the layer or element and the other layer or substrate.

[0224] The present disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the present disclosure, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display substrate, comprising a display area and a non-display area surrounding the display area, wherein the display area comprises a plurality of sub-pixels, and the sub-pixels comprise thin film transistors; The display substrate comprises: A substrate, and a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer stacked in sequence on one side of the substrate, wherein the first conductive layer is arranged close to the substrate, the first conductive layer includes a data line, the semiconductor layer includes a plurality of semiconductor patterns located in different sub-pixels, the semiconductor patterns include a source connection region, a first conductor region and a channel region of the thin film transistor, the source connection region, the first conductor region and the channel region are arranged along a first direction and connected in sequence, and the second conductive layer includes a first transfer pattern, a scan line and a gate of the thin film transistor; A first via is provided on the first insulating layer, and the first via exposes a portion of the data line, the source connection area and the first conductor area. The data line and the source connection area are respectively overlapped with the first transfer pattern through the first via, and the first transfer pattern and the first conductor area have no overlap in their orthographic projection on the substrate.

2. The display substrate according to claim 1, wherein: The semiconductor pattern further includes: The second conductor region is connected between the first conductor region and the channel region, the thickness of the first conductor region is less than the thickness of the second conductor region, the thickness of the first conductor region is less than or equal to the thickness of the source connection region, and the thickness of the second conductor region is less than or equal to the thickness of the channel region.

3. The display substrate according to claim 1, wherein: The semiconductor pattern further includes: The drain connection region, the third conductor region and the fourth conductor region of the thin film transistor, the channel region, the fourth conductor region, the third conductor region and the drain connection region are arranged along the first direction and connected in sequence, and the thickness of the third conductor region is less than the thickness of the fourth conductor region; The second conductive layer also includes a second transfer pattern, which is located on a side of the gate away from the first transfer pattern. A second via is also provided on the first insulating layer, and the second via exposes the drain connection area and the third conductor area. The second transfer pattern is overlapped with the drain connection area through the second via, and the orthographic projections of the second transfer pattern and the third conductor area on the substrate do not overlap.

4. The display substrate according to claim 3, wherein: The sub-pixel further includes a common electrode and a first pixel electrode, the second transfer pattern overlaps with an orthographic projection of the common electrode on the substrate, and the second transfer pattern constitutes the first pixel electrode.

5. The display substrate according to claim 3, wherein: The sub-pixel further includes a common electrode and a first pixel electrode, and the second transfer pattern has no overlap with the orthographic projection of the common electrode on the substrate; The semiconductor pattern further includes: a fifth conductor region, located at a side of the drain connection region away from the channel region and connected to the drain connection region, the fifth conductor region overlaps with the positive projection of the common electrode on the substrate, and the fifth conductor region constitutes the first pixel electrode.

6. The display substrate according to any one of claims 1 to 5, wherein: The sub-pixel further includes a first common electrode, a first pixel electrode, a second common electrode, and a second pixel electrode, the first pixel electrode is located in the semiconductor layer or the second conductive layer, the first common electrode and the first pixel electrode are arranged in different layers and their orthographic projections on the substrate overlap, and the display substrate further includes: a third conductive layer, disposed on a side of the second conductive layer away from the substrate, and comprising the second common electrode; and A transparent conductive layer is arranged on the side of the third conductive layer away from the substrate, including the second pixel electrode, the second pixel electrode and the second common electrode have overlapping positive projections on the substrate, the second pixel electrode is connected to the first pixel electrode through a via hole, and the first pixel electrode is also connected to the drain connection area of ​​the thin film transistor.

7. The display substrate according to claim 6, wherein: The first pixel electrode includes a plurality of sub-electrodes, which are arranged along a second direction and connected in sequence, the second direction intersects with the first direction, and different sub-electrodes have different widths along the first direction.

8. The display substrate according to claim 7, wherein: Along the second direction and in a direction away from the channel region, the widths of the plurality of sub-electrodes along the first direction increase sequentially.

9. The display substrate according to claim 7, wherein: In an orthographic projection on the substrate, the plurality of sub-electrodes are substantially aligned away from edges of the channel region.

10. The display substrate according to claim 7, wherein: The first common electrode is located on the first conductive layer, and the first common electrode is located between two adjacent data lines; The second conductive layer also includes a third transfer pattern, which is located on a side of the first transfer pattern and the gate away from the scanning line. The second common electrode and the first common electrode are respectively connected to the third transfer pattern through vias, and the third transfer pattern has no overlap with the orthographic projection of the first pixel electrode on the substrate.

11. The display substrate according to claim 10, wherein: The plurality of sub-electrodes include a first sub-electrode, a second sub-electrode and a third sub-electrode connected in sequence, the first sub-electrode being connected to the drain connection region of the thin film transistor and being located on a side of the drain connection region away from the channel region; In the orthographic projection on the substrate, the second sub-electrode and the third switching pattern are arranged along the first direction, the first common electrode overlaps with the second sub-electrode and the third sub-electrode respectively, and the first common electrode does not overlap with the first sub-electrode.

12. The display substrate according to claim 11, wherein: The third conductive layer further comprises: A fourth transfer pattern, wherein the fourth transfer pattern and the second common electrode are separated from each other, the second sub-electrode and the second pixel electrode are respectively connected to the fourth transfer pattern through vias, and in the orthographic projection on the substrate, the fourth transfer pattern is located in the area of ​​the second sub-electrode.

13. The display substrate according to claim 7, wherein: The first common electrode is located in the third conductive layer, and the first common electrode and the second common electrode share the same electrode; The second conductive layer further includes a second transfer pattern, the second transfer pattern is located at a side of the gate away from the first transfer pattern, and the second transfer pattern is used to connect the first pixel electrode and the second pixel electrode; In an orthographic projection on the substrate, the same electrode covers the first transfer pattern and the gate and has no overlap with the second transfer pattern.

14. The display substrate according to claim 13, wherein: The first pixel electrode is located in the semiconductor layer, the plurality of sub-electrodes include a fourth sub-electrode and a fifth sub-electrode connected in sequence, the fourth sub-electrode is connected to the drain connection region of the thin film transistor, and is located on a side of the drain connection region away from the channel region; In the orthographic projection on the substrate, the second switching pattern is located within the range of the fourth sub-electrode, and the same electrode overlaps with the edge of the fourth sub-electrode close to the channel region and the fifth sub-electrode respectively.

15. The display substrate according to claim 13, wherein: The display substrate comprises: a second insulating layer, disposed between the second conductive layer and the third conductive layer; and An organic insulating layer is disposed between the second insulating layer and the third conductive layer, wherein the organic insulating layer and the orthographic projection of the first pixel electrode on the substrate at least partially do not overlap.

16. The display substrate according to claim 6, wherein: In the orthographic projection on the substrate, the first pixel electrode and the second pixel electrode have no overlap with the scanning line respectively, the first pixel electrode is located in the area of ​​the second pixel electrode, and the gap width between the second pixel electrodes of two adjacent sub-pixels is greater than or equal to 5 microns and less than or equal to 15 microns.

17. The display substrate according to claim 6, wherein: In the orthographic projection on the substrate, the first common electrode and the second common electrode have no overlap with the data line respectively, the second common electrode has an overlapping area with the scan line, and the width of the overlapping area along the first direction is smaller than the width of the non-overlapping area along the first direction.

18. A display device comprising: An opposing substrate, an electrophoretic solution, and a display substrate as claimed in any one of claims 1 to 17, wherein the electrophoretic solution is located between the opposing substrate and the display substrate, and the second conductive layer is located on a side of the substrate close to the electrophoretic solution.

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