Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display. The display panel at least comprises a substrate, a first conductive layer, a second conductive layer and a third conductive layer which are sequentially stacked, the first wire is located on the first conductive layer; in the overline area, the second routing line comprises a first routing line section, a second routing line section and a third routing line section which are connected in sequence; wherein the first wiring section and the third wiring section are both located on the second conductive layer, and the second wiring section is located on the third conductive layer and electrically connected with the first wiring section and the third wiring section through via holes; the orthographic projection of the first wiring section and the orthographic projection of the third wiring section on the substrate are located on the two sides of the orthographic projection of the first conductive layer on the substrate respectively; the second wiring section and the first conductive layer are arranged in an overlapping manner.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the display industries such as OLED, LCD, and MLED, a signal circuit needs to be formed on the backplane to realize the driving function of the device; usually, metal layers such as the gate layer (Gate layer), the source and drain metal layer (SD layer), and the shield layer (Shield layer) are often used as signal routing due to their good conductivity, and are switched or overlapped at locations where they need to be interspersed. Since the thicker the signal line, the lower the resistance, the metal layer is often made thicker in order to ensure the uniformity of the panel when pursuing high PPI and high refresh rate. However, the thicker the metal, the obvious step difference will result, which can easily cause poor coverage of the passivation layer PVX at the adjacent stacked lines, leading to short circuits, especially when the voltage difference between the two overlapping layers of routing is large, which will lead to a high incidence of display panel defects.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device, which can improve the yield of the display panel by increasing the step difference between two adjacent layers of wiring in the cross-line area.

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising a first wiring and a second wiring; the display panel at least comprises a base substrate, a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence;

[0006] The first wiring is located in the first conductive layer;

[0007] The display panel has at least one cross-line area; in the cross-line area, the second routing includes a first routing segment, a second routing segment and a third routing segment connected in sequence; wherein the first routing segment and the third routing segment are both located in the second conductive layer, and the second routing segment is located in the third conductive layer and is electrically connected to the first routing segment and the third routing segment through a via;

[0008] The orthographic projections of the first routing segment and the third routing segment on the base substrate are respectively located on both sides of the orthographic projection of the first conductive layer on the base substrate; the second routing segment is arranged to overlap with the first conductive layer.

[0009] In an exemplary embodiment of the present disclosure, the second routing segment has a second routing segment end and a second routing segment overlapping portion overlapping the first routing segment; the step difference between the second routing segment overlapping portion and the substrate is greater than the step difference between the second routing segment end and the substrate.

[0010] In an exemplary embodiment of the present disclosure, the step difference between the overlapping portion of the second routing segment and the base substrate is 1 to 2 micrometers greater than the step difference between the end portion of the second routing segment and the base substrate.

[0011] In an exemplary embodiment of the present disclosure, the first routing line has an overlapping portion of the first routing line that overlaps with the overlapping portion of the second routing line segment, and the step difference between the surface of the overlapping portion of the first routing line away from the substrate and the surface of the overlapping portion of the second routing line segment close to the substrate is not less than 3 microns.

[0012] In an exemplary embodiment of the present disclosure, in the cross-line region, the display panel is provided with a cross-line insulation unit between the second conductive layer and the third conductive layer;

[0013] The second routing segment is formed on a surface of the cross-line insulation unit away from the substrate;

[0014] Along the extension direction of the second routing line, the cross-line insulation unit includes a first cross-line insulator unit, a second cross-line insulator unit and a third cross-line insulator unit in sequence; the first cross-line insulator unit is provided with a first via hole, and the third cross-line insulator unit is provided with a second via hole; the second routing segment is electrically connected to the first routing segment through the first via hole, and is electrically connected to the third routing segment through the second via hole; the second cross-line insulator unit is overlapped with the first routing line; the second cross-line insulator unit has a protruding structure protruding from the plane where the first cross-line insulator unit and the third cross-line insulator unit are located.

[0015] In an exemplary embodiment of the present disclosure, the slope angle of the second cross-line insulator unit does not exceed 45°.

[0016] In an exemplary embodiment of the present disclosure, the first cross-line insulator unit, the second cross-line insulator unit and the third cross-line insulator unit are located in the same organic layer.

[0017] In an exemplary embodiment of the present disclosure, the second cross-line insulator unit includes a first main structure and a first protruding structure located on a side of the first main structure away from the substrate base, the first main structure and the first cross-line insulator unit and the third cross-line insulator unit are located in the same organic layer, and the first protruding structure is located in another organic layer.

[0018] In an exemplary embodiment of the present disclosure, the second cross-line insulator unit includes a second protruding structure and a second main body structure covering the second protruding structure;

[0019] The second main body structure, the first cross-line insulator unit, and the third cross-line insulator unit are located in one organic layer; and the second protruding structure is located in another organic layer.

[0020] In an exemplary embodiment of the present disclosure, the first routing segment has a first branch routing line arranged in parallel with the first routing line, and the third routing segment has a second branch routing line arranged in parallel with the first routing line;

[0021] The second routing segment includes a plurality of branch routings arranged side by side; one end of the branch routing is electrically connected to the first branch routing through a via, and the other end of the branch routing is electrically connected to the second branch routing through a via.

[0022] In an exemplary embodiment of the present disclosure, in the second routing line, the width of the branch routing line is not less than the width of the first routing line segment and the width of the third routing line segment.

[0023] In an exemplary embodiment of the present disclosure, in the second routing segment, the total number of the branch routing lines is no less than 6.

[0024] In an exemplary embodiment of the present disclosure, in each branch routing of the second routing segment, a spacing between outer edges of two branch routings on both sides is not less than 20 times the width of the first routing segment.

[0025] In an exemplary embodiment of the present disclosure, the base substrate further comprises one or more gate layers, one or more source / drain metal layers and a pixel electrode layer sequentially stacked on one side of the base substrate;

[0026] The first conductive layer is a gate layer, the second conductive layer is a source-drain metal layer, and the third conductive layer is a pixel electrode layer.

[0027] In an exemplary embodiment of the present disclosure, the pixel electrode layer includes a first conductive metal oxide layer, a metal layer, and a second conductive metal oxide layer which are sequentially stacked; wherein the metal layer is between 50 nm and 1000 nm.

[0028] In an exemplary embodiment of the present disclosure, the display panel includes a display area and a first peripheral area located at least on one side of the display area; a gate driving circuit for driving a pixel driving circuit in the display area is provided in the first peripheral area, and the gate driving circuit includes a plurality of shift registers arranged in sequence along a column direction;

[0029] The first wiring is disposed in the first peripheral area and extends along a row direction;

[0030] The second wiring is disposed in the first peripheral area and extends along a row direction.

[0031] In an exemplary embodiment of the present disclosure, the display panel has a first driving line for loading a first driving signal to a shift register and a second driving line for loading a second driving signal to the shift register in the first peripheral area, the first driving line and the second driving line extend along the column direction, and the second driving line is located between the first driving line and the shift register;

[0032] One end of the second wiring is electrically connected to the first driving wiring, and the other end is electrically connected to the shift register; the second driving wiring is arranged as the first wiring and overlaps with the second wiring in the cross-line area.

[0033] In an exemplary embodiment of the present disclosure, one of the first driving signal and the second driving signal is a high-level voltage signal, and the other is a low-level voltage signal.

[0034] According to another aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0037] Figure 1 It is a schematic cross-sectional view of a cross-line region of a display panel in one embodiment of the present disclosure.

[0038] Figure 2 It is a cross-sectional schematic diagram of a display area of ​​a display panel in one embodiment of the present disclosure.

[0039] Figure 3 FIG. 1 is a schematic top view of a display panel in one embodiment of the present disclosure.

[0040] Figure 4 FIG. 1 is a schematic top view of a display panel in one embodiment of the present disclosure.

[0041] Figure 5FIG. 1 is a schematic top view of a display panel in one embodiment of the present disclosure.

[0042] Figure 6 It is a cross-sectional schematic diagram of a cross-line area of ​​a display panel in the related art.

[0043] Figure 7 It is a schematic cross-sectional view of a cross-line region of a display panel in one embodiment of the present disclosure.

[0044] Figure 8 It is a schematic cross-sectional view of a cross-line region of a display panel in one embodiment of the present disclosure.

[0045] Fig. 9 It is a schematic cross-sectional view of a cross-line region of a display panel in one embodiment of the present disclosure.

[0046] Fig.10 It is a partial top view schematic diagram of a cross-line area of ​​a display panel in one embodiment of the present disclosure.

[0047] The reference numerals are as follows:

[0048] AA, display area; ANL, pixel electrode layer; BB1, first peripheral area; Buffer, buffer layer; CA, cross-line area; COML, common electrode layer; DA, cross-line insulation unit; DA1, first cross-line insulator unit; DA2, second cross-line insulator unit; DA21, second convex structure; DA22, second main structure; DA2D, first convex structure; DA2M, first main structure; DA2X, convex structure; DA3, third cross-line insulator unit; DH, row direction; DV, column direction; EL, organic light-emitting functional layer; FA, drive circuit layer; FB, pixel layer; GI, gate insulation layer; GOA, gate drive circuit; GT, gate layer; GT1, first gate layer; GT2, second gate layer; H1, first via hole; H2, second via hole; ITO1, first conductive metal oxide layer; ITO2, second conductive metal oxide layer Material layer; L1, first drive line; L2, second drive line; LA, first line; LA1, overlapping part of first line; LB, second line; LB1, first line segment; LB1D, first branch line; LB2, second line segment; LB2A, second line segment end; LB2B, overlapping part of second line segment; LB2S, branch line; LB3, third line segment; LB3D, second branch line; LS, metal shading layer; ML1, first conductive layer; ML2, second conductive layer; ML3, third conductive layer; PDC, pixel drive circuit; PDL, pixel definition layer; PNL, display panel; PVX1, first passivation layer; PVX2, second passivation layer; SBT, substrate; SCL, semiconductor layer; SD, source and drain metal layer; SR, shift register; CF, color filter layer; PLN1, first planarization layer; PLN2, second planarization layer. DETAILED DESCRIPTION

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0050] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0051] The present disclosure provides a display panel PNL, such as Figure 1 As shown, the display panel PNL includes a first line LA and a second line LB; the display panel PNL at least includes a base substrate SBT, a first conductive layer ML1, a second conductive layer ML2 and a third conductive layer ML3 which are stacked in sequence. The first line LA is located on the first conductive layer ML1; the display panel PNL has at least one cross-line area CA; in the cross-line area CA, the second line LB includes a first line segment LB1, a second line segment LB2 and a third line segment LB3 which are connected in sequence. Wherein, the first line segment LB1 and the third line segment LB3 are both located on the second conductive layer ML2, the second line segment LB2 is located on the third conductive layer ML3 and is electrically connected to the first line segment LB1 and the third line segment LB3 through a via. The orthographic projections of the first line segment LB1 and the third line segment LB3 on the base substrate SBT are respectively located on both sides of the orthographic projection of the first conductive layer ML1 on the base substrate SBT; the second line segment LB2 is overlapped with the first conductive layer ML1. In the related art, a short circuit is prone to occur at the position where the second routing line LB overlaps with the first routing line LA. In the embodiment disclosed herein, the second routing line LB includes a first routing segment LB1, a second routing segment LB2, and a third routing segment LB3, wherein the orthographic projections of the first routing segment LB1 and the third routing segment LB3 on the substrate substrate SBT are respectively located on both sides of the orthographic projection of the first routing line LA on the substrate substrate SBT, and the second routing segment LB2 is located on the third conductive layer ML3, and the second routing segment LB2 is electrically connected to the first routing segment LB1 and the third routing segment LB3 through vias, respectively. In this way, the second routing segment LB2 of the second routing line LB is set on the third conductive layer ML3 in the cross-line area CA, thereby increasing the step difference between the first routing line LA and the second routing line LB in the cross-line area CA, thereby avoiding a short circuit caused by poor coverage of the insulating layer, and especially reducing the occurrence of poor display panel conditions caused by excessive voltage difference between the first routing line LA and the second routing line LB.

[0052] In one embodiment of the present disclosure, the second routing segment LB2 has a second routing segment end LB2A and a second routing segment overlapping portion LB2B overlapping the first routing LA; the step difference between the second routing segment overlapping portion LB2B and the substrate SBT is greater than the step difference between the second routing segment end LB2A and the substrate SBT. In this embodiment, the step difference between the first routing LA and the second routing LB at the overlapping position can be further increased, thereby further increasing the thickness of the insulating layer between the first routing LA and the second routing segment overlapping portion LB2B, and further reducing the risk of short circuit between the first routing LA and the second routing LB in the cross-line area CA.

[0053] As follows, the structure of the display panel PNL of the present disclosure is exemplarily described with reference to the accompanying drawings.

[0054] In one embodiment of the present disclosure, see Figure 2 The display panel includes a base substrate SBT, a driving circuit layer FA and a pixel layer FB which are stacked in sequence; the pixel layer is provided with sub-pixels; the driving circuit layer FA is provided with a pixel driving circuit for driving the sub-pixels.

[0055] The substrate substrate SBT may be a substrate substrate SBT of an inorganic material, or a substrate substrate SBT of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate substrate SBT may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate substrate SBT may be polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In another embodiment of the present disclosure, the substrate substrate SBT may also be a flexible substrate substrate, for example, the material of the substrate substrate SBT may be polyimide (PI). The substrate SBT may also be a composite of multiple layers of materials. For example, in one embodiment of the present disclosure, the substrate SBT may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0056] The driving circuit layer FA is provided with a pixel driving circuit for driving sub-pixels. In the driving circuit layer FA, any pixel driving circuit may include a transistor and a storage capacitor. In one example, the driving circuit layer is provided with a polysilicon semiconductor layer and / or a metal oxide semiconductor layer, so that the transistors in the driving circuit layer include at least metal oxide transistors and / or polysilicon transistors (e.g., low-temperature polysilicon transistors). Further, these transistors may be thin film transistors. Of course, in other embodiments of the present disclosure, polysilicon transistors may also be amorphous silicon transistors; accordingly, the polysilicon semiconductor layer of the driving circuit layer FA may be replaced by an amorphous silicon semiconductor layer.

[0057] In one embodiment of the present disclosure, the polysilicon transistor may be a top-gate thin film transistor, a bottom-gate thin film transistor or a dual-gate thin film transistor, whichever is more effective in controlling the transistor. The metal oxide transistor may be a dual-gate thin film transistor, that is, the channel region of the transistor is sandwiched between the top gate (the gate on the side away from the substrate) and the bottom gate (the gate on the side close to the substrate); in this way, the bottom gate may block light from the side of the substrate to prevent light from irradiating the channel region of the transistor and causing abnormal operation of the transistor. Of course, the metal oxide transistor may also be a top-gate thin film transistor or a bottom-gate thin film transistor.

[0058] In some embodiments of the present disclosure, the gate of the polysilicon transistor can be arranged in the same layer as a gate of the metal oxide transistor, for example, the gate of the polysilicon transistor and the bottom gate of the metal oxide transistor are arranged in the same gate layer. In other embodiments, the gate of the polysilicon transistor and the top gate and the bottom gate of the metal oxide transistor can be arranged in different gate layers respectively.

[0059] In one embodiment of the present disclosure, the driving circuit layer includes multiple metal layers, one of which can be used as the first conductive layer ML1, and another metal layer can be used as the second conductive layer ML2, and the second conductive layer ML2 is located on the side of the first conductive layer ML1 away from the substrate SBT. Furthermore, the third conductive layer ML3 can be located in the pixel layer. Of course, in other embodiments of the present disclosure, the third conductive layer ML3 can also be located in the driving layer.

[0060] As an example, see Figure 2, the driving circuit layer FA includes a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, a first passivation layer PVX1, a source-drain metal layer SD, and a second passivation layer PVX2 which are sequentially stacked on one side of the substrate SBT. Among them, the semiconductor layer SCL is a metal oxide semiconductor layer, the metal oxide semiconductor layer is provided with an active area of ​​a metal oxide transistor, and the gate layer GT is provided with a gate of a metal oxide transistor. In the present disclosure, the active area of ​​the transistor includes a channel area of ​​the transistor and a source and a drain located on both sides of the channel area; wherein the channel area maintains semiconductor characteristics, and the source and the drain are conductorized. In the present disclosure, the source-drain metal layer SD can be one layer, or two layers, or three layers. Figure 3 In the example, the source-drain metal layer SD is a layer, including the source-drain metal layer SD arranged on the side of the gate layer GT away from the substrate SBT.

[0061] Exemplarily, the gate layer GT material may be one or more of Mo (molybdenum), Ti (titanium), Al (aluminum), Nd (neodymium), Cu (copper), or alloys of the above materials. The gate layer GT may be a single-layer structure or a composite structure formed by multiple layers. Exemplarily, the gate layer GT has a thickness of 400nm-800nm.

[0062] Exemplarily, the material of the first passivation layer PVX1 may be SiNx or SiOx, or a composite layer formed by the two, with a thickness of 400nm-800nm.

[0063] Exemplarily, the material of the second passivation layer PVX2 may be SiNx or SiOx, or a composite layer formed by the two, with a thickness of 400nm-800nm.

[0064] In one example, see Figure 2 The driving circuit layer FA of the display panel PNL includes a gate layer GT, a source-drain metal layer SD and other metal layers stacked in sequence; the first gate layer GT1 can be used as ML1 for setting the first wiring LA; the second gate layer GT2 can be used as the second conductive layer ML2 for setting the first wiring segment LB1 and the third wiring segment LB3.

[0065] In another example, the display panel PNL includes a base substrate SBT and a plurality of gate layers GT and a plurality of source-drain metal layers SD stacked in sequence on one side of the base substrate SBT. The first conductive layer ML1 may be one of the gate layers GT, and the second conductive layer ML2 may be one of the source-drain metal layers SD. Alternatively, the first conductive layer ML1 may be one of the gate layers GT, and the second conductive layer ML2 may be another gate layer GT on the side of the gate layer GT away from the base substrate SBT. Alternatively, the first conductive layer ML1 may be one of the source-drain metal layers SD, and the second conductive layer ML2 may be another source-drain metal layer SD on the side of the source-drain metal layer SD away from the base substrate SBT.

[0066] In one example, the driving circuit layer FA may further include a buffer layer Buffer disposed between the substrate SBT and the semiconductor layer SCL, and the semiconductor layer SCL and the gate layer GT are located on the side of the buffer layer Buffer away from the substrate SBT. The material of the buffer layer Buffer may be an inorganic insulating material such as silicon oxide and silicon nitride. The buffer layer Buffer may be a single inorganic material layer or a multi-layered inorganic material layer.

[0067] In one example, the driving circuit layer FA may also include a metal shading layer LS located between the buffer layer Buffer and the substrate SBT, and the metal shading layer LS may shield at least part of the channel region of the transistor. Furthermore, in some embodiments, the metal shading layer LS may be electrically connected to the source and drain metal layer through vias, so that the metal shading layer LS may transmit signals, shield signals or perform other functions as needed. For example, the metal shading layer LS may be loaded with a common electrode voltage so that the metal shading layer LS can achieve the function of signal shielding. For another example, a portion of the metal shading layer LS is patterned into a conductive wire so that the conductive wire located in the metal shading layer LS can be used to transmit signals, such as transmitting touch signals.

[0068] Exemplarily, the metal light shielding layer LS may be one or more of Mo (molybdenum), Ti (titanium), Al (aluminum), Nd (neodymium), Cu (copper), or alloys of the above materials. The metal light shielding layer LS may be a single-layer structure or a composite structure formed by multiple layers. Exemplarily, the thickness of the metal light shielding layer LS is 400nm-800nm.

[0069] In an example, the metal light-shielding layer LS may also serve as the first conductive layer ML1 , and thus the second conductive layer ML2 may be a gate layer GT or a source-drain metal layer SD.

[0070] See also Figure 2 and Figure 3, the pixel layer FB is provided with array-distributed light-emitting elements, and each light-emitting element emits light under the control of the pixel driving circuit. These light-emitting elements can be used as sub-pixels in the embodiments of the present disclosure. In the present disclosure, the light-emitting element can be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic light-emitting diode (QD-OLED), a quantum dot light-emitting diode (QLED) or other types of light-emitting elements. For example, see Figure 2 In one embodiment of the present disclosure, the light emitting element is an organic light emitting diode (OLED), and the display panel is an OLED display panel. As follows, taking the light emitting element as an organic light emitting diode as an example, a feasible structure of the pixel layer FB is exemplarily introduced.

[0071] In this example, the pixel layer FB can be arranged on the side of the driving circuit layer FA away from the base substrate SBT, which may include a pixel electrode layer ANL, a pixel definition layer PDL, a support column layer, an organic light-emitting functional layer EL and a common electrode layer COML stacked in sequence. Among them, the pixel electrode layer ANL has a plurality of pixel electrodes in the display area of ​​the display panel PNL; the pixel definition layer PDL has a plurality of through pixel openings arranged one by one corresponding to the plurality of pixel electrodes in the display area, and any pixel opening exposes at least a portion of the corresponding pixel electrode. The support column layer includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer PDL away from the base substrate SBT so as to support the fine metal mask (FineMetal Mask, FMM) in the evaporation process. The organic light-emitting functional layer EL at least covers the pixel electrode exposed by the pixel definition layer PDL. Among them, the organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. Each film layer of the organic light-emitting functional layer EL can be prepared by an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation. The common electrode layer COML can cover the organic light-emitting functional layer EL in the display area. In this way, the pixel electrode, the common electrode layer COML and the organic light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML form an organic electroluminescent diode, and any organic electroluminescent diode can be used as a sub-pixel of the display panel.

[0072] Optionally, the display panel PNL may further include a color filter layer CF, which may be disposed on a side of the pixel layer FB away from the substrate SBT (top emission), or on a side of the pixel layer FB close to the substrate SBT (bottom emission). Figure 2In the example, the color filter layer CF is arranged on the side of the driving circuit layer FA away from the base substrate SBT, and a planarization layer PLN is arranged on the side of the color filter layer CF away from the base substrate SBT. The planarization layer PLN is arranged on the side of the color filter layer CF away from the base substrate SBT to provide a planarized surface for the pixel electrode of the pixel layer FB.

[0073] For example, Figure 1 and Figure 2 As shown, the pixel electrode layer ANL can serve as the third conductive layer ML3.

[0074] In one example, the pixel electrode layer ANL includes a first conductive metal oxide layer ITO1 layer, a metal layer, and a second conductive metal oxide layer ITO2 layer stacked in sequence. Optionally, the material of the metal layer in the pixel electrode layer ANL may be silver or aluminum.

[0075] In one example, the material of the metal layer in the pixel electrode layer ANL may be Ag, with a thickness between 50 nm and 1000 nm. For example, the metal layer in the pixel electrode layer ANL is Ag, with a thickness of 500 nm.

[0076] Optionally, the display panel PNL may further include a thin film encapsulation layer. The thin film encapsulation layer is disposed on the surface of the pixel layer FB away from the substrate SBT, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. Among them, the inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the organic light-emitting functional layer EL and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve flattening and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer FB away from the substrate SBT. The first inorganic encapsulation layer covers the display area and extends to the outside of the retaining wall; the organic encapsulation layer covers the display area and extends to the inside of the retaining wall; the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the retaining wall. On the outside of the retaining wall, the second inorganic encapsulation layer contacts the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first and second inorganic encapsulation layers, and the stress of the first and second inorganic encapsulation layers is balanced. The first and second inorganic encapsulation layers enclose the organic encapsulation layer, isolating the organic encapsulation layer from contact with water and oxygen.

[0077] In one embodiment of the present disclosure, see Figure 3 The display panel PNL includes a display area AA and a first peripheral area BB1 located at at least one side of the display area AA. Figure 4As shown, a gate driving circuit GOA for driving a pixel driving circuit PDC in a display area AA is provided in a first peripheral area BB1 of a display panel PNL, and the gate driving circuit GOA includes a plurality of shift registers SR arranged in sequence along a column direction DV. The first wiring LA is provided in the first peripheral area BB1 and extends along a column direction DV; the second wiring LB is provided in the first peripheral area BB1 and extends along a row direction DH. That is, the intersection of the first wiring LA extending along the column direction DV and the second wiring LB extending along the row direction DH forms a cross-line area CA. In the cross-line area, the orthographic projection of the first wiring LA on the substrate substrate SBT at least partially overlaps with the orthographic projection of the second wiring LB on the substrate substrate SBT.

[0078] In one embodiment of the present disclosure, Figure 5 As shown, the display panel PNL has a first drive line L1 for loading a first drive signal to a shift register SR and a second drive line L2 for loading a second drive signal to the shift register SR in the first peripheral area BB1, the first drive line L1 and the second drive line L2 extend along the column direction DV, and the second drive line L2 is located between the first drive line L1 and the shift register SR. One end of the second line LB is electrically connected to the first drive line L1, and the other end is electrically connected to the shift register SR; the second drive line L2 is arranged as a first line LA and overlaps with the second line LB in the cross-line area CA.

[0079] like Figure 6 As shown, in the related art, the thickness of the conductive layer is large, so that the sealing layer of the boundary area of ​​the cross-line area CA is poorly covered, which easily leads to a short circuit of the metal traces (such as the first trace LA and the second trace LB) in the two overlapping conductive layers. In particular, when the voltage between the two overlapping traces is large, the metal traces in the cross-line area are more likely to short-circuit. In the embodiment of the present disclosure, the cross-line area CA adopts Figure 1 In the manner shown, part of the second wiring LB in the cross-line area is arranged in the third conductive layer ML3, thereby increasing the step difference between the first wiring LA and the second wiring LB, and avoiding short circuits in the cross-line area due to poor coverage.

[0080] Exemplarily, one of the first drive signal and the second drive signal is a high-level voltage signal, and the other is a low-level voltage signal. In this example, the routing line loaded with the high-level voltage signal overlaps with the routing line loaded with the low-level voltage signal in the cross-line area, and the voltage difference between the two is large due to the opposite electrical properties of the voltages; the insulating layer between the two is easily invalidated under the action of the high voltage difference, thereby causing a short circuit. In the embodiment of the present disclosure, by setting the second routing line segment LB2 of the third conductive layer ML3, the segment difference between the routing line loaded with the high-level voltage signal and the routing line loaded with the low-level voltage signal in the cross-line area is enlarged, and the insulating layer between the two is thickened, thereby reducing the risk of the insulating layer being broken down.

[0081] In one embodiment of the present disclosure, the step difference between the second routing segment overlap portion LB2B and the base substrate SBT is 1 to 2 microns greater than the step difference between the second routing segment end portion LB2A and the base substrate SBT. In this way, the second routing segment overlap portion LB2B is further raised by 1 to 2 microns, and the thickness of the insulating layer between the second routing segment overlap portion LB2B and the first routing LA can be further increased without excessively increasing the thickness of the display panel PNL, thereby further reducing the risk of short circuit.

[0082] In one embodiment of the present disclosure, the first routing line LA has an overlapping portion LA1 of the first routing line that overlaps with the overlapping portion LB2B of the second routing segment, and the step difference between the surface of the overlapping portion LA1 of the first routing line away from the substrate substrate SBT and the surface of the overlapping portion LB2B of the second routing segment close to the substrate substrate SBT is not less than 3 microns. In this way, the thickness of the insulating layer between the overlapping portion LB2B of the second routing segment and the overlapping portion LA1 of the first routing line is at least 3 microns. On the one hand, the reliability of the insulation is improved by the thick insulating layer, and on the other hand, the electric field strength between the second routing segment overlapping portion LB2B and the overlapping portion LA1 of the first routing line is reduced by increasing the distance between the overlapping portion LB2B of the second routing segment and the overlapping portion LA1 of the first routing line, thereby reducing the risk of the insulating layer being broken down.

[0083] In one embodiment of the present disclosure, Figure 7As shown, in the cross-line area CA, the display panel PNL is provided with a cross-line insulation unit DA between the second conductive layer ML2 and the third conductive layer ML3. The second line segment LB2 is formed on the surface of the cross-line insulation unit DA away from the substrate SBT. Along the extension direction of the second line LB, the cross-line insulation unit DA includes a first cross-line insulator unit DA1, a second cross-line insulator unit DA2 and a third cross-line insulator unit DA3 in sequence. The first cross-line insulator unit DA1 is provided with a first via H1, and the third cross-line insulator unit DA3 is provided with a second via H2; the second line segment LB2 is electrically connected to the first line segment LB1 through the first via H1, and is electrically connected to the third line segment LB3 through the second via H2. The second cross-line insulator unit DA2 is arranged to overlap with the first line LA; the second cross-line insulator unit DA2 has a protruding structure DA2X protruding from the plane where the first cross-line insulator unit DA1 and the third cross-line insulator unit DA3 are located. In this way, by setting the surface of the second cross-line insulator unit DA2 away from the substrate substrate SBT to protrude from the plane of the first cross-line insulator unit DA1 and the third cross-line insulator unit DA3 away from the substrate substrate SBT, the thickness of the second cross-line insulator unit DA2 corresponding to the overlapping area of ​​the first routing LA is increased, thereby increasing the step difference between the overlapping portion LB2B of the second routing segment and the first routing LA, further avoiding the possibility of short circuit and improving the yield of the display panel.

[0084] For example, Figure 7 As shown, the protrusion of the second cross-line insulator unit DA2 makes the second cross-line insulator unit DA2 form an "arch" or "hill", forming a relatively gentle inclination angle. Further, the slope angle of the second cross-line insulator unit DA2 does not exceed 45°.

[0085] In one embodiment of the present disclosure, see Figure 7 , the first cross-line insulator unit DA1, the second cross-line insulator unit DA2 and the third cross-line insulator unit DA3 are located in the same organic layer. Figure 2 and Figure 7As shown, the cross-line insulation unit DA includes a first planarization layer PLN1 located between the second conductive layer ML2 (source-drain metal layer SD) and the third conductive layer ML3 (pixel electrode layer ANL). When preparing the display panel, the material layer of the first planarization layer PLN1 can be formed first, and then the material layer of the first planarization layer PLN1 can be patterned to form the first planarization layer PLN1. For example, the material layer of the first planarization layer PLN1 is first formed on the side of the color filter layer CF away from the substrate SBT, and then the material layer of the first planarization layer PLN1 is patterned. Optionally, the material layer of the first planarization layer PLN1 can be exposed and developed using a grayscale mask exposure technique, so that a convex structure DA2X is formed in the second cross-line insulator unit DA2 region. In this embodiment, in the cross-line region, the material layer of the first planarization layer PLN1 is gray-scale exposed using a grayscale mask exposure technique, so that the second cross-line insulator unit DA2 is in the shape of a hill or an arch bridge with a gentle inclination angle, thereby increasing the step difference between the first routing LA and the second routing LB in the cross-line region.

[0086] For example, Figure 7 As shown, the thickness of the first planarization layer PLN1 is 2000nm-3000nm; the maximum thickness of the protruding structure formed on the first planarization layer is 1000nm-2000nm.

[0087] Exemplarily, the material of the first planarization layer may be at least one of acrylic resin, polyimide resin, and benzocyclobutene-based resin.

[0088] In another embodiment of the present disclosure, Figure 8 As shown, the second cross-line insulator unit DA2 includes a first main structure DA2M and the first raised structure DA2D located on the side of the first main structure DA2M away from the substrate SBT, the first main structure DA2M and the first cross-line insulator unit DA1 and the third cross-line insulator unit DA3 are located in the same organic layer, and the first raised structure DA2D is located in another organic layer. In this way, the first raised structure DA2D can further increase the step difference of the cross-line area CA, the first routing LA and the second routing LB, and reduce the risk of short circuit in the cross-line area CA.

[0089] For example, see Figure 2 and Figure 8, the display panel PNL is provided with a first planarization layer PLN1 on the side of the source and drain metal layer away from the base substrate SBT, and the first planarization layer PLN1 forms a first main structure DA2M, a first cross-line insulator unit DA1 and a third cross-line insulator unit DA3 in the cross-line area CA. After the first planarization layer PLN1 is formed, a second planarization layer PLN2 can be formed on the side of the first planarization layer PLN1 away from the base substrate SBT, and the second planarization layer PLN2 forms a first convex structure DA2D in the cross-line area CA through exposure and development technology. Furthermore, the second planarization layer PLN2 is completely removed in the area outside the cross-line area CA, and only the first convex structure DA2D is retained in the cross-line area CA. In this way, the first convex structure DA2D formed can further increase the step difference between the first routing LA and the second routing LB in the cross-line area CA by adding the second planarization layer instead of thinning the thickness of the first planarization layer PLN1, thereby reducing the risk of short circuit in the cross-line area CA.

[0090] In another embodiment of the present disclosure, Fig. 9 As shown, the second cross-line insulator unit DA2 includes a second convex structure DA21 and a second main structure DA22 covering the second convex structure DA21. The second main structure DA22, the first cross-line insulator unit DA1, and the third cross-line insulator unit DA3 are located in one organic layer; the second convex structure DA21 is located in another organic layer.

[0091] For example, see Figure 2 and Fig. 9 The second protruding structure DA21 is located in the black matrix layer, and the second main structure DA22 is the first planarization layer PLN1.

[0092] For example, during the preparation of the display panel PNL, a color filter layer CF may be formed on the side of the source / drain metal layer SD away from the substrate SBT, and the color filter layer CF includes a plurality of color resist units and a black matrix layer. The black matrix layer may form a second raised structure DA21 in the cross-line area CA. Furthermore, the second raised structure DA21 is formed in the portion of the black matrix layer located in the cross-line area CA by grayscale exposure technology. Of course, in other embodiments of the present disclosure, the second raised structure DA21 may also be provided in the same layer as the color resist unit.

[0093] After the color filter layer is formed, a first planarization layer PLN1 is formed, and the first planarization layer PLN1 forms a first cross-line insulator unit DA1, a second main structure DA22 and a third cross-line insulator unit DA3 in the cross-line area CA.

[0094] Generally, the source and drain metal layer is thicker than the pixel electrode layer. When the second wiring segment LB2 is set in the pixel electrode layer, it may cause uneven charge distribution, current concentration at the edge, and then generate tip discharge, affecting the yield of the display panel.

[0095] In one embodiment of the present disclosure, see Fig.10 , the first routing segment LB1 has a first branch routing LB1D arranged in parallel with the first routing LA, and the third routing segment LB3 has a second branch routing LB3D arranged in parallel with the first routing LA. The second routing segment LB2 includes a plurality of branch routings LB2S arranged side by side; one end of the branch routing LB2S is electrically connected to the first branch routing LB1D through a via, and the other end is electrically connected to the second branch routing LB3D through a via. In other words, the second routing segment LB2 is divided into a plurality of side-by-side branch routings LB2S, and each branch routing LB2S is electrically connected to the first branch routing LB1D and the second branch routing LB3D through a via. By increasing the projected area of ​​the second routing segment LB2 on the substrate SBT, the deficiency in thickness of the third conductive layer is compensated, thereby improving the performance of the display panel. In addition, the second wiring segment LB2 has a plurality of parallel branch wirings LB2S, so as to avoid the problem of charge concentration at the edge due to the excessive area of ​​the second wiring segment LB2, suppress tip discharge, and improve the reliability of the display panel PNL.

[0096] For example, Figure 1 and Fig.10 As shown, the second routing segment LB2 has a connection structure at the end, and the connection structure connects the ends of the branch routing LB2S to each other; the connection structure is electrically connected to the first branch routing LB1D and the second branch routing LB3D through vias.

[0097] In an exemplary embodiment, Fig.10 As shown, the first line LA has an overlapping area with the branch line LB2S, and the overlapping area can be partially hollowed out. For example, the overlapping area is hollowed out in the middle. Of course, it is also possible to hollow out other positions of the overlapping area while ensuring that the first line LA is electrically conductive. In this way, the parasitic capacitance of the overlapping area between the first line LA and the branch line LB2S can be reduced, further improving the performance of the display panel.

[0098] The middle area of ​​the overlapping portion LA1 of the first wiring corresponding to the crossing area CA is hollowed out.

[0099] In one embodiment of the present disclosure, in the second routing line LB, the width of the branch routing line LB2S is not less than the width of the first routing line segment LB1 and the width of the third routing line segment LB3. Exemplarily, in the second routing line segment LB2, the total number of the branch routing lines LB2S is not less than 6. In this way, the resistance of the second routing line segment LB2 can be reduced by as many branch routing lines LB2S as possible.

[0100] In one embodiment of the present disclosure, in each branch wiring LB2S of the second wiring segment LB2, the distance between the outer edges of the two branch wirings LB2S on the two sides is not less than 20 times the width of the first wiring segment LB1. In this way, the total width of the second wiring segment LB2 can be made larger, and the resistance of the second wiring segment LB2 can be reduced as much as possible.

[0101] In one example of the present disclosure, the following method can be used to prepare Figure 2 and Figure 7 The display panel PNL shown in the example. The preparation method includes:

[0102] S1. Forming a metal light shielding layer LS, a buffer layer Buffer, a semiconductor layer SCL and a gate insulating layer GI in sequence on a glass substrate.

[0103] S2. A gate layer GT is formed on the side of the gate insulating layer GI away from the glass substrate; in the display area, the gate layer GT forms the gate of the transistor in the driving circuit layer through processes such as exposure and etching; in the non-display area, the gate layer GT is patterned to form a variety of signal lines (for example, a driving power supply voltage line VDD, a reference power supply voltage line VSS, and a clock signal line CLK for connecting to GOA). One of these lines can be used as the first line LA. The material of the gate layer GT is copper, and the thickness is 400nm.

[0104] S3, forming a first passivation layer PVX1 on the side of the gate layer GT away from the glass substrate. The first passivation layer PVX1 is a SiOx material with a thickness of 400 nm.

[0105] S4. Form a source-drain metal layer SD on the side of the first passivation layer PVX1 away from the glass substrate. In the display area of ​​the display panel, the source-drain metal layer SD forms a connecting line. In the non-display area of ​​the display panel, the source-drain metal layer SD can form the first line segment LB1 and the third line segment LB3 of the second line LB described in the present disclosure. The source-drain metal layer SD is made of copper with a thickness of 400 nm.

[0106] S5, forming a second passivation layer PVX2 on the side of the source-drain metal layer SD away from the glass substrate. The second passivation layer PVX2 is a SiOx material with a thickness of 400 nm.

[0107] S6. Form a color filter layer CF on the side of the second passivation layer PVX2 away from the glass substrate. Form a first planarization layer PLN1 on the side of the color filter layer CF away from the glass substrate. The thickness of the first planarization layer PLN1 is 2um. In the cross-line area of ​​the first peripheral area BB1, grayscale exposure is performed on the first planarization layer PLN1 using a grayscale mask exposure technology to form a first planarization layer with a raised "hill-like structure".

[0108] S7. A pixel electrode layer is formed on the side of the first planarization layer PLN1 away from the substrate SBT. The pixel electrode layer includes a first conductive metal oxide layer ITO1, an Ag layer, and a second conductive metal oxide layer ITO2, which are stacked. The first conductive metal oxide layer ITO1 is 70nm, the Ag layer is 500nm, and the second conductive metal oxide layer ITO2 is 12nm. The pixel electrode layer can be used as the third conductive layer ML3 of the present disclosure. The second routing segment LB2 located on the third conductive layer ML3 is electrically connected to the first routing segment LB1 and the third routing segment LB3 located on the second conductive layer ML2 through a via.

[0109] S8. On the side of the pixel electrode layer away from the base substrate SBT, a pixel definition layer PDL, a support column layer, an organic light-emitting functional layer EL and a common electrode layer COML are sequentially formed to form a pixel layer FB; and a thin film encapsulation layer is formed on the side of the pixel layer FB away from the base substrate SBT.

[0110] The embodiment of the present disclosure also provides a display device, which includes the above-mentioned display panel PNL. Exemplarily, the display device may include but is not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator. Here, the embodiment of the present disclosure does not limit this.

[0111] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that: The display panel comprises a first wiring and a second wiring; the display panel comprises at least a base substrate, a first conductive layer, a second conductive layer and a third conductive layer which are stacked in sequence; The first wiring is located in the first conductive layer; The display panel has at least one cross-line area; in the cross-line area, the second routing includes a first routing segment, a second routing segment and a third routing segment connected in sequence; wherein the first routing segment and the third routing segment are both located in the second conductive layer, and the second routing segment is located in the third conductive layer and is electrically connected to the first routing segment and the third routing segment through a via; The orthographic projections of the first routing segment and the third routing segment on the base substrate are respectively located on both sides of the orthographic projection of the first conductive layer on the base substrate; the second routing segment is arranged to overlap with the first conductive layer.

2. The display panel according to claim 1, characterized in that: The second routing segment has a second routing segment end and a second routing segment overlapping portion overlapping the first routing segment; a step difference between the second routing segment overlapping portion and the base substrate is greater than a step difference between the second routing segment end and the base substrate.

3. The display panel according to claim 2, characterized in that: The step difference between the overlapping portion of the second routing segment and the base substrate is 1 to 2 micrometers greater than the step difference between the end portion of the second routing segment and the base substrate.

4. The display panel according to claim 3, characterized in that: The first routing line has an overlapping portion of the first routing line overlapping the overlapping portion of the second routing line segment, and the step difference between the surface of the overlapping portion of the first routing line away from the substrate and the surface of the overlapping portion of the second routing line segment close to the substrate is not less than 3 microns.

5. The display panel according to claim 1, characterized in that: In the cross-line region, the display panel is provided with a cross-line insulation unit between the second conductive layer and the third conductive layer; The second routing segment is formed on a surface of the cross-line insulation unit away from the substrate; Along the extension direction of the second routing line, the cross-line insulation unit includes a first cross-line insulator unit, a second cross-line insulator unit and a third cross-line insulator unit in sequence; the first cross-line insulator unit is provided with a first via hole, and the third cross-line insulator unit is provided with a second via hole; the second routing segment is electrically connected to the first routing segment through the first via hole, and is electrically connected to the third routing segment through the second via hole; the second cross-line insulator unit is overlapped with the first routing line; the second cross-line insulator unit has a protruding structure protruding from the plane where the first cross-line insulator unit and the third cross-line insulator unit are located.

6. The display panel according to claim 5, characterized in that: The slope angle of the second cross-line insulator unit does not exceed 45°.

7. The display panel according to claim 5, characterized in that: The first cross-line insulator unit, the second cross-line insulator unit and the third cross-line insulator unit are located in the same organic layer.

8. The display panel according to claim 5, characterized in that: The second cross-line insulator unit includes a first main structure and a first protruding structure located on a side of the first main structure away from the substrate. The first main structure and the first cross-line insulator unit and the third cross-line insulator unit are located in the same organic layer, and the first protruding structure is located in another organic layer.

9. The display panel according to claim 5, characterized in that: The second cross-line insulator unit includes a second protruding structure and a second main body structure covering the second protruding structure; The second main body structure, the first cross-line insulator unit, and the third cross-line insulator unit are located in an organic layer; The second protrusion structure is located in another organic layer.

10. The display panel according to claim 1, characterized in that: The first routing segment has a first branch routing line arranged in parallel with the first routing line, and the third routing segment has a second branch routing line arranged in parallel with the first routing line; The second routing segment includes a plurality of branch routings arranged side by side; one end of the branch routing is electrically connected to the first branch routing through a via, and the other end of the branch routing is electrically connected to the second branch routing through a via.

11. The display panel according to claim 10, characterized in that: In the second routing line, the width of the branch routing line is not less than the width of the first routing line segment and the width of the third routing line segment.

12. The display panel according to claim 10, characterized in that: In the second routing segment, the total number of the branch routing lines is no less than 6.

13. The display panel according to claim 10, characterized in that: In each branch routing of the second routing segment, a distance between outer edges of two branch routings on two sides is not less than 20 times the width of the first routing segment.

14. The display panel according to claim 1, characterized in that: The base substrate further includes one or more gate layers, one or more source / drain metal layers and a pixel electrode layer which are sequentially stacked on one side of the base substrate; The first conductive layer is a gate layer, the second conductive layer is a source-drain metal layer, and the third conductive layer is a pixel electrode layer.

15. The display panel according to claim 14, characterized in that: The pixel electrode layer includes a first conductive metal oxide layer, a metal layer, and a second conductive metal oxide layer which are stacked in sequence; wherein the metal layer is between 50nm and 1000nm.

16. The display panel according to claim 1, characterized in that: The display panel comprises a display area and a first peripheral area located at least on one side of the display area; a gate driving circuit for driving a pixel driving circuit in the display area is arranged in the first peripheral area, and the gate driving circuit comprises a plurality of shift registers arranged in sequence along a column direction; The first wiring is disposed in the first peripheral area and extends along a row direction; The second wiring is disposed in the first peripheral area and extends along a row direction.

17. The display panel according to claim 16, characterized in that: The display panel has a first driving line for loading a first driving signal to a shift register and a second driving line for loading a second driving signal to the shift register in the first peripheral area, the first driving line and the second driving line extend along the column direction, and the second driving line is located between the first driving line and the shift register; One end of the second wiring is electrically connected to the first driving wiring, and the other end is electrically connected to the shift register; the second driving wiring is arranged as the first wiring and overlaps with the second wiring in the cross-line area.

18. The display panel according to claim 17, characterized in that: One of the first driving signal and the second driving signal is a high-level voltage signal, and the other is a low-level voltage signal.

19. A display device, characterized in that: A display panel comprising any one of claims 1 to 18.

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