Display substrate and display device

Abstract

A display substrate comprises a substrate body, a plurality of first light-emitting elements arranged on the substrate body, a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of second light-emitting elements and a plurality of first auxiliary wires. The plurality of first light-emitting elements are located in the first display area, and the plurality of first pixel circuits, the plurality of second pixel circuits and the plurality of second light-emitting elements are located in the second display area. The second display area comprises a first sub-area located on at least one side of the first display area and a second sub-area located on at least one side of the first sub-area. The plurality of first pixel circuits are located in the first sub-area, and at least one first pixel circuit is connected with at least one first light-emitting element through at least one conductive connecting line. The plurality of first auxiliary wires are located in the second sub-area, at least one first auxiliary wire and at least one conductive connecting wire are arranged on the same layer, and the plurality of first auxiliary wires are configured to receive constant voltage signals.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. Under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present application provide a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, comprising: a substrate, a plurality of light-emitting elements arranged on the substrate, a plurality of pixel circuits, and a plurality of first auxiliary wirings. The substrate comprises a first display area and a second display area located at least on one side of the first display area, and the second display area comprises: a first sub-area located at least on one side of the first display area, and a second sub-area located at least on one side of the first sub-area. The plurality of light-emitting elements comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of pixel circuits comprises a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area, the plurality of first pixel circuits being located in the first sub-area, at least one first pixel circuit of the plurality of first pixel circuits being connected to at least one first light-emitting element of the plurality of first light-emitting elements through at least one conductive connecting line; at least one second pixel circuit of the plurality of second pixel circuits being connected to at least one second light-emitting element of the plurality of second light-emitting elements. The at least one conductive connecting line extends from the first sub-area to the first display area. A plurality of first auxiliary routing lines are located in the second sub-area of ​​the second display area, at least one of the plurality of first auxiliary routing lines is arranged in the same layer as the at least one conductive connection line, and the plurality of first auxiliary routing lines are configured to receive a constant voltage signal.

[0006] In some exemplary embodiments, an extension direction of at least one first auxiliary routing line among the plurality of first auxiliary routing lines is the same as an extension direction of the at least one conductive connection line.

[0007] In some exemplary embodiments, the display substrate further includes: a plurality of second auxiliary routing lines located in the second sub-area, the extension direction of the plurality of second auxiliary routing lines intersecting with the extension direction of the plurality of first auxiliary routing lines, and the plurality of second auxiliary routing lines being connected with the plurality of first auxiliary routing lines to form a mesh structure.

[0008] In some exemplary embodiments, the first auxiliary routing includes: a first main body extending along a first direction, a plurality of first extension portions and a plurality of second extension portions extending along a second direction, and a plurality of first auxiliary connection electrodes, the second direction intersecting the first direction; the plurality of second extension portions are connected to the plurality of first auxiliary connection electrodes in a one-to-one correspondence, the plurality of first extension portions and the plurality of second extension portions are connected on the same side of the first main body and are arranged at intervals along the first direction; the first auxiliary connection electrode is connected to a second auxiliary routing extending along the second direction.

[0009] In some exemplary embodiments, the plurality of second auxiliary routing lines and the plurality of first auxiliary routing lines are located in different conductive layers, and at least one insulating layer is provided between the conductive layer where the first auxiliary routing lines are located and the conductive layer where the second auxiliary routing lines are located; the second auxiliary routing line includes: a second main body extending along the second direction and at least one second auxiliary connection electrode extending along the first direction. The second auxiliary connection electrode of the second auxiliary routing line is connected to the first auxiliary connection electrode of the first auxiliary routing line through an auxiliary transfer hole provided in the insulating layer.

[0010] In some exemplary embodiments, the first sub-area is located on both sides of the first display area along the first direction, and the second sub-area includes: a first partition and a second partition located on both sides of the first sub-area along the first direction, and a third partition and a fourth partition located on both sides of the first display area along the second direction, and the multiple auxiliary transfer holes in the first partition, the second partition, the third partition and the fourth partition are arranged in a V shape.

[0011] In some exemplary embodiments, the maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the first partition and the second partition along the first direction is greater than the maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the third partition and the fourth partition along the first direction; the maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the first partition and the second partition along the second direction is greater than the maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the third partition and the fourth partition along the second direction.

[0012] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a circuit structure layer and at least two conductive connection layers sequentially arranged on the substrate, the material of the at least two conductive connection layers including a transparent conductive material; the at least two conductive connection layers are provided with the at least one conductive connection line, and the first auxiliary routing line and the second auxiliary routing line are located in the two conductive connection layers and in different layers.

[0013] In some exemplary embodiments, the at least two conductive connection layers include: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer arranged in sequence along a direction away from the substrate; the first auxiliary routing is located in the first conductive connection layer, and the second auxiliary routing is located in the second conductive connection layer.

[0014] In some exemplary embodiments, a plurality of pixel circuits arranged along a first direction are a row of pixel circuits, a plurality of pixel circuits arranged along a second direction are a column of pixel circuits, and the first direction intersects with the second direction. The circuit structure layer comprises: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged on the substrate. The first gate metal layer comprises: a plurality of scan lines, the scan lines are connected to a row of pixel circuits; the second gate metal layer comprises: a plurality of first initial signal lines, the first initial signal lines are connected to a row of pixel circuits; the third source-drain metal layer comprises: a plurality of data lines and a plurality of first data transfer lines, the plurality of data lines and the plurality of first data transfer lines are arranged at intervals along the first direction; the data lines are connected to a column of pixel circuits, and the orthographic projection of the first data transfer line on the substrate overlaps with the orthographic projection of a column of pixel circuits on the substrate. The first auxiliary wiring comprises a first main body extending along the first direction, the orthographic projection of the first main body on the substrate is located between the scan lines connected to a row of pixel circuits and the orthographic projection of the first initial signal lines on the substrate. The second auxiliary routing includes a second main portion extending along the second direction, and at least a portion of the second main portion is located between a data line connected to a column of pixel circuits and a first data transfer line that overlaps with the orthographic projection of the column of pixel circuits on the substrate in an orthographic projection of the substrate.

[0015] In some exemplary embodiments, the substrate further includes: a first border area located on one side of the second display area, the first border area being provided with a first peripheral power line and a plurality of power switching electrodes, and the plurality of second auxiliary lines being connected to the first peripheral power line through the plurality of power switching electrodes.

[0016] In some exemplary embodiments, the display substrate further includes: a plurality of first power lines located in the second display area, the plurality of first power lines are arranged along a first direction and extend along a second direction, and the first direction intersects the second direction. The plurality of pixel circuits further include: a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits arranged along the second direction are a column of invalid pixel circuits, the plurality of second pixel circuits arranged along the second direction are a column of second pixel circuits, and the plurality of first pixel circuits arranged along the second direction are a column of first pixel circuits. The power transfer electrode connected to the second auxiliary wiring is located between a first power line connected to a column of invalid pixel circuits and a first power line connected to an adjacent column of second pixel circuits, or between a column of invalid pixel circuits aligned along the second direction and a first power line connected to a column of first pixel circuits and a first power line connected to an adjacent column of second pixel circuits.

[0017] In some exemplary embodiments, the substrate further includes: a border area located on at least one side of the second display area, and the display substrate further includes: a third auxiliary routing line located in the border area, the third auxiliary routing line is connected to the plurality of first auxiliary routing lines and is configured to transmit a constant voltage signal.

[0018] In some exemplary embodiments, the at least one conductive connection line includes: a third main body extending along a first direction, and a conductive connection part extending along a second direction, the first direction intersecting the second direction; the conductive connection part is connected to the first pixel circuit in the first sub-area, and the third main body is connected to the first light-emitting element in the first display area. The display substrate further includes: a plurality of fourth auxiliary wirings located in the first sub-area and extending along the first direction, the plurality of fourth auxiliary wirings are arranged in the same layer as the at least one conductive connection line, and the plurality of fourth auxiliary wirings meet at least one of the following conditions: located between the conductive connection parts of adjacent conductive connection lines, and located between the third main bodies of adjacent conductive connection lines.

[0019] On the other hand, this embodiment provides a display device, comprising a display substrate as described above, and a sensor located on the non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the substrate of the display substrate at least partially overlaps with the orthographic projection of the first display area of ​​the display substrate on the substrate.

[0020] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0022] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of a display area of ​​at least one embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of an arrangement of pixel circuits in the second display area of ​​at least one embodiment of the present disclosure;

[0025] Figure 4 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0026] Figure 5 A partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0027] Fig. 6A A partial schematic diagram of a semiconductor layer and a first gate metal layer in a second sub-region of a second display region according to at least one embodiment of the present disclosure;

[0028] Figure 6B A partial schematic diagram of a second sub-region of a second display region after a second gate metal layer is formed according to at least one embodiment of the present disclosure;

[0029] Figure 6C A partial schematic diagram of a second sub-area of ​​a second display area after forming a first source-drain metal layer according to at least one embodiment of the present disclosure;

[0030] Fig.6D A schematic diagram of a second sub-region of a second display region after a second source-drain metal layer is formed according to at least one embodiment of the present disclosure;

[0031] Fig. 6E A schematic diagram of a second sub-region of a second display region after a third source-drain metal layer is formed according to at least one embodiment of the present disclosure;

[0032] Fig. 7A A partial schematic diagram of a second sub-area of ​​a second display area after a first conductive connection layer is formed according to at least one embodiment of the present disclosure;

[0033] Figure 7B for Fig. 7A A schematic diagram of a first conductive connection layer in FIG.

[0034] Figure 7C A partial schematic diagram of a second sub-area of ​​a second display area after a second conductive connection layer is formed according to at least one embodiment of the present disclosure;

[0035] Fig.7D for Figure 7C A schematic diagram of a second conductive connection layer in FIG.

[0036] Fig. 7E It is a partial schematic diagram of the second sub-area of ​​the second display area after the third conductive connection layer is formed according to at least one embodiment of the present disclosure;

[0037] Figure 8 It is a partial schematic diagram of the first conductive connection layer, the second conductive connection layer and the third conductive connection layer of the second sub-region of at least one embodiment of the present disclosure;

[0038] Fig. 9 A schematic diagram of the arrangement of a plurality of auxiliary transfer holes in the second sub-area of ​​at least one embodiment of the present disclosure;

[0039] Fig. 10A A partial schematic diagram of the boundary position between the display area and the first frame area of ​​at least one embodiment of the present disclosure;

[0040] Fig. 10B for Fig. 10A A schematic diagram of a first gate metal layer and a second gate metal layer in a first border area B1;

[0041] Fig. 10C for Fig. 10A A schematic diagram of a second source / drain metal layer in FIG.

[0042] Fig. 10D for Fig. 10A A schematic diagram of a second source-drain metal layer and a third source-drain metal layer in FIG.

[0043] Fig.10E for Fig. 10A A schematic diagram of a third source / drain metal layer in FIG.

[0044] Fig.10F for Fig. 10A A schematic diagram of a second source-drain metal layer, a third source-drain metal layer and a first conductive connection layer in FIG.

[0045] Figure 10G for Fig. 10A A schematic diagram of a first conductive connection layer in FIG.

[0046] Fig. 10H for Fig. 10A A schematic diagram of a second source-drain metal layer, a third source-drain metal layer, a first conductive connection layer, and a second conductive connection layer;

[0047] Fig.10I for Fig. 10A A schematic diagram of a second conductive connection layer in FIG.

[0048] Fig.11 is another partial plan view of the second display area of ​​at least one embodiment of the present disclosure;

[0049] Fig.12 A partial plan view of a first sub-area of ​​a second display area according to at least one embodiment of the present disclosure;

[0050] Fig.13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the accompanying drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0052] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0053] In addition, when describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0054] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0055] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include at least one of the features. In the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise clearly defined.

[0056] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the meanings of the above terms in this application can be understood according to the circumstances.

[0057] In the present application, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.

[0058] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0059] In this application, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this application, a channel region refers to a region where current mainly flows.

[0060] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, the "source electrode" and the "drain electrode" may be interchanged. In addition, the gate electrode may also be referred to as a control electrode.

[0061] In the present application, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0062] In the present application, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in a strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0063] The "light transmittance" in this application refers to the ability of light to pass through a medium, which is the percentage of the luminous flux passing through a transparent or translucent body to its incident luminous flux.

[0064] In this application, "about" or "substantially" means that the limit is not strictly defined and the process and measurement errors are allowed. In this application, "same" means that the numerical value differs within 10%.

[0065] In the present application, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the present application, "A extends along direction B" means "the main part of A extends along direction B.

[0066] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and in-screen hole have appeared one after another. These technologies are to reduce the area occupied by the camera by digging holes in part of the display area and placing a camera below the hole area, thereby increasing the screen-to-body ratio. However, the above technology requires digging out part of the display area, which will cause part of the display screen to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method is usually used in the camera area under the screen. The pixel circuit external method refers to setting the pixel circuit connected to the light-emitting element in the camera area under the screen in the normal display area, and arranging the light-emitting element and the pixel circuit separately to improve the light transmittance of the camera area under the screen. Since there is no pixel circuit in the camera area under the screen, there is no other light-shielding layer in this area except the anode of the light-emitting element, so a higher light transmittance can be achieved. However, the multiple light-emitting elements in the under-screen camera area need to be connected to the multiple pixel circuits in the normal display area through multiple conductive connecting lines. The environments of the multiple conductive connecting lines vary depending on the setting positions, which is not conducive to the uniformity of the arrangement of the conductive connecting lines. There are also problems such as poor etching uniformity and cumbersome signal compensation.

[0067] The present embodiment provides a display substrate, comprising: a substrate, a plurality of light-emitting elements arranged on the substrate, a plurality of pixel circuits, and a plurality of first auxiliary wirings. The substrate comprises a first display area and a second display area located at least on one side of the first display area, and the second display area comprises: a first sub-area located at least on one side of the first display area, and a second sub-area located at least on one side of the first sub-area. The plurality of light-emitting elements comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of pixel circuits comprises a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area, the plurality of first pixel circuits are located in the first sub-area, at least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first light-emitting element among the plurality of first light-emitting elements through at least one conductive connecting line; at least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second light-emitting element among the plurality of second light-emitting elements. The at least one conductive connecting line extends from the first sub-area to the first display area. The plurality of first auxiliary wirings are located in the second sub-area of ​​the second display area, at least one first auxiliary wiring among the plurality of first auxiliary wirings is arranged in the same layer as the at least one conductive connecting line, and the plurality of first auxiliary wirings are configured to receive a constant voltage signal.

[0068] In some examples, the first sub-region of the second display region may also be referred to as a transition region, and a plurality of first pixel circuits may be disposed in the first sub-region and electrically connected to a plurality of first light-emitting elements in the first display region through a plurality of conductive connecting lines. A plurality of conductive connecting lines connected to the plurality of first pixel circuits may extend from the first sub-region to the first display region and be connected to a plurality of first light-emitting elements in the first display region. In other words, a plurality of conductive connecting lines may be disposed in the first sub-region and the first display region.

[0069] The display substrate provided in this embodiment arranges a plurality of first auxiliary wirings provided in the same layer as the conductive connection lines in the second sub-area of ​​the second display area, which can facilitate the wiring etching uniformity of the conductive layer where the conductive connection lines are located and facilitate stabilizing the circuit under the conductive layer where the conductive connection lines are located.

[0070] In some exemplary embodiments, the extension direction of at least one of the plurality of first auxiliary routings is the same as the extension direction of at least one conductive connection line. In some examples, the display substrate may include a plurality of conductive connection lines having the same extension direction, and the extension direction of the plurality of first auxiliary routings may be the same as the extension direction of the plurality of conductive connection lines. For example, the plurality of first auxiliary routings and the plurality of conductive connection lines may both extend in the first direction. In other examples, the display substrate may include a plurality of conductive connection lines having the same extension direction, and the extension direction of the plurality of first auxiliary routings may be different from the extension direction of the plurality of conductive connection lines. For example, the plurality of conductive connection lines may extend in the second direction, and the plurality of first auxiliary routings may extend in the first direction, the first direction intersecting the second direction, for example, the first direction being perpendicular to the second direction. In other examples, the display substrate may include two groups of conductive connection lines having intersecting extension directions, and the extension direction of the plurality of first auxiliary routings may be the same as the extension direction of one of the groups of conductive connection lines.

[0071] In some exemplary embodiments, the display substrate may further include: a plurality of second auxiliary routing lines located in the second sub-area, the extension direction of the plurality of second auxiliary routing lines intersects with the extension direction of the plurality of first auxiliary routing lines, and the plurality of second auxiliary routing lines and the plurality of first auxiliary routing lines may be connected to form a mesh structure. For example, the plurality of first auxiliary routing lines may extend along the first direction, and the plurality of second auxiliary routing lines may extend along the second direction. In this example, the plurality of first auxiliary routing lines and the plurality of second auxiliary routing lines are connected to form a mesh structure, which may be beneficial to the uniformity of routing etching of the conductive layer where the conductive connection lines are located.

[0072] In some exemplary embodiments, the first auxiliary routing may include: a first main body extending along a first direction, a plurality of first extensions and a plurality of second extensions extending along a second direction, and a plurality of first auxiliary connection electrodes, wherein the second direction intersects the first direction. The plurality of second extensions are connected to the plurality of first auxiliary connection electrodes one by one, the plurality of first extensions are connected to the plurality of second extensions on the same side of the first main body, and are arranged at intervals along the first direction; the first auxiliary connection electrode is connected to a second auxiliary routing extending along the second direction. In some examples, at least one insulating layer may be provided between the conductive layer where the first auxiliary routing is located and the conductive layer where the second auxiliary routing is located; the second auxiliary routing includes: a second main body extending along the second direction and at least one second auxiliary connection electrode extending along the first direction; the second auxiliary connection electrode of the second auxiliary routing may be connected to the first auxiliary connection electrode of the first auxiliary routing through an auxiliary transfer hole provided in the insulating layer. By providing the auxiliary transfer hole, this example can improve the situation where the gap between the via holes provided in the insulating layer in the second display area is too large, resulting in inconsistent environment.

[0073] In some exemplary embodiments, the substrate may further include: a frame region located on at least one side of the second display region, and the display substrate may further include: a third auxiliary routing line located in the frame region, the third auxiliary routing line being connected to the plurality of first auxiliary routing lines and configured to transmit a constant voltage signal. In this example, by providing a third auxiliary routing line in the frame region to provide a constant voltage signal to the plurality of first auxiliary routing lines, it is beneficial to stabilize the lower circuit of the film layer where the plurality of first auxiliary routing lines and the plurality of conductive connection lines are located.

[0074] In some exemplary embodiments, at least one conductive connection line may include: a third main body extending along the first direction, and a conductive connection part extending along the second direction; the conductive connection part is connected to the first pixel circuit in the first sub-area, and the third main body is connected to the first light-emitting element in the first display area. The display substrate may also include: a plurality of fourth auxiliary lines located in the first sub-area and extending along the first direction, the plurality of fourth auxiliary lines are arranged in the same layer as the plurality of conductive connection lines, and the plurality of fourth auxiliary lines meet at least one of the following: located between the conductive connection parts of adjacent conductive connection lines and between the third main bodies of adjacent conductive connection lines. For example, the plurality of fourth auxiliary lines may be located between the conductive connection parts of adjacent conductive connection lines, or may be located between the third main bodies of adjacent conductive connection lines, or may be located between the conductive connection parts of adjacent conductive connection lines and between the third main bodies of adjacent conductive connection lines. In this example, by arranging the fourth auxiliary lines in the intervals between the conductive connection lines, the consistency of the surrounding environment of the conductive connection lines can be improved, which is conducive to optimizing the compensation rules for the conductive connection lines and improving the etching uniformity of the conductive connection lines.

[0075] The solution of this embodiment is described below by means of some examples.

[0076] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate may include: a display area AA, and a frame area BB surrounding the periphery of the display area AA. For example, the frame area BB may include: a first frame area B1, a second frame area B2, a third frame area B3, and a fourth frame area B4 located around the display area AA. The first frame area B1 and the second frame area B2 may be located on opposite sides of the display area AA along the second direction D2, and the third frame area B3 and the fourth frame area B4 may be located on opposite sides of the display area AA along the first direction D1. Among them, the first direction D1 intersects with the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2. In some examples, the first frame area B1 may be the lower frame of the display substrate, the second frame area B2 may be the upper frame of the display substrate, the third frame area B3 may be the left frame of the display substrate, and the fourth frame area B4 may be the right frame of the display substrate.

[0077] In some examples, such as Figure 1 As shown, the display area AA may include: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the first display area A1 may be located in the top center of the display area AA, and the second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located in other positions such as the upper left corner or the upper right corner of the display area AA, and the second display area A2 may surround at least one side of the first display area A1.

[0078] In some examples, such as Figure 1 As shown, the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be a circle or an ellipse. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon or other shapes.

[0079] In some examples, the first display area A1 may be a light-transmitting display area, which may also be referred to as a Full Display with Camera (FDC) area, configured to display images and transmit light; the second display area A2 may be referred to as a normal display area, configured to display images. For example, the orthographic projection of a sensor (e.g., hardware such as a camera or infrared sensor) on the display substrate may be at least partially located within the first display area A1 of the display substrate. In some examples, such as Figure 1As shown, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0080] In some examples, such as Figure 1 As shown, the pixel density of the first display area A1 may be less than or equal to the pixel density of the second display area A2. For example, the pixel density of the first display area A1 may be equal to the pixel density of the second display area A2. In some examples, the ratio of the resolution of the first display area A1 to the resolution of the second display area A2 may be approximately 0.8 to 1.2. This embodiment is not limited to this.

[0081] In some examples, the display substrate may include at least: a plurality of first light-emitting elements 31 located in the first display area A1, a plurality of second light-emitting elements 32 located in the second display area A2, and a plurality of pixel circuits. The plurality of pixel circuits located in the second display area A2 may include: a plurality of first pixel circuits 41, a plurality of second pixel circuits 42, and a plurality of invalid pixel circuits.

[0082] In some examples, at least one first pixel circuit 41 among the plurality of first pixel circuits 41 may be electrically connected to at least one first light-emitting element 31 among the plurality of first light-emitting elements 31 through a conductive connection line 51. The first pixel circuit 41 may be configured to provide a driving signal to the connected first light-emitting element 31 to drive the corresponding first light-emitting element 31 to emit light. For example, the plurality of first pixel circuits 41 and the plurality of first light-emitting elements 31 may be in a one-to-one driving relationship, or may be in a one-to-many driving relationship. Since the first light-emitting element 31 and the first pixel circuit 41 are located in different areas, there may be no overlapping portion between the orthographic projection of at least one first pixel circuit 41 on the substrate and the orthographic projection of at least one first light-emitting element 31 on the substrate.

[0083] In some examples, at least one second pixel circuit 42 among the plurality of second pixel circuits 42 may be electrically connected to at least one second light emitting element 32 among the plurality of second light emitting elements 32, and the orthographic projection of at least one second pixel circuit 42 on the substrate may at least partially overlap with the orthographic projection of at least one second light emitting element 32 on the substrate. The second pixel circuit 42 may be configured to provide a driving signal to the connected second light emitting element 32 to drive the corresponding second light emitting element 32 to emit light. For example, the plurality of second pixel circuits 42 and the plurality of second light emitting elements 32 may be in a one-to-one driving relationship, or may be in a one-to-many driving relationship.

[0084] Figure 2A schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 3 FIG. 1 is a schematic diagram of an arrangement of pixel circuits in the second display area of ​​at least one embodiment of the present disclosure. Figure 2 and Figure 3 As shown, the second display area A2 may include: a first sub-area A21 and a second sub-area A22. The first sub-area A21 may be located on both sides of the first display area A1 along the first direction D1, and the second sub-area A22 may surround the first sub-area A1. The second sub-area A22 may include: a first partition A221 and a second partition A222 located on both sides of the second sub-area A21 along the first direction D1, and a third partition A223 and a fourth partition A224 located on both sides of the first sub-area A21 along the second direction D2. The third partition A223 and the fourth partition A224 are located on both sides of the first display area A1 along the second direction D2.

[0085] In some examples, the multiple pixel circuits of the second display area A2 may include: multiple first pixel circuits 41, multiple invalid pixel circuits 43, and multiple second pixel circuits 42. The multiple first pixel circuits 41 and the multiple invalid pixel circuits 43 may be arranged between the multiple second pixel circuits 42 along the first direction D1. The multiple first pixel circuits 41 may be located in the first sub-area A21. The first sub-area A21 may also be referred to as a transition area. This example can help improve the uniformity of components of multiple film layers in the etching process by setting multiple invalid pixel circuits 43 in the second display area A2. For example, the invalid pixel circuit 43 may have a structure substantially the same as the first pixel circuit 41 in its row or column, except that it is not electrically connected to any light-emitting element.

[0086] In some examples, at least one first pixel circuit 41 can be electrically connected to at least one first light-emitting element 31 through a conductive connection line 51, and is configured to drive the at least one first light-emitting element 31 to emit light. For example, a single first light-emitting element 31 emitting a first color light (e.g., green G) in the first display area A1 can be driven by a first pixel circuit 41, a single first light-emitting element 31 emitting a second color light (e.g., red R) in the first display area A1 can be driven by a first pixel circuit 41, and a single first light-emitting element 31 emitting a third color light (e.g., blue B) in the first display area A1 can be driven by a first pixel circuit 41. In some examples, the first pixel circuit driving the first region light-emitting element 31 emitting the first color light can be located on the side of the first pixel circuit driving the first region light-emitting element 31 emitting the second color light and the third color light close to the first display area A1. In some examples, the conductive connection line 51 can be made of a transparent conductive material to improve the light transmittance of the display substrate. For example, a plurality of conductive connection lines 51 can be arranged in at least one conductive connection layer. In some other examples, two first light emitting elements 31 emitting first color light (eg, green G) in the first display area A1 may be driven by the same first pixel circuit 41 .

[0087] In some examples, since the second display area A2 is not only provided with a second pixel circuit 42 electrically connected to the second light-emitting element 32, but also provided with a first pixel circuit 41 electrically connected to the first light-emitting element 31, the number of pixel circuits in the second display area A2 is greater than the number of second light-emitting elements 32. In some examples, the area for setting the newly added pixel circuit (including the first pixel circuit 41 and the invalid pixel circuit 43) can be obtained by reducing the size of the second pixel circuit 42 in the first direction D1. For example, the size of the pixel circuit in the first direction D1 can be smaller than the size of the second light-emitting element in the first direction D1.

[0088] In this example, a plurality of pixel circuits in the second display area A2 can be arranged in an array along the first direction D1 and the second direction D2. Each of the original a pixel circuit columns can be compressed along the first direction D1 to add an arrangement space for a new pixel circuit column, and the space occupied by the a pixel circuit columns before compression and the a+1 pixel circuit columns after compression can be the same. Wherein, a can be an integer greater than 1. In some examples, a can be equal to 4. That is, along the first direction D1, a first pixel circuit column 410 or an invalid pixel circuit column 430 can be arranged for every four second pixel circuit columns 420. However, this embodiment is not limited to this. For example, a can be equal to 2 or 3.

[0089] In other examples, the original b pixel circuit rows can be compressed along the second direction D2 to add an arrangement space for a new pixel circuit row, and the space occupied by the b pixel circuit rows before compression and the b+1 pixel circuit rows after compression is the same. Wherein, b can be an integer greater than 1. Alternatively, the area for setting the newly added pixel circuit can be obtained by reducing the size of the second pixel circuit in the first direction D1 and the second direction D2. In this example, the first sub-area can be located on both sides of the first display area along the second direction.

[0090] In this example, a pixel circuit column may include a plurality of pixel circuits sequentially arranged along the second direction D2. A pixel circuit row may include a plurality of pixel circuits sequentially arranged along the first direction D1. A plurality of pixel circuits in a pixel circuit row may all be connected to the same gate line.

[0091] In some examples, in the second display area A2, a plurality of second pixel circuit columns 420, a plurality of first pixel circuit columns 410, and a plurality of invalid pixel circuit columns 430 may be arranged at intervals along the first direction D1. Each second pixel circuit column 420 (also referred to as a column of second pixel circuits) includes a plurality of second pixel circuits 42 arranged in sequence along the second direction D2; each first pixel circuit column 410 (also referred to as a column of first pixel circuits) includes a plurality of first pixel circuits 41 arranged in sequence along the second direction D2, and each invalid pixel circuit column 430 (also referred to as a column of invalid pixel circuits) includes a plurality of invalid pixel circuits 43 arranged in sequence along the second direction D2. For example, in the first sub-area A21, one first pixel circuit column 410 may be arranged every four second pixel circuit columns 420, and in the second sub-area A22, one invalid pixel circuit column 430 may be arranged every four second pixel circuit columns 420. Multiple invalid pixel circuit columns 430 in the third partition A223 and the fourth partition A224 of the second sub-region A22 can be aligned along the second direction D2, and multiple first pixel circuit columns 410 in the first sub-region A21 can be aligned along the second direction D2 with some invalid pixel circuit columns 430 in the third partition A223 and the fourth partition A224.

[0092] In some examples, the plurality of conductive connection lines 51 may extend at least along the first direction D1. The plurality of conductive connection lines 51 may extend from the first display area A1 to the first sub-area A21 of the second display area A2 and connect to the plurality of first pixel circuits 41 in the first sub-area A21.

[0093] Figure 4 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described by taking a 7T1C structure as an example. In some examples, such as Figure 4As shown, the pixel circuit of this example may include a first transistor (also referred to as a first reset transistor) T1, a second transistor (also referred to as a threshold compensation transistor) T2, a third transistor (also referred to as a driving transistor) T3, a fourth transistor (also referred to as a data writing transistor) T4, a fifth transistor (also referred to as a first light emission control transistor) T5, a sixth transistor (also referred to as a second light emission control transistor) T6, a seventh transistor (also referred to as a second reset transistor) T7 and a storage capacitor Cst. The light emitting element EL may include an anode, a cathode and an organic light emitting layer disposed between the anode and the cathode.

[0094] In some examples, such as Figure 4 As shown, the display substrate may include: a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emitting control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 may be configured to provide a constant first power signal VDD to the pixel circuit, the second power line PL2 may be configured to provide a constant second power signal VSS to the cathode of the light emitting element EL, and the first power signal VDD is greater than the second power signal VSS. The scan line GL may be configured to provide a scan signal SCAN to the pixel circuit, the data line DL may be configured to provide a data signal DATA to the pixel circuit, the light emitting control line EML may be configured to provide a light emitting control signal EM to the pixel circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, the second reset control line RST2 electrically connected to the pixel circuit of the jth row and the first reset control line RST1 electrically connected to the pixel circuit of the j+1th row may be an integrated structure, wherein j is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be achieved.

[0095] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their sizes can be, for example, between the first power signal VDD and the second power signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.

[0096] In some examples, such as Figure 4As shown, the third transistor T3 is electrically connected to the light emitting element EL, and outputs a driving current under the control of the scan signal SCAN, the data signal DATA, the first power signal VDD, the second power signal VSS and other signals to drive the light emitting element EL to emit light. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GL, the second electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the first electrode of the second transistor T2 is electrically connected to the second electrode of the driving transistor T3. The gate of the fifth transistor T5 is electrically connected to the light emitting control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light emitting control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting element EL. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light emitting element EL and is configured to reset the anode of the light emitting element EL. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0097] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3, the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0098] Below Figure 4 The working process of the pixel circuit is described as follows. Figure 4 The pixel circuit shown in the figure includes a plurality of transistors which are all P-type transistors. In some examples, in a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage and a third stage.

[0099] The first stage is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, which initializes the first node N1 and clears the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, which turns off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the light-emitting element EL does not emit light.

[0100] The second stage is called the data writing stage or the threshold compensation stage. The scanning signal SCAN provided by the scanning line GL is a low level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the light control signal EM provided by the light control line EML are both high level signals, and the data line DL outputs the data signal DATA. In this stage, since the first electrode of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The scanning signal SCAN is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light emitting element EL, the anode of the light emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the light emitting element EL is ensured not to emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, so that the first transistor T1 is turned off. The light control signal EM provided by the light control line EML is a high level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.

[0101] The third stage is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, and the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the first power signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0102] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0103] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0104] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first power signal output by the first power line PL1.

[0105] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0106] Figure 5 A partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 5 The structure of a second light-emitting element and a second pixel circuit in the second display area is used as an example for illustration. In this example, the same type of multiple transistors in the pixel circuit is used as an example for illustration. For example, multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In other examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors.

[0107] In some examples, such as Figure 5As shown, in a direction perpendicular to the display substrate, the second display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 11, three conductive connection layers 12, a light emitting structure layer 13 and a packaging structure layer 14 sequentially arranged on the substrate 10. The circuit structure layer 11 of the second display area may include at least: a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of invalid pixel circuits, each pixel circuit may include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 of the second display area may include at least: a plurality of second light emitting elements.

[0108] In some examples, Figure 5 In the figure, a thin film transistor 21 and a capacitor 22 included in the second pixel circuit are used as an example for illustration. In some examples, the circuit structure layer 11 of the second display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate 10. A first gate insulating layer 101 may be arranged between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be arranged between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be arranged between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first flat layer 105 may be arranged between the first source-drain metal layer and the second source-drain metal layer, a second flat layer 106 may be arranged between the second source-drain metal layer and the third source-drain metal layer, and a third flat layer 107 may be arranged on the side of the third source-drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103 and the passivation layer 104 can be inorganic insulating layers, and the first flat layer 105, the second flat layer 106 and the third flat layer 107 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can also be provided on the side of the semiconductor layer close to the substrate, and the buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate, and can also increase the adhesion of the film layer in the display substrate on the substrate. In other examples, a bottom shading metal layer (BSM, Bottom Shielding Metal) can be provided on the side of the buffer layer close to the substrate, and the bottom shading metal layer can be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to avoid external light from affecting the performance of the thin film transistor. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first flat layer can be provided between the first source and drain metal layer and the second source and drain metal layer. In some other examples, the circuit structure layer may omit the third source-drain metal layer, or the circuit structure layer may further include a fourth source-drain metal layer located on a side of the third source-drain metal layer away from the substrate.

[0109] In some examples, such as Figure 5As shown, the three conductive connection layers 12 may include: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer sequentially arranged along the direction of the substrate 10. A fourth flat layer 108 may be arranged between the first conductive connection layer and the second conductive connection layer, a fifth flat layer 109 may be arranged between the second conductive connection layer and the third conductive connection layer, and a sixth flat layer 110 may be arranged on the side of the third conductive connection layer away from the substrate 10. The fourth flat layer 108, the fifth flat layer 109, and the sixth flat layer 110 may be organic insulating layers. In some examples, the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer may be made of transparent conductive materials, such as indium tin oxide (ITO).

[0110] In some examples, such as Figure 5As shown, the semiconductor layer of the second display area may include at least: an active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first area 2101, a second area 2102, and a channel area 2100 located between the first area 2101 and the second area 2102. The first gate metal layer may include at least: a gate electrode 213 of the thin film transistor 21, and a first electrode plate 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel area 2100 of the active layer 210 on the substrate 10. The second gate metal layer may include at least: a second electrode plate 222 of the capacitor 22. The orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may overlap. The first source-drain metal layer may include at least: a source electrode 211 and a drain electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least: a first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain electrode 212 of the thin film transistor 21 of the pixel circuit through the third pixel via hole opened in the passivation layer 104 and the first flat layer 105. The third source-drain metal layer can at least include: a second transfer electrode 232, and the second transfer electrode 232 can be connected to the first transfer electrode 231 through a fourth pixel via hole opened in the second flat layer 106. The first conductive connection layer can at least include: a third transfer electrode 233, and the third transfer electrode 233 can be connected to the second transfer electrode 232 through a fifth pixel via hole opened in the third flat layer 107. The second conductive connection layer can at least include: a fourth transfer electrode 234, and the fourth transfer electrode 234 can be connected to the third transfer electrode 233 through a sixth pixel via hole opened in the fourth flat layer 108. The third conductive connection layer can at least include: a fifth transfer electrode 235, and the fifth transfer electrode 235 can be connected to the fourth transfer electrode 234 through a seventh pixel via hole opened in the fifth flat layer 109. In some examples, the orthographic projections of the fifth pixel via hole, the sixth pixel via hole, and the seventh pixel via hole on the substrate may be rectangular or circular.For example, the orthographic projections of the seventh pixel via and the fifth pixel via on the substrate may overlap, and the orthographic projections of the sixth pixel via on the substrate and the orthographic projections of the seventh pixel via on the substrate may not overlap. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the second source-drain metal layer, the third source-drain metal layer, and the three conductive connection layers. However, this embodiment is not limited to this. In other examples, the number of conductive connection layers can be one, two, or more.

[0111] In some examples, the orthographic projections of the third switching electrode 233, the fourth switching electrode 234, and the fifth switching electrode 235 on the substrate may be rectangular. The orthographic projections of the third switching electrode 233, the fourth switching electrode 234, and the fifth switching electrode 235 on the substrate may overlap, and may at least partially overlap with the orthographic projection of the second switching electrode 232 on the substrate.

[0112] In some examples, such as Figure 5 As shown, the light emitting structure layer 13 of the display area may include: a pixel definition layer 304 and a plurality of light emitting elements (for example, including a plurality of second light emitting elements located in the second display area and a plurality of first light emitting elements located in the first display area). For example, each light emitting element may include: a stacked first electrode 301, an organic light emitting layer 302, and a second electrode 303. The first electrode 301 of the light emitting element may be an anode. For example, the first electrode 301 of the second light emitting element located in the second display area A2 may be disposed on the fifth flat layer 110, and electrically connected to the fifth transfer electrode 235 through the eighth pixel via hole opened in the fifth flat layer 110. The pixel definition layer 304 is disposed on the first electrode 301 and the fifth flat layer 110, and the pixel definition layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light emitting layer 302 may be disposed in a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light emitting layer 302 and connected to the organic light emitting layer 302. The organic light emitting layer 302 can emit light of corresponding colors under the drive of the first electrode 301 and the second electrode 303. An isolation column layer can be further provided on the side of the pixel definition layer 304 away from the substrate 10, and the isolation column layer can include a plurality of isolation columns (PS).

[0113] In some examples, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0114] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, FineMetalMask) or an open mask (Open Mask), or by inkjet technology.

[0115] In some examples, such as Figure 5 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 1401, a second encapsulation layer 1402, and a third encapsulation layer 1403 stacked. Among them, the first encapsulation layer 1401 and the third encapsulation layer 1403 may be made of inorganic materials, the second encapsulation layer 1402 may be made of organic materials, and the second encapsulation layer 1402 may be arranged between the first encapsulation layer 1401 and the third encapsulation layer 1403 to ensure that external water vapor cannot enter the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0116] The film layer structure of the second sub-area of ​​the second display area is described below by way of example. 6A to 7DIn the figure, a row (eg, the jth row) and three columns (eg, the i-1th column to the i+1th column) of pixel circuits in the second sub-area of ​​the second display area are taken as an example for illustration. 6A to 7D Can be Figure 1 A partial enlarged schematic diagram of the area S1 in the middle. Among them, the pixel circuits in the i-1th column to the i+1th column are all second pixel circuit columns, and i is an integer greater than 0. In this example, in the second display area, a column of first pixel circuits or a column of invalid pixel circuits is arranged every four columns of second pixel circuits. The equivalent circuit diagram of the second pixel circuit can be as follows Figure 4 As shown, it may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0117] Fig. 6A FIG. 1 is a partial schematic diagram of a semiconductor layer and a first gate metal layer in a second sub-region of a second display region according to at least one embodiment of the present disclosure. Fig. 6A As shown, the semiconductor layer of the second sub-region may include: active layers of multiple transistors of multiple second pixel circuits (for example, active layers of the first transistor T1 to the seventh transistor T7). The active layers of the first transistor T1 to the seventh transistor T7 of a single second pixel circuit may be an integrated structure connected to each other.

[0118] In some examples, such as Fig. 6A As shown, the first gate metal layer of the second sub-region may include: gates of multiple transistors of multiple second pixel circuits (for example, including gates of the first transistor T1 to the seventh transistor T7), multiple scan lines (for example, including the scan line GL(j)), multiple first reset control lines (for example, including the first reset control line RST1(j)), and multiple light-emitting control lines (for example, including the light-emitting control line EML(j)). The scan line GL(j), the first reset control line RST1(j), and the light-emitting control line EML(j) may all extend along the first direction D1; for example, the scan line GL(j) and the first reset control line RST1(j) may be in the shape of a zigzag line extending along the first direction D1, and the light-emitting control line EML(j) may be in the shape of a straight line extending along the first direction D1.

[0119] In some examples, the first reset control line RST1(j) connected to the pixel circuit of the j-th row can be used as the second reset control line connected to the pixel circuit of the j-1-th row. The scan line GL(j) and the gate of the second transistor T2 and the gate of the fourth transistor T4 of the second pixel circuit located in the j-th row can be an integrated structure connected to each other. The first reset control line RST1(j) and the gate of the first transistor T1 of the second pixel circuit located in the j-th row can be an integrated structure connected to each other. The light emission control line EML(j) and the gate of the fifth transistor T5 and the gate of the sixth transistor T6 of the second pixel circuit located in the j-th row can be an integrated structure connected to each other. The gate of the third transistor T3 of the second pixel circuit can also serve as the first electrode of the storage capacitor of the second pixel circuit.

[0120] Figure 6B FIG. 1 is a partial schematic diagram of a second sub-region of a second display region after forming a second gate metal layer according to at least one embodiment of the present disclosure. Figure 6B As shown, the second gate metal layer of the second sub-region may include: a plurality of first initial signal lines (for example, including the first initial signal line INIT1(j)), a plurality of second initial signal lines (for example, including the second initial signal line INIT2(j-1)), and a second electrode of a storage capacitor Cst of a plurality of second pixel circuits. The second plates of the storage capacitors Cst of the plurality of second pixel circuits in the same row may be an integrated structure connected to each other. The plurality of first initial signal lines and the plurality of second initial signal lines may extend along the first direction D1, for example, may be a fold line extending along the first direction D1.

[0121] Figure 6C FIG. 1 is a partial schematic diagram of a second sub-area of ​​a second display area after forming a first source-drain metal layer according to at least one embodiment of the present disclosure. Figure 6C As shown, the first source-drain metal layer of the second sub-region may include: a plurality of pixel connection electrodes (eg, including the first pixel connection electrode 401 to the sixth pixel connection electrode 406 ), and a plurality of first transmission lines 55 .

[0122] In some examples, the first transmission line 55 may be located between two adjacent rows of pixel circuits (e.g., the jth row and the j+1th row of pixel circuits) and extend along the first direction D1. The first transmission line 55 may be connected to the pixel connection electrode to which the invalid pixel circuit is connected to form a power transmission network to facilitate the discharge of static electricity in the second display area.

[0123] In some examples, the active layer of the first transistor T1 of the second pixel circuit located in the j-th row can be connected to the first initial signal line INIT1(j) through the first pixel connection electrode 401, the gate of the third transistor T3 can be connected to the active layer of the second transistor T2 through the second pixel connection electrode 402, the active layer of the fourth transistor T4 can be connected to the fourth pixel connection electrode 404, the active layer of the fifth transistor T5 can be connected to the second electrode of the storage capacitor Cst through the third pixel connection electrode 403, and the active layer of the sixth transistor T6 can be connected to the fifth pixel connection electrode 405; the active layer of the seventh transistor T7 of the second pixel circuit located in the j-1-th row can be connected to the second initial signal line INIT2(j-1) through the sixth pixel connection electrode 406.

[0124] In some examples, the orthographic projection of the first pixel connection electrode 401 on the substrate may be roughly a rectangular ring. The orthographic projection of the second pixel connection electrode 402 on the substrate may be roughly a fold line extending along the second direction D2. The orthographic projection of the third pixel connection electrode 403 on the substrate may be roughly a strip extending along the second direction D2. The orthographic projection of the fourth pixel connection electrode 404 on the substrate may be roughly a rectangle. The orthographic projection of the fifth pixel connection electrode 405 on the substrate may be roughly a rectangle. The orthographic projection of the sixth pixel connection electrode 406 on the substrate may be roughly a dumbbell extending along the second direction D2. In this example, the shapes of the multiple pixel connection electrodes connected to the invalid pixel circuit may be roughly the same as the shapes of the multiple pixel connection electrodes connected to the second pixel circuit, which is beneficial to improve the uniformity of the first source and drain metal layer in the etching process.

[0125] Fig.6D FIG. 1 is a schematic diagram of a second sub-area of ​​a second display area after forming a second source / drain metal layer according to at least one embodiment of the present disclosure. Fig.6D As shown, the second source-drain metal layer of the second sub-area may include: a plurality of first power lines (e.g., a first power line PL1a), a plurality of switching electrodes (e.g., including a first switching electrode 231 and a sixth switching electrode 236). The plurality of first power lines PL1a may extend along the second direction D2, for example, in the shape of a zigzag extending along the second direction D2. For example, a first power line PL1a may be connected to the third pixel connection electrode 403 to achieve connection with the active layer of the fifth transistor T5 of the second pixel circuit and the second electrode of the storage capacitor Cst. A first power line connected to the invalid pixel circuit may be connected to the first transmission line 55 to form a power transmission network.

[0126] In some examples, the sixth switching electrode 236 can be connected to the fourth pixel connection electrode 404 to achieve an active layer connection with the fourth transistor T4 of the second pixel circuit. The first switching electrode 231 can be connected to the fifth pixel connection electrode 405 to achieve an active layer connection with the sixth transistor T4 of the second pixel circuit.

[0127] Fig. 6E FIG. 1 is a schematic diagram of a second sub-area of ​​a second display area after forming a third source / drain metal layer according to at least one embodiment of the present disclosure. Fig. 6E As shown, the third source-drain metal layer of the second sub-region may include: a plurality of first data transfer lines 56, a plurality of data lines (for example, including data lines DLa), and a plurality of transfer electrodes (for example, including second transfer electrodes 232). The plurality of first data transfer lines 56 and the plurality of data lines DLa may extend along the second direction D2 and be arranged at intervals along the first direction D1. For example, the data line DLa may be connected to the sixth transfer electrode 236 to achieve electrical connection with the second pixel circuit, and is configured to provide a data signal to the second pixel circuit.

[0128] In some examples, the first data transfer line 56 can be connected to the second data transfer line extending along the first direction D1, and connected to the data line close to the third frame area or the fourth frame area through the second data transfer line extending along the first direction D1, so that the data line close to the third frame area or the fourth frame area can be connected to the first frame area from a position away from the third frame area or the fourth frame area through the second data transfer line and the first data transfer line 56. For example, the second data transfer line can be located between adjacent row pixel circuits. The first data transfer line 56 extends to the first frame area, so that the routing lines for transmitting data signals in the first frame area can be centrally arranged in the middle position of the display substrate, which is beneficial to reduce the size of the first frame area and to achieve a narrow frame design.

[0129] In some examples, the second switching electrode 232 can be connected to the first switching electrode 231 to achieve electrical connection with the second pixel circuit. In this example, the second switching electrode 232 can be connected to the anode of the second light emitting element to achieve electrical connection between the second pixel circuit and the second light emitting element.

[0130] Fig. 7A It is a partial schematic diagram of the second sub-area of ​​the second display area after the first conductive connection layer is formed according to at least one embodiment of the present disclosure. Figure 7B for Fig. 7A Schematic diagram of the first conductive connection layer in FIG. Figure 7C The diagram is a partial schematic diagram of the second sub-area of ​​the second display area after the second conductive connection layer is formed according to at least one embodiment of the present disclosure. Fig.7D for Figure 7C Schematic diagram of the second conductive connection layer in FIG. Fig. 7E It is a partial schematic diagram of the second sub-area of ​​the second display area after the third conductive connection layer is formed according to at least one embodiment of the present disclosure. Figure 8 It is a partial schematic diagram of the first conductive connection layer, the second conductive connection layer and the third conductive connection layer of the second sub-region of at least one embodiment of the present disclosure.

[0131] In some examples, such as Fig. 7A and, Figure 7B and Figure 8 As shown, the first conductive connection layer of the second sub-area may include: a plurality of first auxiliary wirings 61 and a plurality of transfer electrodes (for example, including the third transfer electrode 233). The plurality of first auxiliary wirings 61 are arranged along the second direction D2. The first auxiliary wiring 61 may include: a first main body 611 extending along the first direction D1, a plurality of first extensions 612 and a plurality of second extensions 613 extending along the second direction D2, and a plurality of first auxiliary connection electrodes 614. The plurality of first extensions 612 may be connected to the plurality of first auxiliary connection electrodes 614 in a one-to-one correspondence. The plurality of first extensions 612, the plurality of second extensions 613, and the plurality of first auxiliary connection electrodes 614 may be connected to the same side of the first main body 611 along the second direction D2. The first main body 611, the plurality of first extensions 612, the plurality of second extensions 613, and the plurality of first auxiliary connection electrodes 614 are an integrated structure.

[0132] In some examples, the orthographic projection of the first extension portion 612 and the second extension portion 613 on the substrate may be approximately in the shape of a folded line extending along the second direction D2. The orthographic projection of the first auxiliary connection electrode 614 on the substrate may be approximately in the shape of a rectangle. The first extension portion 612 and the second extension portion 613 of the same first auxiliary wiring 61 may be arranged at intervals along the first direction D2. Along the second direction D2, the first extension portions 612 and the second extension portions 613 of multiple first auxiliary wirings 61 may be arranged in alignment.

[0133] In some examples, such as Fig. 7A and Figure 7B As shown, the orthographic projection of the first main body 611 on the substrate may be located between the orthographic projection of the scan line GL(j) and the first initial signal line INIT1(j) on the substrate, and the orthographic projections of the first main body 611 and the first initial signal line INIT1(j) on the substrate may partially overlap. In other examples, the orthographic projections of the first main body 611 and the first initial signal line INIT1(j) on the substrate may not overlap. The arrangement of this example can reduce the increase in routing load caused by routing overlap.

[0134] In some examples, such as Fig. 7A , Figure 7B and Figure 8As shown, the orthographic projection of the first extension portion 612 (or the second extension portion 613) on the substrate may partially overlap with the orthographic projection of the storage capacitor Cst of the second pixel circuit on the substrate. The orthographic projection of the first auxiliary connection electrode 614 on the substrate may at least partially overlap with the orthographic projection of the connection position of the fifth transistor of the second pixel circuit and the first power line PL1a on the substrate.

[0135] In some examples, such as Fig. 7A As shown, a single first auxiliary connection electrode 614 can be located between two adjacent third transfer electrodes 233 along the first direction D1. The first auxiliary connection electrode 614 can be aligned with the adjacent third connection electrodes 233 along the first direction D1. The third transfer electrode 233 can be connected to the second transfer electrode 232 to achieve electrical connection with the pixel circuit.

[0136] In some examples, such as Figure 7C , Fig.7D and Figure 8 As shown, the second conductive connection layer of the second sub-area may include: a plurality of second auxiliary traces 62 and a plurality of switching electrodes (eg, including a fourth switching electrode 234). Fig. 7E and Figure 8 As shown, the third conductive connection layer of the second sub-region may include: a plurality of switching electrodes (eg, including a fifth switching electrode 235 ).

[0137] In some examples, such as Figure 7C , Fig.7D and Figure 8 As shown, a plurality of second auxiliary wirings 62 may extend along the second direction D2 and be arranged along the first direction D1. The second auxiliary wiring 62 may include: a second main body 621 extending along the second direction D2 and a plurality of second auxiliary connection electrodes 622. The second main body 621 and the plurality of second auxiliary connection electrodes 622 are an integral structure. The orthographic projection of the second main body 621 on the substrate may be a fold line extending along the second direction D2. The orthographic projection of the second main body 621 on the substrate may be located between the orthographic projection of the data line DLa connected to a second pixel circuit column and the first data transfer line 56 arranged in the second pixel circuit column on the substrate. The orthographic projection of the second main body 621 on the substrate may not overlap with the orthographic projection of the data line DLa connected to the second pixel circuit column and the first data transfer line 56 arranged in the second pixel circuit column on the substrate. The arrangement of this example can reduce the increase in wiring load caused by wiring overlap.

[0138] In some examples, the orthographic projection of the second auxiliary connection electrode 622 on the substrate may be a rectangle. A single second auxiliary connection electrode 622 may be located between two adjacent fourth transfer electrodes 234 along the first direction D1. The second auxiliary connection electrode 622 may be aligned with the adjacent fourth transfer electrodes 234 along the first direction D1. The orthographic projection of the second auxiliary connection electrode 622 on the substrate may cover the orthographic projection of the first auxiliary connection electrode 614 on the substrate. The fourth transfer electrode 234 may be connected to the third transfer electrode 233 to achieve electrical connection with the pixel circuit.

[0139] In some examples, the plurality of first auxiliary wirings 61 and the plurality of second auxiliary wirings 62 may be connected in the second sub-area A22 to form a mesh structure. The insulating layer disposed between the second conductive connection layer and the first conductive connection layer may be a fourth planar layer 108 (eg, Figure 5 The fourth planar layer 108 may be provided with a plurality of auxiliary via holes K1. The second auxiliary connection electrode 621 may be electrically connected to the first auxiliary connection electrode 614 through at least one auxiliary via hole K1.

[0140] Fig. 9 FIG. 1 is a schematic diagram of the arrangement of multiple auxiliary transfer holes in the second sub-area of ​​at least one embodiment of the present disclosure. Fig. 9 As shown, the first sub-area A21 is located at both sides of the first display area A1 along the first direction D1. The second sub-area A22 may include: a first partition A221 and a second partition A222 located at both sides of the second sub-area A21 along the first direction D1, and a third partition A223 and a fourth partition A224 located at both sides of the first sub-area A21 along the second direction D2. The third partition A223 and the fourth partition A224 are located at both sides of the first display area A1 along the second direction D2.

[0141] In some examples, in the first partition A221 and the second partition A222, the multiple auxiliary adapter holes K1 may be arranged in a V-shape; in the first partition A221 and the second partition A222, the V-shaped arrangement of the multiple auxiliary adapter holes K1 is substantially the same. In the third partition A223 and the fourth partition A224, the multiple auxiliary adapter holes K1 may be arranged in a V-shape; in the third partition A223 and the fourth partition A224, the V-shaped arrangement of the multiple auxiliary adapter holes K1 is substantially the same. The size of the V-shape formed by the arrangement of the multiple auxiliary adapter holes K1 in the first partition A221 may be larger than the size of the V-shape formed by the arrangement of the multiple auxiliary adapter holes K1 in the third partition A223. Among them, the maximum length of the V-shaped arrangement formed by the multiple auxiliary transfer holes K1 in the first partition A221 along the first direction D1 can be greater than the maximum length of the V-shaped arrangement formed by the multiple auxiliary transfer holes K1 in the third partition A223 along the first direction D1; the maximum length of the V-shaped arrangement formed by the multiple auxiliary transfer holes K1 in the first partition A221 along the second direction D2 can be greater than the maximum length of the V-shaped arrangement formed by the multiple auxiliary transfer holes K1 in the third partition A223 along the second direction D2. The arrangement method of this example can ensure that the first auxiliary wiring corresponding to each row of pixel circuits in the second sub-area can be connected to the same number of second auxiliary wirings, that is, each row of pixel circuits can correspond to an adjacent number of auxiliary transfer holes, thereby ensuring the uniformity of the arrangement of the auxiliary transfer holes in the second sub-area.

[0142] This example can not only realize the mesh connection of multiple first auxiliary routing lines and multiple second auxiliary routing lines through multiple auxiliary transfer holes, but also improve the situation where the via gap corresponding to adjacent third transfer electrodes (or fourth transfer electrodes, or fifth transfer electrodes) located on the same conductive connection layer connected to each row of pixel circuits is too large, resulting in inconsistent opening environment.

[0143] Fig. 10A This is a partial schematic diagram of the boundary between the display area and the first frame area of ​​at least one embodiment of the present disclosure. Fig. 10A Can be Figure 1 A partial enlarged schematic diagram of the middle area S2. Fig. 10A In the figure, the second source-drain metal layer, the third source-drain metal layer, the first conductive connection layer, the second conductive connection layer and the third conductive connection layer are taken as examples for illustration, and the remaining film layers are omitted for illustration. Fig. 10AIn the example, the partial film layer corresponding to the pixel circuits of two rows (e.g., the j-1st row and the jth row) and nine columns (e.g., the i-2nd column to the i+6th column) in the second sub-area of ​​the second display area is used for illustration. For example, the pixel circuits of the i-2nd column and the i+3rd column include a plurality of invalid pixel circuits, and the pixel circuits of the i-1st column to the i+2nd column and the i+4th column to the i+6th column include a plurality of second pixel circuits. In this example, an invalid pixel circuit column or a first pixel circuit column may be arranged every four second pixel circuit columns. For example, the pixel circuits of the i-2nd column and the i+3rd column may be invalid pixel circuit columns in the first sub-area of ​​the second display area. In some examples, the data line connected to the first pixel circuit column in the first sub-area and the data line connected to the invalid pixel circuit column aligned in the second sub-area may be disconnected, and the data line connected to the first pixel circuit column may be connected to the data line connected to the second pixel circuit column aligned in the second direction by a first light-emitting element connected to the first pixel circuit column through a jumper. A first pixel circuit column located in the first sub-area and an invalid pixel circuit column aligned in the second sub-area may be connected to the same first power line.

[0144] Fig. 10B for Fig. 10A Schematic diagram of the first gate metal layer and the second gate metal layer in the first border area B1. Fig. 10C for Fig. 10A Schematic diagram of the second source and drain metal layer in . Fig. 10D for Fig. 10A Schematic diagram of the second source-drain metal layer and the third source-drain metal layer in FIG. Fig.10E for Fig. 10A Schematic diagram of the third source and drain metal layer in . Fig.10F for Fig. 10A Schematic diagram of the second source-drain metal layer, the third source-drain metal layer and the first conductive connection layer. Figure 10G for Fig. 10A Schematic diagram of the first conductive connection layer in FIG. Fig. 10H for Fig. 10A Schematic diagram of the second source-drain metal layer, the third source-drain metal layer, the first conductive connection layer and the second conductive connection layer. Fig.10I for Fig. 10A Schematic diagram of the second conductive connection layer in .

[0145] In some examples, such as Fig. 10A and Fig. 10BAs shown, the first gate metal layer of the first frame region B1 may include: a plurality of first data lead lines 581, and the second gate metal layer of the first frame region B1 may include: a plurality of second data lead lines 582. The plurality of first data lead lines 581 and the plurality of second data lead lines 582 may be arranged at intervals along the first direction D1. The orthographic projections of the plurality of first data lead lines 581 on the substrate and the orthographic projections of the plurality of second data lead lines 582 on the substrate may not overlap.

[0146] In some examples, such as Fig. 10A and Fig. 10C As shown, the second source-drain metal layer may include: a plurality of first power lines (for example, including first power lines PL1a and PL1b) located in the second sub-area, a plurality of transfer electrodes (for example, including a first transfer electrode 231 and a sixth transfer electrode 236), and a first peripheral power line 71 located in the first border area B1, a plurality of first power connection electrodes 711, a plurality of second power connection electrodes 712, and a plurality of data transfer electrodes 731a and 731b. The first peripheral power line 71 may be configured to transmit a first power signal.

[0147] In some examples, the first power lines PL1a and PL1b may extend along the second direction D2. The first power line PL1a may be connected to a second pixel circuit column, the first power line PL1b may be connected to an invalid pixel circuit column, or a first pixel circuit column and an aligned invalid pixel circuit column. For example, a first pixel circuit column located in the first sub-area and an invalid pixel circuit column aligned in the third sub-area and the fourth sub-area may be connected to the same first power line PL1b. The first power lines PL1a and PL1b may extend to the first border area B1 and be connected to the first peripheral power line 71. The first peripheral power line 71 may extend at least along the first direction D1. The first power line PL1a and the first peripheral power line 71 may be an integral structure, and the first power line PL1b and the first peripheral power line 71 may be an integral structure.

[0148] In some examples, the first power line PL1b may be connected to a first power connection electrode 711 in the first frame area B1. For example, the first power line PL1b and the first power connection electrode 711 may be an integral structure. The orthographic projection of the first power connection electrode 711 on the substrate may be a rectangle extending along the first direction D1. The first power connection electrode 711 may be located between the connected first power line PL1b and the first power line PL1a adjacent to the first direction D1.

[0149] In some examples, the second power connection electrode 712 can be connected to the first peripheral power line 71. For example, the second power connection electrode 712 and the first peripheral power line 71 can be an integral structure. The orthographic projection of the second power connection electrode 712 on the substrate can be a rectangle extending along the second direction D2. The second power connection electrode 712 can be located between the first power line PL1b and the first power line PL1a adjacent to the first direction D1, and located on the side of the first power connection electrode 711 away from the display area.

[0150] In some examples, in the first frame area B1, a plurality of data switching electrodes 731a and 731b may be located on a side of the first peripheral power line 71 close to the display area. Two data switching electrodes 731a and 731b may be disposed between two adjacent first power lines PL1a, or between a first power line PL1a and a first power line PL1b adjacent along the first direction D1. The two data switching electrodes 731a and 731b may be arranged along the second direction D2.

[0151] In some examples, the data transfer electrode 731a may be formed by an interlayer insulating layer 103 (eg, Figure 5 The via hole opened in the second gate metal layer is connected to the first data lead line 581, and the data transfer electrode 731b can pass through the interlayer insulating layer 103 and the second gate insulating layer 102 (as shown in FIG. Figure 5 The via holes opened in the first gate metal layer are connected to the second data lead lines 582 located in the first gate metal layer. In this way, the multiple data transfer electrodes 731a can be connected to the multiple first data lead lines 581 located in the second gate metal layer, and the multiple data transfer electrodes 731b can be connected to the multiple second data lead lines 582 located in the first gate metal layer, so as to realize the transmission of data signals.

[0152] In some examples, such as Fig. 10A , Fig. 10D and Fig.10E As shown, the third source-drain metal layer may include: a plurality of data lines (for example, including data lines DLa and DLb) located in the second sub-area, a plurality of first data transfer lines 56, a plurality of invalid data transfer lines 57, a plurality of transfer electrodes (for example, including second transfer electrodes 232), and a second peripheral power line 72 and a plurality of third power connection electrodes 713 located in the first frame area B1. The second peripheral power line 72 is configured to transmit a second power signal. The second peripheral power line 72 may extend at least along the first direction D1 in the first frame area B1. The orthographic projection of the second peripheral power line 72 on the substrate may at least partially overlap with the orthographic projection of the first peripheral power line 71 on the substrate.

[0153] In some examples, the data lines DLa and DLb may extend along the second direction D2. The data line DLa may be connected to a column of second pixel circuits, and the data line DLb may be connected to a column of invalid pixel circuits. The data lines DLa and DLb may extend to the first border area B1. The data line DLa may be electrically connected to the data transfer electrode 731a (or 731b) in the first border area B1.

[0154] In some examples, the orthographic projection of the first data transfer line 56 on the substrate may overlap with the orthographic projection of a column of second pixel circuits on the substrate, and the orthographic projection of the invalid data transfer line 57 on the substrate may overlap with the orthographic projection of a column of invalid pixel circuits on the substrate. The first data transfer line 56 and the invalid data transfer line 57 may extend to the first frame area B1, and the first data transfer line 56 may be electrically connected to the data transfer electrode 731b (or 731a) in the first frame area B1.

[0155] In some examples, the data line DLb connected to a column of invalid pixel circuits and the invalid data transfer line 57 overlapping with the orthographic projection of the column of invalid pixel circuits on the substrate can be connected in the first border area B1 and electrically connected to the first power line PL1b connected to the column of invalid pixel circuits through the first power connection electrode 711. The data line DLb connected to a column of invalid pixel circuits and the invalid data transfer line 57 overlapping with the orthographic projection of the column of invalid pixel circuits on the substrate can be an integrated structure.

[0156] In some examples, the data line DLa connected to the pixel circuit in the i-th column may be connected to a data switching electrode 731b in the first border area B1, and the first data switching line 56 located in the pixel circuit in the i-th column may be connected to a data switching electrode 731a in the first border area B1.

[0157] In some examples, the orthographic projection of the third power connection electrode 713 on the substrate may be a rectangle extending along the second direction D2 . The third power connection electrode 713 may be electrically connected to the second power connection electrode 712 .

[0158] In some examples, such as Fig. 10A , Fig.10F and Figure 10G As shown, the first conductive connection layer may include: a plurality of first auxiliary traces 61 located in the second sub-area, a plurality of transfer electrodes (for example, including the third transfer electrode 233), and a plurality of fourth power connection electrodes 714 located in the first frame area B1. The orthographic projection of the fourth power connection electrode 714 on the substrate is a rectangle extending along the first direction D1. The fourth power connection electrode 714 may be electrically connected to the third power connection electrode 713.

[0159] In some examples, such as Fig. 10A , Fig. 10H and Fig.10I As shown, the second conductive connection layer may include: a plurality of second auxiliary wirings 62 located in the second sub-area, a plurality of transfer electrodes (for example, including a fourth transfer electrode 234), and a plurality of power connection lines 715 located in the first frame area B1. The power connection line 715 may extend along a third direction intersecting both the first direction D1 and the second direction D2. The power connection line 715 is connected to the second auxiliary wiring 62 and the fourth power connection electrode 714. The power connection line 715 and the second auxiliary wiring 62 may be an integral structure, and are connected to the fourth power connection electrode 714 through a via provided in the fourth flat layer between the second conductive connection layer and the first conductive connection layer. The second auxiliary wiring 62 may be electrically connected to the first peripheral power line 71 through the power connection line 715, the fourth power connection electrode 714, the third power connection electrode 713, and the second power connection electrode 712, so that the mesh structure formed by the second auxiliary wiring 62 and the first auxiliary wiring 61 receives a constant first power signal. In this example, the plurality of power transfer electrodes connected to the second auxiliary wiring 62 may include: a second power connection electrode, a third power connection electrode, and a fourth power connection electrode. For example, the second power connection electrode 712, the third power connection electrode 713, and the fourth power connection electrode 714 may be located between the first power line PL1b connected to a column of invalid pixel circuits (such as the i-2 column) (or a column of invalid pixel circuits and a column of first pixel circuits aligned along the second direction) and the first power line PL1a adjacent along the first direction D1, and the second auxiliary wiring 62 may be located in the area where a column of second pixel circuits (such as the i-th column) is located. In other examples, the power transfer electrode connected to the second auxiliary wiring 62 may include: a second power connection electrode, the fourth power connection electrode and the third power connection electrode may be omitted, and the power connection line 715 located in the second conductive connection layer may be directly electrically connected to the second power connection electrode located in the second source-drain metal layer through the vias provided in the fourth flat layer, the third flat layer, and the second flat layer. This embodiment is not limited to this.

[0160] In some examples, such as Fig. 10A As shown, the third conductive connection layer may include: a plurality of switching electrodes (eg, including a fifth switching electrode 235 ) located in the second sub-region. The fifth switching electrode 235 may be connected to the fourth switching electrode 234 .

[0161] In this example, the mesh structure formed by connecting the plurality of first auxiliary lines 61 and the plurality of second auxiliary lines 62 is connected to the first peripheral power line 71, and is configured to access the first power signal of the constant voltage. In other examples, the mesh structure formed by connecting the plurality of first auxiliary lines and the plurality of second auxiliary lines can be connected to the second peripheral power line, and is configured to access the second power signal of the constant voltage.

[0162] The arrangement of the plurality of first auxiliary wirings and the plurality of second auxiliary wirings in this example can be beneficial to improving the circuit stability under the conductive connection layer. In addition, the second power connection electrode to the fourth power connection electrode are arranged between the first power line connected to a column of invalid pixel circuits (or a column of invalid pixel circuits and a column of first pixel circuits aligned along the second direction) and the first power line connected to an adjacent column of second pixel circuits, which can make up for the uneven density of the planar layer vias between the first power line connected to a column of invalid pixel circuits (or a column of invalid pixel circuits and a column of first pixel circuits aligned along the second direction) and the first power line connected to an adjacent column of second pixel circuits, thereby reducing the risk of defects.

[0163] Fig.11 FIG. 4 is another partial schematic plan view of the second display area of ​​at least one embodiment of the present disclosure. Fig.11 Can be Figure 1 A partial enlarged schematic diagram of the middle area S3. Fig.11 Take a conductive connection layer (for example, the third conductive connection layer) of the second sub-region as an example for illustration. Fig.11 As shown, the third conductive connection layer may include: a plurality of switching electrodes (e.g., the fifth switching electrode 235) and a plurality of first auxiliary routing lines 61 located in the second sub-area A22, and a third auxiliary routing line 63 located in the third frame area B3. The plurality of first auxiliary routing lines 61 may extend along the first direction D1 and be arranged in sequence along the second direction D2. The third auxiliary routing line 63 may extend around the edge of the second sub-area A22. The plurality of first auxiliary routing lines 61 may extend to the third frame area B3 and be connected to the third auxiliary routing line 63. The third auxiliary routing line 63 may be configured to transmit a constant voltage signal so that the plurality of first auxiliary routing lines 61 are all connected to the constant voltage signal. For example, the constant voltage signal may be a first power supply signal or a second power supply signal. The third auxiliary routing line 63 may be a ring-shaped routing line located in the frame area. For example, the third auxiliary routing line 63 and the plurality of first auxiliary routing lines 61 may be an integral structure. However, this embodiment is not limited thereto. In other examples, the third auxiliary routing line and the plurality of first auxiliary routing lines may be located in different conductive connection layers. For example, a plurality of first auxiliary routing lines may be located in the third conductive connection layer, and a third auxiliary routing line may be located in the first conductive connection layer or the second conductive connection layer.

[0164] In some examples, each conductive connection layer can be provided with a plurality of first auxiliary routing lines 61 located in the second sub-area A22 and a third auxiliary routing line 63 located in the frame area. In other examples, the display substrate includes a plurality of conductive connection layers, and one of the plurality of conductive connection layers can be provided with a plurality of first auxiliary routing lines located in the second sub-area and a third auxiliary routing line located in the frame area.

[0165] In some examples, the line spacing between adjacent first auxiliary traces along the second direction D2 can be determined according to the line spacing between adjacent conductive connection lines along the second direction D2. For example, the line spacing between adjacent first auxiliary traces along the second direction D2 can be the same as the line spacing between adjacent conductive connection lines along the second direction D2.

[0166] In some examples, the line width of the first auxiliary trace 61 (ie, the length of the trace along the direction perpendicular to the extension) can be determined according to the line width of the conductive connection line. For example, the line width of the first auxiliary trace 61 can be the same as the line width of the conductive connection line.

[0167] In this example, by setting multiple first auxiliary routing lines located in the second sub-area and a third auxiliary routing line located in the frame area, and the third auxiliary routing lines and multiple first auxiliary routing lines are connected to a constant voltage signal, the constant voltage signal can be spread over the entire surface of the display substrate, which is beneficial to stabilizing the circuit structure under the conductive connection layer.

[0168] Fig.12 4 is a partial plan view of a first sub-area of ​​a second display area according to at least one embodiment of the present disclosure. Fig.12 Can be Figure 1 A partial enlarged schematic diagram of the middle area S4. Fig.12 Take a conductive connection layer (for example, the third conductive connection layer) of the first sub-region as an example for illustration. Fig.12 As shown, the third conductive connection layer of the first sub-region may include: a plurality of conductive connection lines 51, and a plurality of fourth auxiliary wirings 64a and 64b. The conductive connection line 51 may include: a third main body 511 extending along the first direction D1 and a conductive connection part 512 extending along the second direction D2. The third main body 511 and the conductive connection part 512 are an integral structure. The third main body 511 may extend to the first display area and be connected to the anode of the first light-emitting element in the first display area; the conductive connection part 512 may be connected to the second pixel circuit in the first sub-region. A plurality of fourth auxiliary wirings 64a and 64b may extend along the first direction D1 and be arranged in sequence along the second direction D2. A plurality of fourth auxiliary wirings 64a may be arranged between the conductive connection parts 512 of adjacent conductive connection lines 51; at least one fourth auxiliary wiring 64b may be arranged between the third main bodies 511 of adjacent conductive connection lines 51, or no fourth auxiliary wiring is arranged.

[0169] In some examples, the line spacing between adjacent fourth auxiliary traces along the second direction D2 can be determined according to the line spacing between the third main body portions 511 of the conductive connection lines 51 adjacent to each other along the second direction D2. For example, the line spacing between adjacent fourth auxiliary traces along the second direction D2 can be the same as the line spacing between the third main body portions 511 of the conductive connection lines 51 adjacent to each other along the second direction D2.

[0170] In some examples, the line width of the fourth auxiliary line (ie, the line length along the direction perpendicular to the extension) can be determined according to the line width of the conductive connection line 51. For example, the line width of the fourth auxiliary line and the line width of the conductive connection line 51 can be the same.

[0171] In this example, by setting a plurality of fourth auxiliary wirings in the first sub-area, the surrounding environment of the conductive connecting wire can be kept consistent, which is beneficial to optimizing the complicated compensation rules of the conductive connecting wire and improving the etching uniformity of the conductive connecting wire.

[0172] Fig.13 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.13 As shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 can be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 can at least partially overlap with the first display area A1. For example, the orthographic projection of the sensor 92 on the display substrate 91 can be located within the range of the first display area A1. In some examples, the sensor 92 can be a camera or an infrared sensor.

[0173] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large area of ​​wall, an information query device (such as business query equipment for e-government, banks, hospitals, power and other departments), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0174] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0175] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a first display area and a second display area located at at least one side of the first display area, wherein the second display area comprises: a first sub-area located at at least one side of the first display area, and a second sub-area located at at least one side of the first sub-area; A plurality of light emitting elements, including a plurality of first light emitting elements located in the first display area and a plurality of second light emitting elements located in the second display area; a plurality of pixel circuits, comprising a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area, the plurality of first pixel circuits being located in the first sub-area, at least one first pixel circuit among the plurality of first pixel circuits being connected to at least one first light-emitting element among the plurality of first light-emitting elements through at least one conductive connecting line; at least one second pixel circuit among the plurality of second pixel circuits being connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one conductive connecting line extending from the first sub-area to the first display area; A plurality of first auxiliary routing lines are located in the second sub-area of ​​the second display area, at least one of the plurality of first auxiliary routing lines is arranged in the same layer as the at least one conductive connecting line, and the plurality of first auxiliary routing lines are configured to receive a constant voltage signal.

2. The display substrate according to claim 1, characterized in that: An extension direction of at least one first auxiliary routing line among the plurality of first auxiliary routing lines is the same as an extension direction of the at least one conductive connecting line.

3. The display substrate according to claim 1 or 2, characterized in that: The display substrate further includes: a plurality of second auxiliary routing lines located in the second sub-area, the extension direction of the plurality of second auxiliary routing lines intersects with the extension direction of the plurality of first auxiliary routing lines, and the plurality of second auxiliary routing lines are connected with the plurality of first auxiliary routing lines to form a mesh structure.

4. The display substrate according to claim 3, characterized in that: The first auxiliary routing includes: a first main body extending along a first direction, a plurality of first extension parts and a plurality of second extension parts extending along a second direction, and a plurality of first auxiliary connection electrodes, the second direction intersects with the first direction; the plurality of second extension parts are connected to the plurality of first auxiliary connection electrodes one by one, the plurality of first extension parts and the plurality of second extension parts are connected on the same side of the first main body, and are arranged at intervals along the first direction; the first auxiliary connection electrode is connected to a second auxiliary routing extending along the second direction.

5. The display substrate according to claim 4, characterized in that: The plurality of second auxiliary routing lines and the plurality of first auxiliary routing lines are located in different conductive layers, and at least one insulating layer is provided between the conductive layer where the first auxiliary routing lines are located and the conductive layer where the second auxiliary routing lines are located; The second auxiliary wiring includes: a second main body extending along the second direction and at least one second auxiliary connection electrode extending along the first direction; The second auxiliary connection electrode of the second auxiliary wiring is connected to the first auxiliary connection electrode of the first auxiliary wiring through the auxiliary transfer hole opened in the insulating layer.

6. The display substrate according to claim 5, characterized in that: The first sub-area is located on both sides of the first display area along the first direction, and the second sub-area includes: a first partition and a second partition located on both sides of the first sub-area along the first direction, and a third partition and a fourth partition located on both sides of the first display area along the second direction, and the multiple auxiliary transfer holes in the first partition, the second partition, the third partition and the fourth partition are arranged in a V shape.

7. The display substrate according to claim 6, characterized in that: The maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the first partition and the second partition along the first direction is greater than the maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the third partition and the fourth partition along the first direction; The maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the first partition and the second partition along the second direction is greater than the maximum length of the V-shape formed by the arrangement of the multiple auxiliary transfer holes in the third partition and the fourth partition along the second direction.

8. The display substrate according to claim 3, characterized in that: In a direction perpendicular to the display substrate, the display substrate includes: a circuit structure layer and at least two conductive connection layers arranged in sequence on the substrate, the material of the at least two conductive connection layers includes a transparent conductive material; the at least two conductive connection layers are provided with the at least one conductive connection line, and the first auxiliary routing line and the second auxiliary routing line are located in the at least two conductive connection layers and are located in different layers.

9. The display substrate according to claim 8, characterized in that: The at least two conductive connection layers include: a first conductive connection layer, a second conductive connection layer and a third conductive connection layer arranged in sequence along a direction away from the substrate; the first auxiliary routing is located in the first conductive connection layer, and the second auxiliary routing is located in the second conductive connection layer.

10. The display substrate according to claim 9, characterized in that: A plurality of pixel circuits arranged along a first direction is a row of pixel circuits, and a plurality of pixel circuits arranged along a second direction is a column of pixel circuits, and the first direction intersects with the second direction; The circuit structure layer comprises: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer which are sequentially arranged on the substrate; The first gate metal layer includes: a plurality of scan lines, the scan lines are connected to the row of pixel circuits; the second gate metal layer includes: a plurality of first initial signal lines, the first initial signal lines are connected to the row of pixel circuits; the third source-drain metal layer includes: a plurality of data lines and a plurality of first data transfer lines, the plurality of data lines and the plurality of first data transfer lines are arranged at intervals along the first direction; the data lines are connected to the column of pixel circuits, and the orthographic projection of the first data transfer lines on the substrate overlaps with the orthographic projection of the column of pixel circuits on the substrate; The first auxiliary wiring includes a first main body extending along the first direction, and the first main body is projected on the substrate between the scan line connected to the row of pixel circuits and the first initial signal line on the substrate; The second auxiliary routing includes a second main portion extending along the second direction, and at least a portion of the second main portion is located between the orthographic projection of the substrate and a data line connected to the column of pixel circuits and a first data transfer line that overlaps with the orthographic projection of the column of pixel circuits on the substrate.

11. The display substrate according to claim 3, characterized in that: The substrate further includes: a first frame area located at one side of the second display area, the first frame area is provided with a first peripheral power line and a plurality of power switching electrodes, and the plurality of second auxiliary wirings are connected to the first peripheral power line through the plurality of power switching electrodes.

12. The display substrate according to claim 11, characterized in that: The display substrate further includes: a plurality of first power lines located in the second display area, the plurality of first power lines are arranged along a first direction and extend along a second direction, and the first direction intersects with the second direction; The plurality of pixel circuits further include: a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits arranged along the second direction are a column of invalid pixel circuits, the plurality of second pixel circuits arranged along the second direction are a column of second pixel circuits, and the plurality of first pixel circuits arranged along the second direction are a column of first pixel circuits; The power conversion electrode connected to the second auxiliary wiring is located between a first power line connected to a column of invalid pixel circuits and a first power line connected to an adjacent column of second pixel circuits, or, is located between a column of invalid pixel circuits aligned along the second direction and a first power line connected to a column of first pixel circuits and a first power line connected to an adjacent column of second pixel circuits.

13. The display substrate according to claim 1, characterized in that: The substrate further includes: a frame area located at at least one side of the second display area, and the display substrate further includes: a third auxiliary wiring located in the frame area, the third auxiliary wiring is connected to the plurality of first auxiliary wirings and is configured to transmit a constant voltage signal.

14. The display substrate according to claim 1, characterized in that: The at least one conductive connection line includes: a third main body portion extending along a first direction, and a conductive connection portion extending along a second direction, the first direction intersecting the second direction; the conductive connection portion is connected to the first pixel circuit in the first sub-area, and the third main body portion is connected to the first light-emitting element in the first display area; The display substrate also includes: a plurality of fourth auxiliary routing lines located in the first sub-area and extending along the first direction, the plurality of fourth auxiliary routing lines are arranged in the same layer as the at least one conductive connecting line, and the plurality of fourth auxiliary routing lines satisfy at least one of the following: located between conductive connecting portions of adjacent conductive connecting lines, and located between third main portions of adjacent conductive connecting lines.

15. A display device, characterized in that: It comprises a display substrate as claimed in any one of claims 1 to 14, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor on the substrate of the display substrate at least partially overlaps with the orthographic projection of the first display area of ​​the display substrate on the substrate.

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