Display panel, preparation method thereof and display device

Abstract

The invention relates to a display panel, a preparation method thereof and a display device. The display panel is provided with an opening area and a display area, and comprises a substrate; the isolation structure is located on one side of the substrate and located in the opening area; the isolation structure comprises a first isolation part and a second isolation part which are sequentially arranged in the direction away from the substrate base plate, and is provided with an opening penetrating through the first isolation part and the second isolation part; the surface, close to the substrate, of the second isolation part is provided with a first edge close to the opening, and the surface, away from the substrate, of the first isolation part is provided with a second edge close to the opening; the orthographic projection of the second edge on the substrate surrounds the orthographic projection of the first edge on the substrate; the driving circuit layer is located on one side of the substrate and located in the display area, and the light-emitting device is located on the side, away from the substrate, of the driving circuit layer; the light emitting device includes a first electrode; the first electrode is electrically connected with the driving circuit layer; wherein the second isolation part and the first electrode are arranged on the same layer and are electrically insulated.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) has the advantages of self-luminescence, fast response, wide viewing angle, high brightness, bright colors, and light weight, and is considered to be the next generation of display technology.

[0003] With the development of display technology, narrow borders and full screens have become one of the development directions of display products. In order to reduce the screen border and increase the screen-to-body ratio, some OLED display products use the HIAA (Hole in Active Area) design, that is, a hole is made in the AA area (Active Area, effective display area), and sensors such as cameras are set on the non-display side of the screen, and are set opposite to the hole in the AA area. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display panel and a manufacturing method thereof, and a display device.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present disclosure provides a display panel having an opening area and a display area, wherein the display area surrounds the opening area; the display panel comprises:

[0006] substrate substrate;

[0007] An isolation structure located at one side of the base substrate and located in the opening area; the isolation structure comprises a first isolation portion and a second isolation portion sequentially arranged in a direction away from the base substrate, and an opening penetrating the first isolation portion and the second isolation portion is provided; a surface of the second isolation portion close to the base substrate has a first edge close to the opening, and a surface of the first isolation portion away from the base substrate has a second edge close to the opening; an orthographic projection of the second edge on the base substrate surrounds an orthographic projection of the first edge on the base substrate;

[0008] A driving circuit layer located on one side of the base substrate and a light emitting device located on a side of the driving circuit layer away from the base substrate, wherein the driving circuit layer and the light emitting device are located in the display area; the light emitting device comprises a first electrode; and the first electrode is electrically connected to the driving circuit layer;

[0009] Wherein, the second isolation portion is arranged in the same layer as the first electrode and is electrically insulated.

[0010] In some embodiments, the driving circuit layer includes:

[0011] A first thin film transistor; the first thin film transistor comprises a first active layer, a first gate and a first source-drain electrode; wherein the first gate is located between the first active layer and the layer where the first source-drain electrode is located;

[0012] an interlayer dielectric layer located between the layer where the first source-drain electrode is located and the gate;

[0013] A passivation layer located at a side of the layer where the first source-drain electrode is located away from the substrate;

[0014] The first isolation portion includes a first isolation layer disposed in the same layer as the interlayer dielectric layer and a second isolation layer disposed in the same layer as the passivation layer.

[0015] In some embodiments, the driving circuit layer further includes:

[0016] a first gate insulating layer located between the first active layer and the first gate and a second gate insulating layer located between the first gate and the interlayer dielectric layer;

[0017] A storage capacitor; the storage capacitor comprises a first plate and a second plate; wherein the first plate is disposed in the same layer as the first gate; and the second plate is located between the second gate insulating layer and the interlayer dielectric layer;

[0018] The first isolation portion further includes a third isolation layer located on a side of the first isolation layer close to the base substrate;

[0019] The third isolation layer includes: a first sub-isolation layer disposed in the same layer as the first gate insulation layer, and / or a second sub-isolation layer disposed in the same layer as the second gate insulation layer.

[0020] In some embodiments, the driving circuit layer further includes:

[0021] A second thin film transistor; the second thin film transistor comprises a second active layer, a second gate and a second source-drain electrode; wherein the second gate is arranged in the same layer as the second electrode plate, the second source-drain electrode is arranged in the same layer as the first source-drain electrode, and the second active layer is located between the second gate and the second source-drain electrode;

[0022] a third gate insulating layer located between the second active layer and the second gate;

[0023] The first isolation portion further includes a fourth isolation layer disposed at the same layer as the third gate insulation layer.

[0024] In some embodiments, the driving circuit layer further includes: a buffer layer located between the third gate insulating layer and the second gate;

[0025] The first isolation portion further includes a fifth isolation layer disposed at the same layer as the second buffer layer.

[0026] In some embodiments, the isolation structure further comprises:

[0027] a third isolation portion provided in the same layer as the first active layer; and / or,

[0028] A fourth isolation portion is disposed in the same layer as the second active layer.

[0029] In some embodiments, the first isolation portion further includes a third isolation portion disposed in the same layer as the first active layer;

[0030] The orthographic projection of the first part of the third isolation part on the substrate overlaps with the orthographic projection of the first isolation part on the substrate, and the orthographic projection of the second part of the third isolation part on the substrate is located on the side of the orthographic projection of the first isolation part on the substrate close to the opening.

[0031] In some embodiments, the thickness of the second portion is less than the thickness of the first portion.

[0032] In some embodiments, the first isolation portion has a first side facing the opening;

[0033] The first side surface at least includes a first sub-surface and a second sub-surface arranged in the thickness direction of the display panel, wherein the distance from the first sub-surface to the central axis of the opening is different from the distance from the second sub-surface to the center of the opening area.

[0034] In a second aspect, the present disclosure further proposes a method for preparing a display panel, wherein the display panel has an opening area and a display area; the display area surrounds the opening area; the preparation method comprises:

[0035] providing a substrate base plate;

[0036] An isolation structure, a driving circuit layer and a first electrode of the light-emitting device are formed on one side of the base substrate; the driving circuit layer is located in the display area, and the first electrode is located on the side of the driving circuit layer away from the base substrate and is electrically connected to the driving circuit layer; the isolation structure is located in the isolation area, and includes a first isolation portion and a second isolation portion sequentially arranged in a direction away from the base substrate, and an opening penetrating the first isolation portion and the second isolation portion is provided; the surface of the second isolation portion close to the base substrate has a first edge close to the opening, and the surface of the first isolation portion away from the base substrate has a second edge close to the opening; the orthographic projection of the first edge on the base substrate surrounds the orthographic projection of the second edge on the base substrate;

[0037] The second isolation portion is formed synchronously with the first electrode, and the second isolation portion is electrically insulated from the first electrode.

[0038] In a third aspect, the present disclosure further provides a display device, comprising:

[0039] A display panel as described in any one of the above;

[0040] A photosensitive element is located on the non-display side of the display panel and is arranged opposite to the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0042] Figure 1 is a schematic diagram of a planar structure of a display panel in some embodiments;

[0043] Figure 2 is a schematic cross-sectional view of an isolation structure in some embodiments;

[0044] Figure 3 is a schematic diagram of an etching process in some embodiments;

[0045] Figure 4 is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure;

[0046] Figure 5 is a schematic diagram of a cross-sectional structure of a display panel in some other embodiments of the present disclosure;

[0047] Figure 6 is a schematic diagram of a cross-sectional structure of a display panel in some other embodiments of the present disclosure;

[0048] Figure 7is a schematic diagram of a cross-sectional structure of a display panel in some other embodiments of the present disclosure;

[0049] Figure 8 is a schematic diagram of a planar structure of an isolation structure in an embodiment of the present disclosure;

[0050] Fig. 9 is a schematic cross-sectional structural diagram of an isolation structure in some embodiments of the present disclosure;

[0051] Fig.10 is a schematic cross-sectional structural diagram of an isolation structure in some other embodiments of the present disclosure;

[0052] Fig.11 It is a schematic diagram of the preparation process of the isolation structure in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0053] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0055] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0056] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0057] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0059] In the related art, in order to increase the screen-to-body ratio of the display screen, an opening can be set in the OLED display panel, and some photosensitive elements such as a camera can be set on the back side of the opening. However, setting the opening in the display area easily allows water vapor and oxygen to corrode the OLED display panel through the opening, thereby causing problems such as poor display.

[0060] Figure 1 Schematic diagram of the planar structure of the display panel in some embodiments. Figure 1It can be seen that the display panel has an opening area HA, a display area AA surrounding the opening area HA, and a non-display area NA surrounding the display area AA. Among them, the display panel includes a driving circuit layer located in the display area AA, a light-emitting device located on one side of the driving circuit layer, and an isolation structure located in the opening area HA. ​​The driving circuit layer includes a pixel circuit. The pixel circuit includes a thin film transistor, the thin film transistor includes a gate, a source, a drain and an active layer, and the light-emitting device includes a first electrode and a second electrode arranged in sequence in a direction away from the thin film transistor. The first electrode is electrically connected to the pixel circuit. The pixel circuit provides a driving signal for the thin film transistor. An opening is opened in the opening area HA, and the opening passes through the isolation structure, or it can also be understood that the isolation structure is arranged around the opening to isolate the opening and the display area AA.

[0061] Figure 2 Schematic diagram of the cross-sectional structure of the isolation structure in some embodiments. Figure 2 Also along Figure 1 The cross-sectional structure diagram of the cutting line AB in the display panel shown in the figure, wherein the cutting line AB passes through the center O of the opening area HA, and the center O refers to the center within the process fluctuation range. In some embodiments, the opening area HA can also be a symmetrical shape such as a circle or a quadrilateral, or an asymmetrical shape. Figure 2 The embodiment shown shows a case where the opening area HA is circular. In some embodiments, when the opening area HA is an asymmetric shape, the cutting line AB may not pass through the center O of the opening area HA. Figure 2 It is also a schematic diagram of the cross-sectional structure of the opening area HA.

[0062] Depend on Figure 2 It can be seen that the isolation structure 50 includes a first support portion 51, a second support portion 52, a third support portion 53 and a partition portion 54. The second support portion 52 is provided with a groove, the first support portion 51 and the third support portion 53 are located in the groove, and the third support portion 53 is located on the side of the first support portion 51 close to the partition portion 54. The partition portion 54 covers the second support portion 52 and the third support portion 53. Moreover, a part of the partition portion 54 is directly opposite to the second support portion 52 and the third support portion 53, and the other part is located on the side of the part close to the groove, so as to play a role in isolating the film layer located on the side of the partition portion 54 away from the first support portion 51.

[0063] In the related art, the partition portion 54 is arranged in the same layer as the source and drain of the thin film transistor. Wherein, "arranged in the same layer" means that multiple structures are formed by the same material layer through the same composition process, that is, in this embodiment, the partition portion 54 and the source and drain of the thin film transistor are formed by the same material layer through the same composition process. For example, the material of the source and drain includes a Ti layer, an Al layer and a Ti layer stacked in sequence, and the material of the partition portion 54 includes a Ti layer, an Al layer and a Ti layer stacked in sequence. A light-emitting device is arranged in the display area. When forming the first electrode of the light-emitting device, a first electrode material layer is first formed, and then the first electrode material layer is etched using a composition process. Wherein, the first electrode material layer covers the display area AA and the opening area HA, that is, a portion of the first electrode material layer is located on the side of the partition portion 54 away from the first support portion 51.

[0064] Figure 3 Schematic diagram of the etching process in some embodiments. Figure 3 As shown in (a) of FIG. 5 , the first electrode material layer 7 is located on the side of the partition portion 54 away from the first support portion 51. In this case, during the etching process of the first electrode material layer, since the material of the first electrode material layer includes ITO (indium tin oxide), Ag and ITO stacked in sequence, as shown in FIG. Figure 3 As shown in (b), after the first electrode material layer 7 is etched, the etching solution will contain silver ions (Ag + ), and the material of the partition portion 54 includes a Ti layer, an Al layer and a Ti layer stacked in sequence, wherein Al is formed into aluminum ions (Al 3+ ),like Figure 3 As shown in (c), Ag in the etching solution + and the electrons (e - ) react to generate solid Ag particles, which are attached to the surface of the partition portion 54. The presence of Ag particles may cause the display panel to have a GDS (Growing Dark Spot) defect, and the black spots gradually grow larger and may even cause the entire display panel to fail.

[0065] In other embodiments, the partition structure 40 is made of PI (polyimide) material as a whole. However, since PI material is an organic material, it has low density and may cause the display panel to be corroded by water vapor and oxygen.

[0066] In order to at least alleviate or solve one of the above-mentioned technical problems, the present disclosure provides a display panel and a method for manufacturing the same, and a display device.

[0067] Figure 4 is a schematic diagram of the cross-sectional structure of a display panel in some embodiments of the present disclosure. Figure 5It is a schematic diagram of the cross-sectional structure of the display panel in some other embodiments of the present disclosure. Figure 6 It is a schematic diagram of the cross-sectional structure of the display panel in some other embodiments of the present disclosure. Figure 7 It is a schematic diagram of the cross-sectional structure of the display panel in some other embodiments of the present disclosure.

[0068] The schematic diagram of the planar structure of the display panel in the embodiment of the present disclosure is Figure 1 The display panel planar structure diagram is the same as shown. Figure 1 As shown, a display panel in an embodiment of the present disclosure has an opening area HA and a display area AA, wherein the display area AA surrounds the opening area HA. Figures 4 to 7 In different embodiments of the present disclosure, Figure 1 Schematic diagram of the cross-sectional structure cut along the center cutting line CB.

[0069] In some embodiments, Figures 4 to 7 As shown, the display panel of the present disclosure includes: a base substrate 10 and an isolation structure 40, a driving circuit layer 20 and a light emitting device 30 located on one side of the base substrate 10. The isolation structure 40 is located in the opening area HA, the light emitting device 30 is located on the side of the driving circuit layer 20 away from the base substrate 10, and the driving circuit layer 20 and the light emitting device 30 are located in the display area AA.

[0070] like Figures 4 to 7 As shown, the isolation structure 40 includes a first isolation portion 41 and a second isolation portion 42 which are sequentially arranged in a direction away from the base substrate 10, and an opening penetrating the first isolation portion 41 and the second isolation portion 42 is provided; the surface of the second isolation portion 42 close to the base substrate 10 has a first edge 402 close to the opening. Specifically, the second isolation portion 42 has an upper surface away from the base substrate 10 and a lower surface close to the base substrate 10, wherein the lower surface has a first edge 402 close to the opening, and the upper surface has a first edge 403 close to the opening. The surface of the first isolation portion 41 away from the base substrate 10 has a second edge 401 close to the opening, which can also be understood as the first isolation portion 41 and the second isolation portion 42 having an interface, and the edge of the interface close to the opening is the second edge 401.

[0071] Figure 8 Schematic diagram of the plane structure of the isolation structure in the embodiment of the present disclosure. Figure 8 It can be seen that the orthographic projection of the second edge 401 on the base substrate 10 surrounds the orthographic projection of the first edge 402 on the base substrate 10. This design can ensure that the surface of the second isolation portion 42 close to the base substrate 10 at least exceeds the surface of the first isolation portion 41 away from the base substrate 10 in the direction close to the opening, thereby ensuring the isolation effect of the isolation structure 40.

[0072] Alternatively, if Figures 4 to 7As shown, the surface of the second isolation portion 42 away from the base substrate 10 has a fourth edge 403 close to the opening, and the orthographic projection of the fourth edge 403 on the base substrate 10 surrounds the orthographic projection of the first edge 402 on the base substrate 10, thereby further ensuring the isolation function of the isolation structure 40.

[0073] Optionally, the opening in the embodiment of the present disclosure may be of any shape, for example, circular, polygonal, etc. Figure 8 The illustrated embodiment merely exemplarily shows the case where the opening is circular in shape, and does not limit the opening.

[0074] The light emitting device 30 comprises a first electrode 301 and a second electrode 302 arranged in sequence in a direction away from the base substrate 10; the first electrode 301 is electrically connected to the driving circuit layer 20. The second isolation portion 42 is arranged in the same layer as the first electrode 301 and is electrically insulated.

[0075] The partition structure of the disclosed embodiment includes a second isolation portion 42 arranged in the same layer as the first electrode 301. Compared with the partition structure including a partition portion 54 arranged in the same layer as the source and drain of the thin film transistor, it can avoid the precipitation of Ag particles during the etching process of the material layer of the first electrode 301, thereby avoiding the occurrence of GDS adverse phenomenon.

[0076] Optionally, the base substrate 10 is a glass substrate. For example, the glass substrate can be at least one of alkali-free glass, alkali glass, aluminum oxide glass, high borosilicate glass and quartz glass. In other embodiments, the base substrate 10 can be a flexible substrate.

[0077] Optionally, a first dielectric layer 11 and a first buffer layer 12 are further provided between the base substrate 10 and the driving circuit layer 20, and are stacked in sequence in a direction away from the base substrate 10. The material of the first dielectric layer 11 includes at least one of PI and rubber material, and the material of the first buffer layer 12 includes a silicon compound, for example, at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0078] Optionally, the light emitting device 22 may be an organic light emitting diode (OLED), wherein the organic light emitting diode (OLED) may emit, for example, red light, green light, blue light or white light.

[0079] Optionally, the second electrode 303 may be made of metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0080] Optionally, the first electrode 301 may be a single-layer structure or a multi-layer structure stacked along the thickness direction of the display panel, and each layer of the structure may be made of materials such as metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, in one example, the first electrode 301 includes ITO, Ag, and ITO stacked on one side.

[0081] Optionally, the light emitting layer 222 may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light emitting material or a phosphorescent light emitting material, and may emit red light, green light, blue light, or may emit white light.

[0082] In some embodiments, the driving circuit layer 20 includes: a first thin film transistor 21, an interlayer dielectric layer 204 located between the layer where the first source and drain electrodes are located and the gate, and a passivation layer 205 located on the side of the layer where the first source and drain electrodes are located away from the substrate 10. The first thin film transistor 21 includes a first active layer 213, a first gate 214 and a first source and drain electrode, wherein the first gate 214 is located between the first active layer 213 and the layer where the first source and drain electrodes are located. The first source and drain electrodes include a first source 211 and a first drain 212.

[0083] Optionally, the driving circuit layer 20 further includes a planarization layer 206 located between the light emitting device 30 and the passivation layer 205. The first electrode 301 is electrically connected to the first thin film transistor through a via hole penetrating the planarization layer 206 and the passivation layer 205. Figures 4 to 7 In the illustrated embodiment, the first electrode 301 is electrically connected to the first drain electrode 212 through a via hole penetrating the planarization layer 206 and the passivation layer 205 .

[0084] The first isolation portion 41 includes a first isolation layer 414 disposed at the same layer as the interlayer dielectric layer 204 and a second isolation layer 415 disposed at the same layer as the passivation layer 205 .

[0085] Since the materials of the interlayer dielectric layer 204 and the passivation layer 205 both include inorganic insulating materials, the disclosed embodiment enables the first isolation portion 41 to include a first isolation layer 414 disposed on the same layer as the interlayer dielectric layer 204 and a second isolation layer 415 disposed on the same layer as the passivation layer 205, so that the material of the first isolation portion 41 includes an inorganic insulating material, or the film layer material in the first isolation portion 41 that is in direct contact with the second isolation portion 42 is an inorganic insulating layer material. On this basis, during the process of etching the material layer of the first electrode 301 to form the first electrode 301 located in the display area AA and the first electrode 301 located in the opening area HA, the material layer of the first isolation portion 41 will not be affected by the etching solution, etc., and the preparation process can be simplified, reducing the difficulty of preparation. In addition, the first isolation portion 41 is made of inorganic materials, which, compared with organic materials, can reduce the erosion from water and oxygen when the isolation is achieved. At the same time, since the first isolation portion 41 is made of insulating material, when the first electrode material layer is etched to form the second isolation portion 42, the first isolation portion 41 can be prevented from being etched by metal ions such as Ag in the etching solution. + impact.

[0086] Optionally, the first active layer 213 includes a first channel portion and a first source connection portion and a first drain connection portion located on both sides of the first channel portion, the first source connection portion is connected to the drain 212 of the first thin film transistor 21, and the first drain connection portion is connected to the source 211 of the first thin film transistor 21. The first source connection portion and the first drain connection portion can be doped with impurities (for example, N-type impurities or P-type impurities) with a higher impurity concentration than the first channel portion. The first channel portion is directly opposite to the first gate 213 of the first thin film transistor 21. When the voltage signal loaded on the first gate 213 reaches a certain value, a carrier path is formed in the first channel portion to conduct the drain 212 and the source 211 of the first thin film transistor 21.

[0087] Optionally, the first active layer 213 may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. For example, in one example, the material of the first active layer 213 includes p-Si.

[0088] In some embodiments, the driving circuit layer 20 further includes: a storage capacitor 22, a first gate insulating layer 201 located between the first active layer 213 and the first gate 214, and a second gate insulating layer 202 located between the first gate 214 and the interlayer dielectric layer 204. The storage capacitor 22 includes a first electrode 222 and a second electrode 221. The first electrode 222 is disposed in the same layer as the first gate 214, and the second electrode 221 is located between the second gate insulating layer 202 and the interlayer dielectric layer 204.

[0089] The first isolation portion 41 further includes a third isolation layer located on the side of the first isolation layer 414 close to the base substrate 10. The third isolation layer includes: a first sub-isolation layer 411 disposed on the same layer as the first gate insulation layer 201, and / or a second sub-isolation layer 412 disposed on the same layer as the second gate insulation layer 202.

[0090] For example, in Figure 4 In the embodiment shown, the third isolation layer includes: a first sub-isolation layer 411 disposed in the same layer as the first gate insulation layer 201. Figure 5 and Figure 7 In the embodiment shown, the third isolation layer includes: a second sub-isolation layer 412 disposed in the same layer as the second gate insulation layer 202. Figure 6 In the illustrated embodiment, the third isolation layer includes: a first sub-isolation layer 411 disposed at the same layer as the first gate insulation layer 201 and / or a second sub-isolation layer 412 disposed at the same layer as the second gate insulation layer 202 .

[0091] Specifically, in one example, the thickness of the third isolation portion 43 is 50 nm, the thickness of the first sub-isolation layer 411 or the second sub-isolation layer 412 is 250 nm, the thickness of the first isolation layer is 500 nm, and the thickness of the second isolation layer is 300 nm.

[0092] The materials of the first gate insulating layer 201 and the second gate insulating layer 202 both include inorganic materials. Therefore, in the first isolation portion 41 of the embodiment of the present disclosure, the material of the first sub-isolation layer 411 disposed on the same layer as the first gate insulating layer 201 includes an inorganic material, and the material of the second sub-isolation layer 412 disposed on the same layer as the second gate insulating layer 202 includes an inorganic material. Moreover, in the embodiment of the present disclosure, the third isolation layer includes: the first sub-isolation layer 411 disposed on the same layer as the first gate insulating layer 201, and / or, the second sub-isolation layer 412 disposed on the same layer as the second gate insulating layer 202. Among them, the number of film layers included in the third isolation layer can be selected according to actual needs to meet the needs of different display panels, while also simplifying the preparation process and reducing the difficulty of preparation.

[0093] In some embodiments, the driving circuit layer 20 further includes: a second thin film transistor 23, and a third gate insulating layer 203 located between the second active layer 233 and the second gate 234. The second thin film transistor 23 includes a second active layer 233, a second gate 234, and a second source-drain electrode. The second source-drain electrode includes a second source 231 and a second drain 232. The second gate 234 is arranged in the same layer as the second electrode plate 221, the second source-drain electrode is arranged in the same layer as the first source-drain electrode, and the second active layer 233 is located between the second gate 234 and the second source-drain electrode. The first isolation portion 41 also includes a fourth isolation layer 413 arranged in the same layer as the third gate insulating layer 203.

[0094] Similarly, the material of the third gate insulating layer 203 includes an inorganic insulating material. Therefore, the material of the fourth insulating layer 43 disposed in the same layer as the third gate insulating layer 203 in the first insulating portion 41 of the present disclosure is an inorganic insulating material. In practical applications, the film layers disposed in the same layer as multiple film layers in the third gate insulating layer 203, the first gate insulating layer 201, the second gate insulating layer 202, the passivation layer 205, and the interlayer dielectric layer 204 can be selected to form different combinations to prepare the first insulating portion 41, and the thickness of the first insulating portion 41 can be appropriately adjusted to meet the requirements of different display panels for the thickness of the partition structure 40, while also simplifying the preparation process and reducing the difficulty of preparation.

[0095] Optionally, the second active layer 233 includes a second channel portion and a second source connection portion and a second drain connection portion located on both sides of the second channel portion, the second drain connection portion is connected to the drain 232 of the second thin film transistor 23, and the second source connection portion is connected to the source 211 of the second thin film transistor 21. The second source connection portion and the second drain connection portion can be doped with impurities (for example, N-type impurities or P-type impurities) with a higher impurity concentration than the second channel portion. The second channel portion is directly opposite to the second gate 234 of the second thin film transistor 23. When the voltage signal loaded on the second gate 234 reaches a certain value, a carrier path is formed in the second channel portion to conduct the second drain 232 and the second source 231 of the second thin film transistor 23.

[0096] Optionally, the second active layer 233 may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. For example, in one example, the material of the second active layer 233 includes IZTO.

[0097] In some embodiments, the driving circuit layer 20 further includes: a second buffer layer 208 located between the third gate insulating layer 203 and the second gate 234 , and the first isolation portion 41 further includes a fifth isolation layer 418 disposed on the same layer as the second buffer layer 208 .

[0098] Similarly, the material of the second buffer layer 208 includes an inorganic material. Therefore, the material of the fifth isolation layer 418 disposed in the same layer as the second buffer layer 208 in the first isolation portion 41 of the embodiment of the present disclosure is an inorganic material. In addition, the embodiment of the present disclosure can prepare the first isolation portion 41 by selecting a plurality of film layers disposed in the same layer in the second buffer layer 208, the third gate insulation layer 203, the first gate insulation layer 201, the second gate insulation layer 202, the passivation layer 205 and the interlayer dielectric layer 204 to form different combinations, and can also appropriately adjust the thickness of the first isolation portion 41 to meet the thickness requirements of different display panels for the partition structure 40, while simplifying the preparation process and reducing the difficulty of preparation.

[0099] Optionally, the first gate insulating layer 201, the second gate insulating layer 202, the third gate insulating layer 203 and the interlayer dielectric layer 204 can all be a single-layer structure, or a multi-layer structure stacked along the thickness direction of the display panel, and each layer can be prepared using any one or more combinations of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON).

[0100] Optionally, the material of the passivation layer 205 and the second buffer layer 208 may include a silicon compound, for example, at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0101] Optionally, the planarization layer 206 is made of an organic insulating material, for example, the organic insulating material may include one or more resin materials such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc. The organic insulating material may also be elastic, for example, the organic insulating material may include one or more elastic materials such as urethane, thermoplastic polyurethane (TPU), etc.

[0102] In some embodiments, Figures 4 to 7 As shown, the driving circuit layer 20 further includes a pixel defining layer 207 located on the side of the planarization layer 206 away from the base substrate 10 and located in the display area AA. The pixel defining layer 207 defines a pixel opening. At least part of the light emitting device 30 is located in the pixel opening. For example, in Figures 4 to 7 In the illustrated embodiment, part of the first electrode 301 is located in the pixel opening, the light emitting layer 302 is located in the pixel opening, part of the second electrode 302 is located in the pixel opening, and another part of the first electrode 301 is located on a side of the pixel defining layer 207 away from the base substrate 10 .

[0103] Optionally, the material of the pixel defining layer 207 may include one or more organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin.

[0104] In some embodiments, the isolation structure 40 further includes a third isolation portion 43 disposed in the same layer as the first active layer 213 ; and / or the isolation structure 40 further includes a fourth isolation portion 44 disposed in the same layer as the second active layer 233 .

[0105] Specifically, in Figure 4 , Figure 5 and Figure 6 In the embodiment shown, the isolation structure 40 further includes a third isolation portion 43 disposed in the same layer as the first active layer 213. Figure 7 In the illustrated embodiment, the isolation structure 40 further includes a third isolation portion 43 disposed in the same layer as the first active layer 213 and a fourth isolation portion 44 disposed in the same layer as the second active layer 233. In other embodiments, the isolation structure 40 further includes a fourth isolation portion 44 disposed in the same layer as the second active layer 233.

[0106] In the embodiment of the present disclosure, the third isolation portion 43 disposed in the same layer as the first active layer 213 can be used as a sacrificial layer. Since the third isolation portion 43 is located on the side of the first isolation portion 41 close to the substrate 10, the etching rate of the entire first isolation portion 41 can be judged according to the morphology of the third isolation portion 43 during the process of etching the first isolation portion 41. For example, the etching rate of the entire first isolation portion 41 can be judged according to the minimum thickness of the third isolation portion 43. Optionally, the third isolation portion 43 includes a first part and a second part, wherein the first part overlaps with the orthographic projection of the first isolation portion 41 on the substrate 10, and the second part does not overlap with the orthographic projection of the first isolation portion 41 on the substrate 10. In this case, the etching rate of the entire first isolation portion 41 can be judged according to the thickness change of the second part, or the etching rate of the entire first isolation portion 41 can be judged according to whether the second part still exists during the etching process.

[0107] Similarly, the fourth isolation portion 44 is located between two film layers in the first isolation portion 41, for example, Figure 7 In the illustrated embodiment, the fourth isolation portion 44 is located between the first isolation layer 414 and the fifth isolation layer 418. In other embodiments, the fourth isolation portion 44 is located between the first isolation layer 414 and the fourth isolation layer 413. The fourth isolation portion 44 can also be used as an intermediate sacrificial layer to determine the etching rate of the film layer located on the side of the fourth isolation portion 44 away from the substrate 10 in the first isolation layer 414. The embodiment of the present disclosure detects the etching rate of the third isolation portion 43 and / or the fourth isolation portion 44 during the etching of the first isolation portion 41 to ensure the normal progress of etching.

[0108] Fig. 9 It is a schematic diagram of the cross-sectional structure of the isolation structure in some embodiments of the present disclosure. Fig.10It is a schematic diagram of the cross-sectional structure of the isolation structure in other embodiments of the present disclosure.

[0109] In some embodiments, Fig. 9 and Fig.10 As shown, the first isolation portion 41 further includes a third isolation portion 43 disposed in the same layer as the first active layer 213. The orthographic projection of the first portion 431 of the third isolation portion 43 on the base substrate 10 overlaps with the orthographic projection of the first isolation portion 41 on the base substrate 10, and the orthographic projection of the second portion 432 of the third isolation portion 43 on the base substrate 10 is located on the side of the orthographic projection of the first isolation portion 41 on the base substrate 10 close to the opening.

[0110] In some embodiments, Fig. 9 and Fig.10 As shown, the thickness d2 of the second portion 432 is smaller than the thickness d1 of the first portion 431 .

[0111] In the embodiment of the present disclosure, the etching rate of the entire first isolation portion 41 can be determined by observing the thickness change of the second portion 432 or the presence or absence of the second portion 432 .

[0112] In some embodiments, Fig. 9 and Fig.10 As shown, the first isolation portion 41 has a first side surface 410 facing the opening.

[0113] The first side surface 410 at least includes a first sub-surface 420 and a first sub-surface 430 arranged in the thickness direction of the display panel, wherein the distance from the first sub-surface 420 to the central axis OO of the opening is different from the distance from the first sub-surface 430 to the central axis OO of the opening area HA, that is, the first side surface 410 presents a concave-convex structure in the thickness direction of the display panel. Alternatively, it can also be understood that the first isolation portion 41 in the embodiment of the present disclosure includes a plurality of inorganic film layers, on this basis, the distance between the edge of at least two of the inorganic film layers close to the opening and the center of the opening can be different. In this way, the first side surface with a concave-convex structure can increase the partition effect of the partition structure 40. Among them, the concave-convex structure of the first side surface 410 can be achieved by utilizing the different etching rates of different inorganic film layers. In other words, the material of the inorganic film layer included in the first isolation portion 41 can be selected, and the concave-convex structure of the first side surface 410 can be controlled by the etching rates corresponding to different materials.

[0114] For example, in Fig. 9In the illustrated embodiment, the first side surface 410 includes a first sub-surface 420, a second sub-surface 430, and a third sub-surface 440 arranged in sequence along a direction close to the third isolation portion 43, wherein the first sub-surface 420 and the second sub-surface 4302 have different distances from the central axis OO of the opening. Furthermore, the third sub-surface 440 and the first sub-surface 420 also have different distances from the central axis OO of the opening.

[0115] exist Fig.10 In the illustrated embodiment, the first side surface 410 includes a first sub-surface 420, a second sub-surface 430, a third sub-surface 440, a fourth sub-surface 450, and a fifth sub-surface 460 arranged in sequence along a direction close to the third isolation portion 43, wherein the first sub-surface 420, the second sub-surface 430, the third sub-surface 440, and the fifth sub-surface 460 have different distances from the central axis OO of the opening. The fourth sub-surface 450 and the third sub-surface 440 have the same distances from the central axis OO of the opening.

[0116] The first side surface 410 of the disclosed embodiment is designed to have a concave-convex structure, which can improve the partition effect when the thickness of the inorganic film layer is limited, and extend the water vapor intrusion path to improve the water vapor protection effect.

[0117] Specifically, in some embodiments, Fig. 9 As shown, the isolation structure 40 surrounds the opening and includes a first isolation part 41, a second isolation part 42 and a third isolation part 43 stacked in sequence. The first isolation part 41 includes a first sub-isolation layer 411, a first isolation layer 414 and a second isolation layer 415 stacked in sequence in a direction away from the third isolation part 43, or the first isolation part 41 includes a second sub-isolation layer 412, a first isolation layer 414 and a second isolation layer 415 stacked in sequence in a direction away from the third isolation part 43. The second isolation part 42 exceeds any film layer in the first isolation part 41 on the side close to the opening. The material of the third isolation part includes p-Si, and the first sub-isolation layer 411 or the second sub-isolation layer 412 includes SiO and SiN stacked in sequence in a direction close to the third isolation part 43. The first isolation layer 414 includes SiN and SiO stacked in sequence in a direction close to the third isolation part 43. The second isolation layer 415 includes SiN. Furthermore, the thickness of the second isolation layer 415 is 300 nm, the thickness of SiN in the first isolation layer 414 is 300 nm, the thickness of SiO is 200 nm, the thickness of SiO in the first sub-isolation layer 411 or the second sub-isolation layer 412 is 120 nm, and the thickness of SiN is 140 nm. Furthermore, a concave-convex structure is formed on the first side surface of the first isolation portion 41 facing the opening to enhance the isolation effect.

[0118] Specifically, in other embodiments, Fig.10As shown, the isolation structure 40 includes a first isolation part 41, a second isolation part 42 and a third isolation part 43. The first isolation part 41 includes a first sub-isolation layer 411, a fifth isolation layer 418, a fourth isolation layer 413, a first isolation layer 414 and a second isolation layer 415 which are sequentially stacked in a direction away from the third isolation part 43, or the first isolation part 41 includes a second sub-isolation layer 412, a fifth isolation layer 418, a fourth isolation layer 413, a first isolation layer 414 and a second isolation layer 415 which are sequentially stacked in a direction away from the third isolation part 43. The material of the fifth isolation layer 418 includes SiO with a thickness of 300nm, and the material of the fourth isolation layer includes SiO with a thickness of 140nm. The materials and thicknesses of the remaining film layers in the first isolation part 41 are as follows: Fig.10 The materials and thicknesses of the corresponding film layers in the illustrated embodiment are the same.

[0119] Optionally, the display panel in the embodiment of the present disclosure further includes a semiconductor portion 223 disposed in the same layer as the first active layer 213. The semiconductor portion 223 overlaps with the orthographic projection of the first electrode plate 222 on the base substrate 10.

[0120] The present disclosure provides a method for preparing a display panel, wherein the display panel has an opening area HA and a display area AA; the display area AA surrounds the opening area HA. ​​The preparation method comprises steps S10 to S30:

[0121] Step S10: providing a base substrate 10.

[0122] Step S20, forming an isolation structure 40, a driving circuit layer 20 and a first electrode 301 of the light-emitting device 30 on one side of the base substrate 10. The driving circuit layer 20 is located in the display area AA, and the first electrode 301 is located on the side of the driving circuit layer 20 away from the base substrate 10, and is electrically connected to the driving circuit layer 20; the isolation structure 40 is located in the isolation area, and includes a first isolation portion 41 and a second isolation portion 42 sequentially arranged in a direction away from the base substrate 10, and is provided with an opening penetrating the first isolation portion 41 and the second isolation portion 42; the surface of the second isolation portion 42 close to the base substrate 10 has a first edge 402 close to the opening, and the surface of the first isolation portion 41 away from the base substrate 10 has a second edge 401 close to the opening; the orthographic projection of the first edge 402 on the base substrate 10 surrounds the orthographic projection of the second edge 401 on the base substrate 10. The first isolation portion 41 is made of inorganic material.

[0123] Step S30, forming a second electrode 302 on a side of the first electrode 301 away from the base substrate 10;

[0124] The second isolation portion 42 in step S20 is formed simultaneously with the first electrode 301 , and the second isolation portion 42 is electrically insulated from the first electrode 301 .

[0125] Fig.11 It is a schematic diagram of the preparation process of the isolation structure in some embodiments of the present disclosure.

[0126] In some embodiments, Fig. 9 As shown, in step S20, the step of forming the isolation structure 40 on one side of the base substrate 10 includes: step S21 to step S25:

[0127] Step S21: Fig.11 As shown in (a), a third isolation portion 43 having a via hole is formed on one side of the base substrate 10. A first isolation material layer 1 and a second isolation material layer 2 are sequentially formed on one side of the third isolation portion 43. The first isolation material layer 1 covers the via hole and the third isolation portion 43, and the second isolation material layer 2 covers the first isolation material layer.

[0128] Step S22: Fig.11 As shown in (b), a photoresist (PR) is coated on the side of the second isolation material layer 2 away from the base substrate 10, and the second isolation material layer 2 is patterned to form a second isolation portion 42 with a second sub-hole located in the opening area HA and a first electrode 301 located in the display area AA.

[0129] Step S23: Fig.11 As shown in (c), the first isolation material layer is etched for the first time to form a first intermediate isolation material layer 5 and a third intermediate isolation material layer 6. The side of the first intermediate isolation material layer 5 close to the opening can be understood as being perpendicular to the surface of the substrate 10.

[0130] Specifically, the first etching is physical etching. Physical etching is that the positive ions in the plasma are accelerated under the action of the electric field and vertically bombard the film surface. It is anisotropic etching (the etching rate is higher in the direction of the electric field), that is, Fig.11 The vertical etching in the direction indicated by the arrow (c) can be used for etching with finer line widths and the etching process can be precisely controlled. Fig.11 As can be seen from (c) in FIG. 1 , physical etching can be used to make the side surface of the first intermediate isolation material layer 5 close to the opening be understood to be perpendicular to the surface of the base substrate 10 .

[0131] Specifically, during the first etching process, the third isolation portion 43 is used as a sacrificial layer. Therefore, during the first etching process, the portion of the third isolation portion 43 directly opposite to the opening may be completely sacrificed, may be completely retained, or may be partially retained, that is, the first isolation material layer 1 is vertically etched to the third isolation portion 43, or at least a portion of the third isolation portion 43 is also vertically etched. Fig.11(c) in the figure exemplarily shows that a part of the third isolation portion 43 directly opposite to the opening is retained, that is, the corresponding third intermediate isolation material layer 6 is obtained. Therefore, the morphology of the third isolation portion 43 before the first etching starts and after the first etching is completed may be the same or different.

[0132] Optionally, during the first etching process, the etching thickness is above 1000 nm, the etching gas is CF4 or O2, the etching pressure is 10 mT, and the power and bias power of the plasma source can be within the range of 10 to 20 kW.

[0133] Step S24: Fig.11 As shown in (d), the first intermediate isolation material layer 5 and the third intermediate isolation material layer 6 are etched for the second time to form a first isolation portion 41 having a first sub-hole located in the opening area HA. ​​The isolation structure 40 includes a first isolation portion 41, a second isolation portion 42 and a third isolation portion 43, and the first sub-hole, the second sub-hole and the via hole are connected to form an opening.

[0134] Specifically, the second etching is chemical etching. Chemical etching uses the chemical activity of free radicals to react chemically with the covering material on the substrate. It is isotropic etching (the etching rate in each direction is the same). Fig.11 Etching in the direction indicated by the arrow (d) in the figure has a high selectivity ratio for the underlying material of the material to be etched, that is, it causes little damage to the substrate and the equipment used is simple. Fig.11 In (c), the side of the first intermediate isolation material layer 5 close to the opening can be understood as being perpendicular to the surface of the base substrate 10, and the film layer of the first intermediate isolation material layer 5 can be etched in a direction away from the center of the opening, so that the surface of the second isolation portion 42 close to the base substrate 10 on the side close to the center of the opening exceeds the surface of the first isolation portion 41 away from the base substrate 10, thereby achieving an isolation effect. At the same time, since the first intermediate isolation material layer 5 includes multiple film layers arranged in a direction perpendicular to the base substrate 10, that is, at this time, the surfaces of each film layer close to the center of the opening are flush. In this way, when chemical etching is performed, the concave-convex structure of the first side can be achieved by different etching rates of different film layers, thereby improving the isolation effect of the partition structure 40.

[0135] Optionally, during the second etching process, the etching thickness is above 1000 nm, the etching gas is CF4 or O2, the etching pressure is 100-150 mT, the power of the plasma source can be in the range of 10-20 kW, and the bias power is about 0.5 kW.

[0136] Step S25: Fig.11 As shown in (e) in FIG. 1 , the photoresist is removed to obtain a partition structure 40 .

[0137] In some embodiments, the step of forming the driving circuit layer 20 includes steps S201 to S205:

[0138] Step S201 : forming a first active layer 213 of a first thin film transistor 21 .

[0139] Step S202 , forming a first gate 214 of the first thin film transistor 21 on a side of the first active layer 213 away from the base substrate 10 .

[0140] Step S203 , forming an interlayer dielectric layer 204 on a side of the first gate 214 away from the base substrate 10 .

[0141] Step S204 , forming a first source-drain electrode on a side of the interlayer dielectric layer 204 away from the base substrate 10 .

[0142] Step S205 , forming a passivation layer 205 on a side of the first source-drain electrode away from the base substrate 10 .

[0143] In this case, the step of forming an isolation structure 40 on one side of the base substrate 10 includes: forming a first isolation layer 414 and a second isolation layer 415 on one side of the base substrate 10; wherein the first isolation layer 414 is formed synchronously with the interlayer dielectric layer 204 in step S203, and the second isolation layer 415 is formed synchronously with the passivation layer 205 in step S205.

[0144] In some embodiments, in step S202 , while forming the first gate 214 of the first thin film transistor 21 on the side of the first active layer 213 away from the base substrate 10 , the first electrode 222 of the storage capacitor 22 is also formed.

[0145] The steps of forming the driving circuit layer 20, in addition to steps S201 to S205, further include steps S206 and S207:

[0146] Step S206 , forming a first gate insulating layer 201 on a side of the first active layer 213 away from the base substrate 10 . The first gate electrode 214 is located on a side of the first gate insulating layer 201 away from the base substrate 10 .

[0147] Step S207, forming a second gate insulating layer 202 on the side of the first gate 214 away from the substrate 10. Forming a second plate 221 of the storage capacitor 22 on the side of the second gate insulating layer 202 away from the substrate plate. The interlayer dielectric layer is located on the side of the second plate away from the substrate.

[0148] In this case, the step of forming the isolation structure 40 also includes: forming a third isolation layer; wherein the third isolation layer includes: a first sub-isolation layer 411 formed synchronously with the first gate insulation layer 201 in step S206, and / or, a second sub-isolation layer 412 formed synchronously with the second gate insulation layer 202 in step 207.

[0149] In some embodiments, in step S207, while forming the second electrode 221 of the storage capacitor 22 on the side of the second gate insulating layer 202 away from the substrate electrode, the second gate 234 of the second thin film transistor 23 is formed. In step S204, while forming the first source-drain electrode on the side of the interlayer dielectric layer 204 away from the substrate 10, the second source-drain electrode of the second thin film transistor 23 is formed.

[0150] The steps of forming the driving circuit layer 20 include steps S208 and S209 in addition to steps S201 to S207:

[0151] Step S208 , forming a third gate insulating layer 203 on a side of the second electrode plate 221 away from the base substrate 10 .

[0152] Step S209 , forming a second active layer 233 of the second thin film transistor 23 on a side of the third gate insulating layer 203 away from the base substrate 10 ; wherein the interlayer dielectric layer 204 is located on a side of the second active layer 233 away from the base substrate 10 .

[0153] In this case, the step of forming the isolation structure 40 further includes: forming a fourth isolation layer 413 ; wherein the fourth isolation layer 413 is formed simultaneously with the third gate insulation layer 203 in step S308 .

[0154] In some embodiments, the step of forming the driving circuit layer 20, in addition to steps S201 to S209, further includes step S210:

[0155] Step S210 , forming a second buffer layer 208 on a side of the second electrode plate 221 away from the base substrate 10 . The third gate insulating layer 203 is located on a side of the second buffer layer 208 away from the base substrate 10 .

[0156] In this case, the step of forming the isolation structure 40 further includes: forming a fifth isolation layer 418 ; wherein the fifth isolation layer 418 is formed simultaneously with the second buffer layer 208 in step S210 .

[0157] In some embodiments, the step of forming the isolation structure 40 also includes: forming a third isolation portion 43, and the third isolation portion 43 is formed synchronously with the first active layer 213 in step S201; and / or, forming a fourth isolation portion 44, and the fourth isolation portion 44 is formed synchronously with the second active layer 233 in step S209.

[0158] In a specific embodiment, the method for preparing a display panel includes steps S1 to S7:

[0159] Step S1 : forming a first semiconductor material layer on one side of the base substrate 10 , and patterning the first semiconductor material layer to obtain a first active layer 213 located in the display area AA and a third isolation portion 43 located in the opening area HA.

[0160] Step S2, forming a first gate insulating material layer on the side of the first active layer 213 and the third isolation portion 43 away from the base substrate 10, wherein the first gate insulating material layer covers the display area AA and the opening area HA, or the first gate insulating material layer covers the display area AA. Forming a first gate material layer on the side of the first gate insulating material layer away from the base substrate 10, and patterning the first gate material layer to obtain a first gate 213 of the first thin film transistor 21 located in the display area AA and a first electrode 222 of the storage capacitor 22.

[0161] Step S3, forming a second gate insulating material layer on the side of the first gate 213 and the first electrode 222 away from the base substrate 10, wherein the first gate insulating material layer covers the display area AA and the opening area HA, or the first gate insulating material layer covers the display area AA. Forming a second electrode material layer on the side of the second gate insulating layer away from the base substrate 10, and patterning the second electrode material layer to obtain the second electrode 221 of the storage capacitor 22.

[0162] Step S4, forming an interlayer dielectric material layer on the side of the second electrode 221 away from the base substrate 10, the interlayer dielectric material layer covers the display area AA and the opening area HA. ​​Forming a source-drain electrode material layer on the side of the interlayer dielectric material layer away from the base substrate 10, and patterning the source-drain electrode material layer to obtain a first source 211 and a first drain 212 of the first thin film transistor 21.

[0163] Step S5, forming a passivation material layer and a planarization material layer on the side of the first source electrode 211 and the first drain electrode 212 away from the base substrate 10, wherein the passivation material layer covers the display area AA and the opening area HA. ​​The planarization material layer covers the display area AA.

[0164] Step S6: Process the passivation material layer and the planarization material layer located in the display area AA to form a via hole penetrating the passivation material layer and the planarization material layer, and form a first electrode material layer on a side of the planarization material layer away from the base substrate 10, so that the first electrode material layer is electrically connected to the first drain electrode 212 through the via hole. The first electrode material layer covers the display area AA and the opening area HA.

[0165] Step S7, performing patterning on the first electrode material layer located in the opening area HA to obtain a second isolation portion 42 having a third sub-hole.

[0166] Step S8, when the first gate insulating material layer in step S2 and the second gate insulating material layer in step S3 only cover the display area AA, the passivation material layer and the interlayer dielectric material layer are sequentially etched to obtain the first isolation portion 41. At this time, the first isolation portion 41 includes: a second isolation layer 415 disposed in the same layer as the passivation layer 205 and a first isolation layer 414 disposed in the same layer as the interlayer dielectric layer 204. When the first gate insulating material layer in step S2 and the second gate insulating material layer in step S3 both cover the display area AA and the opening area HA, the passivation material layer, the interlayer dielectric material layer, the second gate insulating material layer and the first gate insulating material layer are sequentially etched to obtain the first isolation portion 41. At this time, the first isolation portion includes: a second isolation layer 415 disposed in the same layer as the passivation layer 205, a first isolation layer 414 disposed in the same layer as the interlayer dielectric layer 204, a second sub-isolation layer 412 disposed in the same layer as the second gate insulating layer 202, and a first sub-isolation layer 411 disposed in the same layer as the first gate insulating layer 201. When the first gate insulating material layer in step S2 covers the display area AA and the opening area HA, and the second gate insulating material layer in step S3 only covers the display area AA, the passivation material layer, the interlayer dielectric material layer and the first gate insulating material layer are etched in sequence to obtain the first isolation portion 41. At this time, the first isolation portion 41 includes: a second isolation layer 415 arranged on the same layer as the passivation layer 205, a first isolation layer 414 arranged on the same layer as the interlayer dielectric layer 204, and a first sub-isolation layer 411 arranged on the same layer as the first gate insulating layer 201. In the case where the first gate insulating material layer in step S2 only covers the display area AA, and the second gate insulating material layer in step S3 covers the display area AA and the opening area HA, the passivation material layer, the interlayer dielectric material layer and the second gate insulating material layer are sequentially etched to obtain the first isolation portion 41. At this time, the first isolation portion 41 includes: a second isolation layer 415 disposed in the same layer as the passivation layer 205, a first isolation layer 414 disposed in the same layer as the interlayer dielectric layer 204, and a second sub-isolation layer 412 disposed in the same layer as the second gate insulating layer 202. During the etching process, the third isolation portion 43 is used as a sacrificial layer to detect the etching rate.

[0167] In another specific embodiment, in step S3, while the second electrode material layer is patterned to obtain the second electrode 221 of the storage capacitor 22, the second gate 234 of the second thin film transistor 23 is also formed. In this case, the method for preparing the display panel, in addition to steps S1 to S8, further includes step S9:

[0168] Step S9, forming a third gate insulating material layer on the side of the second electrode 221 away from the base substrate 10, the third gate insulating material layer covers the display area AA and the opening area HA, or the third gate insulating material layer covers the display area AA. Forming a second active material layer on the side of the third gate insulating material layer away from the base substrate 10, the second active material layer covers the display area AA and the opening area HA. ​​The second active material layer is patterned to obtain a second active layer 233 located in the display area AA and a fourth isolation portion 44 located in the opening area HA, or only forming the second active layer 233 located in the display area AA.

[0169] The interlayer dielectric material layer is located on a side of the second active layer 233 away from the base substrate 10 .

[0170] Accordingly, when the third gate insulating material layer covers the display area AA and the opening area HA, step S8 also requires etching the third gate insulating material layer to obtain a fourth isolation layer 413 disposed in the same layer as the third gate insulating layer 203 in the first isolation portion 41 .

[0171] The disclosed embodiment can use the second isolation portion 42 provided in the same layer as the first electrode 301 as a mask to etch the inorganic film layer to form the first isolation portion 41 when forming the HIAA (Hole In Active Area) isolation structure, so that the isolation structure 40 can be formed more easily and the isolation (Undercut) effect of the isolation structure 40 can be ensured. For example, an encapsulation layer is formed on the other side of the light-emitting device 30 away from the base substrate 10, and the isolation structure will make the break of the encapsulation layer clearer. The encapsulation layer is an encapsulation film layer that prevents the penetration of external water vapor, oxygen, etc. At the same time, the first isolation portion 41 of the inorganic material can also isolate water vapor and oxygen to prevent the display panel from being corroded.

[0172] The present disclosure also provides a display device, comprising a display panel and a photosensitive element as described in any embodiment of the present disclosure. The photosensitive element is located on the non-display side of the display panel and is arranged opposite to the opening. The photosensitive element can be a camera or the like.

[0173] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel has an opening area and a display area, wherein the display area surrounds the opening area; the display panel comprises: substrate substrate; An isolation structure located at one side of the base substrate and located in the opening area; the isolation structure comprises a first isolation portion and a second isolation portion sequentially arranged in a direction away from the base substrate, and an opening penetrating the first isolation portion and the second isolation portion is provided; a surface of the second isolation portion close to the base substrate has a first edge close to the opening, and a surface of the first isolation portion away from the base substrate has a second edge close to the opening; an orthographic projection of the second edge on the base substrate surrounds an orthographic projection of the first edge on the base substrate; A driving circuit layer located on one side of the base substrate and a light emitting device located on a side of the driving circuit layer away from the base substrate, wherein the driving circuit layer and the light emitting device are located in the display area; the light emitting device comprises a first electrode; and the first electrode is electrically connected to the driving circuit layer; Wherein, the second isolation portion is arranged in the same layer as the first electrode and is electrically insulated.

2. The display panel according to claim 1, characterized in that: The driving circuit layer comprises: A first thin film transistor; the first thin film transistor comprises a first active layer, a first gate and a first source-drain electrode; wherein the first gate is located between the first active layer and the layer where the first source-drain electrode is located; an interlayer dielectric layer located between the layer where the first source-drain electrode is located and the gate; A passivation layer located at a side of the layer where the first source-drain electrode is located away from the substrate; The first isolation portion includes a first isolation layer disposed in the same layer as the interlayer dielectric layer and a second isolation layer disposed in the same layer as the passivation layer.

3. The display panel according to claim 2, characterized in that: The driving circuit layer also includes: a first gate insulating layer located between the first active layer and the first gate and a second gate insulating layer located between the first gate and the interlayer dielectric layer; A storage capacitor; the storage capacitor comprises a first plate and a second plate; wherein the first plate is disposed in the same layer as the first gate; and the second plate is located between the second gate insulating layer and the interlayer dielectric layer; The first isolation portion further includes a third isolation layer located on a side of the first isolation layer close to the base substrate; The third isolation layer includes: a first sub-isolation layer disposed in the same layer as the first gate insulation layer, and / or a second sub-isolation layer disposed in the same layer as the second gate insulation layer.

4. The display panel according to claim 3, characterized in that: The driving circuit layer also includes: A second thin film transistor; the second thin film transistor comprises a second active layer, a second gate and a second source-drain electrode; wherein the second gate is arranged in the same layer as the second electrode plate, the second source-drain electrode is arranged in the same layer as the first source-drain electrode, and the second active layer is located between the second gate and the second source-drain electrode; a third gate insulating layer located between the second active layer and the second gate; The first isolation portion further includes a fourth isolation layer disposed at the same layer as the third gate insulation layer.

5. The display panel according to claim 4, characterized in that: The driving circuit layer further includes: a buffer layer located between the third gate insulating layer and the second gate; The first isolation portion further includes a fifth isolation layer disposed at the same layer as the second buffer layer.

6. The display panel according to claim 4, characterized in that: The isolation structure also includes: a third isolation portion provided in the same layer as the first active layer; and / or, A fourth isolation portion is disposed in the same layer as the second active layer.

7. The display panel according to claim 4, characterized in that: The first isolation portion further includes a third isolation portion disposed in the same layer as the first active layer; The orthographic projection of the first part of the third isolation part on the substrate overlaps with the orthographic projection of the first isolation part on the substrate, and the orthographic projection of the second part of the third isolation part on the substrate is located on the side of the orthographic projection of the first isolation part on the substrate close to the opening.

8. The display panel according to claim 7, characterized in that: The thickness of the second portion is smaller than the thickness of the first portion.

9. The display panel according to any one of claims 1 to 8, characterized in that: The first isolation portion has a first side surface facing the opening; The first side surface at least includes a first sub-surface and a second sub-surface arranged in the thickness direction of the display panel, wherein the distance from the first sub-surface to the central axis of the opening is different from the distance from the second sub-surface to the center of the opening area.

10. A method for preparing a display panel, characterized in that: The display panel has an opening area and a display area; the display area surrounds the opening area; the preparation method includes: providing a substrate base plate; An isolation structure, a driving circuit layer and a first electrode of the light-emitting device are formed on one side of the base substrate; the driving circuit layer is located in the display area, and the first electrode is located on the side of the driving circuit layer away from the base substrate and is electrically connected to the driving circuit layer; the isolation structure is located in the isolation area, and includes a first isolation portion and a second isolation portion sequentially arranged in a direction away from the base substrate, and an opening penetrating the first isolation portion and the second isolation portion is provided; the surface of the second isolation portion close to the base substrate has a first edge close to the opening, and the surface of the first isolation portion away from the base substrate has a second edge close to the opening; the orthographic projection of the first edge on the base substrate surrounds the orthographic projection of the second edge on the base substrate; The second isolation portion is formed synchronously with the first electrode, and the second isolation portion is electrically insulated from the first electrode.

11. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9; A photosensitive element is located on the non-display side of the display panel and is arranged opposite to the opening.

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