Display substrate and driving method thereof, display panel and display device

Abstract

A display substrate, a display panel and a display device, the display substrate comprising: a first substrate (101); the first transparent electrode layer (110) is arranged on the first substrate (101); the second transparent electrode layer (120) is arranged on one side, deviating from the first substrate (101), of the first transparent electrode layer (110); the M first common signal lines (111) and the N second common signal lines (112) are arranged in the first transparent electrode layer (110), and the M first common signal lines (111) are electrically connected through the N second common signal lines (112); and a sub-pixel (PX) disposed on the first substrate (101), wherein each sub-pixel (PX) comprises a pixel electrode (121) located in a second transparent electrode layer (120), and a transparent conductive structure (D) is defined by M first common signal lines (111) and N second common signal lines (112); in the thickness direction of the display substrate, the pixel electrode (121) and the transparent conductive structure (D) are overlapped, and in the overlapped area, the pixel electrode (121) and the transparent conductive structure (D) are configured to form a storage capacitor (Cst) of a sub-pixel (PX); m and N are positive integers.

Description

Display substrate and driving method thereof, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a driving method thereof, a display panel, and a display device. Background Art

[0002] With the continuous advancement of technology, people have an increasing demand for displays in various life scenarios. Transmissive Liquid Crystal Display (LCD) technology is mature, but in outdoor scenes with strong external light, transmissive LCDs often suffer from problems such as dim screens and severe heat generation. In comparison, reflective LCDs have obvious advantages. They do not require a backlight and directly reflect ambient light to achieve display. The stronger the ambient light, the clearer and more vivid the displayed image.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate and a driving method thereof, a display panel, and a display device.

[0005] According to a first aspect of the present disclosure, there is provided a display substrate, comprising:

[0006] a first substrate;

[0007] a first transparent electrode layer provided on the first base substrate;

[0008] a second transparent electrode layer disposed on a side of the first transparent electrode layer facing away from the first base substrate;

[0009] M first common signal lines and N second common signal lines are provided in the first transparent electrode layer, the M first common signal lines are arranged along a first direction, the N second common signal lines are arranged along a second direction, the first direction and the second direction intersect, and the M first common signal lines are electrically connected through the N second common signal lines; and

[0010] A sub-pixel is provided on the first substrate;

[0011] The sub-pixel includes a pixel electrode located in the second transparent electrode layer, and the M first common signal lines and the N second common signal lines form a transparent conductive structure; and

[0012] In the thickness direction of the display substrate, the pixel electrode and the transparent conductive structure overlap, and in the overlapping area, the pixel electrode and the transparent conductive structure are configured to form a storage capacitor of the sub-pixel;

[0013] Both M and N are positive integers.

[0014] According to an embodiment of the present disclosure, the pixel electrode includes a middle portion and an edge portion surrounding the middle portion, and in a thickness direction of the display substrate, the edge portion overlaps with the transparent conductive structure.

[0015] According to an embodiment of the present disclosure, the portion of the edge portion that overlaps with the transparent conductive structure is formed as the first plate of the storage capacitor, and the transparent conductive structure is formed as the second plate of the storage capacitor. In the same sub-pixel, the portion of the edge portion that overlaps with the transparent conductive structure has a positive projection on the first substrate that includes a continuous annular structure.

[0016] According to an embodiment of the present disclosure, the display substrate includes a data line provided on the first base substrate and electrically connected to the sub-pixel, the data line extending along the second direction, and at least one first common signal line including at least one first line segment;

[0017] In the thickness direction of the display substrate, the data line overlaps with the at least one first line segment, and in the overlapping area, the orthographic projection of the data line on the first base substrate is located within the orthographic projection of the first line segment on the first base substrate;

[0018] At least one of the first line segments includes a first edge and a second edge arranged in sequence along the first direction, and the data line includes a third edge and a fourth edge arranged in sequence along the first direction. In the overlapping area between the data line and at least one of the first line segments, the distance between the first edge of the first line segment and the third edge of the data line is smaller than the distance between the second edge of the first line segment and the fourth edge of the data line.

[0019] According to an embodiment of the present disclosure, the display substrate includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a switching transistor, and the plurality of switching transistors are arranged in an array along the first direction and the second direction;

[0020] An orthographic projection of at least one of the first line segments on the first substrate is located between orthographic projections of two adjacent switching transistors along the second direction on the first substrate.

[0021] According to an embodiment of the present disclosure, in the thickness direction of the display substrate, at least one of the first line segments overlaps with an edge of the pixel electrode close to the data line, and the overlapping portion forms an adjustment portion of the transparent conductive structure, and the size of the adjustment portion in the first direction is positively correlated with the capacitance of the storage capacitor.

[0022] According to an embodiment of the present disclosure, the display substrate further includes a data line, a first gate line, and a second gate line disposed on the first base substrate and electrically connected to the sub-pixel, the N second common signal lines, the first gate line, and the second gate line all extend along the first direction, and the sub-pixel includes a switching transistor;

[0023] The switching transistor includes a first electrode, a second electrode, a first gate electrode and a second gate electrode; the first electrode is electrically connected to the data line, the second electrode is electrically connected to the pixel electrode, the first gate electrode is electrically connected to the first gate line, and the second gate electrode is electrically connected to the second gate line;

[0024] In the thickness direction of the display substrate, at least one second common signal line overlaps with both the first gate line and the second gate line.

[0025] According to an embodiment of the present disclosure, the display substrate further includes a data line and a third gate line disposed on the first base substrate and electrically connected to the sub-pixel, the N second common signal lines and the third gate line all extend along the first direction, and the sub-pixel includes a switching transistor;

[0026] The switching transistor includes a first electrode, a second electrode, a first gate and a second gate, wherein the first gate and the second gate are arranged along the first direction; the first electrode is electrically connected to the data line, the second electrode is electrically connected to the pixel electrode, and the first gate and the second gate are both electrically connected to the third gate line;

[0027] In the thickness direction of the display substrate, at least one of the second common signal lines overlaps with the third gate line.

[0028] According to an embodiment of the present disclosure, the display substrate further includes an active layer located on a side of the first transparent electrode layer close to the first base substrate, and the switching transistor further includes a first channel portion and a second channel portion located in the active layer, an orthographic projection of the first channel portion on the first base substrate at least partially overlaps with an orthographic projection of the first gate electrode on the first base substrate, and an orthographic projection of the second channel portion on the first base substrate at least partially overlaps with an orthographic projection of the second gate electrode on the first base substrate;

[0029] A width-to-length ratio of either the first channel portion or the second channel portion is less than or equal to 4.

[0030] According to an embodiment of the present disclosure, the channel lengths of the first channel portion and the second channel portion are substantially the same.

[0031] According to an embodiment of the present disclosure, a first hollow structure is provided on at least one of the second common signal lines, and in the thickness direction of the display substrate, the first hollow structure overlaps with both the first gate line and the second gate line.

[0032] According to an embodiment of the present disclosure, an overlapping dimension between the first hollow structure and the first gate line in the second direction and an overlapping dimension between the first hollow structure and the second gate line in the second direction are both smaller than a dimension of the data line in the first direction.

[0033] According to an embodiment of the present disclosure, the orthographic projection of the first hollow structure on the first substrate includes a strip structure extending along the first direction, and the size of the first hollow structure in the second direction is greater than or equal to the size of the data line in the first direction.

[0034] According to an embodiment of the present disclosure, at least one of the second common signal lines includes a first sub-line and a second sub-line arranged along the second direction, and the first hollow structure separates the first sub-line from the second sub-line;

[0035] In a thickness direction of the display substrate, the first sub-line of at least one second common signal line at least partially overlaps with the first gate line, and the second sub-line at least partially overlaps with the second gate line.

[0036] According to an embodiment of the present disclosure, the display substrate includes a plurality of sub-pixels, and in the thickness direction of the display substrate, the first gate line and the second gate line electrically connected to the same sub-pixel respectively overlap with the pixel electrodes of two sub-pixels adjacently arranged along the second direction;

[0037] Wherein, for the first gate line and the second gate line connected to the x-th sub-pixel, in the thickness direction of the display substrate, the pixel electrode of the x-th sub-pixel overlaps with the first gate line, and an orthographic projection of the overlapping portion on the first base substrate defines a first area, and the pixel electrode of the x+1-th sub-pixel overlaps with the second gate line, and an orthographic projection of the overlapping portion on the first base substrate defines a second area;

[0038] An orthographic projection of the first sub-line of at least one second common signal line on the first substrate at least partially overlaps with the first region, and an orthographic projection of the second sub-line on the first substrate at least partially overlaps with the second region;

[0039] Wherein, x is a positive integer.

[0040] According to an embodiment of the present disclosure, the orthographic projection of the first sub-line of at least one second common signal line on the first substrate covers the first area, and the orthographic projection of the second sub-line on the first substrate covers the second area.

[0041] According to an embodiment of the present disclosure, the first sub-line and the second sub-line are electrically connected via a connecting bridge located at at least one end of the first hollow structure, and a size of the connecting bridge in the first direction is greater than or equal to a size of the data line in the first direction.

[0042] According to an embodiment of the present disclosure, the connection bridge does not overlap with the data line, and a distance between the connection bridge and the data line in the first direction is smaller than a width of the data line.

[0043] According to an embodiment of the present disclosure, in the thickness direction of the display substrate, the pixel electrode and the third gate line overlap, and the orthographic projection of the overlapping portion on the first base substrate defines a third area, and the orthographic projection of at least one second common signal line on the first base substrate at least partially overlaps with the third area.

[0044] According to an embodiment of the present disclosure, an orthographic projection of at least one second common signal line on the first substrate covers the third area.

[0045] According to an embodiment of the present disclosure, a second hollow structure is provided on at least one of the second common signal lines, and the orthographic projection of the switch transistor on the first substrate is located within the orthographic projection of the second hollow on the first substrate.

[0046] According to an embodiment of the present disclosure, the display substrate includes a plurality of sub-pixels arranged in an array along the first direction and the second direction;

[0047] A second gate line electrically connected to the second gates of the switching transistors of the sub-pixels in the nth row and a first gate line electrically connected to the first gates of the switching transistors of the sub-pixels in the (n+1)th row are electrically connected to the same scan signal terminal;

[0048] Wherein, n is a positive integer.

[0049] According to a second aspect of the present disclosure, a display panel is provided, comprising a color filter substrate and the above-mentioned display substrate; the display panel further comprises:

[0050] Color filter substrate, the display substrate and the color filter substrate are arranged relative to each other:

[0051] a liquid crystal layer located between the display substrate and the color filter substrate;

[0052] Wherein, the color filter substrate includes a second base substrate and a common electrode provided on the second base substrate;

[0053] The common electrode is electrically connected to the first common signal line and the second common signal line in the display substrate; the liquid crystal layer includes a plurality of liquid crystal molecules, and the common electrode and the pixel electrode on the display substrate are configured to form an electric field that drives the liquid crystal molecules to rotate in response to a driving signal.

[0054] According to an embodiment of the present disclosure, a ratio of a cell thickness of the liquid crystal layer to a distance between the first transparent electrode layer and the second transparent electrode layer is greater than or equal to 20:1.

[0055] According to a third aspect of the present disclosure, a reflective display device is provided, comprising the above-mentioned display panel, and further comprising:

[0056] First polarizer;

[0057] a selective wavelength transmission film disposed on a side of the display panel away from the first polarizer;

[0058] a second polarizer disposed on a side of the selective wavelength transmission film away from the first polarizer;

[0059] The first polarizer has a first transmission axis and is configured to generate a first polarized light having a polarization direction parallel to the first transmission axis; the second polarizer has a second transmission axis and is configured to generate a second polarized light having a polarization direction parallel to the second transmission axis; and the extension direction of the first transmission axis and the extension direction of the second transmission axis intersect;

[0060] The selective wavelength transmission film is configured to reflect the first polarized light and transmit the second polarized light.

[0061] According to an embodiment of the present disclosure, the display device further includes a light absorbing layer disposed on a side of the selective wavelength transmission film away from the display panel, and the light absorbing layer is configured to absorb the second polarized light transmitted by the selective wavelength transmission film.

[0062] According to a fourth aspect of the present disclosure, a method for driving a display substrate is provided, wherein the display substrate includes:

[0063] a first substrate;

[0064] a first transparent electrode layer provided on the first base substrate;

[0065] a second transparent electrode layer disposed on a side of the first transparent electrode layer facing away from the first base substrate;

[0066] M first common signal lines and N second common signal lines are provided in the first transparent electrode layer, the M first common signal lines are arranged along a first direction, the N second common signal lines are arranged along a second direction, the first direction and the second direction intersect, the M first common signal lines are electrically connected through the N second common signal lines, and both M and N are positive integers; and

[0067] A sub-pixel is provided on the first substrate;

[0068] The sub-pixel includes a pixel electrode located in the second transparent electrode layer, and the M first common signal lines and the N second common signal lines form a transparent conductive structure; and

[0069] In the thickness direction of the display substrate, the pixel electrode and the transparent conductive structure overlap, and in the overlapping area, the pixel electrode and the transparent conductive structure are configured to form a storage capacitor of the sub-pixel;

[0070] The display substrate further includes a data line, a first gate line and a second gate line, and the sub-pixel includes a switching transistor;

[0071] The switching transistor includes a first electrode, a second electrode, a first gate electrode, and a second gate electrode; the first electrode is electrically connected to the data line, the second electrode is electrically connected to the pixel electrode, the first gate electrode is electrically connected to the first gate line, and the second gate electrode is electrically connected to the second gate line.

[0072] The display substrate includes a plurality of sub-pixels arranged in an array along the first direction and the second direction;

[0073] A second gate line electrically connected to the second gates of the switching transistors of the sub-pixels in the nth row and a first gate line electrically connected to the first gates of the switching transistors of the sub-pixels in the (n+1)th row are electrically connected to the same scan signal terminal;

[0074] Wherein, n is a positive integer;

[0075] The driving method includes:

[0076] In a first data writing phase of the n-th row of sub-pixels, a valid level signal is provided to a first gate line electrically connected to the n-th row of sub-pixels, and an invalid level signal is provided to a second gate line electrically connected to the n-th row of sub-pixels;

[0077] In the second data writing phase of the n-th row of sub-pixels, providing an effective level signal to the first gate line electrically connected to the n-th row of sub-pixels, and providing an effective level signal to the second gate line electrically connected to the n-th row of sub-pixels;

[0078] In the display phase of the nth row of sub-pixels, an inactive level signal is provided to the first gate line electrically connected to the nth row of sub-pixels, and an active level signal is provided to the second gate line electrically connected to the nth row of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0080] FIG1 schematically shows a plan view of a display substrate according to an embodiment of the present disclosure;

[0081] FIG2 schematically shows a cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0082] FIG3 schematically shows a plan view of a first transparent electrode layer according to an embodiment of the present disclosure;

[0083] FIG4 schematically shows a plan view of a second transparent electrode layer according to an embodiment of the present disclosure;

[0084] FIG5 schematically shows a plan view of a sub-pixel and its surroundings according to an embodiment of the present disclosure;

[0085] FIG6 schematically shows a plan view of a middle portion and an edge portion of a pixel electrode according to an embodiment of the present disclosure;

[0086] FIG7 schematically shows a plan view of a first line segment of a pixel electrode according to an embodiment of the present disclosure;

[0087] FIG8 schematically shows a diagram of the dimensions between a data line, a first line segment, and a pixel electrode according to an embodiment of the present disclosure;

[0088] FIG9 schematically shows a schematic diagram of an adjustment portion according to an embodiment of the present disclosure;

[0089] FIG10 schematically shows a schematic diagram of a pixel electrode overlapping a first line segment according to an embodiment of the present disclosure;

[0090] FIG11 schematically shows a plan view of a gate layer according to an embodiment of the present disclosure;

[0091] FIG12 schematically shows a plan view of an active layer according to an embodiment of the present disclosure;

[0092] FIG13 schematically shows a plan view of a gate layer and an active layer according to an embodiment of the present disclosure;

[0093] FIG14 schematically shows a plan view of a source-drain electrode layer according to an embodiment of the present disclosure;

[0094] FIG15 schematically shows a plan view of a gate layer, an active layer, and a source-drain electrode layer according to an embodiment of the present disclosure;

[0095] FIG16 schematically shows one of the driving timing diagrams according to an embodiment of the present disclosure;

[0096] FIG17 schematically shows a schematic diagram of electrical connection between a gate line and a scan signal terminal according to an embodiment of the present disclosure;

[0097] FIG18 schematically shows a second driving timing diagram according to an embodiment of the present disclosure;

[0098] FIG19 schematically shows a plan view of a first hollow structure and a second hollow structure according to an embodiment of the present disclosure;

[0099] FIG20 schematically shows a plan view of a first void structure overlapping with a first grid line and a second grid line according to an embodiment of the present disclosure;

[0100] FIG21 schematically shows a schematic diagram of the dimensions of the first void structure overlapping with the first grid line and the second grid line according to an embodiment of the present disclosure;

[0101] FIG22 schematically shows a plan view of a single gate line driving switch transistor in an embodiment of the present disclosure;

[0102] FIG23 schematically shows a cross-sectional view of a switch transistor in an embodiment of the present disclosure and a cross-sectional view of a single-gate transistor having the same channel length as the switch transistor in the embodiment of the present disclosure;

[0103] FIG24 is a schematic diagram of FIG22 along the section line FF';

[0104] FIG25 schematically shows a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0105] FIG26 schematically shows a schematic diagram of a twisted nematic liquid crystal display panel according to an embodiment of the present disclosure;

[0106] FIG27 schematically shows a schematic diagram of a color filter substrate according to an embodiment of the present disclosure;

[0107] FIG28 schematically shows a schematic diagram of a display device according to an embodiment of the present disclosure;

[0108] FIG29 schematically shows a schematic diagram of a display device in a bright state according to an embodiment of the present disclosure;

[0109] FIG30 schematically shows a schematic diagram of a display device in a dark state according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0110] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0111] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0112] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0113] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0114] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0115] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0116] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0117] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0118] In a pair of proportions, a fully reflective liquid crystal display panel is provided, in which the display panel includes a first substrate and a plurality of pixel units arranged on the first substrate and arranged in an array along a first direction and a second direction. The pixel unit includes a plurality of sub-pixels, and in the same pixel unit, different sub-pixels are used to display different colors. For example, the pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel cooperate with their respective corresponding color resistances (e.g., red color resistance, green color resistance, and blue color resistance) to achieve the display of corresponding colors. For ease of understanding, the first sub-pixel can be described as a red sub-pixel, the second sub-pixel can be described as a green sub-pixel, and the third sub-pixel can be described as a blue sub-pixel.

[0119] The display panel also includes multiple gate lines and multiple data lines. The gate lines extend along a first direction, and the data lines extend along a second direction. A gate line is electrically connected to a row of sub-pixels, and a data line is electrically connected to a column of sub-pixels. In other words, one sub-pixel is connected to one gate line and one data line. This type of display panel is also called a 1G1D display panel.

[0120] A sub-pixel includes a switching transistor and a pixel storage capacitor electrically connected to the switching transistor. The gate of the switching transistor is electrically connected to the gate line, and the first and second electrodes of the switching transistor are electrically connected to the data line and the pixel storage capacitor, respectively. The switching transistor is turned on and off by an electrical signal on the gate line, while the voltage written to the pixel storage capacitor is determined by an electrical signal on the data line.

[0121] The display panel further includes a gate layer, a pixel electrode layer, and a common electrode layer sequentially arranged in a direction away from the first base substrate. The gate line and the gate of the switching transistor may be located in the gate layer. The sub-pixel further includes a pixel electrode, a common electrode, and a liquid crystal layer. The pixel electrode is located in the pixel electrode layer, and the common electrode is located in the common electrode layer. Liquid crystal in the liquid crystal layer can be deflected in response to a voltage between the pixel electrode and the common electrode, thereby realizing the display function of the sub-pixel.

[0122] The pixel storage capacitor includes a first plate and a second plate arranged with an insulating space, and the common electrode is electrically connected to a common signal terminal for providing a common voltage through a common signal line. The first plate and the common signal line are both located in the gate layer and the two can form an integrated structure, or in other words, in this comparative example, the common signal line is reused to form the first plate of the pixel storage capacitor. For example, the second plate is located in the pixel electrode layer, and in the thickness direction of the display panel, the common signal line and the second plate at least partially overlap, and the portion where the common signal line and the second plate overlap can be reused as the first plate of the pixel storage capacitor.

[0123] In this comparative example, the gate layer is made of metal material, so the common signal line located in the gate layer is not light-transmitting (or has a low light transmittance). Therefore, the layout of the common signal line will occupy the pixel opening area of ​​the sub-pixel, thereby making the pixel opening ratio low; not only that, the size of the common signal line is limited by the pixel opening ratio, and the overlapping area between the common signal line and the pixel electrode can only be adjusted within a small range, which makes the capacitance of the pixel storage capacitor relatively small and the design flexibility poor, making it difficult to meet the needs of large capacitance.

[0124] In view of this, an embodiment of the present disclosure provides a display substrate, which includes: a first base substrate; a first transparent electrode layer arranged on the first base substrate; a second transparent electrode layer arranged on a side of the first transparent electrode layer facing away from the first base substrate; a plurality of first common signal lines and a plurality of second common signal lines arranged in the first transparent electrode layer, the plurality of first common signal lines being arranged along a first direction, the plurality of second common signal lines being arranged along a second direction, the first direction and the second direction intersecting, the plurality of first common signal lines being electrically connected through the plurality of second common signal lines; and a sub-pixel arranged on the first base substrate; wherein the sub-pixel includes a pixel electrode located in the second transparent electrode layer, the plurality of first common signal lines and the plurality of second common signal lines forming a transparent conductive structure; and, in a thickness direction of the display substrate, the pixel electrode and the transparent conductive structure overlap, and in the overlapping area, the pixel electrode and the transparent conductive structure are configured to form a storage capacitor of the sub-pixel.

[0125] In the embodiment of the present disclosure, the first common signal line and the second common signal line are located in the first transparent electrode layer, which can be made of a transparent conductive material. For example, the transparent conductive material can include, but is not limited to, indium tin oxide (ITO). In other words, in the embodiment of the present disclosure, the first common signal line and the second common signal line are made of a transparent conductive material having a light transmittance greater than that of a conductive film layer (e.g., a gate layer) made of a non-transparent metal material.

[0126] The common signal lines (first and second common signal lines) in the disclosed embodiment are located in the first transparent electrode layer and are made of a transparent conductive material. Compared to the comparative example in which the common signal lines are located in the gate layer and made of an opaque metal material, the common signal lines in the disclosed embodiment have better light transmittance. Furthermore, when the transparent common signal lines are used to form storage capacitors, the disclosed embodiment can alleviate the situation where the pixel opening area is squeezed, thereby improving the pixel aperture ratio.

[0127] The display substrate according to the embodiment of the present disclosure will be described in detail below with reference to FIG. 1 to FIG. 19 .

[0128] FIG. 1 schematically shows a plan view of a display substrate according to an embodiment of the present disclosure.

[0129] 1 , the display substrate according to the embodiment of the present disclosure includes a display area AA and a peripheral area NA located at least on one side of the display area AA.

[0130] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a polygon (e.g., a rectangle) with straight edges, a circle or an ellipse with curved edges, or a semicircle or a semiellipse with both straight and curved edges. In the embodiment of the present disclosure, the display area AA is provided as a region having a quadrilateral shape with straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0131] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a longitudinal portion extending in the second direction Y and a transverse portion extending in the first direction X.

[0132] The display substrate may further include a gate drive circuit 11 and a drive chip 12 located in the peripheral area NA. For example, the gate drive circuit 11 may be located on at least one side of the display area AA. In the embodiment shown in FIG1 , the gate drive circuit 11 is respectively located on the left and right sides of the display area AA. It should be noted that the left and right sides may be the left and right sides of the display substrate (screen) viewed by the human eye during display. For example, the drive chip 12 may be located on at least one side of the display area AA. In the embodiment shown in FIG1 , the drive chip 12 is located on the lower side of the display area AA. It should be noted that the lower side may be the lower side of the display substrate (screen) viewed by the human eye during display.

[0133] The driver chip 12 includes a data driver circuit that sequentially latches input data according to a clock signal, converts the latched data into analog signals, and then inputs them to the data lines of the display substrate. The gate driver circuit 11 is typically implemented by a shift register, which converts the clock signal into on / off voltages and outputs them to the gate lines of the display substrate.

[0134] It should be noted that although Figure 1 shows that the gate drive circuit 11 is located on the left and right sides of the display area AA and the drive chip 12 is located on the lower side of the display area AA, the embodiments of the present disclosure are not limited to this. The gate drive circuit 11 and the drive chip 12 can be located at any suitable position in the peripheral area NA.

[0135] For example, the gate driver circuit 11 can adopt GOA technology, i.e., Gate Driver on Array. In GOA technology, the gate driver circuit 11 is directly set on the display substrate to replace the external chip. Each GOA unit serves as a first-level shift register, and each level of shift register is connected to a gate line. The shift registers at each level output scanning signals in turn in sequence to achieve row-by-row scanning of the pixel unit. In some embodiments, each level of shift register can also be connected to multiple gate lines. In this way, it can adapt to the development trend of high resolution and narrow frame of display substrates. The driver chip 12 can be folded to the back side of the display substrate through structures such as flip-chip film.

[0136] The display substrate (or array substrate) of the disclosed embodiment can be applied to a fully reflective liquid crystal display device. A fully reflective liquid crystal display device does not have a backlight source, but instead uses ambient light to achieve its display function. This type of display device has higher display brightness in application scenarios with strong ambient light (such as outdoor billboards, etc.), and the stronger the ambient light, the clearer the displayed image and the more vivid the colors. The specific structure and operating principle of the fully reflective liquid crystal display device will be described in detail below, so it will not be repeated here.

[0137] In an embodiment of the present disclosure, the display substrate may further include a first base substrate 101, a plurality of pixel units P disposed on the first base substrate 101 and located in the display area AA, and the plurality of pixel units P may be arranged in an array along the second direction Y and the first direction X. Each pixel unit P may include a plurality of sub-pixels PX, for example, a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel cooperate with color resistance (for example, red color resistance, green color resistance, and blue color resistance) to achieve the display of corresponding colors. For ease of understanding, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be described as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively, but the embodiments of the present disclosure are not limited thereto.

[0138] In an embodiment of the present disclosure, the display substrate further includes a plurality of gate lines GL and a plurality of data lines DL. The gate lines GL extend along a first direction X, and the data lines DL extend along a second direction Y. In an embodiment of the present disclosure, one sub-pixel PX is correspondingly connected to one data line DL and at least one gate line GL.

[0139] Figure 2 schematically shows a cross-sectional view of a display substrate according to an embodiment of the present disclosure, Figure 3 schematically shows a plan view of a first transparent electrode layer according to an embodiment of the present disclosure, Figure 4 schematically shows a plan view of a second transparent electrode layer according to an embodiment of the present disclosure, and Figure 5 schematically shows a plan view of a sub-pixel and its periphery according to an embodiment of the present disclosure. The light-transmitting conductive structure D of the embodiment of the present disclosure will first be introduced below with reference to Figures 1 to 5.

[0140] In the embodiment of the present disclosure, the display substrate further includes a first transparent electrode layer 110 disposed on a first base substrate 101, a second transparent electrode layer 120 disposed on a side of the first transparent electrode layer 110 facing away from the first base substrate 101, and a sub-pixel PX disposed on the first base substrate 101. The sub-pixel PX includes a pixel electrode 121 located in the second transparent electrode layer 120. It should be noted that in the embodiment of the present disclosure, the display substrate may include multiple sub-pixels PX. For clarity, unless otherwise specified, the embodiment of the present disclosure is described using one sub-pixel PX as an example. Therefore, the sub-pixel PX herein may refer to one of the multiple sub-pixels PX in the display substrate.

[0141] In an embodiment of the present disclosure, the display substrate further includes M first common signal lines 111 and N second common signal lines 112 disposed in the first transparent electrode layer 110, where M and N are positive integers. The M first common signal lines 111 are arranged along a second direction Y, and the N second common signal lines 112 are arranged along a first direction X. The second direction Y intersects the first direction X, and the M first common signal lines 111 are electrically connected via the N second common signal lines 112. For example, the second direction Y can be the vertical direction in FIG. 1 , and the first direction X can be the horizontal direction in FIG. 1 , i.e., the second direction Y and the first direction X are perpendicular to each other. The M first common signal lines 111 and the N second common signal lines 112 form a transparent conductive structure D.

[0142] It should be noted that, in the embodiments of the present disclosure, a plurality of first common signal lines 111 and a plurality of second common signal lines 112 may be provided in the first transparent electrode layer 110, and the plurality of first common signal lines 111 and the plurality of second common signal lines 112 may intersect with each other to form a mesh. The M first common signal lines 111 may refer to two adjacent first common signal lines 111, and the N second common signal lines 112 may refer to two adjacent second common signal lines 111. In other words, the light-transmitting conductive structure D is located in one of the grids of the mesh structure formed by the plurality of first common signal lines 111 and the plurality of second common signal lines 112, and specifically may be the portion of the grid covered by the same pixel electrode 121, as shown by the dotted line in FIG. 3 .

[0143] It should also be noted that, in the embodiment of the present disclosure, in the mesh structure formed by multiple first common signal lines 111 and multiple second common signal lines 112, each grid may include a light-transmitting conductive structure D. For clarity, unless otherwise specified, the embodiment of the present disclosure is described using a light-transmitting conductive structure D as an example. Therefore, the transparent conductive structure D surrounded by the M first common signal lines 111 and the N second common signal lines 112 in the foregoing text may refer to one of the multiple transparent conductive structures D in the mesh structure.

[0144] Exemplarily, two adjacent transparent conductive structures D share a first common signal line 111 (or a second common signal line 112) therebetween. For example, two adjacent transparent conductive structures D in the second direction Y share a second common signal line 112, and two adjacent transparent conductive structures D in the first direction X share a first common signal line 111.

[0145] 5 , the pixel electrode 121 and the transparent conductive structure D overlap in the thickness direction of the display substrate, and in the overlapping region, the pixel electrode 121 and the transparent conductive structure D are configured to form a storage capacitor Cst of the sub-pixel PX.

[0146] The sub-pixel PX further includes a switching transistor T disposed on the first substrate, and the pixel electrode 121 is electrically connected to the switching transistor T. The switching transistor T is electrically connected to the data line DL, the gate line GL, and the pixel electrode 121. In response to an active level signal on the gate line GL, the switching transistor T can transmit the data voltage on the data line DL to the pixel electrode 121 and store it in the storage capacitor Cst formed by the pixel electrode 121 and the transparent conductive structure D. In this way, during the light-emitting phase, the pixel electrode 121 can be maintained at a desired potential, thereby cooperating with the common electrode and liquid crystal layer to achieve continuous display for one frame period.

[0147] The first transparent electrode layer 110 and the second transparent electrode layer 120 are both made of transparent conductive materials, which can be the same or different. For example, the first transparent electrode layer 110 and the second transparent electrode layer 120 are made of the same material, which can include indium tin oxide.

[0148] The pixel electrode 121 may include a planar structure, and the pixel electrodes 121 of different sub-pixels PX are insulated and spaced apart. The transparent conductive structure D may include a ring structure.

[0149] In the embodiments of the present disclosure, a corresponding position on the pixel electrode 121 can be selected to overlap with the transparent conductive structure D according to actual needs to form a storage capacitor Cst. For example, at least one side edge of the pixel electrode 121 can be selected to overlap with the transparent conductive structure D, thereby forming a storage capacitor Cst in an "I" shape, an "L" shape, or a ring shape.

[0150] The common signal lines (first common signal lines 111 and second common signal lines 112) in the embodiment of the present disclosure are located in the first transparent electrode layer 110 and are made of a transparent conductive material. Compared with the method in which the common signal lines are set in the gate layer and made of an opaque metal material in the comparative example, the common signal lines in the embodiment of the present disclosure have better light transmittance. Furthermore, when the storage capacitor is formed using transparent common signal lines (specifically, the transparent conductive structure D surrounded by the first common signal line 111 and the second common signal line 112), the embodiment of the present disclosure can improve the situation where the pixel opening area is occupied (specifically, the pixel opening area is occupied by the non-transparent common signal line in the comparative example), thereby improving the pixel aperture ratio. In addition, the transparent conductive structure D has a high light transmittance, and its size will be greatly reduced due to the limitation of the pixel aperture ratio. Therefore, the size adjustment range of the transparent conductive structure D can be greatly increased. Subsequently, the storage capacitor Cst formed based on the transparent conductive structure D and the pixel electrode 121 has a larger adjustment space, which is conducive to forming a storage capacitor Cst with a larger capacitance in the display substrate.

[0151] The display substrate according to the embodiment of the present disclosure will be further described below with reference to FIG. 1 to FIG. 19 .

[0152] FIG6 schematically illustrates a plan view of the middle portion and edge portion of a pixel electrode according to an embodiment of the present disclosure. Referring to FIG3 to FIG6 , in some specific embodiments, the pixel electrode 121 includes a middle portion 1211 and an edge portion 1212 surrounding the middle portion 1211. In the thickness direction of the display substrate, the edge portion 1212 overlaps with the transparent conductive structure D, and the middle portion 1211 is spaced apart from the transparent conductive structure D. In other words, in the embodiment of the present disclosure, the pixel electrode 121 overlaps with the transparent conductive structure D only at its edge.

[0153] The inventors discovered during their research that although both the pixel electrode 121 and the transparent conductive structure D are made of indium tin oxide, a transparent conductive material with a relatively high transmittance, for example, a transmittance of approximately 90% in the visible light band. However, the indium tin oxide material still has a certain absorption effect on light, and as the film thickness increases, the absorption amount increases, resulting in a gradual decrease in transmittance. Moreover, there is a certain reflection effect at the interface between the pixel electrode 121 and the transparent conductive structure D, which causes the transmittance to further decrease. This makes the transmittance of the overlapping area of ​​the pixel electrode 121 and the transparent conductive structure D relatively low compared to the area where only the pixel electrode 121 and the transparent conductive structure D are set.

[0154] Therefore, in the embodiment of the present disclosure, the pixel electrode 121 overlaps the transparent conductive structure D only at its edges, thereby limiting the overlapping region with relatively low light transmittance to the periphery of the pixel electrode 121, while maintaining relatively good light transmittance in the central region of the pixel electrode 121. This prevents the pixel electrode 121 from overlapping with the transparent conductive structure D excessively, thereby preventing the overall light transmittance of the sub-pixel PX from decreasing.

[0155] Optionally, the overlapping regions of the pixel electrode 121 and the transparent conductive structure D can be dispersed at edge positions. For example, at least one edge of the pixel electrode 121 can overlap with the transparent conductive structure D; or for another example, at least two edges of the pixel electrode 121 can overlap with the transparent conductive structure D.

[0156] In some specific embodiments, the portion of the edge portion 1212 that overlaps with the transparent conductive structure D is formed as the first plate of the storage capacitor Cst, and the transparent conductive structure D is formed as the second plate of the storage capacitor Cst. In the same sub-pixel PX, the orthographic projection of the portion of the edge portion 1212 that overlaps with the transparent conductive structure D on the first base substrate 101 includes a continuous ring structure.

[0157] Thus, the four sides of the pixel electrode 121 can be overlapped with the transparent conductive structure D. This prevents the overlapping area of ​​the pixel electrode 121 and the transparent conductive structure D from being concentrated in a certain position, thereby avoiding the problem of reduced overall light transmittance in a certain area and large differences in light transmittance at different positions.

[0158] In an embodiment of the present disclosure, the display substrate further includes a first insulating layer PVX1 located between the first transparent electrode layer 110 and the second transparent electrode layer 120. The transparent conductive structure D and the pixel electrode 121 are separated by the first insulating layer PVX1, thereby isolating the transparent conductive structure D and the pixel electrode 121 from each other to form a storage capacitor Cst.

[0159] For example, the area of ​​the transparent conductive structure D can be set to 5000 μm 2 Up to 6000μm 2 , for example 5756μm 2 , which can be determined according to actual needs and is not limited here.

[0160] In addition to increasing the pixel aperture ratio and expanding the adjustment range of the pixel capacitor value, the embodiments of the present disclosure also reduce the power consumption of the display substrate in the following manner.

[0161] In some specific embodiments, the display substrate includes data lines DL disposed on a first base substrate 101 and electrically connected to sub-pixels (e.g., the data lines DL on the left side of FIG. 7 ). The data lines DL extend along a second direction Y. At least one first common signal line 111 is disposed corresponding to at least one data line DL, and different first common signal lines 111 are disposed corresponding to different data lines DL. The first common signal line 111 and the corresponding data line DL are disposed in parallel. For example, the orthographic projections of the first common signal line 111 and the corresponding data line DL on the first base substrate 101 overlap.

[0162] FIG7 schematically shows a plan view of a first line segment of a pixel electrode according to an embodiment of the present disclosure. Referring to FIG3 to FIG7 , at least one first common signal line 111 includes at least one first line segment 1111. In the thickness direction of the display substrate, at least one data line DL overlaps with the at least one first line segment 1111, and in the overlapping region, the orthographic projection of the data line DL on the first base substrate 101 is within the orthographic projection of the first line segment 1111 on the first base substrate 101.

[0163] Figure 8 schematically shows a schematic diagram of the dimensions between the data line, the first line segment and the pixel electrode according to an embodiment of the present disclosure. In combination with Figures 3 to 8, in an embodiment of the present disclosure, at least one first line segment 1111 includes a first edge 1111a and a second edge 1111b arranged in sequence along the second direction Y, and the data line DL includes a third edge DLa and a fourth edge DLb arranged in sequence along the second direction Y. In the overlapping area of ​​the data line DL and the first line segment 1111, the spacing d1 between the first edge 1111a of the first line segment 1111 and the third edge DLa of the data line DL is smaller than the spacing d2 between the second edge 1111b of the first line segment 1111 and the fourth edge DLb of the data line DL.

[0164] 7 , the data line DL is located in the first line segment 1111 and is disposed near the left side of the first line segment 1111. The left edge of the data line DL is closer to the left edge of the first line segment 1111, while the right edge of the data line DL is farther from the right edge of the first line segment 1111.

[0165] Optionally, the pixel electrodes 121, the data lines DL and the first line segments 1111 are arranged to overlap in pairs. For example, referring to FIG8 , the left edge of the pixel electrode 121 is located to the left of the right edge of the data line DL and to the right of the left edge of the data line DL.

[0166] In some specific embodiments, in the overlapping region between the data line DL and the first line segment 1111, a distance d1 between a first edge 1111a of the first line segment 1111 and a third edge DLa of the data line DL is smaller than a dimension d3 of the data line DL in the first direction X, and a distance between a second edge 1111b of the first line segment 1111 and a fourth edge DLb of the data line DL is larger than the dimension d3 of the data line DL in the first direction X. For example, the width of the data line DL may be set to 6 μm, and the distance between the left edge of the first line segment 1111 and the left edge of the data line DL may be set to 2.3 μm.

[0167] It should be noted that, in the embodiments of the present disclosure, the spacing may refer to an average spacing or a minimum spacing, and the width may refer to an average width or a minimum width.

[0168] In some specific embodiments, the display substrate includes a plurality of sub-pixels PX, each of which includes a switching transistor T. The plurality of switching transistors T are arranged in an array along a first direction X and a second direction Y. The orthographic projection of at least one first line segment 111 on the first base substrate 101 is located between the orthographic projections of two adjacent switching transistors T along the second direction Y. For example, at least one column of switching transistors T is electrically connected to a data line DL, and the orthographic projection of at least one first line segment 1111 on the first base substrate 101 is located between the orthographic projections of two adjacent switching transistors T in the column of switching transistors T on the first base substrate 101. In other words, in the embodiments of the present disclosure, the first line segment 1111 may refer to the portion of the first common signal line 111 located between two adjacent switching transistors T along the second direction Y.

[0169] The first common signal line 111 can be shared by two adjacent transparent conductive structures D. The first line segment 1111 can be used to form two transparent conductive structures D arranged along the first direction X. For example, with reference to FIG7 and FIG8 , the right side of the first line segment 1111 is used to form the transparent conductive structure D shown in the figures, and the left side of the first line segment 1111 can be used to form the transparent conductive structure to the left of the transparent conductive structure D shown in the figures (not shown in the figures, but its structure is substantially the same as the transparent conductive structure D shown in the figures).

[0170] In an embodiment of the present disclosure, by making the distance between the first edge 1111a of the first line segment 1111 and the third edge DLa of the data line DL as small as possible, the non-overlapping capacitance between the data line DL and the first common signal line 111 can be reduced, thereby reducing the load on the signal line to reduce power consumption.

[0171] Figure 9 schematically shows a schematic diagram of an adjustment portion according to an embodiment of the present disclosure, and Figure 10 schematically shows a schematic diagram of the overlap of a pixel electrode and a first line segment according to an embodiment of the present disclosure. With reference to Figures 9 and 10 , in some specific embodiments, in the thickness direction of the display substrate, at least one first line segment 1111 overlaps with a side edge of the pixel electrode 121 close to the data line DL (for example, the left edge of the pixel electrode 121), and the overlapping portion forms an adjustment portion D1 of the transparent conductive structure D, and a dimension dd of the adjustment portion D1 in the first direction X is positively correlated with the capacitance of the storage capacitor Cst.

[0172] By making the distance between the second edge 1111b of the first line segment 1111 and the fourth edge DLb of the data line DL larger, in addition to avoiding the pixel opening area as much as possible, the resistance of the surrounding portion can be reduced when the first common signal line 111 is arranged around the switching transistor T. This is conducive to improving the voltage drop problem on the first common signal line 111, thereby improving uniformity.

[0173] Specifically, in the embodiment of the present disclosure, the data line DL and the switch transistor T electrically connected thereto are disposed adjacent to each other. For example, referring to FIG. 4 , the switch transistor T is located on the right side of the data line DL electrically connected thereto.

[0174] In the embodiment of the present disclosure, the switching transistor T and its surroundings can be set as a non-display area of ​​the sub-pixel PX (for example, this portion can be shielded by a structure such as a black matrix). Therefore, in the embodiment of the present disclosure, the portion of the first line segment 1111 located on this non-display area and its connecting area serves as the adjustment portion D1 of the transparent conductive structure D, so as to adjust the overlapping area, so that the size adjustment space of the transparent conductive structure D avoids (or involves as little as possible) the pixel opening area of ​​the sub-pixel PX as much as possible, thereby reducing the impact of the size adjustment of the transparent conductive structure D on the pixel aperture ratio.

[0175] Optionally, the adjustment portion D1 includes two ends arranged along the second direction Y and a recessed structure DO located between the two ends. The size of the recessed structure DO in the first direction X is smaller than the sizes of the two ends in the first direction X. In this way, the width of the portion of the adjustment portion D1 close to the switching transistor T can be larger, while the width of the portion away from the switching transistor T can be smaller, which is beneficial to improving the pixel aperture ratio.

[0176] In some specific embodiments, the display substrate further includes a data line DL, a first gate line GL1, and a second gate line GL2 disposed on the first base substrate 101 and electrically connected to the sub-pixel PX. The N second common signal lines 112, the first gate line GL1, and the second gate line GL2 all extend along the first direction. In other words, the switching transistor T in the embodiment of the present disclosure adopts a dual-gate design, with two gates connected to two gate lines.

[0177] In an embodiment of the present disclosure, the plurality of gate lines GL on the display substrate may be divided into a plurality of gate line groups. The plurality of gate line groups are arranged along the second direction Y. At least one gate line group is electrically connected to at least one row of sub-pixels PX, and different gate line groups are electrically connected to different rows of sub-pixels PX. Each gate line group includes two gate lines arranged along the second direction Y, namely, a first gate line GL1 and a second gate line GL2.

[0178] Figure 11 schematically shows a plan view of the gate layer according to an embodiment of the present disclosure, Figure 12 schematically shows a plan view of the active layer according to an embodiment of the present disclosure, Figure 13 schematically shows a plan view of the gate layer and the active layer according to an embodiment of the present disclosure, Figure 14 schematically shows a plan view of the source-drain electrode layer according to an embodiment of the present disclosure, and Figure 15 schematically shows a plan view of the gate layer, the active layer and the source-drain electrode layer according to an embodiment of the present disclosure.

[0179] With reference to Figures 11 to 15 , the subpixel PX includes a switching transistor T, which includes a first electrode S1, a second electrode S2, a first gate G1, and a second gate G2. The first electrode S1 is electrically connected to the data line DL, the second electrode S2 is electrically connected to the pixel electrode 121, the first gate G1 is electrically connected to the first gate line GL1, and the second gate G2 is electrically connected to the second gate line GL2. At least one second common signal line 112 overlaps with both the first gate line GL1 and the second gate line GL2 in the thickness direction of the display substrate.

[0180] In an embodiment of the present disclosure, the first gate line GL1 and the second gate line GL2 both extend along the first direction X, and the first gate line GL1 and the second gate line GL2 are parallel and insulated from each other. In this way, for the switching transistor T, the switching transistor T will only be turned on when the two gate lines GL electrically connected to it provide valid level signals at the same time.

[0181] In an embodiment of the present disclosure, at least one second common signal line 112 is disposed correspondingly to at least one gate line group, and different second common signal lines 112 are disposed correspondingly to different gate line groups. In the thickness direction of the display substrate, the second common signal line 112 overlaps with the first gate line GL1 and the second gate line GL2 in the gate line group disposed corresponding thereto. For example, referring to FIG6 , the second common signal line 112, the first gate line GL1, and the second gate line GL2 are disposed in parallel, the upper half of the second common signal line 112 overlaps with the first gate line GL1, and the lower half of the second common signal line 112 overlaps with the second gate line GL2.

[0182] In an embodiment of the present disclosure, the first gate line GL1 can be integrally formed with the first gate G1 of the switching transistor T, the second gate line GL2 can be integrally formed with the second gate G2 of the switching transistor T, and the first electrode S1 of the switching transistor T can be integrally formed with the data line DL. The first gate G1 and the second gate G2 of the switching transistor T can be arranged along the second direction Y.

[0183] In some specific embodiments, the display substrate further includes an active layer ACT located on a side of the first transparent electrode layer 110 close to the first base substrate 101. The active layer ACT may include semiconductor materials such as a-Si, LTPS, and LTPO.

[0184] The switching transistor T further includes a first channel portion A11 and a second channel portion A12 located in the active layer ACT. The orthographic projection of the first channel portion A11 on the first substrate 101 at least partially overlaps with the orthographic projection of the first gate G1 on the first substrate 101. The orthographic projection of the second channel portion A12 on the first substrate 101 at least partially overlaps with the orthographic projection of the second gate G2 on the first substrate 101. The width-to-length ratio of either the first channel portion A11 or the second channel portion A12 is less than 4.

[0185] Optionally, the ratio of the channel width of any one of the first channel portion A11 and the second channel portion A12 to the sum of the channel lengths of the first channel portion A11 and the second channel portion A12 is less than or equal to 2.

[0186] When the switching transistor T is in the off state, ideally, the off-state resistance is infinite, and no charge on the storage capacitor Cst leaks out through the switching transistor T. However, in reality, the off-state resistance of the switching transistor T cannot be infinite. According to the leakage current expression, when other parameters such as film thickness remain unchanged, the leakage current decreases as the channel length L of the switching transistor T increases. The embodiments of the present disclosure extend the channel length of the switching transistor T, thereby reducing the leakage current. Lower leakage current results in lower power consumption of the display substrate.

[0187] In some specific embodiments, the first channel portion A11 and the second channel portion A12 have substantially the same channel length. For example, the channel width of either the first channel portion A11 or the second channel portion A12 is set to 17.5 μm, and the channel length is set to 5 μm. This channel length is greater than the 4 μm channel length of a switching transistor on a conventional display substrate. The sum of the first channel portion A11 and the second channel portion A12 is much greater than the channel length of a switching transistor on a conventional display substrate, thereby significantly improving leakage current.

[0188] In the embodiment of the present disclosure, the display substrate further includes a gate layer GT, a gate insulating layer GI, a source / drain electrode layer SD, and a second insulating layer PVX2, which are sequentially arranged in a direction away from the first base substrate 101.

[0189] ACT is located between the gate insulating layer GI and the source-drain electrode layer SD. The first electrode S1 and the second electrode S2 of the switching transistor T are located in the source-drain electrode layer SD. The first gate line GL1, the second gate line GL2, and the first gate G1 and the second gate G2 of the switching transistor T are all located in the gate layer GT. This structure of the switching transistor T is also called a bottom-gate structure. It should be noted that the embodiments of the present disclosure are described using a bottom-gate structure as an example, but this does not constitute a limitation on the switching transistor T in the embodiments of the present disclosure. For example, the switching transistor T in the embodiments of the present disclosure may also adopt a top-gate structure.

[0190] In some specific embodiments, the first insulating layer PVX1 and the second insulating layer PVX2 can be etched simultaneously, thereby saving one patterning process.

[0191] In the embodiment of the present disclosure, a connection via H1 is provided on the second insulating layer PVX2 , and the pixel electrode 121 is electrically connected to the second electrode S2 of the switch transistor T through the connection via H1 .

[0192] The switching transistor T further includes a first connection portion A21, a first connection portion A22, a third connection portion A23, and a fourth connection portion A24 located in the active layer ACT, and a bridge portion S3 located in the source-drain electrode layer SD. The second channel portion A12 is located between the first connection portion A21 and the first connection portion A22, and the first channel portion A11 is located between the third connection portion A23 and the fourth connection portion A24. The first connection portion A21 is electrically connected to the first electrode S1 of the switching transistor T, the fourth connection portion A24 is electrically connected to the second electrode S2 of the switching transistor T, and the first connection portion A22 and the third connection portion A23 are electrically connected via the bridge portion S3.

[0193] In the embodiment of the present disclosure, the orthographic projection of at least one of the first gate G1 and the second gate G2 on the first base substrate 101 may include an I-shape, a U-shape, or an L-shape, which may be determined according to actual needs and is not limited here.

[0194] In the embodiment of the present disclosure, the first connection portion A21, the second channel portion A12, the first connection portion A22, the third connection portion A23, the first channel portion A11, and the fourth connection portion A24 are arranged in sequence in the second direction Y. For example, the orthographic projection of the first connection portion A21, the first channel portion A11, the first connection portion A22, the third connection portion A23, the second channel portion A12, and the fourth connection portion A24 on the first base substrate 101 may form an I-shape.

[0195] The first gate line GL1 bends in a direction away from the second gate line GL2 and is electrically connected to the first gate G1 of the switching transistor T at the bend. The second gate line GL2 bends in a direction away from the first gate line GL1 and is electrically connected to the second gate G2 of the switching transistor T at the bend. For example, referring to FIG. 7 , the first gate line GL1 bends upward and the second gate line GL2 bends downward. This helps to free up space for the bridge portion S3, thereby realizing a dual-gate design of the switching transistor T.

[0196] In some specific embodiments, power consumption can be reduced by reducing the refresh frequency of the screen. The refresh frequency can be determined according to actual needs. For example, for quasi-static display scenarios (such as electronic price tags in supermarkets and outdoor billboards, etc.), a refresh rate of 1Hz (hereinafter also referred to as low-frequency drive) can be selected. Optionally, other lower refresh rates can also be used. Compared with a refresh rate of 60Hz, a refresh rate of 1Hz consumes less power. However, the display process is divided into a data writing phase and a display phase in terms of time. The data writing phase writes the data signal, and the display phase applies a negative bias to the switching transistor T to ensure that it is not turned on during the display phase. When driven at a low frequency, the same bias will be applied to the switching transistor T for a long time, which can easily lead to problems such as threshold voltage drift of the switching transistor T. Therefore, the embodiments of the present disclosure improve this problem in the following ways.

[0197] In the embodiment of the present disclosure, the switching transistor T adopts the above-mentioned dual-gate design. Therefore, it can be equivalent to two transistors connected in series, hereinafter referred to as the first transistor M1 and the second transistor M2, respectively. The gate of the first transistor M1 is the above-mentioned first gate G1, and the gate of the second transistor M2 is the above-mentioned second gate G2.

[0198] FIG16 schematically shows one of the driving timing diagrams according to an embodiment of the present disclosure. Referring to FIG16 , in the first data writing phase t1, a valid level signal is provided to the first gate line GL1, and an invalid level signal is provided to the second gate line GL2. At this time, the first transistor M1 is turned on, and the second transistor M2 is turned off. Therefore, the switching transistor T is in the off state as a whole.

[0199] In the second data writing phase t2, an active level signal is provided to the first gate line GL1, and an active level signal is provided to the second gate line GL2. At this time, the first transistor M1 is turned on, and the second transistor M2 is also turned on. Therefore, the switching transistor T is in the on state as a whole, and the storage capacitor Cst begins to charge.

[0200] In the display phase t3, an inactive level signal is provided to the first gate line GL1, and an active level signal is provided to the second gate line GL2. At this time, the first transistor M1 is turned off, and the second transistor M2 is turned on. Therefore, the switching transistor T is in the off state as a whole, the storage capacitor Cst is fully charged, and the driving voltage is continuously provided.

[0201] Therefore, the embodiment of the present disclosure extends the time when the first transistor M1 and the second transistor M2 are applied with a forward bias, and correspondingly shortens the time when the negative bias is applied, while ensuring that the switching transistor T is cut off. This can improve the problem of threshold voltage drift caused by the transistors being applied with the same bias for a long time.

[0202] During low-frequency driving, the storage capacitor Cst is required to maintain the voltage across its terminals for a longer period of time to keep the image unchanged until the next frame arrives. Therefore, the charging time of the storage capacitor Cst will also be extended. Therefore, it is necessary to adjust the size of the storage capacitor Cst to match the charging time. In some specific embodiments, in addition to increasing the width of the first portion D1 of the transparent conductive structure D to increase the overlapping area between the transparent conductive structure D and the pixel electrode 121, thereby increasing the storage capacitor Cst, the dimensions of the transparent conductive structure D and the pixel electrode 121 in the thickness direction of the display substrate can also be reduced. For example, the thickness of the second insulating layer PVX2 provided between the transparent conductive structure D and the pixel electrode 121 can be reduced to increase the storage capacitor Cst.

[0203] Figure 17 schematically shows a schematic diagram of the electrical connection between the gate line and the scan signal terminal according to an embodiment of the present disclosure. Referring to Figure 17, in some specific embodiments, the display substrate includes a plurality of sub-pixels PX arranged in an array along the second direction Y and the first direction X. The second gate line GL2 electrically connected to the second gate G2 of the switching transistor T of the sub-pixel PX in the nth row and the first gate line GL1 electrically connected to the first gate G1 of the switching transistor T of the sub-pixel PX in the n+1th row are electrically connected to the same scan signal terminal. Wherein, n is a positive integer. In this way, the first gate line GL1 and the previous second gate line GL2 can be loaded with the same electrical signal. In this way, the effective level signals output by the two adjacent scan signal terminals can be staggered to achieve line-by-line scanning. This method can also be called De-stress. Compared with independently connecting each first gate line GL1 and second gate line GL2 to the scan signal terminal, this method can reduce the scanning frequency.

[0204] Optionally, when the duration of the valid level signal of the previous scan signal terminal reaches 1 / 2 of the expected duration, the next scan signal terminal is enabled to output a valid level signal. In other words, the duration of the first data writing phase t1 and the second data writing phase t2 can be the same.

[0205] Figure 18 schematically shows a second driving timing diagram according to an embodiment of the present disclosure. Referring to Figures 17 and 18, in the first data writing phase t1 of the sub-pixel in the nth row, the scanning signal terminal FO1 provides a valid level signal to the first gate line GL1 electrically connected thereto, and the scanning signal terminal FO2 provides an invalid level signal to the second gate line GL2 electrically connected thereto.

[0206] In the second data writing phase t2 of the n-th row sub-pixels, the scanning signal terminal FO1 provides an effective level signal to the first gate line GL1 electrically connected thereto, and the scanning signal terminal FO2 provides an effective level signal to the second gate line GL2 electrically connected thereto. Since the second gate line GL2 electrically connected to the n-th row sub-pixels and the first gate line GL1 electrically connected to the (n+1)-th row sub-pixels PX are both electrically connected to the scanning signal terminal FO2, the scanning signal terminal FO2 also provides an effective level signal to the first gate line GL1 electrically connected to the (n+1)-th row sub-pixels PX. That is, the (n+1)-th row sub-pixels PX are now in the first data writing phase t1.

[0207] During the display phase t3 of the n-th row of sub-pixels, the scan signal terminal FO1 provides an invalid level signal to the first gate line GL1 electrically connected thereto, and the scan signal terminal FO2 provides an effective level signal to the second gate line GL2 electrically connected thereto. Since the second gate line GL2 electrically connected to the n-th row of sub-pixels and the first gate line GL1 electrically connected to the (n+1)-th row of sub-pixels PX are both electrically connected to the scan signal terminal FO2, the scan signal terminal FO2 also provides an effective level signal to the first gate line GL1 electrically connected to the (n+1)-th row of sub-pixels PX, and the scan signal terminal FO3 provides an effective level signal to the second gate line GL2 electrically connected to the (n+1)-th row of sub-pixels PX. In other words, the (n+1)-th row of sub-pixels PX is now in the second data writing phase t2. And so on, thereby achieving row-by-row scanning.

[0208] Figure 19 schematically shows a plan view of the first hollow structure and the second hollow structure according to an embodiment of the present disclosure, Figure 20 schematically shows a plan view of the first hollow structure overlapping with the first grid line and the second grid line according to an embodiment of the present disclosure, and Figure 21 schematically shows a size schematic diagram of the first hollow structure overlapping with the first grid line and the second grid line according to an embodiment of the present disclosure.

[0209] 9 , 10 , and 19 to 21 , in some specific embodiments, a first hollow structure V1 is provided on at least one second common signal line 112 , and in the thickness direction of the display substrate, the first hollow structure V1 overlaps with both the first gate line GL1 and the second gate line GL2 .

[0210] In an embodiment of the present disclosure, the first hollow structure V1 extends along the second direction Y. For example, the first hollow structure V1 is arranged parallel to at least one of the second common signal line 112, the first gate line GL1, and the second gate line GL2. The first hollow structure V1 is used to reduce the amount of overlap between the second common signal line 112 and the first gate line GL1 and the second gate line GL2, thereby reducing the parasitic capacitance between the second common signal line 112 and the gate line GL. This can reduce the load on the signal line, thereby reducing power consumption.

[0211] In some specific embodiments, the overlapping dimension d5 of the first hollow structure V1 and the first gate line GL1 in the second direction Y and the overlapping dimension d6 of the first hollow structure V1 and the second gate line GL2 in the second direction Y are both smaller than the dimension d3 of the data line DL in the first direction X (also referred to as the width of the data line DL in the disclosed embodiment). For example, the overlapping dimension d5 of the first hollow structure V1 and the first gate line GL1 in the second direction Y and the overlapping dimension d6 of the first hollow structure V1 and the second gate line GL2 in the second direction Y are the same, and the width of the first gate line GL1 is the same as the dimension of the second gate line GL2 in the second direction Y. In this way, the width of the first hollow structure V1 satisfies the minimum wrapping value of its overlap with the first gate line GL1 and the second gate line GL2, and the wrapping value may refer to: a range of values ​​set to ensure that the first hollow structure V1 and the first gate line GL1 and the second gate line GL2 are not affected by process fluctuations (for example, process fluctuations cause some places to overlap and some places not to overlap).

[0212] In some specific embodiments, the orthographic projection of the first hollow structure V1 on the first base substrate 101 includes a strip structure extending along the second direction Y, and the dimension d4 of the first hollow structure V1 in the second direction Y (also referred to as the width of the first hollow structure V1 in the embodiments of the present disclosure) is greater than or equal to the dimension d3 of the data line DL in the first direction X. For example, the dimension d4 of the first hollow structure V1 in the second direction Y is set to 6 μm. The dimension d3 of the data line DL in the first direction X can be set to 6 μm. In this way, the width of the first hollow structure V1 simultaneously meets the requirements of exposure accuracy, the minimum wrapping value overlapping with the first gate line GL1 and the second gate line GL2, and the first hollow structure V1 is not too wide to cause the first sub-line 112a and the second sub-line 112b to be too thin, thereby avoiding the problem of excessive resistance of the first sub-line 112a and the second sub-line 112b caused by this.

[0213] For example, referring to FIG. 21 , the upper edge of the first hollow structure V1 overlaps with the first gate line GL1 , and the lower edge of the first hollow structure V1 overlaps with the second gate line GL2 .

[0214] In some specific embodiments, the at least one second common signal line 112 includes a first sub-line 112a and a second sub-line 112b arranged along the second direction Y. The first hollow structure V1 separates the first sub-line 112a from the second sub-line 112b. In the thickness direction of the display substrate, the first sub-line 112a of the at least one second common signal line 112 at least partially overlaps with the first gate line GL1, and the second sub-line 112b at least partially overlaps with the second gate line GL2.

[0215] For example, the upper edge of the first sub-line 112a is located above the upper edge of the first gate line GL1, and the lower edge of the first sub-line 112a is located above the lower edge of the first gate line GL1. The non-overlapping area between the two is also the area where the first void structure V1 is located.

[0216] For example, the upper edge of the second sub-line 112b is below the upper edge of the second gate line GL2, and the lower edge of the first sub-line 112a is below the lower edge of the second gate line GL2. The non-overlapping area between the two is also the area where the first void structure V1 is located.

[0217] In some embodiments, the light transmittance of the first transparent electrode layer 110 is substantially the same as the light transmittance of the second transparent electrode layer 120. For example, both are made of indium tin oxide, and both have a light transmittance of approximately 90%.

[0218] 20 , in some specific embodiments, the display substrate includes a plurality of sub-pixels PX. In the thickness direction of the display substrate, the first gate line GL1 and the second gate line GL2 electrically connected to the same sub-pixel PX respectively overlap with the pixel electrodes 121 of two adjacent sub-pixels PX arranged along the second direction Y.

[0219] For example, for the first gate line GL1 and the second gate line GL2 connected to the x-th subpixel PX, in the thickness direction of the display substrate, the pixel electrode 121 of the x-th subpixel PX overlaps with the first gate line GL1, and the orthographic projection of the overlapping portion on the first base substrate 101 defines a first region. The pixel electrode 121 of the x+1-th subpixel PX overlaps with the second gate line GL2, and the orthographic projection of the overlapping portion on the first base substrate 101 defines a second region. The orthographic projection of the first subline 112a of at least one second common signal line 112 on the first base substrate 101 at least partially overlaps with the first region, and the orthographic projection of the second subline 112b on the first base substrate 101 at least partially overlaps with the second region. Where x is a positive integer. In this way, the first subline 112a can be located in the overlapping region between the first gate line GL1 and the pixel electrode 121 to at least partially shield the parasitic capacitance between the first gate line GL1 and the pixel electrode 121. The second sub-line 112 b is located in the overlapping region of the second gate line GL2 and the pixel electrode 121 to at least partially shield the parasitic capacitance between the second gate line G1 and the pixel electrode 121 .

[0220] In some specific embodiments, the orthographic projection of the first sub-line 112a of the at least one second common signal line 112 on the first base substrate 101 covers the first area, and the orthographic projection of the second sub-line 112b on the first base substrate 101 covers the second area. In this way, the first sub-line 112 can cover the overlapping area between the first gate line GL1 and the pixel electrode 121, thereby shielding the parasitic capacitance between the first gate line G1 and the pixel electrode 121 to a greater extent. The second sub-line 112b can cover the overlapping area between the second gate line GL2 and the pixel electrode 121, thereby shielding the parasitic capacitance between the second gate line G1 and the pixel electrode 121 to a greater extent.

[0221] Exemplarily, referring to Figure 20, for the first gate line GL1 and the second gate line GL2 electrically connected to the x-th sub-pixel PX, the upper edge of the first gate line GL1 is located between the upper edge of the first sub-line 112a and the lower edge of the pixel electrode 121 of the x-th sub-pixel PX, and the lower edge of the first gate line GL1 is located on the side of the lower edge of the first sub-line 112a away from the lower edge of the pixel electrode 121 of the x-th sub-pixel PX; the upper edge of the second gate line GL2 is located on the side of the upper edge of the second sub-line 112b away from the pixel electrode 121 of the x+1-th sub-pixel PX (or close to the pixel electrode 121 of the x-th sub-pixel PX), and the lower edge of the second gate line GL2 is located between the lower edge of the second sub-line 112b and the upper edge of the pixel electrode 121 of the x+1-th sub-pixel PX.

[0222] 21 , in some specific embodiments, the first sub-line 112 a and the second sub-line 112 b are electrically connected via a connecting bridge B located at at least one end of the first hollow structure V1. A dimension d7 of the connecting bridge B in the second direction Y is greater than or equal to a dimension d3 of the data line DL in the first direction X. For example, the dimension d7 of the connecting bridge B in the second direction Y can be set to 6 μm to 10 μm, for example, 6 μm, and the dimension d3 of the data line DL in the first direction X can be set to 6 μm to 10 μm, for example, 6 μm.

[0223] Optionally, the dimensions of the connecting bridge B in the second direction Y and the first direction X may be the same.

[0224] Therefore, the connecting bridge B can not only meet the minimum line width exposure requirements, but also maintain a certain width to appropriately reduce the resistance. At the same time, the area of ​​the connecting bridge B is moderate, and the overlapping area between it and the first gate line GL1 and the second gate line GL2 is not too large, avoiding the problem of increased signal line load.

[0225] In some specific embodiments, the connecting bridge B does not overlap with the data line DL, and the distance between the connecting bridge B and the data line DL in the first direction X is smaller than the width of the data line DL. The distance between the connecting bridge B and the data line DL in the second direction Y is set to 2.3 μm to 3 μm. In this way, the connecting bridge B can avoid the data line DL, thereby preventing the connection bridge B from overlapping with the data line DL and increasing the load on the data line DL.

[0226] By adopting at least one of the above-mentioned size designs, on the basis of satisfying the composition accuracy limitation (for example, the line width of the routing (or opening) is at least not less than the minimum exposure accuracy), the capacitance between the first common signal line 111 (or the second common signal line 121) and other routing lines is reduced as much as possible, thereby maximizing the reduction of routing load, which is beneficial to reducing display power consumption.

[0227] Furthermore, through at least one of the aforementioned dimension designs, the first common signal line 111 and the second common signal line 121 can meet the expected dimension wrapping relationship with other lines, thereby preventing differences in the overlapping relationship between the lines due to process fluctuations, which in turn causes differences in capacitance between the lines and affects display uniformity. For example, a portion of the data line DL (or gate line GL) that should have been covered by the first common signal line 111 (or second common signal line 121) may be exposed after the patterning process due to the reserved spacing being too small.

[0228] Optionally, the two connecting bridges B located at the left and right ends of the first void structure V1 have the same size in the second direction Y, but their sizes in the first direction X can be the same or different, which can be determined according to actual needs and is not limited here.

[0229] In some specific embodiments, a second hollow structure V2 is provided on at least one second common signal line 112, and the orthographic projection of the switching transistor T on the first base substrate 101 is located within the orthographic projection of the second hollow structure on the first base substrate 101. In the embodiment of the present disclosure, the second hollow structure V2 specifically exposes the first channel portion and the second channel portion of the switching transistor T, thereby preventing the electrical signal on the second common signal line 112 from pulling the first channel portion and the second channel portion, thereby affecting the characteristics of the switching transistor T.

[0230] In some specific embodiments, in order to reduce the load while maximizing the pixel aperture ratio, methods such as reducing the trace width, reducing the area of ​​the pixel aperture region occupied by the switch transistor T, and reducing the trace spacing may be adopted.

[0231] The inventors discovered during their research that, during variable frequency driving, it is necessary to design larger pixel electrodes to form larger storage capacitors to prevent leakage problems during low-frequency driving. However, at the same time, the larger pixel electrodes will form additional parasitic capacitances with the gate lines GL. During high-frequency driving, the additional parasitic capacitances formed between the pixel electrodes and the gate lines GL may cause the sub-pixels to be unable to reach the optimal flip voltage of the liquid crystal. Specifically, the charging time is closely related to the driving frequency and resolution. When the resolution is constant, the charging time is inversely proportional to the driving frequency. When the driving frequency is high, the charging time is short, and display anomalies caused by insufficient charging may occur; when the driving frequency is low, the charging time is long, the leakage time is also long, and related defects such as leakage current may also occur.

[0232] In view of this, the embodiments of the present disclosure improve the switching transistor T of the sub-pixel to reduce its leakage current, thereby improving the leakage problem during low-frequency driving. The switching transistor T in the embodiment of the present disclosure still adopts a dual-gate design, but unlike the previous embodiment, the two gates are arranged along the extension direction of the gate line and are electrically connected to the same gate line.

[0233] Specifically, under ideal conditions, when the switching transistor T is in the off state, no charge on the pixel storage capacitor Cst leaks out through the switching transistor T, that is, there is no leakage current. However, in reality, there will always be some leakage current, and when the leakage current is large, the pixel voltage cannot be maintained. Especially when driven at low frequencies, the leakage time is long and the leakage current situation will be aggravated. According to the leakage current expression, when other parameters such as film thickness remain unchanged, the leakage current decreases as the channel length L increases. Therefore, in order to reduce leakage current, the embodiment of the present disclosure selects a switching transistor T with a longer channel.

[0234] FIG22 schematically illustrates a plan view of a single gate line driving switching transistor in an embodiment of the present disclosure. Referring to FIG22 , in some specific embodiments, the display substrate further includes a data line DL and a third gate line GL3 disposed on a first base substrate 101 and electrically connected to a subpixel PX. N second common signal lines 112 and the third gate line GL3 each extend along a first direction X. The subpixel PX includes a switching transistor T. The switching transistor T includes a first electrode S1, a second electrode S2, a first gate G1, and a second gate G2. The first gate G1 and the second gate G2 are arranged along the first direction X. The first electrode S1 is electrically connected to the data line DL, the second electrode S2 is electrically connected to the pixel electrode 121, and the first gate G1 and the second gate G2 are both electrically connected to the third gate line GL3. At least one second common signal line 112 overlaps with the third gate line GL3 in the thickness direction of the display substrate.

[0235] In other words, in the embodiment of the present disclosure, the switching transistor T adopts a dual-gate design, and the two gates of the switching transistor T are arranged along the extension direction of the third gate line GL3, and the two gates are connected to the same third gate line G3. In this way, the switching transistor T is equivalent to two transistors M1 and M2 connected in series, with a longer equivalent channel length, which can alleviate the problem of large leakage current during low-frequency driving.

[0236] Specifically, the leakage current I of the switching transistor T ds It can be calculated by the following formula.

[0237] Where W is the channel width of the switching transistor T, L is the channel length of the switching transistor T, C is a constant, V ds is the source-drain voltage of the switching transistor T, V th is the threshold voltage of the switching transistor T.

[0238] Different from the switching transistor T driven by dual gate lines, the switching transistor T driven by single gate line has fewer gate lines, which can reduce the impact on the pixel aperture ratio.

[0239] Figure 23 schematically shows a cross-sectional view of the switching transistor in the embodiment of the present disclosure and a cross-sectional view of a single-gate transistor having the same channel length as the switching transistor in the embodiment of the present disclosure. Referring to Figure 23, the lower figure is a schematic diagram of the switching transistor T in the embodiment of the present disclosure, and the upper figure is a single-gate transistor having the same channel length as the switching transistor T in the embodiment of the present disclosure.

[0240] Referring to the lower figure in Figure 23, when the voltage Vg on the third gate line is applied to the two gates of the switching transistor T, the gate voltages on the two gates of the switching transistor T are not exactly the same. Let the voltage at the midpoint of the two gates be Vm, then the voltage V2 on the second electrode S2 = Vg, and the voltage V1 on the second electrode S1 = Vg-Vm < V2. Since the transistors M1 and M2 are in series, the leakage current Ids1 of the transistor M1 and the leakage current Ids2 of the transistor M2 satisfy: Ids1 = Ids2, the source-drain voltage Vds1 of the transistor M1 and the source-drain voltage Vds2 of the transistor M2 satisfy: Vds1 < Vds2 = 1 / 2Vds, and the leakage current Ids1 of the switching transistor T dual =Ids1.

[0241] Referring to the upper figure in FIG23 , for a single-gate transistor having the same channel length as the switch transistor T in the disclosed embodiment, the single-gate transistor includes an active layer ACT′, a first electrode S1′, and a second electrode S2′. The gate voltage of the right half of the single-gate transistor is equal to Vg, the source-drain voltage is approximately equal to 1 / 2 Vds, and the leakage current of the single-gate transistor is I single Obviously, I dual <I single , that is, the leakage current of the dual-gate switch transistor T in the embodiment of the present disclosure is smaller.

[0242] FIG24 is a schematic diagram along section line FF′ of FIG22 . Referring to FIG22 and FIG24 together, in some specific embodiments, the pixel electrode 121 and the third gate line GL3 overlap in the thickness direction of the display substrate, and the orthographic projection of the overlapping portion on the first base substrate 101 defines a third region. The orthographic projection of at least one second common signal line 112 on the first base substrate 101 at least partially overlaps with the third region. In this way, the second common signal line 112 can be located in the overlapping region between the third gate line GL3 and the pixel electrode 121 to at least partially shield the parasitic capacitance between the third gate line GL3 and the pixel electrode 121.

[0243] In some specific embodiments, the orthographic projection of at least one second common signal line 112 on the first base substrate 101 covers the third area. In this way, the second common signal line 112 can cover the overlapping area of ​​the third gate line GL3 and the pixel electrode 121, thereby shielding the parasitic capacitance between the third gate line GL3 and the pixel electrode 121 to a greater extent.

[0244] It should be noted that the second common signal line 112 of the disclosed embodiment extends into the overlapping region between the third gate line GL and the pixel electrode 121 and is located between the third gate line GL and the pixel electrode 121 in the thickness direction of the display substrate. Thus, the extent to which the second common signal line 112 extends allows for adjustability of the storage capacitor Cst and the parasitic capacitance, thereby enabling variable frequency drive within different ranges. For example, if the area of ​​the sub-pixel PX is 201*201um, the area of ​​the pixel electrode 121 can be 197*197um. In this case, the size of the projected area of ​​the second common signal line 112 on the pixel electrode 121 in the second direction Y can be set to 11um. In this case, drive with an upper frequency limit of 60Hz can be achieved. To achieve variable frequency drive with a higher upper frequency limit, it is sufficient to increase the size of the projected area of ​​the second common signal line 112 on the pixel electrode 121 in the second direction Y. Furthermore, since the second common signal line 112 is a transparent signal line, it does not affect the pixel aperture ratio.

[0245] Optionally, the display substrate of the embodiment of the present disclosure can support variable frequency driving with a variable frequency range of 15 to 60 Hz. However, the embodiment of the present disclosure can also meet the requirements of other variable frequency ranges by adopting different overlapping areas of the second common signal line 112, the third gate line GL and the pixel electrode 121.

[0246] Compared with the traditional solution, the embodiment of the present disclosure can simultaneously achieve a larger storage capacitor Cst and a smaller parasitic capacitance between the gate line and the pixel electrode, and the size of the storage capacitor Cst and the parasitic capacitance are adjustable, thereby being able to adapt to the needs of various driving frequencies to achieve variable frequency driving.

[0247] It should be noted that for details not described in the embodiments of the present disclosure, reference can be made to the aforementioned embodiments (such as the second hollow structure, etc.), and therefore, they will not be repeated here.

[0248] At least some embodiments of the present disclosure further provide a display panel. FIG25 schematically illustrates a display panel according to an embodiment of the present disclosure. Referring to FIG25 , the display panel includes the display substrate described above, having a display area AA and a peripheral area NA, and related structures therein. For example, the display panel may be a liquid crystal display panel.

[0249] In some specific embodiments, the display panel includes a twisted nematic (TN) liquid crystal display panel. FIG26 schematically illustrates a twisted nematic liquid crystal display panel according to an embodiment of the present disclosure. Referring to FIG26 , in this embodiment, the display panel further includes a color filter substrate 200. The display substrate 100 and the color filter substrate 200 are disposed opposite each other, and the display panel further includes a liquid crystal layer LC located between the display substrate and the color filter substrate 200.

[0250] FIG27 schematically illustrates a color filter substrate according to an embodiment of the present disclosure. Referring to FIG27 , the color filter substrate 200 includes a second base substrate 201 and a common electrode VCOM disposed on the second base substrate 201. The common electrode VCOM is electrically connected to the first common signal line 111 and the second common signal line 112 in the display substrate 100. The liquid crystal layer LC includes a plurality of liquid crystal molecules. The common electrode VCOM and the pixel electrodes 121 on the display substrate 100 are configured to generate an electric field that drives the liquid crystal molecules to rotate in response to a drive signal. After light passes through the liquid crystal layer LC, it enters the color resist layer E. Based on the wavelength-selective transmittance of the color resist in the color resist layer E, the corresponding color is displayed.

[0251] In some specific embodiments, the color filter substrate 200 further includes a spacer PS disposed on a side of the common electrode VCOM away from the second base substrate 201 . The spacer PS is used to play a supporting role to maintain the cell thickness of the liquid crystal layer LC.

[0252] In some specific embodiments, the ratio of the cell thickness of the liquid crystal layer LC to the distance between the first transparent electrode layer 110 and the second transparent electrode layer 120 is greater than or equal to 20:1.

[0253] In the embodiments of the present disclosure, the cell thickness of the liquid crystal layer LC is much greater than the distance between the first transparent electrode layer 110 and the second transparent electrode layer 120. For example, the cell thickness of the liquid crystal layer LC can be in the micrometer range, for example, the cell thickness of the liquid crystal layer LC can be 4 μm. The distance between the first transparent electrode layer 110 and the second transparent electrode layer 120 can be in the nanometer range, for example, the cell thickness of the liquid crystal layer LC can be set to 200 nm. Therefore, compared to the storage capacitance between the pixel electrode 121 and the transparent conductive structure D, the capacitance formed between the common electrode VCOM and the pixel electrode 121 (the difference between the two capacitances can be as much as 20 times) is negligible.

[0254] In some specific embodiments, the display substrate 100 and the color film substrate 200 are bonded by a sealant located in the peripheral area. The sealant includes a first conductive structure. The plurality of first common signal lines 111 and the plurality of second common signal lines 112 are electrically connected to the common electrode through the first conductive structure.

[0255] For example, the first common signal lines 111 and the second common signal lines 112 may intersect with each other to form a mesh structure. The mesh structure of the first common signal lines 111 and the second common signal lines 112 may extend to the peripheral area of ​​the display panel and be electrically connected to the common electrode on the color filter substrate 200 through the conductive structure in the sealant, thereby providing a common voltage signal to the common electrode on the color filter substrate 200. For example, the conductive structure in the sealant may include a spherical metal structure.

[0256] In other specific embodiments, the display panel may also be a display substrate in any one of an in-plane switching (IPS) type liquid crystal display panel, a fringe field switching (FFS) type liquid crystal display panel, an advanced super dimension switch (ADS) type liquid crystal display panel, and a high advanced super dimension switch (HADS) type liquid crystal display panel.

[0257] At least some embodiments of the present disclosure further provide a display device, which may include any device or product having a display function. For example, the display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0258] In an embodiment of the present disclosure, the display device includes a reflective display device. Figure 28 schematically shows a schematic diagram of a display device according to an embodiment of the present disclosure. Referring to Figure 28, the reflective display device in this embodiment includes a first polarizer PVA1, a display panel PAN, a selective wavelength transmission film APF, and a second polarizer PVA2, wherein the display panel PAN is the display panel in the aforementioned embodiment.

[0259] The first polarizer PVA1 has a first transmission axis and is configured to generate first polarized light with a polarization direction parallel to the first transmission axis. The second polarizer PVA2 has a second transmission axis and is configured to generate second polarized light with a polarization direction parallel to the second transmission axis. The selective wavelength transmission film (APF) is configured to reflect the first polarized light and transmit the second polarized light.

[0260] Exemplarily, the first polarizer PVA1 is located on the light-emitting side of the display panel PAN, the second polarizer PVA2 is located on the back side of the display panel PAN, and the second light transmission axis is perpendicular to the first light transmission axis.

[0261] Figure 29 schematically shows a schematic diagram of a display device in a bright state according to an embodiment of the present disclosure. Referring to Figure 29, the ambient light is linearly polarized after passing through the first polarizer PVA1, and is still linearly polarized after passing through the unpowered display panel PAN, and then enters the selective wavelength transmission film APF. At this time, the polarization direction of the linear polarization light is parallel to the transmission direction of the selective wavelength transmission film APF. The linear polarization light passes through the selective wavelength transmission film APF and enters the second polarizer PVA2, and is absorbed by the second polarizer PVA2. The light cannot return, and at this time, the display device is in a dark state.

[0262] Figure 30 schematically shows a schematic diagram of the display device in a dark state according to an embodiment of the present disclosure. Referring to Figure 30, when the display panel PAN is powered on, the ambient light is linearly polarized after passing through the first polarizer PVA1. After passing through the powered display panel PAN, the polarization direction is rotated 90°, and then enters the selective wavelength transmission film APF. Since the selective wavelength transmission film APF has a reflective characteristic for polarized light in this polarization direction, the light is reflected by the selective wavelength transmission film APF (without entering the second polarizer PVA2) back to the display panel PAN. When the light is emitted from the display panel PAN, the polarization direction is rotated 90° again, so that it can be emitted through the first polarizer PVA1. At this time, the display device is in a bright state.

[0263] In some specific embodiments, the display device further includes a light absorbing layer XL disposed on a side of the selective wavelength transmission film APF facing away from the display panel PAN. The light absorbing layer XL is configured to absorb the second polarized light transmitted by the selective wavelength transmission film APF. Optionally, the light absorbing layer XL may include a light-absorbing material such as black ink, thereby preventing light from passing through the light absorbing layer XL.

[0264] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate and display panel PAN. For details, please refer to the above description and will not be repeated here.

[0265] At least some embodiments of the present disclosure also provide a method for driving a display substrate, wherein the display substrate includes: a first base substrate 101; a first transparent electrode layer 110 disposed on the first base substrate 101; a second transparent electrode layer 120 disposed on a side of the first transparent electrode layer 110 facing away from the first base substrate 101; a plurality of first common signal lines 111 and a plurality of second common signal lines 112 disposed in the first transparent electrode layer 110, wherein the plurality of first common signal lines 111 are arranged along a second direction Y, and the plurality of second common signal lines 112 are arranged along a first direction X, with the second direction Y intersecting the first direction X, and the plurality of first common signal lines 111 are electrically connected via the plurality of second common signal lines 112; and a sub-pixel PX disposed on the first base substrate 101. The sub-pixel PX includes a pixel electrode 121 disposed in the second transparent electrode layer 120, and the plurality of first common signal lines 111 and the plurality of second common signal lines 112 form a transparent conductive structure D. Furthermore, in the thickness direction of the display substrate, the pixel electrode 121 overlaps with the transparent conductive structure D, and in the overlapping region, the pixel electrode 121 and the transparent conductive structure D are configured to form a storage capacitor Cst for the subpixel PX. The display substrate further includes a data line DL, a first gate line GL1, and a second gate line GL2. The subpixel PX includes a switching transistor T. The switching transistor T includes a first electrode S1, a second electrode S2, a first gate G1, and a second gate G2. The first electrode S1 is electrically connected to the data line DL, the second electrode S2 is electrically connected to the pixel electrode 121, the first gate G1 is electrically connected to the first gate line GL1, and the second gate G2 is electrically connected to the second gate line GL2. The display substrate includes a plurality of subpixels PX arranged in an array along the second direction Y and the first direction X. The second gate line GL2 electrically connected to the second gate G2 of the switching transistor T of the subpixel PX in the nth row and the first gate line GL1 electrically connected to the first gate G1 of the switching transistor T in the subpixel PX in the (n+1)th row are electrically connected to the same scan signal terminal. Where n is a positive integer.

[0266] 16 to 18 , the driving method in the embodiment of the present disclosure includes:

[0267] In the first data writing phase t1 of the nth row subpixels PX, a valid level signal is provided to the first gate line GL1 electrically connected to the nth row subpixels PX, and an invalid level signal is provided to the second gate line GL2 electrically connected to the nth row subpixels PX.

[0268] In the second data writing phase t2 of the nth row sub-pixels PX, an active level signal is provided to the first gate line GL1 electrically connected to the nth row sub-pixels, and an active level signal is provided to the second gate line GL2 electrically connected to the nth row sub-pixels.

[0269] In the display phase of the nth row of sub-pixels PX, an inactive level signal is supplied to the first gate line GL1 electrically connected to the nth row of sub-pixels, and an active level signal is supplied to the second gate line GL2 electrically connected to the nth row of sub-pixels.

[0270] For example, in the first data writing phase t1 of the nth row of sub-pixels, the scanning signal terminal FO1 provides an active level signal to the first gate line GL1 electrically connected thereto, and the scanning signal terminal FO2 provides an inactive level signal to the second gate line GL2 electrically connected thereto.

[0271] In the second data writing phase t2 of the n-th row sub-pixels, the scanning signal terminal FO1 provides an effective level signal to the first gate line GL1 electrically connected thereto, and the scanning signal terminal FO2 provides an effective level signal to the second gate line GL2 electrically connected thereto. Since the second gate line GL2 electrically connected to the n-th row sub-pixels and the first gate line GL1 electrically connected to the (n+1)-th row sub-pixels PX are both electrically connected to the scanning signal terminal FO2, the scanning signal terminal FO2 also provides an effective level signal to the first gate line GL1 electrically connected to the (n+1)-th row sub-pixels PX. That is, the (n+1)-th row sub-pixels PX are now in the first data writing phase t1.

[0272] During the display phase t3 of the n-th row of sub-pixels, the scan signal terminal FO1 provides an invalid level signal to the first gate line GL1 electrically connected thereto, and the scan signal terminal FO2 provides an effective level signal to the second gate line GL2 electrically connected thereto. Since the second gate line GL2 electrically connected to the n-th row of sub-pixels and the first gate line GL1 electrically connected to the (n+1)-th row of sub-pixels PX are both electrically connected to the scan signal terminal FO2, the scan signal terminal FO2 also provides an effective level signal to the first gate line GL1 electrically connected to the (n+1)-th row of sub-pixels PX, and the scan signal terminal FO3 provides an effective level signal to the second gate line GL2 electrically connected to the (n+1)-th row of sub-pixels PX. In other words, the (n+1)-th row of sub-pixels PX is now in the second data writing phase t2. And so on, thereby achieving row-by-row scanning.

[0273] It should be noted that for any incomplete description in the embodiments of the present disclosure, reference can be made to the aforementioned embodiments, and thus no further details will be given here.

[0274] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: include: a first substrate base plate; A first transparent electrode layer is provided on the first substrate; A second transparent electrode layer is disposed on a side of the first transparent electrode layer away from the first substrate; M first common signal lines and N second common signal lines are arranged in the first transparent electrode layer, the M first common signal lines are arranged along a first direction, the N second common signal lines are arranged along a second direction, the first direction and the second direction intersect, and the M first common signal lines are electrically connected through the N second common signal lines; and, A sub-pixel is arranged on the first substrate; Wherein, the sub-pixel includes a pixel electrode located in the second transparent electrode layer, and the M first common signal lines and the N second common signal lines form a transparent conductive structure; and, In the thickness direction of the display substrate, the pixel electrode and the transparent conductive structure overlap, and in the overlapping area, the pixel electrode and the transparent conductive structure are configured to form a storage capacitor of the sub-pixel; Both M and N are positive integers.

2. The display substrate according to claim 1, wherein: The pixel electrode includes a middle portion and an edge portion surrounding the middle portion, and in a thickness direction of the display substrate, the edge portion overlaps with the transparent conductive structure.

3. The display substrate according to claim 2, wherein: The portion of the edge portion that overlaps with the transparent conductive structure forms a first electrode plate of the storage capacitor, and the transparent conductive structure forms a second electrode plate of the storage capacitor. In the same sub-pixel, the portion of the edge portion that overlaps with the transparent conductive structure has an orthographic projection on the first substrate that includes a continuous annular structure.

4. The display substrate according to claim 1, wherein: The display substrate comprises a data line disposed on the first base substrate and electrically connected to the sub-pixel, the data line extending along the second direction, and at least one of the first common signal lines comprises at least one first line segment; In the thickness direction of the display substrate, the data line intersects with the at least one first line segment. overlap, and in the overlapping area, the orthographic projection of the data line on the first substrate is located within the orthographic projection of the first line segment on the first substrate; At least one of the first line segments includes a first edge and a second edge arranged in sequence along a first direction, and the data line includes a third edge and a fourth edge arranged in sequence along the first direction, and in an overlapping area between the data line and at least one of the first line segments, a spacing between the first edge of the first line segment and the third edge of the data line is smaller than a spacing between the second edge of the first line segment and the fourth edge of the data line.

5. The display substrate according to claim 4, wherein: The display substrate comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a switch transistor, and the plurality of switch transistors are arranged in an array along the first direction and the second direction; An orthographic projection of at least one of the first line segments on the first substrate is located between orthographic projections of two adjacent switch transistors along the second direction on the first substrate.

6. The display substrate according to claim 4, wherein: In the thickness direction of the display substrate, at least one of the first line segments overlaps with an edge of the pixel electrode close to the data line, and the overlapping portion forms an adjustment part of the transparent conductive structure, and the size of the adjustment part in the first direction is positively correlated with the capacitance of the storage capacitor.

7. The display substrate according to claim 1, wherein: The display substrate further comprises a data line, a first gate line and a second gate line which are arranged on the first base substrate and are electrically connected to the sub-pixel, the N second common signal lines, the first gate line and the second gate line all extend along the first direction, and the sub-pixel comprises a switch transistor; The switch transistor comprises a first electrode, a second electrode, a first gate electrode and a second gate electrode; the first electrode is electrically connected to the data line, the second electrode is electrically connected to the pixel electrode, the first gate electrode is electrically connected to the first gate line, and the second gate electrode is electrically connected to the second gate line; In the thickness direction of the display substrate, at least one of the second common signal lines overlaps with both the first gate line and the second gate line.

8. The display substrate according to claim 1, wherein: The display substrate further comprises a data line and a third gate line disposed on the first base substrate and electrically connected to the sub-pixel, the N second common signal lines and the third gate line all extend along the first direction, and the sub-pixel comprises a switch transistor; The switch transistor comprises a first electrode, a second electrode, a first gate and a second gate, the first gate and the second gate are arranged along the first direction; the first electrode is electrically connected to the data line, the second electrode is electrically connected to the pixel electrode, and the first gate and the second gate are both electrically connected to the third gate line; In the thickness direction of the display substrate, at least one of the second common signal lines overlaps with the third gate line.

9. The display substrate according to claim 7 or 8, wherein: The display substrate further includes an active layer located on a side of the first transparent electrode layer close to the first base substrate, the switch transistor further includes a first channel portion and a second channel portion located in the active layer, an orthographic projection of the first channel portion on the first base substrate at least partially overlaps with an orthographic projection of the first gate on the first base substrate, and an orthographic projection of the second channel portion on the first base substrate at least partially overlaps with an orthographic projection of the second gate on the first base substrate; A width-to-length ratio of any one of the first channel portion and the second channel portion is less than or equal to 4.

10. The display substrate according to claim 7 or 8, wherein: The first channel portion and the second channel portion have substantially the same channel length.

11. The display substrate according to claim 7, wherein: A first hollow structure is disposed on at least one of the second common signal lines, and in the thickness direction of the display substrate, the first hollow structure overlaps with both the first gate line and the second gate line.

12. The display substrate according to claim 11, wherein: An overlapping dimension between the first hollow structure and the first gate line in the second direction and an overlapping dimension between the first hollow structure and the second gate line in the second direction are both smaller than a dimension of the data line in the first direction.

13. The display substrate according to claim 11, wherein: The orthographic projection of the first hollow structure on the first substrate includes a strip structure extending along the first direction, and a size of the first hollow structure in the second direction is greater than or equal to a size of the data line in the first direction.

14. The display substrate according to claim 11, wherein: At least one of the second common signal lines includes a first sub-line and a second sub-line arranged along a second direction, and the first hollow structure separates the first sub-line from the second sub-line; In the thickness direction of the display substrate, the first sub-line of at least one second common signal line at least partially overlaps with the first gate line, and the second sub-line at least partially overlaps with the second gate line.

15. The display substrate according to claim 14, wherein: The display substrate comprises a plurality of sub-pixels, and in the thickness direction of the display substrate, the first gate line and the second gate line electrically connected to the same sub-pixel overlap with the pixel electrodes of two sub-pixels adjacently arranged along the second direction respectively; Wherein, for the first gate line and the second gate line connected to the x-th sub-pixel, in the thickness direction of the display substrate, the pixel electrode of the x-th sub-pixel overlaps with the first gate line, and the orthographic projection of the overlapping portion on the first substrate defines a first area, and the pixel electrode of the x+1-th sub-pixel overlaps with the second gate line, and the orthographic projection of the overlapping portion on the first substrate defines a second area; The orthographic projection of the first sub-line of at least one of the second common signal lines on the first substrate at least partially overlaps with the first region, and the orthographic projection of the second sub-line on the first substrate at least partially overlaps with the second region; Wherein, x is a positive integer.

16. The display substrate according to claim 15, wherein: The orthographic projection of the first sub-line of at least one of the second common signal lines on the first substrate covers the first area, and the orthographic projection of the second sub-line on the first substrate covers the second area.

17. The display substrate according to claim 14, wherein: The first sub-line and the second sub-line are electrically connected via a connecting bridge located at at least one end of the first hollow structure, and a size of the connecting bridge in the first direction is greater than or equal to a size of the data line in the first direction.

18. The display substrate according to claim 17, wherein: The connection bridge does not overlap with the data line, and a distance between the connection bridge and the data line in the first direction is smaller than a width of the data line.

19. The display substrate according to claim 8, wherein: In the thickness direction of the display substrate, the pixel electrode and the third gate line overlap, and the orthographic projection of the overlapping portion on the first substrate defines a third area, and the orthographic projection of at least one of the second common signal lines on the first substrate at least partially overlaps with the third area.

20. The display substrate according to claim 19, wherein: An orthographic projection of at least one of the second common signal lines on the first substrate covers the third area.

21. The display substrate according to claim 7 or 8, wherein: A second hollow structure is disposed on at least one of the second common signal lines, and the orthographic projection of the switch transistor on the first substrate is located within the orthographic projection of the second hollow on the first substrate.

22. The display substrate according to claim 7 or 8, wherein: The display substrate comprises a plurality of sub-pixels arranged in an array along the first direction and the second direction; A second gate line electrically connected to the second gates of the switch transistors of the sub-pixels in the nth row and a first gate line electrically connected to the first gates of the switch transistors of the sub-pixels in the (n+1)th row are electrically connected to the same scan signal terminal; Wherein, n is a positive integer.

23. A display panel, wherein: A display substrate comprising a color film substrate and any one of claims 1 to 22; The display panel further includes: Color film substrate, the display substrate and the color film substrate are arranged relative to each other: A liquid crystal layer located between the display substrate and the color filter substrate; Wherein, the color filter substrate comprises a second base substrate and a common electrode arranged on the second base substrate; The common electrode is electrically connected to the first common signal line and the second common signal line in the display substrate; the liquid crystal layer includes a plurality of liquid crystal molecules, the common electrode and the display substrate The pixel electrode is configured to form an electric field that drives the liquid crystal molecules to rotate in response to a driving signal.

24. The display panel according to claim 23, wherein: The ratio of the cell thickness of the liquid crystal layer to the distance between the first transparent electrode layer and the second transparent electrode layer is greater than or equal to 20 ∶ 1.

25. A reflective display device, wherein: The display device comprises the display panel according to claim 23 or 24, and further comprises: The first polarizer; A selective wavelength transmission film disposed on a side of the display panel away from the first polarizer; a second polarizer disposed on a side of the selective wavelength transmission film away from the first polarizer; The first polarizer has a first transmission axis, configured to generate a first polarized light whose polarization direction is parallel to the first transmission axis, the second polarizer has a second transmission axis, configured to generate a second polarized light whose polarization direction is parallel to the second transmission axis, and the extension direction of the first transmission axis intersects with the extension direction of the second transmission axis; The selective wavelength transmission film is configured to reflect the first polarized light and transmit the second polarized light.

26. The display device according to claim 25, wherein: The display device further includes a light absorbing layer disposed on a side of the selective wavelength transmission film away from the display panel, and the light absorbing layer is configured to absorb the second polarized light transmitted by the selective wavelength transmission film.

27. A method for driving a display substrate, wherein: The display substrate comprises: a first substrate base plate; A first transparent electrode layer is provided on the first substrate; A second transparent electrode layer is disposed on a side of the first transparent electrode layer away from the first substrate; M first common signal lines and N second common signal lines are arranged in the first transparent electrode layer, the M first common signal lines are arranged along a first direction, the N second common signal lines are arranged along a second direction, the first direction and the second direction intersect, the M first common signal lines are electrically connected through the N second common signal lines, and both M and N are positive integers; and A sub-pixel is arranged on the first substrate; Wherein, the sub-pixel includes a pixel electrode located in the second transparent electrode layer, and the M strips The first common signal line and the N second common signal lines form a transparent conductive structure; and, In the thickness direction of the display substrate, the pixel electrode and the transparent conductive structure overlap, and in the overlapping area, the pixel electrode and the transparent conductive structure are configured to form a storage capacitor of the sub-pixel; The display substrate further comprises a data line, a first gate line and a second gate line, and the sub-pixel comprises a switch transistor; The switch transistor includes a first electrode, a second electrode, a first gate electrode and a second gate electrode; the first electrode is electrically connected to the data line, the second electrode is electrically connected to the pixel electrode, the first gate electrode is electrically connected to the first gate line, and the second gate electrode is electrically connected to the second gate line. The display substrate comprises a plurality of sub-pixels arranged in an array along the first direction and the second direction; A second gate line electrically connected to the second gates of the switch transistors of the sub-pixels in the nth row and a first gate line electrically connected to the first gates of the switch transistors of the sub-pixels in the (n+1)th row are electrically connected to the same scan signal terminal; Wherein, said n is a positive integer; The driving method comprises: In the first data writing phase of the n-th row of sub-pixels, a valid level signal is provided to a first gate line electrically connected to the n-th row of sub-pixels, and an invalid level signal is provided to a second gate line electrically connected to the n-th row of sub-pixels; In the second data writing phase of the n-th row of sub-pixels, providing an effective level signal to a first gate line electrically connected to the n-th row of sub-pixels, and providing an effective level signal to a second gate line electrically connected to the n-th row of sub-pixels; In the display phase of the nth row of sub-pixels, an invalid level signal is provided to the first gate line electrically connected to the nth row of sub-pixels, and a valid level signal is provided to the second gate line electrically connected to the nth row of sub-pixels.

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