System and method for interpolating register-based lookup tables

Abstract

A disclosed computer-implemented method for interpolating a register-based lookup table may include identifying, within a set of registers, a lookup table that has been encoded to be stored within the set of registers. The method may also include receiving a request to look up a value in the lookup table, and responding to the request by interpolating a representation of the requested value from the encoded lookup table stored in the set of registers. Various other methods, systems, and computer readable media are also disclosed.

Description

[0001] Priority application

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 349,559, filed on June 6, 2022, entitled “SYSTEMS AND METHODS FOR INTERPOLATING REGISTER-BASED LOOKUP TABLES,” the entire contents of which are incorporated herein by reference. Background Art

[0003] Accelerated processors can use lookup tables to more efficiently approximate the outputs of various calculations. Nevertheless, many machine learning algorithms make use of various transcendental functions that are not typically supported efficiently in hardware accelerators. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings illustrate several example implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

[0005] Figure 1 is an overview of a register-based lookup table system according to one or more implementations.

[0006] Figure 2 is an example of a method of reducing the size of a lookup table to fit into a limited register space according to one or more implementations.

[0007] Figure 3 is an example block diagram of a register-based lookup table system that interpolates values ​​from a register-based lookup table to approximate a function according to one or more implementations.

[0008] Figure 4 is a block diagram of an example system for interpolating a register-based lookup table according to one or more implementations.

[0009] Figure 5 is a flow chart of an example method for interpolating a register-based lookup table according to one or more implementations.

[0010] Throughout the drawings, the same reference numerals and descriptions represent similar but not necessarily identical elements. Although the example implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been illustrated by example in the drawings and will be described in detail herein. However, the example implementations described herein are not intended to be limited to the specific forms disclosed. On the contrary, the present disclosure covers all modifications, equivalents, and alternatives that fall within the scope of the appended claims. DETAILED DESCRIPTION

[0011] The present disclosure as a whole relates to systems and methods for interpolating register-based lookup tables. While some designs may attempt to include dedicated / hardwired functional units (e.g., hardware accelerators) for specific functions (e.g., sigmoid, Batch Norm, Gaussian error linear unit or "GELU", etc.), the algorithms in the machine learning space change so rapidly that such specialized units can easily become obsolete. In contrast, the specific implementations described herein can utilize a combination of software programmable lookup tables (LUTs) with vector hardware interpolation units to be able to accurately or approximately calculate the results of arbitrary numerical functions depending on the data width (e.g., half-precision floating point or fp16) and the lookup table storage size.

[0012] As an example, relative to machine learning algorithms that involve several computationally expensive numerical function evaluations (e.g., GELU, Batch Norm) that typically degrade performance (otherwise would require easily obsolete hardware units), the systems and methods disclosed herein can provide higher performance for these operations in a flexible, efficient, algorithm-agnostic, and future-proof manner. To illustrate, the equation below shows how to approximate a linear activation function GELU (Gaussian Error Linear Unit) with 6 multiplications, 2 additions, and a hyperbolic tangent function.

[0013]

[0014] Mechanisms that help accelerate these operations (as proposed by embodiments of the present disclosure) can improve the performance of training and inference, especially for transcendental functions like TANH that typically have low throughput.

[0015] In one or more specific implementations, work other than matrix multiplication consumes a large amount of execution time when attempted by existing hardware accelerators. Such operations (e.g., transcendental operations, square root operations, reciprocal operations, compound operations) typically involve functions that are inefficient and slow to pipeline for high throughput. In this way, and as discussed in more detail below, specific implementations of the present disclosure can provide increased computational efficiency in various ways (including using, for example, hardware registers as sources for lookup table inputs, rather than using storage space and cache hierarchies). In one or more specific implementations, the systems and methods described herein can significantly increase the throughput of complex functions, transcendental functions, etc., while maintaining an acceptable level of machine learning accuracy. In addition, the systems and methods described herein can further reduce the power consumption of the accelerated processor by performing interpolation directly from registers.

[0016] As will be described in more detail below, the present disclosure describes various systems and methods for interpolating register-based lookup tables. In one specific implementation, a method for interpolating a register-based lookup table may be performed by a computing device including at least one processor, and may include identifying within a set of registers a lookup table that has been encoded for storage within the set of registers, receiving a request to look up a value in the lookup table, and responding to the request by interpolating a representation of the requested value from the encoded lookup table stored in the set of registers.

[0017] In one or more specific implementations, the method may further include encoding the lookup table by identifying a number of bits available within the set of registers and reducing a size of the lookup table to fit within the number of bits available within the set of registers. For example, reducing the size of the lookup table may include allocating a number of bits to represent mid-range values ​​in the lookup table, and allocating fewer bits to represent at least one of: a set of values ​​greater than the mid-range value, or a set of values ​​less than the mid-range value, relative to the number of bits representing the mid-range value.

[0018] In one or more implementations, the lookup table may include a table having representative outputs of the machine learning function. Additionally, in one or more implementations, the set of registers may include at least two registers of at least one processor of the computing device. In at least one implementation, interpolating the representation of the request value includes identifying an approximate value of the request value within the lookup table. Furthermore, interpolating the representation of the request value may include identifying an exact representation of the request value within the lookup table.

[0019] In one example implementation, a system for interpolating a register-based lookup table may include at least one physical processor, and physical memory including computer executable instructions that, when executed by the at least one physical processor, cause the at least one physical processor to: identify within a set of registers a lookup table that has been encoded to be stored within the set of registers, receive a request to look up a value in the lookup table, and respond to the request by interpolating a representation of the requested value from the encoded lookup table stored in the set of registers.

[0020] In some example implementations, the above method may be encoded as computer-readable instructions on a non-transitory computer-readable medium. For example, the computer-readable medium may include one or more computer-executable instructions that, when executed by at least one processor of a computing device, cause the computing device to: identify within a set of registers a lookup table that has been encoded to be stored within the set of registers, receive a request to look up a value in the lookup table, and respond to the request by interpolating a representation of the requested value from the encoded lookup table stored in the set of registers.

[0021] In more detail, Figure 1 An overview of a register-based lookup table system 102 is shown that uses a programmable / reconfigurable lookup table (LUT) 104 instead of implementing N different hardware functions (sqrt, atan, tanh, 1 / x, etc.). In one or more implementations, as shown, the register-based lookup table system 102 can utilize the lookup table 104 in conjunction with an interpolation unit 106 to generate approximate results for complex machine learning-based operations.

[0022] For example, Figure 1 As shown, the register-based lookup table system 102 can maintain the lookup table 104 across multiple register bits in the register 108, and can then use any remaining register bits for interpolation. For example, in one implementation, the register-based lookup table system 102 can use the sign bit 110a, the exponent bits 110b-110i, and the mantissa bits or fraction bits 110j and 110k for the lookup table 104. In at least one implementation, by using these bits 110a-110k, the size of the lookup table 104 can be 2 11 *2B=4KB. As further shown, in at least one specific implementation, the register-based lookup table system 102 can further use the remaining mantissa bits 1101-110p for interpolation. Using this format, for example, the register-based lookup table system 102 can use a single LUT (e.g., lookup table 104) to generate a GELU equation response instead of performing 6 multiplication operations, 2 addition operations, and 1 hyperbolic tangent operation.

[0023] As described above, in addition to using a lookup table stored in one or more hardware registers, the register-based lookup table system 102 can utilize an interpolation unit 106. In one or more implementations, the interpolation unit 106 can use the contents of the lookup table 104 to compute or approximate the result of an arbitrary function (it can be arbitrary since programmers can load the lookup table contents with anything they want). Figure 1 For the particular implementation shown, lookup table 104 may be too large to be stored in one or two x86 AVX-512 registers (e.g., 64 bytes per zmm register), which would be desirable if lookup table and interpolation instructions were limited to no more than three register operands.

[0024] Therefore, in order to fit the lookup table 104 into the bit limitations of conventional hardware systems, the register-based lookup table system 102 can take advantage of the fact that most functions of interest do not take completely arbitrary random values. For example, the register-based lookup table system 102 can take advantage of the fact that for very large amplitude inputs or very small absolute values, only a few sample points are needed to maintain an accurate interpolation / approximation. This specific implementation is particularly true for many numerical functions used in machine learning. To illustrate, the curves of general functions such as GELU, ReLU, and ELU flatten out quickly for very small inputs and very large inputs.

[0025] Therefore, if Figure 2 As shown, the register-based lookup table system 102 can divide the lookup table 104 into a plurality of regions, wherein the first region 202 covers a range of values ​​where the floating-point exponent is neither very large nor very small. For example, in the illustrated implementation, this is illustrated in the register 108 by the four most significant exponent bits closest to the sign bit ("s"). The register-based lookup table system 102 can further divide the lookup table 104 into a top region 204a, which represents values ​​where the exponent is greater than a threshold range (i.e., the sign bit in the example register 108' indicates that the exponent is positive). The register-based lookup table system 102 can also divide the lookup table 104 into a bottom region 204b, which represents values ​​where the exponent is less than a threshold range (i.e., the sign bit in the example register 108' indicates that the exponent is negative).

[0026] In one or more specific implementations, as shown in the example register 108', the register-based lookup table system 102 can use the three most significant exponent bits (in addition to the sign bit) in conjunction with the values ​​represented in the top region 204a and the bottom region 204b. In this way, the register-based lookup table system 102 can utilize fewer bits to interpolate very large and / or very small inputs (e.g., within the second region 204) because for most functions, very large or very small inputs cause little change in the function output. In addition, as shown in the register 108, the register-based lookup table system 102 can utilize a greater number of bits (e.g., the four most significant bits in addition to the sign bit) in conjunction with the typical range of values ​​of interest (e.g., within the first region 202) to obtain greater precision.

[0027] In one or more implementations, the register-based lookup table system 102 may adjust the number of bits used within a register depending on the region of the lookup table indexed by the register. In at least one implementation, utilizing different numbers of various types of register bits may result in different storage capacity requirements for the associated lookup tables. In more detail, precision registers (e.g., such as register 108) and interpolation registers (e.g., such as example register 108') may include a sign bit (e.g., such as Figure 1 The sign bit 110a shown), the exponent bit (e.g., Figure 1 The exponent bits 110b-110i shown) and the mantissa bits (e.g., Figure 1 110j-110k). However, the register-based lookup table system 102 may not utilize all of the available exponent bits and mantissa bits of a given register in order to reduce the necessary capacity of the associated lookup table. For example, table 206 illustrates how the register-based lookup table system 102 can modify the lookup table size by utilizing different numbers of exponent bits and mantissa bits in the registers indexed into those lookup tables.

[0028] To illustrate, as shown in Table 206, a precision register (e.g., similar to register 108) utilizing a sign bit, 4 exponent bits, and 2 mantissa bits (e.g., "1, 4, 2") can index into a lookup table of size 320B, where a typical range of values ​​of interest (e.g., such as in the first region 202) has higher precision. Similarly, an interpolation register (e.g., similar to example register 108') utilizing a sign bit, 4 exponent bits, and 0 mantissa bits (e.g., "1, 4, 0") can also index into a lookup table of size 320B (although with fewer bits) to interpolate very large or very small inputs. Additionally, as shown in Table 206, a precision register can index into a lookup table of size 288B utilizing a sign bit, 4 exponent bits, and 2 mantissa bits (e.g., "1, 4, 2") and an interpolation register utilizing a sign bit, 3 exponent bits, and 0 mantissa bits (e.g., "1, 3, 0"). Table 206 further illustrates additional bit arrangements for indexing into registers in a lookup table of size 192B, 160B, 128B, or 96B.

[0029] In summary, lookup tables that utilize bit arrangements such as those listed along the top of table 206 are those that use higher precision for typical ranges of values ​​of interest, while lookup tables that utilize bit arrangements such as those listed along the left-hand side of table 206 are those that use fewer bits to interpolate very large and very small inputs. In at least one implementation, table 206 may be in BFloat16 (brain floating point) format. In additional implementations, the same results may apply to FP16 (half-precision floating point) format or another suitable format.

[0030] Figure 3 A potential implementation of a register-based lookup table system 102 within a CPU is shown. To illustrate, in one example, the register-based lookup table system 102 may implement a new instruction for general function evaluation. Figure 3 In the example shown, the small input lookup table 302 can be connected with Figure 2 The first region 202 shown corresponds to values ​​with exponents closer to zero. In one or more implementations, the small input lookup table 302 may use five bits for the lookup table index lookup (e.g., one sign bit, four exponent bits, and a zero mantissa bit), which may require 2 5 = 32 entries, and 2 bytes per entry (for bf16) for a total of 64 bytes.

[0031] Similarly, the large input lookup table 304 can be connected with Figure 2 In at least one implementation, the large input lookup table 304 may also use five bits for the lookup table index lookup (e.g., one sign bit, four exponent bits, and 0 mantissa bits), which may require 2 5 =32 entries, and 2 bytes per entry (for bf16) for a total of 64 bytes. In at least one implementation, small input lookup table 302 and large input lookup table 304 can each fit into a single register (eg, a 512-bit register).

[0032] As mentioned above, Figure 3 The register-based lookup table system 102 is shown to execute new instructions for general function evaluation. For illustration, the general function may be as follows:

[0033] _m512BH VGFUNCBF16(_m512bh src,_m512 LUT1,_m512LUT2)

[0034] For i in [0..31]

[0035] If (abs(src[i]>MAX_LUT1_INPUT)) then output[i] = interpolate(LUT1,src[i])

[0036] Otherwise output[i] = interpolate(LUT2,src[i])

[0037] In at least one implementation, function VGFUNCBF16 includes three register operands, two of which (e.g., LUT1 and LUT2 corresponding to small input lookup table 302 and large input lookup table 304, respectively) specify registers that hold the lookup tables. The first operand "src" provides the input values ​​(x's) (e.g., 32 bfloat16 values ​​packed into a single zmm 512-bit register). If small input lookup table 302 and large input lookup table 304 store samples corresponding to function "f", VGFUNCBF16 fetches each "x" from the source (src) register.

[0038] Next, if Figure 3 As shown, the register-based lookup table system 102 can perform an index range check 306 by using the index of the x value to determine which lookup table should be used. The register-based lookup table system 102 further looks up the two most recent entries (these entries may be consecutive) from the corresponding lookup table, and then performs interpolation based on the two values ​​from the corresponding lookup table using the interpolation unit 308 to calculate / approximate the output f(x). Specifically, the register-based lookup table system 102 can calculate x by using the x value. LO and X HI (eg, the two closest x values ​​corresponding to the lookup table index) to perform the interpolation unit 308. The register-based lookup table system 102 then uses X LO and X HI To find two entries in the lookup table (for example, f(X LO ) and f(X HI )). In at least one specific implementation, the interpolation unit 308 then performs the interpolation based on f(X LO ) and f(X HI ) performs linear interpolation to estimate the value of f(x).

[0039] In one or more implementations, the register-based lookup table system 102 utilizes an interpolation unit to perform the interpolation by using some of the mantissa bits that were not used by the lookup step. Since there are 32 x's in the input source register (src), 32 f(x) outputs are generated. In at least one implementation, the register-based lookup table system 102 can write these outputs to the destination register. For example, in some implementations, 102 can write these outputs to the same source register (src), thereby overwriting the input.

[0040] In some implementations, the register-based lookup table system 102 can determine the exact selection of which exponent and mantissa bits to select from the input (as well as the format and interpolation function of the value) based on the information encoded in the instruction operand. In one example, 6 bits (1, 4, 1) can be used to index into the lookup table. In order to store the lookup table in a single register, the register-based lookup table system 102 can reduce each lookup table entry to one byte, corresponding to (1, 5, 2). In some implementations, the interpolation unit 308 can obtain two one-byte values ​​from consecutive entries, perform interpolation, and output a two-byte bfloat16 value. Additionally, in some implementations, each lookup table (e.g., small input lookup table 302 and large input lookup table 304) can have an associated unique interpolation function.

[0041] Apart from Figure 3 In addition to the examples shown, in additional implementations, the register-based lookup table system 102 may use smaller source / destination registers, such as 256-bit (16 input / output), or even scalar source / destination registers. In one or more implementations, the register size is not critical to the operation of the register-based lookup table system 102. Instead, in one or more implementations, the register-based lookup table system 102 may rely primarily on being able to store the lookup table in registers as large as possible.

[0042] Figure 4 4 is a block diagram of an example system 400 for interpolating a register-based lookup table (e.g., the register-based lookup table system 102 described above). As shown in the figure, the example system 400 may include one or more modules 402 for performing one or more tasks. As will be explained in more detail below, the modules 402 may include an identification module 404, a lookup module 406, and an interpolation module 408. Although illustrated as separate elements, Figure 4 One or more of the modules 402 in may represent portions of a single module or application.

[0043] In some specific implementations, Figure 4 One or more of the modules 402 in the embodiment may represent one or more software applications or programs that, when executed by a computing device, may cause the computing device to perform one or more tasks. For example, as will be described in more detail below, one or more of the modules 402 may represent modules that are stored and configured to run on one or more computing devices. Figure 4One or more of the modules 402 in the embodiment may also represent all or part of one or more special-purpose computers configured to perform one or more tasks. In a preferred embodiment, the modules 402 are implemented as hardware (e.g., circuits) in the physical processor 430, rather than being stored as software modules in the memory 440.

[0044] like Figure 4 As shown, the example system 400 may also include one or more memory devices, such as memory 440. Memory 440 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, memory 440 may store, load, and / or maintain one or more of modules 402. Examples of memory 440 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical drive, cache, variations or combinations of one or more of the above components, or any other suitable memory.

[0045] like Figure 4 As shown, the example system 400 may also include one or more physical processors, such as physical processor 430. Physical processor 430 generally represents a hardware-implemented processing unit of any type or form capable of interpreting and / or executing computer-readable instructions. In one example, physical processor 430 may access and / or modify one or more of modules 402 stored in memory 440. Additionally or alternatively, physical processor 430 may execute one or more of modules 402 to facilitate interpolation of register-based lookup tables. Examples of physical processor 430 include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a portion of one or more of the above components, a variation or combination of one or more of the above components, or any other suitable physical processor.

[0046] like Figure 4 As shown, the example system 400 may also include a group of registers 432. The group of registers 432 may include any suitable number of registers that the physical processor 430 uses to execute instructions. For example, the group of registers 432 may include a single register, two registers, or multiple registers. In some examples, the group of registers 432 may be data registers that may store numerical values, such as integer values, floating point values, and / or any other suitable values. The group of registers 432 may also include registers of any suitable size. For example, the registers in the group of registers 432 may be 8-bit registers, 16-bit registers, 32-bit registers, 64-bit registers, 128-bit registers, etc.

[0047] As mentioned above, and as Figure 4 As shown, system 400 may include an identification module 404 within module 402. In one or more specific implementations, identification module 404 determines which lookup table to apply to an input. For example, identification module 404 may perform an exponential range check on the input value (e.g., Figure 3 In at least one implementation, when the exponent of the input value is close to zero, the identification module 404 can decide to use a small input lookup table (e.g., such as Figure 3 In addition, when the exponent of the input value has a larger magnitude exponent, the identification module 404 may decide to use a large input lookup table (e.g., Figure 3 304).

[0048] As mentioned above, and as Figure 4 As shown, system 400 may include a lookup module 406. In one or more specific implementations, the lookup module 406 identifies at least two values ​​from a specified lookup table based on the bits of the input value. Figure 3 As discussed, the lookup module 406 may utilize one or more of the sign bit, the upper exponent bit, the lower exponent bit, and the mantissa bit to identify the two entries closest to the input value. In at least one specific implementation, the two closest entries may be consecutive.

[0049] As further described above, and as Figure 4 As shown, system 400 may include an interpolation module 408. As used herein, the term "interpolation" refers to estimating a value based on a series of values. For example, in one or more specific implementations, interpolation module 408 may generate an interpolated value based on at least two input values. For example, interpolation module 408 may receive two values ​​identified in a specified lookup table from lookup module 406, and generate an interpolated value based on the received values. In at least one specific implementation, interpolation module 408 generates an interpolated value by determining an intermediate value between received values. For example, interpolation module 408 may determine an average value of received values, a median value of received values, or different intermediate values ​​between received values.

[0050] Many other devices or subsystems can be connected to Figure 4 In contrast, Figure 4 All components shown in the drawings need not be present to practice the specific implementations described and / or illustrated herein. The above-mentioned devices and subsystems may also be used in conjunction with Figure 4The system 400 may also be interconnected in different ways as shown. The system 400 may also employ any number of software, firmware, and / or hardware configurations. For example, one or more of the example implementations disclosed herein may be encoded as a computer program (also referred to as computer software, software application, computer-readable instructions, and / or computer control logic) on a computer-readable medium.

[0051] As used herein, the term "computer-readable medium" generally refers to any form of device, carrier, or medium that can store or carry computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media, such as carrier waves, and non-transitory media, such as magnetic storage media (e.g., hard drives, tape drives, and floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and BLU-ray disks), electronic storage media (e.g., solid-state drives and flash memory media), and other distribution systems.

[0052] Figure 5 is a flow chart of an example computer-implemented method 500 for interpolating a register-based lookup table. Figure 5 The steps shown may be implemented by any suitable computer executable code and / or computing system (including Figure 4 In one example, Figures 1 to 3 Each of the steps shown in may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in more detail below.

[0053] like Figure 5 As shown, at step 502, one or more of the systems described herein may insert a register-based lookup table. For example, as Figure 4 As part of system 400, identification module 404 may identify within a set of registers a lookup table that has been encoded to be stored within the set of registers. Identification module 404 may perform step 502 in any suitable manner. For example, identification module 404 may identify the lookup table in response to a request for an output of a function of a machine learning algorithm. Additionally or alternatively, identification module 404 may identify the lookup table in response to a request for an output of any other suitable type of function.

[0054] As used herein, the term "lookup table" generally refers to any data array that can replace runtime calculations with array index operations. In some implementations, as described above, the savings in processing time can be significant because retrieving values ​​from registers can be much faster than performing overhead calculations. In some implementations, the lookup table can be pre-calculated and / or pre-fetched. In some implementations, the lookup table can be stored in hardware on a dedicated platform. Alternatively, the lookup table can be part of a reconfigurable hardware-implemented solution provided by an FPGA.

[0055] At step 504, as Figure 4 As part of system 400, lookup module 406 can receive a request to find a value in a lookup table. Lookup module 406 can receive the request in any suitable manner and / or context. For example, lookup module 406 can receive the request as a direct addressing request for an output of a function.

[0056] At step 506, as Figure 4 As part of system 400, interpolation module 408 can respond to the request by interpolating a representation of the requested value from an encoded lookup table stored in the set of registers. Interpolation module 408 can interpolate the representation of the requested value in any suitable manner. For example, in some implementations, interpolation module 408 can interpolate the representation of the requested value by identifying an approximate value of the requested value in a lookup table.

[0057] Alternatively, the interpolation module 408 can interpolate the representation of the request value by identifying the exact representation of the request value in the lookup table. For example, in one implementation, the lookup table can include values ​​that serve as indices to the interpolation data structure. Thus, in this implementation, the interpolation module 408 can interpolate the representation of the request value by using two or more values ​​identified by the lookup module 406 in the lookup table as indices to the interpolated value data structure. Using these indices, the interpolation module 408 can identify the exact representation of the request value.

[0058] In some implementations, the system described herein may encode the lookup table for storage within the set of registers. The system described herein may encode the lookup table in any suitable manner. For example, the system described herein may identify the number of bits available within the set of registers and reduce the size of the lookup table to fit the number of bits available within the set of registers. This reduction may be a linear reduction across the values ​​in the lookup table, or may be a nonlinear reduction based on the data in the lookup table. For example, reducing the size of the lookup table may include (1) allocating a number of bits to represent mid-range values ​​in the lookup table, and (2) allocating fewer bits relative to the number of bits representing the mid-range values ​​to represent at least one set of values ​​greater than the mid-range values ​​or at least one set of values ​​less than the mid-range values. Implementations of the present disclosure may also use any other suitable algorithm or mechanism to reduce the size of the lookup table to fit a particular set of registers.

[0059] Specific implementations of the present disclosure may provide various advantages over traditional methods and may be implemented in a variety of environments. For example, specific implementations of the present disclosure may provide higher performance (particularly significantly higher throughput for complex functions, transcendental functions, etc.) than traditional operations with relatively low silicon cost and acceptable impact on machine learning accuracy. Performing interpolation directly from registers may also reduce power consumption (e.g., compared to texture cache methods in accelerated processors that repeatedly read data from a cache hierarchy). These advantages may be implemented in a variety of systems, including accelerated processors and / or hardware accelerators (e.g., central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), neural processing units (NPUs), tensor processing units (TPUs), and / or other hardware accelerators, application specific integrated circuits (ASICs), etc.).

[0060] Although the foregoing disclosures have described various specific implementations using specific block diagrams, flow charts, and examples, each block diagram component, flow chart step, operation, and / or component described and / or shown herein may be implemented individually and / or together using various hardware, software, or firmware (or any combination thereof) configurations. In addition, any disclosure of components contained within other components should be considered exemplary in nature, as many other architectures may be implemented to achieve the same functionality.

[0061] The process parameters and order of steps described and / or shown herein are provided as examples only and may be changed as desired. For example, although the steps described and / or shown herein may be shown or discussed in a particular order, the steps do not necessarily need to be performed in the order shown or discussed. The various example methods described and / or shown herein may also omit one or more of the steps described or shown herein, or include additional steps in addition to those disclosed.

[0062] Although various implementations have been described and / or shown herein in the context of a fully functional computing system, one or more of these example implementations can be distributed as a program product in various forms, regardless of the specific type of computer-readable medium used to actually perform the distribution. The implementation disclosed herein can also be implemented using modules that perform specific tasks. These modules can include scripts, batch processing, or other executable files that can be stored on a computer-readable storage medium or stored in a computing system. In some implementations, these modules can configure a computing system to perform one or more of the example implementations disclosed herein.

[0063] The foregoing description has been provided to enable others skilled in the art to best utilize various aspects of the example implementations disclosed herein. This example description is not intended to be exhaustive or limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The implementations disclosed herein should be considered in all respects to be illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0064] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) used in the specification and claims should be interpreted as allowing both direct and indirect (i.e., via other elements or components) connections. In addition, the terms "a" or "an" used in the specification and claims should be understood to mean "at least one of..." Finally, for ease of use, the terms "including" and "having" (and their derivatives) used in the specification and claims are interchangeable with the word "comprising" and have the same meaning as the word "including".

Claims

1. A computer-implemented method for interpolating a register-based lookup table, at least a portion of the computer-implemented method being performed by a computing device including at least one processor, the computer-implemented method comprising: receiving a request to look up a value in a lookup table encoded for storage within a set of registers; as well as The request is responded to by interpolating a representation of the requested value from an encoded lookup table stored in the set of registers.

2. The computer-implemented method of claim 1 , further comprising encoding the lookup table by: identifying a number of bits available within the set of registers; and The size of the lookup table is reduced to fit within the number of bits available within the set of registers.

3. The computer-implemented method of claim 2 , wherein reducing the size of the lookup table comprises: allocating a number of bits to represent mid-range values ​​in the lookup table; as well as Relative to the number of bits representing the mid-range value, fewer bits are allocated to represent at least one of: a set of values ​​greater than the mid-range value; or A set of values ​​that are less than the mid-range value.

4. The computer-implemented method of claim 1 , wherein the lookup table comprises a table having representative outputs of a machine learning function. 5 . The computer-implemented method of claim 1 , wherein the set of registers comprises at least two registers of the at least one processor of the computing device. 6 . The computer-implemented method of claim 1 , wherein interpolating the representation of the request value comprises identifying an approximation of the request value within the lookup table.

7. The computer-implemented method of claim 1, wherein interpolating the representation of the request value comprises identifying an exact representation of the request value within the lookup table.

8. A system for interpolating a register-based lookup table, the system comprising: at least one physical processor; as well as a physical memory comprising computer executable instructions that, when executed by the at least one physical processor, cause the at least one physical processor to: receiving a request to look up a value in a lookup table encoded for storage within a set of registers; as well as The request is responded to by interpolating a representation of the request value from an encoded lookup table stored in the set of registers.

9. The system of claim 8, wherein the computer executable instructions, when executed by the at least one physical processor, further cause the at least one physical processor to encode the lookup table in the following manner: identifying a number of bits available within the set of registers; and The size of the lookup table is reduced to fit within the number of bits available within the set of registers.

10. The system of claim 9, wherein the computer executable instructions, when executed by the at least one physical processor, cause the at least one physical processor to reduce the size of the lookup table by: allocating a number of bits to represent mid-range values ​​in the lookup table; and Relative to the number of bits representing the mid-range value, fewer bits are allocated to represent at least one of: a set of values ​​greater than the mid-range value; or A set of values ​​that are less than the mid-range value.

11. The system of claim 8, wherein the lookup table comprises a table having representative outputs of a machine learning function.

12. The system of claim 8, wherein the set of registers includes at least two registers of the at least one physical processor.

13. The system of claim 8, wherein interpolating the representation of the request value comprises identifying an approximation of the request value within the lookup table.

14. The system of claim 8, wherein interpolating the representation of the request value comprises identifying an exact representation of the request value within the lookup table.

15. A non-transitory computer-readable medium comprising one or more computer-executable instructions that, when executed by at least one processor of a computing device, cause the computing device to: receiving a request to look up a value in a lookup table encoded for storage within a set of registers; and The request is responded to by interpolating a representation of the request value from an encoded lookup table stored in the set of registers.

16. The non-transitory computer readable medium of claim 15, wherein the one or more computer executable instructions are programmed to cause the computing device to encode the lookup table in the following manner: identifying a number of bits available within the set of registers; and The size of the lookup table is reduced to fit within the number of bits available within the set of registers.

17. The non-transitory computer readable medium of claim 15, wherein the lookup table comprises a table having representative outputs of a machine learning function.

18. The non-transitory computer readable medium of claim 15, wherein the set of registers includes at least two registers of the at least one processor of the computing device.

19. The non-transitory computer readable medium of claim 15, wherein interpolating the representation of the request value comprises identifying an approximation of the request value within the lookup table.

20. The non-transitory computer readable medium of claim 15, wherein interpolating the representation of the request value comprises identifying an exact representation of the request value within the lookup table.

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