Model performance analyzer

Abstract

A performance-enhanced processor-implemented method for identifying an artificial neural network (ANN) model includes receiving an ANN model to run on a target hardware architecture. The ANN model is analyzed based on a set of rules associated with the target hardware architecture. An output is generated based on the set of rules, the output comprising one or more modifications to the ANN model.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 855,351, filed on June 30, 2022, and entitled “MODEL PERFORMANCE LINTER,” the disclosure of which is expressly incorporated by reference in its entirety. Technical Field

[0003] Aspects of the present disclosure generally relate to identifying performance enhancements for artificial neural network models. Background Art

[0004] An artificial neural network may include an interconnected group of artificial neurons (e.g., a neuron model). An artificial neural network may be a computing device or represented as a method performed by a computing device. An artificial neural network may be trained to perform a specific task by processing inputs through various layers of neurons. In particular, these neural networks are used in various technologies such as image recognition, pattern recognition, speech recognition, autonomous driving, and other classification tasks.

[0005] Artificial neural networks (ANNs) can be arranged into a variety of architectures. Each architecture can provide a different way to solve the same problem of performing a given task. However, due to the structural differences between the various ANN model architectures, each ANN model may perform differently on the target hardware system.

[0006] Edge devices, such as smartphones and other mobile computing devices, are widely used. Given the many useful applications of neural networks, there is an increasing demand for use on edge devices and for personalized services on such edge devices. However, edge devices have limited computing resources, and generalized models can utilize more complex networks and more computation. Therefore, the computational cost of operating ANN models can be a problem.

[0007] Furthermore, edge devices are not monolithic in hardware architecture. Additionally, a given ANN model may be formatted and / or optimized for a specific target hardware architecture. Thus, a user may attempt to operate an ANN model on a device having a hardware architecture different from the target architecture. In some instances, the ANN model may not be operable on the device without modification. In other instances, the ANN model may be operable but with reduced performance (e.g., increased latency and / or increased power consumption). Summary of the invention

[0008] In one aspect of the present disclosure, a processor-implemented method includes receiving an artificial neural network (ANN) model to run on a target hardware architecture. The method also includes analyzing the ANN model based on a set of rules associated with the target hardware architecture. The method also includes generating an output based on the set of rules, the output including one or more modifications to the ANN model.

[0009] Another aspect of the present disclosure relates to an apparatus comprising a component for receiving an artificial neural network (ANN) model to run on a target hardware architecture. The apparatus further comprises a component for analyzing the ANN model based on a set of rules associated with the target hardware architecture. The apparatus further comprises a component for generating an output based on the set of rules, the output comprising one or more modifications to the ANN model.

[0010] In another aspect of the present disclosure, a non-transitory computer-readable medium having non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes program code for receiving an artificial neural network (ANN) model to run on a target hardware architecture. The program code also includes program code for analyzing the ANN model based on a set of rules associated with the target hardware architecture. The program code also includes program code for generating an output based on the set of rules, the output including one or more modifications to the ANN model.

[0011] Another aspect of the present disclosure relates to a device having a memory and one or more processors coupled to the memory. The processor is configured to receive an artificial neural network (ANN) model to run on a target hardware architecture. The processor is also configured to analyze the ANN model based on a set of rules associated with the target hardware architecture. The processor is also configured to generate an output based on the set of rules, the output including one or more modifications to the ANN model.

[0012] Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure can be easily used as a basis for modifying or designing other structures for implementing the same purpose as the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features considered to be characteristic of the present disclosure, both in terms of its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the accompanying drawings is provided for illustration and description purposes only and is not intended to be a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The features, nature and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0014] Figure 1 An example implementation of a neural network using a system on a chip (SOC) including a general purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0015] Figure 2A , Figure 2B and Figure 2C is a diagram illustrating a neural network according to aspects of the present disclosure.

[0016] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0017] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0018] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality.

[0019] Figure 5A is a high-level block diagram illustrating an example architecture for improving model performance using a linter in accordance with aspects of the present disclosure.

[0020] Figure 5B is a block diagram illustrating an example architecture of a model performance profiler in accordance with aspects of the present disclosure.

[0021] FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8B as well as FIG. 9A to FIG. 9B is a diagram illustrating an example artificial neural network (ANN) model and corresponding output including modifications to improve model performance in accordance with aspects of the present disclosure.

[0022] Fig.10 is a flow chart illustrating a processor-implemented method of identifying modifications for improving performance of an artificial neural network (ANN) in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the described concepts can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid blurring such concepts, known structures and components are shown in block diagram form.

[0024] Based on the teachings, those skilled in the art will recognize that the scope of the present disclosure is intended to cover any aspect of the present disclosure, whether the aspect is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect. For example, a device may be implemented or a method may be practiced using any number of aspects described. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or structures and functionality that are supplementary to or different from the various aspects of the present disclosure described. It should be understood that any aspect of the present disclosure disclosed may be embodied by one or more elements of a claim.

[0025] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0026] Although specific aspects are described, numerous variations and permutations of these aspects fall within the scope of the present disclosure. Although some benefits and advantages of preferred aspects are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or purposes. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different technologies, system configurations, networks and protocols, some of which are illustrated by way of example in the drawings and the following description of preferred aspects. The specific embodiments and drawings are merely illustrative of the present disclosure and are not limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0027] As mentioned, artificial neural networks (ANNs) have become increasingly popular due to their ability to solve complex problems. As such, ANN models are widely used in a variety of technologies, such as image recognition, pattern recognition, speech recognition, autonomous driving, and other classification tasks.

[0028] Edge devices, such as smartphones and other mobile computing devices, are widely used. Given the many useful applications of neural networks, there is an increasing demand for use on edge devices and for personalized services on such edge devices. However, edge devices have limited computing resources, and generalized models can utilize more complex networks and more computation. Therefore, the computational cost of operating ANN models can be a problem.

[0029] In addition, edge devices are not integrated in the hardware architecture. A given ANN model may be formatted and / or optimized for a specific target hardware architecture. In this way, a user may attempt to operate an ANN model on a device with a hardware architecture different from the target architecture. In some instances, the ANN model cannot be operated on the device without modification. In other instances, the ANN model may be operational, but the performance is weakened (e.g., the delay is extended and / or the power consumption is increased). That is, parts of the ANN model may include structures that are not optimized to run on the user's hardware architecture (e.g., a graphics processing unit (GPU), a neural processing unit (NPU), and a tensor processor). In some instances, performance issues can be solved or improved by replacing mathematically equivalent parts. However, determining the mathematically equivalent part may be very challenging and may require a deep understanding of the hardware backend and ANN model analysis.

[0030] Therefore, to address these and other challenges, aspects of the present disclosure relate to a model performance profiler. A profiler is a code analysis tool for annotating programming errors, vulnerabilities, and genre errors. According to aspects of the present disclosure, the model performance profiler can analyze the ANN model and the target hardware architecture and generate output including one or more model modifications to improve and in some cases optimize the model performance of the target hardware.

[0031] In some aspects, the model performance profiler may be configured to implement the identified model modifications to generate a reconfigured ANN model. The reconfigured ANN model may then be operated to generate inferences. That is, a user may run this tool on their ANN model and make changes to their model so that the model may better fit on a given target hardware architecture (e.g., NPU, tensor processor) and thus improve performance. Additionally, the profiler may provide feedback to the user running the tool and may update the ANN model at any time. Beneficially, aspects of the present disclosure may identify and / or implement model modifications without expert knowledge of the target hardware architecture.

[0032] Figure 1An example implementation of a system on chip (SOC) 100 is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured to determine model modifications for improving performance. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computing device (e.g., a neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at CPU 102 may be loaded from a program memory associated with CPU 102, or may be loaded from memory block 118.

[0033] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 that may, for example, detect and recognize gestures. In one specific implementation, the NPU 108 is implemented in the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0034] SOC 100 may be based on the ARM instruction set. In one aspect of the present disclosure, the instructions loaded into the general purpose processor 102 may include code for receiving an artificial neural network (ANN) model to run on a target hardware architecture. The general purpose processor 102 may also include code for analyzing the ANN model based on a set of rules associated with the target hardware architecture. The general purpose processor 102 may also include code for generating an output based on the set of rules, the output including one or more modifications to the ANN model.

[0035] Deep learning architectures can perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building useful feature representations of the input data. In this way, deep learning solves the main bottleneck of traditional machine learning. Before the advent of deep learning, machine learning methods for object recognition problems may rely heavily on human-designed features, possibly in conjunction with shallow classifiers. A shallow classifier can be a two-class linear classifier, for example, in which the weighted sum of feature vector components can be compared to a threshold to predict which class the input belongs to. Human-designed features can be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, they require training. In addition, deep networks can learn to represent and recognize new types of features that humans may not have considered.

[0036] Deep learning architectures can learn hierarchies of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, can learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0037] Deep learning architectures can perform particularly well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can be combined in different ways at higher levels to recognize cars, trucks, and airplanes.

[0038] Neural networks can be designed to have a variety of connectivity patterns. In a feedforward network, information is passed from a lower layer to a higher layer, where each neuron in a given layer communicates with a neuron in a higher layer. As described above, hierarchical representations can be constructed in successive layers of a feedforward network. Neural networks can also have loops or feedback (also known as top-down) connections. In a loop connection, the output from a neuron in a given layer can be communicated to another neuron in the same layer. The loop architecture can help identify patterns that span more than one input data block in the input data blocks that are sequentially delivered to the neural network. The connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. When the recognition of a high-level concept can assist in discerning specific low-level features of the input, a network with many feedback connections may be helpful.

[0039] The connections between neural network layers can be fully connected or partially connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In a fully connected neural network 202, a neuron in a first layer may communicate its output to each neuron in a second layer, such that each neuron in the second layer will receive input from each neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer may be connected to a limited number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strengths may have different values ​​(e.g., 210, 212, 214, and 216). The locally connected connectivity patterns may produce spatially different receptive fields in higher layers because higher layer neurons in a given region may receive input that is tuned through training to properties of a restricted portion of the total input to the network.

[0040] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 can be configured such that the connection strengths associated with the inputs of each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited for problems where the spatial location of the inputs is meaningful.

[0041] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2D A detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as a vehicle-mounted camera) is illustrated. The DCN 200 of the current example can be trained to identify traffic signs and numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0042] The DCN 200 may be trained by supervised learning. During training, an image (such as an image 226 of a speed limit sign) may be presented to the DCN 200, and a forward pass may then be calculated to produce an output 222. The DCN 200 may include a feature extraction portion and a classification portion. Upon receiving the image 226, a convolutional layer 232 may apply a convolutional kernel (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel of the convolutional layer 232 may be a 5x5 kernel that generates a 28x28 feature map. In this example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels are applied to the image 226 at the convolutional layer 232. A convolutional kernel may also be referred to as a filter or a convolutional filter.

[0043] The first set of feature maps 218 may be subsampled by a maximum pooling layer (not shown) to generate a second set of feature maps 220. The maximum pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (such as 14x14) is smaller than the size of the first set of feature maps 218 (such as 28x28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more sets of subsequent feature maps (not shown).

[0044] exist Figure 2D In the example of , the second set of feature maps 220 are convolved to generate a first feature vector 224. In addition, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of the image 226, such as "sign", "60", and "100". A softmax function (not shown) may convert the numbers in the second feature vector 228 into probabilities. Therefore, the output 222 of the DCN 200 is the probability that the image 226 includes one or more features.

[0045] In this example, the probability of "logo" and "60" in output 222 is higher than the probability of other numbers (such as "30", "40", "50", "70", "80", "90", and "100") in output 222. Before training, the output 222 generated by DCN 200 may be incorrect. Therefore, the error between the output 222 and the target output can be calculated. The target output is the ground truth of image 226 (e.g., "logo" and "60"). The weights of DCN 200 can then be adjusted so that the output 222 of DCN 200 is closer to the target output.

[0046] To adjust the weights, the learning algorithm may calculate a gradient vector for the weights. The gradient may indicate the amount by which the error will increase or decrease when the weights are adjusted. At the top layer, the gradient may correspond directly to the value of the weights connecting the activated neurons in the penultimate layer and the neurons in the output layer. In lower layers, the gradient may depend on the value of the weights and the calculated error gradients of the higher layers. The weights may then be adjusted to reduce the error. This way of adjusting weights may be referred to as "backward propagation" because it involves a "backward pass" through the neural network.

[0047] In practice, the error gradient of the weights can be calculated over a small number of examples so that the calculated gradient is close to the true error gradient. This approximation method can be called stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, new images can be presented to the DCN, and a forward pass through the network can produce an output 222 that can be considered an inference or prediction of the DCN.

[0048] A Deep Belief Network (DBN) is a probabilistic model that includes multiple layers of hidden nodes. A DBN can be used to extract a hierarchical representation of a training dataset. A DBN can be obtained by stacking layers of Restricted Boltzmann Machines (RBMs). RBMs are a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn probability distributions without information about the category to which each input should be classified, RBMs are often used for unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBM of a DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of inputs and target classes from the previous layer) and can be used as a classifier.

[0049] A deep convolutional network (DCN) is a network that is a convolutional network configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning, where both the input and output targets are known for many examples and are used to modify the weights of the network by using a gradient descent method.

[0050] The DCN may be a feed-forward network. In addition, as described above, the connections from a neuron in the first layer of the DCN to a set of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of the DCN may be used for fast processing. For example, the computational burden of the DCN may be much smaller than that of a similarly sized neural network that includes loops or feedback connections.

[0051] The processing of each layer of the convolutional network can be thought of as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on this input can be thought of as three-dimensional, where two spatial dimensions are along the axes of the image and the third dimension captures color information. The output of the convolutional connection can be thought of as forming a feature map in a subsequent layer, where each element in the feature map (e.g., 220) receives input from a range of neurons in the previous layer (e.g., feature map 218) and from each of the multiple channels. The values ​​in the feature map can be further processed with nonlinearities (such as correction, max(0,x)). Values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and can provide additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied by lateral inhibition between neurons in the feature map.

[0052] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are often trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms can further improve the performance of deep learning. Rectified linear units can reduce the training problem known as vanishing gradients. New training techniques can reduce overfitting, allowing larger models to achieve better generalization. Encapsulation techniques can extract data within a given receptive field and further improve overall performance.

[0053] Figure 3 is a block diagram illustrating a deep convolutional network 350. Based on connectivity and weight sharing, the deep convolutional network 350 may include multiple different types of layers. Figure 3 As shown, the deep convolution network 350 includes convolution blocks 354A and 354B. Each of the convolution blocks 354A and 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a maximum pooling layer (MAX POOL) 360.

[0054] The convolution layer 356 may include one or more convolution filters that may be applied to the input data to generate a feature map. Although only two convolution blocks 354A, 354B are shown, the present disclosure is not limited thereto, but instead, any number of convolution blocks 354A, 354B may be included in the deep convolution network 350 according to design preferences. The normalization layer 358 may normalize the output of the convolution filter. For example, the normalization layer 358 may provide whitening or lateral suppression. The maximum pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0055] For example, the parallel filter bank of the deep convolutional network may be loaded onto the CPU 102 or GPU 104 of the SOC 100 to achieve high performance and low power consumption. In an alternative embodiment, the parallel filter bank may be loaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the deep convolutional network 350 may access other processing blocks that may be present on the SOC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0056] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional network 350 may also include a logistic regression (LR) layer 364. There are weights (not shown) to be updated between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350. The output of each of these layers (e.g., 356, 358, 360, 362, 364) can be used as an input to a subsequent layer of these layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn a hierarchical feature representation from the input data 352 (e.g., image, audio, video, sensor data, and / or other input data) supplied at the first convolutional block 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 can be a set of probabilities, where each probability is a probability that the input data includes a feature from a set of features.

[0057] Figure 4 4 is a block diagram illustrating an exemplary software architecture 400 that can modularize artificial intelligence (AI) functions. According to aspects of the present disclosure, by using the architecture, an application can be designed that can enable various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of a system on chip (SOC) 420 to support adaptive rounding as disclosed for post-training quantization of AI application 402.

[0058] The AI ​​application 402 may be configured to call functions defined in the user space 404, which may, for example, provide detection and recognition of scenes indicating the current operating location of the device. For example, the AI ​​application 402 may configure the microphone and camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request for compiled program code associated with a library defined in the AI ​​function application programming interface (API) 406. The request may ultimately rely on the output of a deep neural network configured to provide an inferred response based on, for example, video and positioning data.

[0059] The runtime engine 408 (which may be compiled code of the runtime framework) may further be accessible to the AI ​​application 402. For example, the AI ​​application 402 may cause the runtime engine to request inference at a specific time interval or triggered by an event detected by the user interface of the application. When causing the runtime engine to provide an inference response, the runtime engine may in turn transmit a signal to the operating system in the operating system (OS) space (such as the Linux kernel 412) running on the SOC 420. The operating system may then cause continuous quantization relaxation to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed through drivers (such as drivers 414, 416, or 418 for the DSP 424, GPU 426, or NPU 428, respectively). In an exemplary example, the deep neural network may be configured to run on a combination of processing blocks (such as the CPU 422, DSP 424, and GPU 426), or may run on the NPU 428.

[0060] Application 402 (e.g., an AI application) can be configured to call functions defined in user space 404, which can, for example, provide detection and recognition of scenes indicating the current operating location of the device. For example, application 402 can configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. Application 402 can make a request to compiled program code associated with a library defined in a scene detection (SceneDetect) application programming interface (API) 406 to provide an estimate of the current scene. The request can ultimately rely on the output of a differential neural network configured to provide scene estimates based on, for example, video and positioning data.

[0061] The runtime engine 408 (which may be compiled code of a runtime framework) may further be accessible by the application 402. For example, the application 402 may cause the runtime engine to request scene estimation at a specific time interval or triggered by an event detected by the user interface of the application. Upon causing the runtime engine to estimate the scene, the runtime engine may then transmit a signal to an operating system 410 (such as a Linux kernel 412) running on the SOC 420. The operating system 410 may then cause the calculation to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed through drivers (such as drivers 414-418 for the DSP 424, GPU 426, or NPU 428, respectively). In an illustrative example, the differential neural network may be configured to run on a combination of processing blocks (such as the CPU 422 and GPU 426), or may run on the NPU 428.

[0062] As described, aspects of the present disclosure relate to a model performance profiler for improving the performance of an artificial neural network model. The model performance profiler can analyze an ANN model and a target hardware architecture and generate outputs including one or more model modifications to improve and in some cases optimize ANN model performance on the target hardware (e.g., improve processor efficiency and / or reduce power consumption).

[0063] Figure 5A is a high-level block diagram illustrating an example architecture 500 for improving model performance using a profiler according to aspects of the present disclosure. Figure 5A , the architecture 500 may include a neural network converter 504. The neural network converter 504 may be configured to convert the ANN model 502 into a different network model suitable for operation on the target hardware architecture. For example, the neural network converter 504 may convert a convolutional neural network (e.g., DCN 350) into another type of neural network model (e.g., a recurrent neural network, a transformer neural network, a generative adversarial neural network, or the like).

[0064] The architecture 500 may also include a model architecture performance profiler ("profiler") 510. The profiler 510 may be configured to analyze a neural network model (e.g., a model generated by the neural network converter 504) and a target hardware architecture and determine a set of modifications for improving model performance (e.g., increasing processor efficiency and / or reducing power consumption). In doing so, the profiler 510 may generate an output 514 that identifies certain portions of the neural network model (e.g., the input ANN model 502 or the converted model generated by the neural network converter 504), such as libraries, functions, model structures, and other neural network modifications.

[0065] In some aspects, the architecture 500 may also implement one or more of the modifications included in the output 514. That is, the architecture 500 may reconfigure the neural network model (e.g., the input ANN model 502 or the converted model produced by the neural network converter 504) based on the identified modifications. For example, the architecture may increase the number of input channels (not shown) in the input ANN model 502. To implement such modifications, the architecture 500 may also include a neural network model library generator 506, a neural network context binary generator 508, and a neural network run test module 512. The model library generator 506 may receive the output 514 and may generate a modified or reconfigured neural network model. The model library generator 506 may generate the modified or reconfigured neural network in an application programming interface (API) format that can be understood by a runtime engine. The modified or reconfigured neural network in the API format may be supplied to the context binary generator 508. The context binary generator 508 may generate binary code for executing the modified or reconfigured neural network. The output (e.g., binary code) of context binary generator 508 may then be supplied to neural network run test module 512, which may execute the modified or reconfigured neural network on the target hardware architecture. Advantageously, the modified or reconfigured neural network may have enhanced performance relative to input ANN model 502. For example, for a given task, the modified or reconfigured neural network (including the modifications identified in output 514) may have reduced latency or reduced power consumption compared to the input ANN model (or the converted model produced by neural network converter 504).

[0066] Figure 5B is a block diagram illustrating an example architecture of a model performance profiler 510 according to aspects of the present disclosure. Figure 5B , a model performance profiler (also referred to as a "profiler") 510 may be incorporated with the neural network converter 504. Alternatively, the profiler 510 may be included as a separate module. An ANN model 502 to be run on the target hardware may be received via the neural network converter 504. The ANN model 502 may be converted into a model that is preferred, for example, for the target hardware. In some aspects, the ANN model 502 may already be a desired model or best suited for use on the target platform. In this case, the ANN model 502 may not be converted.

[0067] The neural network converter 504 may include a conversion and quantization module 552 for converting and quantizing the ANN model 502 to produce a converted model 580. The neural network converter 504 may output class and binary outputs 554 and an object representation file 556 for the converted model 580. The class and binary outputs 554 may include C++ classes, functions, and objects of the converted model 580. The object representation file 556 may be, for example, a JavaScript object representation (.json) file and may include human-readable text including data objects, such as attribute-value pairs and arrays of the converted model 580. The class and binary outputs 554 and the object representation file 556 may be used to generate the converted model 580.

[0068] The parser 510 may include a parser 560, a class node pool 562, and a graph constraint module 564. The parser 560 may parse the object representation file 556 to generate a representation of the transformed model 580. The new representation may then be stored in the class node pool 562. The class node pool 562 may be supplied to the graph constraint module 564. Each of the nodes of the new representation of the transformed model 580 may be analyzed based on a set of rules for the target hardware via the graph constraint module 564. The set of rules may, for example, include certain constraints that, if violated, may affect model performance (e.g., processor efficiency and / or power consumption). The graph constraint module 564 may then generate an output 566 based on the set of rules for the target hardware, which identifies modifications to the transformed model 580 that may improve performance.

[0069] In some aspects, the neural network converter 504 may generate an intermediate representation operation graph 558. In this way, the analyzer 510 may apply the set of rules based on the pattern within the intermediate representation. The search module 568 may scan the intermediate representation operation graph (OpGraph) 558 to identify matches for the pattern it requested. Then, for each matching pattern in the matching pattern, the pattern constraint module 570 may apply the set of rules to identify the nodes associated with the matching pattern. The attribute lookup module 572 may determine the attribute name based on the category node pool 562. Then, the modification of the attribute corresponding to the identified node may be included in the output 566. In some aspects, the output 566 may be a human-readable file and may include, for example, an indication of the node name, input tensors, output tensors, a description of the problem or constraints violated, a suggested solution, and / or other modification information.

[0070] In some aspects, one or more of the modifications included in output 566 may be implemented on converted model 580 to produce an updated model with enhanced performance (eg, improved processing speed / efficiency and / or reduced power consumption).

[0071] FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8B as well as FIG. 9A to FIG. 9B is a diagram illustrating an example ANN model and corresponding output including modifications for improving model performance according to aspects of the present disclosure. Fig. 6A and Figure 6B , a parser (e.g., 510) may receive the ANN model 600 or a corresponding description or specification (e.g., object representation). The parser 510 may apply a set of rules corresponding to a target hardware architecture (e.g., NPU or tensor processor). Fig. 6A In the example of , the analyzer 510 can determine that the convolution nodes 602a-e each have a channel size specification that can hinder processing efficiency. Figure 6B , the analyzer 510 may then generate an output file 650 including modifications 652 to improve processing efficiency. For example, the output file 650 may include a suggestion to increase the channel size to 32. Specifically, the output 650 may, for example, indicate the graph / node name, input tensors, output tensors, suggestions, and additional parameters involved. Of course, this list is exemplary and non-limiting, and additional and / or different modification information may also be included.

[0072] In addition, the analyzer 510 can identify that each of the convolution nodes 602a-e includes 2x2 padding. Applying the set of rules for the target hardware, the analyzer 510 can also include in the output 650 a modification 654 that suggests padding before the convolution sequence (e.g., before node 602a). In addition, the analyzer 510 can suggest using effective or zero padding for subsequent convolution nodes (e.g., at 602b-e).

[0073] exist Fig. 7A and Figure 7B In an example of , the analyzer 510 may receive the ANN model 700 or a corresponding description or specification (e.g., an object representation). The analyzer 510 may apply a set of rules corresponding to a target hardware architecture (e.g., an NPU or a tensor processor). The analyzer 510 may determine that using the element-wise division function RealDiv 702 may violate the constraints specified in the set of rules. Therefore, the analyzer 510 may generate an output 750 that includes a modification 752 that recommends replacing RealDiv 702 with a multiply by reciprocal function.

[0074] exist Fig. 8A and Figure 8BIn an example of , the analyzer 510 may receive an ANN model 800 or a corresponding description or specification (e.g., an object representation). The analyzer 510 may apply a set of rules corresponding to a target hardware architecture (e.g., an NPU or a tensor processor). The analyzer 510 may determine that using a parameterized rectified linear unit (prelu) 802a-d may violate constraints specified in the set of rules. Therefore, the analyzer 510 may generate an output 850 that includes modifications 852a-d that recommend replacing the prelu 802a-d with a rectified linear unit.

[0075] exist Fig.9A and Fig. 9B In an example of , the analyzer 510 may receive the ANN model 900 or a corresponding description or specification (e.g., an object representation). The analyzer 510 may apply a set of rules corresponding to a target hardware architecture (e.g., an NPU or a tensor processor). The analyzer 510 may determine that using the transpose node 902 may violate the constraints specified in the set of rules. Therefore, the analyzer 510 may generate an output 950 that includes a modification 952 that recommends removing the transpose node 902.

[0076] Fig.10 1 is a flow chart illustrating a processor-implemented method 1000 of identifying modifications for improving the performance of an artificial neural network (ANN) in accordance with aspects of the present disclosure. Fig.10 As shown in FIG. 1 , at block 1002, a processor-implemented method 1000 receives an ANN model to run on a target hardware architecture. Figure 5A and Figure 5B As shown in , a profiler 510 may receive an ANN model 502 to be run on target hardware. In some aspects, the ANN model 502 may be converted to a different neural network model that is preferred for the target hardware, for example, via a neural network converter 504. In some aspects, the ANN model 502 may already be the desired model or best suited for use on the target platform. In this case, the ANN model 502 may not be converted.

[0077] At block 1004, the processor-implemented method 1000 analyzes the ANN model based on a set of rules associated with the target hardware architecture. Figure 5A As described, the analyzer 510 can be configured to analyze a neural network model (e.g., a model generated by the neural network converter 504) and a target hardware architecture and determine a set of modifications for improving model performance (e.g., improving processor efficiency and / or reducing power consumption). In addition, the analyzer can compare the received neural network model (e.g., ANN model 502 or a neural network model generated via the converter 504) with a set of rules specified for the target hardware architecture.

[0078] At block 1006, the processor-implemented method 1000 generates an output based on the set of rules, the output comprising one or more modifications to the ANN model. Figure 5A As described, the analyzer 510 may generate an output 514 that identifies certain portions of a neural network model (e.g., the input ANN model 502 or a converted model generated by the neural network converter 504), such as libraries, functions, model structures, and other neural network modifications.

[0079] At block 1008, the processor-implemented method 1000 may optionally implement at least one of the one or more modifications in the ANN model to generate an updated model. Figure 5A As described, the architecture 500 may also implement one or more of the modifications included in the output 514. That is, the architecture 500 may reconfigure the neural network model (e.g., the input ANN model 502 or the converted model produced by the neural network converter 504) based on the identified modifications. For example, the architecture may increase the number of input channels (not shown) in the input ANN model 502. To implement such modifications, the architecture 500 may also include a neural network model library generator 506, a neural network context binary generator 508, and a neural network run test module 512. The model library generator 506 may receive the output 514 and may generate a modified or reconfigured neural network model. The model library generator 506 may generate the modified or reconfigured neural network in an application programming interface (API) format that can be understood by a runtime engine. The modified or reconfigured neural network in the API format may be supplied to the context binary generator 508. The context binary generator 508 may generate binary code for executing the modified or reconfigured neural network. The output (e.g., binary code) of context binary generator 508 may then be supplied to neural network run test module 512, which may execute the modified or reconfigured neural network on the target hardware architecture. Advantageously, the modified or reconfigured neural network may have enhanced performance relative to input ANN model 502. For example, the modified or reconfigured neural network (including the modifications identified in output 514) may have reduced latency or reduced power consumption for a given task compared to the input ANN model (or the converted model produced by neural network converter 504).

[0080] Specific implementation examples are described in the following numbered clauses:

[0081] 1. A processor-implemented method, the processor-implemented method comprising:

[0082] receiving an artificial neural network (ANN) model to run on a target hardware architecture;

[0083] analyzing the ANN model based on a set of rules associated with the target hardware architecture; and

[0084] An output is generated based on the set of rules, the output comprising one or more modifications to the ANN model.

[0085] 2. The processor-implemented method of clause 1, further comprising implementing at least one of the one or more modifications in the ANN model to generate an updated model.

[0086] 3. A processor-implemented method according to clause 1 or 2, further comprising operating the updated model on the target hardware architecture to generate inferences.

[0087] 4. A processor-implemented method according to any one of clauses 1 to 3, further comprising:

[0088] Parsing a representation of the ANN model;

[0089] determining a set of nodes corresponding to the representation; and

[0090] A set of constraints is applied to each node in the set of nodes based on the set of rules.

[0091] 5. A processor-implemented method according to any one of clauses 1 to 4, the processor-implemented method further comprising:

[0092] receiving a graphical representation of the ANN model;

[0093] identifying one or more patterns within the graphical representation;

[0094] applying the set of rules to the one or more patterns to determine nodes associated with the one or more patterns; and

[0095] Modifications to the nodes associated with the one or more patterns are output.

[0096] 6. A device, comprising:

[0097] Memory; and

[0098] at least one processor, the at least one processor coupled to the memory, the at least one processor configured to:

[0099] receiving an artificial neural network (ANN) model to run on a target hardware architecture;

[0100] analyzing the ANN model based on a set of rules associated with the target hardware architecture; and

[0101] An output is generated based on the set of rules, the output comprising one or more modifications to the ANN model.

[0102] 7. The apparatus of clause 6, wherein the at least one processor is further configured to implement at least one of the one or more modifications in the ANN model to generate an updated model.

[0103] 8. An apparatus according to clause 6 or 7, wherein the at least one processor is further configured to operate the updated model on the target hardware architecture to generate inferences.

[0104] 9. An apparatus according to any of clauses 6 to 8, wherein the at least one processor is further configured to:

[0105] parsing a representation of the ANN model;

[0106] determining a set of nodes corresponding to the representation; and

[0107] A set of constraints is applied to each node in the set of nodes based on the set of rules.

[0108] 10. An apparatus according to any of clauses 6 to 9, wherein the at least one processor is further configured to:

[0109] receiving a graphical representation of the ANN model;

[0110] identifying one or more patterns within the graphical representation;

[0111] applying the set of rules to the one or more patterns to determine nodes associated with the one or more patterns; and

[0112] Modifications to the nodes associated with the one or more patterns are output.

[0113] 11. A non-transitory computer readable medium having program code recorded thereon, the program code being executed by a processor and comprising:

[0114] program code for receiving an artificial neural network (ANN) model to run on a target hardware architecture;

[0115] program code for analyzing the ANN model based on a set of rules associated with the target hardware architecture; and

[0116] Program code for generating an output based on the set of rules, the output comprising one or more modifications to the ANN model.

[0117] 12. The non-transitory computer-readable medium of clause 11, wherein the program code further comprises program code for implementing at least one of the one or more modifications in the ANN model to generate an updated model.

[0118] 13. The non-transitory computer-readable medium of clause 11 or 12, wherein the program code further comprises program code for operating the updated model on the target hardware architecture to generate inferences.

[0119] 14. The non-transitory computer readable medium of any one of clauses 11 to 13, wherein the program code further comprises:

[0120] Program code for parsing a representation of the ANN model;

[0121] program code for determining a set of nodes corresponding to the representation; and

[0122] Program code for applying a set of constraints to each node in the set of nodes based on the set of rules.

[0123] 15. The non-transitory computer readable medium of any one of clauses 11 to 14, wherein the program code further comprises:

[0124] program code for receiving a graphical representation of the ANN model;

[0125] program code for identifying one or more patterns within the graphical representation;

[0126] program code for applying the set of rules to the one or more patterns to determine nodes associated with the one or more patterns; and

[0127] Program code for outputting modifications to the node associated with the one or more patterns.

[0128] 16. A device, comprising:

[0129] means for receiving an artificial neural network (ANN) model for execution on a target hardware architecture;

[0130] for analyzing the target hardware architecture based on a set of rules associated with the target hardware architecture

[0131] Components of the ANN model; and

[0132] Means for generating an output based on the set of rules, the output comprising one or more modifications to the ANN model.

[0133] 17. The apparatus of clause 16, further comprising means for implementing at least one of the one or more modifications in the ANN model to generate an updated model.

[0134] 18. An apparatus according to clause 16 or 17, further comprising means for operating the updated model on the target hardware architecture to generate inferences.

[0135] 19. The apparatus according to any one of clauses 16 to 18, further comprising:

[0136] means for parsing a representation of said ANN model;

[0137] means for determining a set of nodes corresponding to the representation; and

[0138] Means for applying a set of constraints to each node in the set of nodes based on the set of rules.

[0139] 20. The apparatus according to any of clauses 16 to 19, further comprising:

[0140] means for receiving a graphical representation of said ANN model;

[0141] means for identifying one or more patterns within said graphical representation;

[0142] means for applying the set of rules to the one or more patterns to determine nodes associated with the one or more patterns; and

[0143] Means for outputting modifications to the node associated with the one or more patterns.

[0144] In one aspect, the receiving means, analyzing means, generating means, determining means and / or operating means may be the GPU 104, a program memory associated with the GPU 104, the fully connected layer 362, the NPU 428 and / or the routing connection processing unit 216 configured to perform the recited functions. In another configuration, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

[0145] The various operations of the above methods may be performed by any suitable components capable of performing the corresponding functions. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where operations are illustrated in the accompanying drawings, these operations may have corresponding paired components plus function components with similar numbers.

[0146] As used, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, and the like. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0147] As used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0148] The various illustrative logical blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0149] The steps or algorithms of the methods described in conjunction with the present disclosure may be directly embodied in hardware, software modules executed by a processor, or a combination of the two. The software module may reside in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction, perhaps multiple instructions, and may be distributed over several different code segments, distributed between different programs, and distributed across multiple storage media. The storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative solution, the storage medium may be integral with the processor.

[0150] The disclosed methods include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchanged with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0151] The functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link various circuits together, including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus. The network adapter may be used to implement signal processing functions. For some aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0152] The processor may be responsible for managing the bus and general processing, including executing software stored on the machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Software should be broadly interpreted as meaning instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. By way of example, a machine-readable medium may include a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a disk, an optical disk, a hard disk drive, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may include packaging materials.

[0153] In hardware implementation, machine-readable media can be a part of a processing system separated from a processor. However, as will be readily appreciated by those skilled in the art, machine-readable media or any part thereof can be outside a processing system. By way of example, machine-readable media can include a transmission line, a carrier wave modulated by data, and / or a computer product separated from a device, all of which can be accessed by a processor through a bus interface. Alternatively or in addition thereto, machine-readable media or any part thereof can be integrated into a processor, such as with a cache and / or a general register stack. Although the various components discussed can be described as having specific locations, such as local components, they can also be configured in various ways, such as certain components being configured as a part of a distributed computing system.

[0154] The processing system can be configured as a general processing system having one or more microprocessors providing processor functionality and an external memory providing at least a portion of a machine-readable medium, all of which are linked together with other supporting circuit systems through an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and neural system model. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) having at least a portion of a processor, a bus interface, a user interface, a support circuit, and a machine-readable medium integrated in a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuits, or circuits capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how to best implement the functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0155] The machine-readable medium may include multiple software modules. These software modules include instructions that cause the processing system to perform various functions when executed by the processor. The software module may include a sending module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, when a triggering event occurs, the software module may be loaded from a hard drive into a RAM. During the execution of the software module, the processor may load some of the instructions into a cache to increase access speed. Then one or more cache lines may be loaded into a general register stack for execution by the processor. When the functionality of a software module is mentioned below, it will be understood that such functionality is implemented by the processor when executing instructions from the software module. In addition, it should be understood that various aspects of the present disclosure produce improvements in the functionality of processors, computers, machines, or other systems that implement such aspects.

[0156] If implemented in software, each function can be stored on a computer-readable medium or sent by it as one or more instructions or codes.Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transmission of a computer program from one place to another.Storage media can be any available medium that can be accessed by a computer.By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices, or may be used to carry or store the desired program code in the form of an instruction or data structure and any other medium that can be accessed by a computer.In addition, any connection is also appropriately referred to as computer-readable media.For example, if software is sent from a website, server or other remote source using a coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared (IR), radio and microwaves, then the coaxial cable, optical cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray Optical disks, where magnetic disks typically reproduce data magnetically, and optical disks reproduce data optically with lasers. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Additionally, for other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0157] Thus, some aspects may include a computer program product for performing the operations presented. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) thereon instructions that can be executed by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging materials.

[0158] In addition, it should be understood that the modules and / or other appropriate components for performing the described methods and techniques can be downloaded and / or otherwise obtained by the user terminal and / or base station where applicable. For example, such a device can be coupled to a server to facilitate the transmission of the components for performing the described methods. Alternatively, the various methods described can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk) so that once the storage component is coupled to or provided to the device, the user terminal and / or base station can obtain the various methods. In addition, any other suitable technology suitable for providing the described methods and techniques to the device can be used.

[0159] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A processor-implemented method, the processor-implemented method comprising: receiving an artificial neural network (ANN) model to run on a target hardware architecture; analyzing the ANN model based on a set of rules associated with the target hardware architecture; as well as An output is generated based on the set of rules, the output comprising one or more modifications to the ANN model.

2. The processor-implemented method of claim 1 , further comprising implementing at least one of the one or more modifications in the ANN model to generate an updated model.

3. The processor-implemented method of claim 2 , further comprising operating the updated model on the target hardware architecture to generate inferences.

4. The processor-implemented method of claim 1 , further comprising: parsing a representation of the ANN model; determining a set of nodes corresponding to the representation; as well as A set of constraints is applied to each node in the set of nodes based on the set of rules.

5. The processor-implemented method of claim 1 , further comprising: receiving a graphical representation of the ANN model; identifying one or more patterns within the graphical representation; applying the set of rules to the one or more patterns to determine nodes associated with the one or more patterns; as well as Modifications to the nodes associated with the one or more patterns are output.

6. A device, comprising: Memory; and at least one processor, the at least one processor coupled to the memory, the at least one processor configured to: receiving an artificial neural network (ANN) model to run on a target hardware architecture; analyzing the ANN model based on a set of rules associated with the target hardware architecture; and An output is generated based on the set of rules, the output comprising one or more modifications to the ANN model.

7. The apparatus of claim 6, wherein the at least one processor is further configured to implement at least one of the one or more modifications in the ANN model to generate an updated model.

8. The apparatus of claim 7, wherein the at least one processor is further configured to operate the updated model on the target hardware architecture to generate inferences.

9. The apparatus of claim 6, wherein the at least one processor is further configured to: parsing a representation of the ANN model; determining a set of nodes corresponding to the representation; and A set of constraints is applied to each node in the set of nodes based on the set of rules.

10. The apparatus of claim 6, wherein the at least one processor is further configured to: receiving a graphical representation of the ANN model; identifying one or more patterns within the graphical representation; applying the set of rules to the one or more patterns to determine nodes associated with the one or more patterns; and Modifications to the nodes associated with the one or more patterns are output.

11. A non-transitory computer readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code for receiving an artificial neural network (ANN) model to run on a target hardware architecture; program code for analyzing the ANN model based on a set of rules associated with the target hardware architecture; and Program code for generating an output based on the set of rules, the output comprising one or more modifications to the ANN model.

12. The non-transitory computer readable medium of claim 11, wherein the program code further comprises program code for implementing at least one of the one or more modifications in the ANN model to generate an updated model.

13. The non-transitory computer readable medium of claim 12, wherein the program code further comprises program code for operating the updated model on the target hardware architecture to generate inferences.

14. The non-transitory computer readable medium of claim 11, wherein the program code further comprises: Program code for parsing a representation of the ANN model; program code for determining a set of nodes corresponding to the representation; and Program code for applying a set of constraints to each node in the set of nodes based on the set of rules.

15. The non-transitory computer readable medium of claim 11, wherein the program code further comprises: program code for receiving a graphical representation of the ANN model; program code for identifying one or more patterns within the graphical representation; program code for applying the set of rules to the one or more patterns to determine nodes associated with the one or more patterns; and Program code for outputting modifications to the node associated with the one or more patterns.

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