Display substrate and display device

Abstract

A display substrate is provided. The display substrate comprises a planarization layer; the light-emitting element is located on the planarization layer and comprises a first electrode, an organic layer located on the first electrode and a second electrode located on the side, away from the first electrode, of the organic layer; an auxiliary electrode located in a different layer from the second electrode; one or more first connection structures electrically connecting the auxiliary electrode and the second electrode, respectively; and one or more second connection structures electrically connecting the auxiliary electrode and the second electrode, respectively, wherein each of the one or more first connection structures comprises a conductive channel, and the conductive channel comprises a sintered conductive material; and the one or more second connection structures do not include the conductive channel.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a display substrate and a display device. Background Art

[0002] In recent years, more and more technology companies have focused on the development of transparent displays. For example, transparent displays have been used for store window displays. Viewers can not only see the information displayed on the transparent display screen, but also see the objects behind the transparent display. Both the real product and the product-related information on the screen can be presented at the same time, so that customers can understand the full content of the product information and get a better display experience. Transparent display panels have been used for vehicle displays and various other commercial scenarios, such as window displays in hotel or department store environments. Transparent display panels have the advantages of good display quality and high-realistic display effects. Summary of the invention

[0003] In a first aspect, the present disclosure provides a display substrate, comprising: a planarization layer; a light-emitting element located on the planarization layer, comprising a first electrode, an organic layer located on the first electrode, and a second electrode located on a side of the organic layer away from the first electrode; an auxiliary electrode, which is located in a different layer from the second electrode; one or more first connection structures, which electrically connect the auxiliary electrode to the second electrode respectively; and one or more second connection structures, which electrically connect the auxiliary electrode to the second electrode respectively; wherein each of the one or more first connection structures comprises a conductive path, the conductive path comprises a sintered conductive material; and the conductive path is not included in the one or more second connection structures.

[0004] In some embodiments of the present disclosure, the display substrate includes a light-emitting area and a transparent area; wherein the one or more first connection structures and the one or more second connection structures are located in the transparent area.

[0005] In some embodiments of the present disclosure, each first connecting structure is separated from the light-emitting area by a first shortest distance; each second connecting structure among the one or more second connecting structures is separated from the light-emitting area by a second shortest distance; and the first shortest distance is greater than the second shortest distance.

[0006] In some embodiments of the present disclosure, the display substrate also includes a planarization layer extending at least partially in the light-emitting area; wherein the orthographic projection of the planarization layer on the base substrate does not overlap with the orthographic projection of each first connecting structure on the base substrate, but at least partially overlaps with the orthographic projection of each second connecting structure on the base substrate.

[0007] In some embodiments of the present disclosure, each first connection structure includes a structure stacked in sequence, which includes a connecting electrode, a portion of the organic layer located on the connecting electrode, and a portion of the second electrode, which is located on a side of the portion of the organic layer away from the connecting electrode.

[0008] In some embodiments of the present disclosure, the sintered conductive material includes at least one of the organic material of the portion of the organic layer, the conductive material of the connecting electrode, or the conductive material of the portion of the second electrode.

[0009] In some embodiments of the present disclosure, the sintered conductive material includes the organic material of the portion of the organic layer, the conductive material of the connecting electrode, and the conductive material of the portion of the second electrode.

[0010] In some embodiments of the present disclosure, the auxiliary electrode is located on a side of the connecting electrode away from the organic layer; the second electrode is connected to the connecting electrode through the conductive channel, and further connected to the auxiliary electrode through the connecting electrode; and the auxiliary electrode extends at least partially in one or more sub-pixels.

[0011] In some embodiments of the present disclosure, each of the one or more second connection structures includes a first connection electrode, a second connection electrode, and a third connection electrode stacked in sequence; wherein the second electrode is in direct contact with at least one of the first connection electrode, the second connection electrode, or the third connection electrode.

[0012] In some embodiments of the present disclosure, the auxiliary electrode is located on a side of the first connecting electrode away from the second connecting electrode; the first connecting electrode extends through a via to connect to the auxiliary electrode; and the auxiliary electrode extends at least partially in one or more sub-pixels.

[0013] In some embodiments of the present disclosure, the display substrate also includes a pixel defining layer surrounding the sub-pixel area; the orthographic projection of the planarization layer on the base substrate at least partially overlaps with the orthographic projection of the pixel defining layer on the base substrate; and the orthographic projection of the pixel defining layer on the base substrate does not overlap with the orthographic projection of the second connecting electrode on the base substrate, and does not overlap with the orthographic projection of the third connecting electrode on the base substrate.

[0014] In some embodiments of the present disclosure, the second electrode extends from the light emitting area, across the pixel defining layer, into the transparent area to directly contact at least one of the first connecting electrode, the second connecting electrode, or the third connecting electrode.

[0015] In some embodiments of the present disclosure, each second connection structure also includes at least one of the following: a remaining organic layer, which is stacked on a side of the third connection electrode away from the second connection electrode, the remaining organic layer is located in the same layer as the organic layer and is at least partially separated from the organic layer; or a remaining second electrode, which is stacked on a side of the remaining organic layer away from the third connection electrode, the remaining second electrode is located in the same layer as the second electrode and is at least partially separated from the second electrode.

[0016] In some embodiments of the present disclosure, the first electrode includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence; the first sublayer and the first connecting electrode are located in the same layer and are separated from each other by a pixel defining layer; the second sublayer and the second connecting electrode are located in the same layer and are separated from each other by the pixel defining layer; and the third sublayer and the third connecting electrode are located in the same layer and are separated from each other by the pixel defining layer.

[0017] In some embodiments of the present disclosure, the display substrate also includes one or more dummy structures; wherein each of the one or more dummy structures includes a structure stacked in sequence, which includes a connecting electrode, a portion of the organic layer located on the connecting electrode, and a portion of the second electrode, which is located on a side of the portion of the organic layer away from the connecting electrode; each dummy structure does not include a conductive path connecting the portion of the second electrode and the auxiliary electrode; and the portion of the second electrode is electrically isolated from the auxiliary electrode.

[0018] In some embodiments of the present disclosure, the ratio of the number of the one or more second connection structures to the number of the one or more first connection structures in the display substrate is greater than or equal to 0.9:1.0.

[0019] In some embodiments of the present disclosure, a ratio of the number of the one or more second connection structures to the number of the one or more first connection structures in the display substrate is in a range of 0.9:1.0 to 1.0:0.9.

[0020] In some embodiments of the present disclosure, the display substrate includes a plurality of first repeating units and a plurality of second repeating units; each of the plurality of first repeating units includes at least one first connecting structure among the one or more first connecting structures and at least one second connecting structure among the one or more second connecting structures; each of the second repeating units includes at least one dummy structure among one or more dummy structures and at least one second connecting structure among the one or more second connecting structures; each of the plurality of first repeating units includes the conductive path, while each of the plurality of second repeating units does not include the conductive path.

[0021] In some embodiments of the present disclosure, in a row of repeating units, the first repeating units and the second repeating units are arranged alternately; and in a column of repeating units, the first repeating units and the second repeating units are arranged alternately.

[0022] In a second aspect, the present disclosure provides a display device including the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the invention.

[0024] Figure 1 is a schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure.

[0025] Figure 2 is a cross-sectional view of a display substrate in some embodiments according to the present disclosure.

[0026] Figure 3 is a schematic diagram showing the structure of a connection structure in some embodiments according to the present disclosure.

[0027] Figure 4 is a cross-sectional view of a display substrate in some embodiments according to the present disclosure.

[0028] Figure 5 is a schematic diagram showing the structure of a connection structure in some embodiments according to the present disclosure.

[0029] Figure 6 is a cross-sectional view of a display substrate in some embodiments according to the present disclosure.

[0030] Figure 7 is a schematic diagram showing the structure of a connection structure in some embodiments according to the present disclosure.

[0031] Figure 8 is a schematic diagram showing the structure of a connection structure in some embodiments according to the present disclosure.

[0032] Fig. 9A is a cross-sectional view of a connection structure according to some embodiments of the present disclosure.

[0033] Fig. 9B is a cross-sectional view of a connection structure according to some embodiments of the present disclosure.

[0034] Fig. 10A The structure of a portion of a display substrate in some embodiments of the present disclosure is shown.

[0035] Fig. 10B Shows Fig. 10A The structure of the light shielding layer in a portion of the display substrate shown in FIG.

[0036] Fig. 10C Shows Fig. 10A The structure of the semiconductor material layer in a portion of the display substrate is shown in FIG.

[0037] Fig. 10D Shows Fig. 10A The structure of the gate layer in a portion of the display substrate is shown in FIG.

[0038] Fig. 10E Shows Fig. 10A The structure of the signal line layer in a portion of the display substrate shown in FIG.

[0039] Fig.10F Shows Fig. 10A The structure of the planarization layer in a portion of the display substrate is shown in FIG.

[0040] Figure 10G Shows Fig. 10A The structure of the first conductive layer in a portion of the display substrate is shown in FIG.

[0041] Fig. 10H Shows Fig. 10A The structure of the second conductive layer in a portion of the display substrate is shown in FIG.

[0042] Fig.10I Shows Fig. 10A . The structure of the third conductive layer in a portion of the display substrate is shown in FIG.

[0043] Fig.10J Shows Fig. 10A The structure of a pixel defining layer in a portion of a display substrate shown in FIG.

[0044] Figure 10K Shows Fig. 10A The structure of the black matrix layer in a portion of the display substrate shown in FIG.

[0045] Fig.11A Shows Fig. 10A The structure of the planarization layer and the signal line layer in a portion of the display substrate shown in FIG.

[0046] Fig. 11B The structure of the auxiliary electrode in some embodiments according to the present disclosure is shown.

[0047] Fig. 11C Shows Fig. 10A The structure of the gate layer and the signal line layer in a portion of the display substrate shown in FIG.

[0048] Fig.11D The structure of the auxiliary electrode in some embodiments according to the present disclosure is shown.

[0049] Fig.11E The structure of the pixel defining layer and the auxiliary electrode in some embodiments according to the present disclosure is shown.

[0050] Fig.11F The structure of the auxiliary electrode in some embodiments according to the present disclosure is shown.

[0051] Fig.11G The structure of the auxiliary electrode and multiple connection structures in some embodiments of the present disclosure are shown.

[0052] Fig.11H The structures of a planarization layer, an auxiliary electrode, and a plurality of connection structures in some embodiments of the present disclosure are shown.

[0053] Fig. 12A The structure of a planarization layer in a portion of a display substrate in some embodiments according to the present disclosure is shown.

[0054] Fig. 12B The structure of a planarization layer and a signal line layer in a portion of a display substrate in some embodiments according to the present disclosure is shown.

[0055] Fig. 12C The structures of a planarization layer, an auxiliary electrode, and a plurality of connection structures in some embodiments of the present disclosure are shown.

[0056] Fig.13A The structure of a planarization layer in a portion of a display substrate in some embodiments according to the present disclosure is shown.

[0057] Fig. 13B The structure of a planarization layer and a signal line layer in a portion of a display substrate in some embodiments according to the present disclosure is shown.

[0058] Fig. 13C The structures of a planarization layer, an auxiliary electrode, and a plurality of connection structures in some embodiments of the present disclosure are shown.

[0059] Fig.14 is a circuit diagram of a pixel driving circuit in a portion of a display substrate in some embodiments according to the present disclosure.

[0060] Fig.15 is a schematic diagram showing the structure of a corresponding first connection structure in some embodiments of the present disclosure.

[0061] Fig.16 is a schematic diagram showing the structure of a corresponding second connection structure in some embodiments of the present disclosure.

[0062] Fig.17 is a schematic diagram of a portion of a display substrate according to some embodiments of the present disclosure.

[0063] Fig.18 is a circuit diagram of a pixel driving circuit in a portion of a display substrate in some embodiments according to the present disclosure.

[0064] Fig.19 is a schematic diagram showing the structure of a corresponding dummy structure in some embodiments of the present disclosure.

[0065] Fig. 20 is a schematic diagram showing the structure of a corresponding second connection structure in some embodiments of the present disclosure.

[0066] Fig.21 is a schematic diagram of a portion of a display substrate according to some embodiments of the present disclosure.

[0067] Fig. 22 The values ​​of voltage drop in the display substrate having different ratios of the number of second connection structures to the number of first connection structures according to some embodiments of the present disclosure are shown.

[0068] Fig.23 is a schematic diagram showing the layout of a display substrate in some embodiments according to the present disclosure.

[0069] Fig.24 is a schematic diagram showing the layout of a display substrate in some embodiments according to the present disclosure.

[0070] Fig.25 is a schematic diagram showing the layout of a display substrate in some embodiments according to the present disclosure. DETAILED DESCRIPTION

[0071] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0072] The present disclosure particularly provides a display substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides a display substrate. In some embodiments, the display substrate includes a planarization layer; a light-emitting element located on the planarization layer, which includes a first electrode, an organic layer located on the first electrode, and a second electrode located on a side of the organic layer away from the first electrode; an auxiliary electrode, which is located in a different layer from the second electrode; one or more first connection structures, which electrically connect the auxiliary electrode to the second electrode respectively; and one or more second connection structures, which electrically connect the auxiliary electrode to the second electrode respectively. Optionally, each of the one or more first connection structures includes a conductive path, and the conductive path includes a sintered conductive material. Optionally, the conductive path is not included in the one or more second connection structures.

[0073] Figure 1 Schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure. Figure 1 , the display substrate includes a sub-pixel region SR and an inter-sub-pixel region ISR. As used herein, the sub-pixel region refers to the light-emitting region of the sub-pixel, such as a region corresponding to a pixel electrode in a liquid crystal display substrate, a region corresponding to a light-emitting layer in a light-emitting diode display substrate. Optionally, the pixel may include a plurality of separate light-emitting regions corresponding to a plurality of sub-pixels in the pixel. Optionally, the sub-pixel region is a light-emitting region of a red sub-pixel. Optionally, the sub-pixel region is a light-emitting region of a green sub-pixel. Optionally, the sub-pixel region is a light-emitting region of a blue sub-pixel. Optionally, the sub-pixel region is a light-emitting region of a white sub-pixel.

[0074] As used herein, the inter-subpixel region refers to the region between adjacent sub-pixel regions, such as the region corresponding to the black matrix in the liquid crystal display, the region corresponding to the pixel defining layer or the black matrix in the organic light emitting diode display panel. Optionally, the inter-subpixel region is the region between adjacent sub-pixel regions in the same pixel. Optionally, the inter-subpixel region is the region between two adjacent sub-pixel regions in two adjacent pixels. Optionally, the inter-subpixel region is the region between the sub-pixel region of the red sub-pixel and the sub-pixel region of the adjacent green sub-pixel. Optionally, the inter-subpixel region is the region between the sub-pixel region of the red sub-pixel and the sub-pixel region of the adjacent blue sub-pixel. Optionally, the inter-subpixel region is the region between the sub-pixel region of the green sub-pixel and the sub-pixel region of the adjacent blue sub-pixel.

[0075] Reference Figure 1, the display substrate includes a light emitting element LE located in a sub-pixel region SR and a connection structure CS located in an inter-sub-pixel region ISR. The connection structure CS can be disposed at any appropriate position in the inter-sub-pixel region ISR. In one example, the display substrate includes a plurality of pixels px. Each pixel in the plurality of pixels px includes one or more sub-pixels, for example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel. In another example, the connection structure CS is disposed in the inter-sub-pixel region ISR between two sub-pixels located between two adjacent pixels in the plurality of pixels px, such as Figure 1 In another example, the connection structure CS is disposed in the inter-sub-pixel region ISR between two sub-pixels of the same pixel among the plurality of pixels px.

[0076] Figure 2 is a cross-sectional view of a display substrate in some embodiments of the present disclosure. For example, Figure 2 Can be along Figure 1 The cross-sectional view of the display substrate taken along the line AA' is shown. Figure 2 In some embodiments, the display substrate includes a planarization layer PLN; a light emitting element LE located on the planarization layer PLN and located in the sub-pixel region SR; and a connection structure CS located in the inter-sub-pixel region ISR.

[0077] In some embodiments, the light emitting element LE includes a first electrode E1 (e.g., an anode), an organic layer OL located on the first electrode E1, and a second electrode E2 (e.g., a cathode) located on a side of the organic layer OL away from the first electrode E1. The organic layer OL may include one or more organic material layers. In one example, the organic layer OL includes a light emitting layer. In another example, the organic layer OL further includes at least one of a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, an electron injection layer, or a charge generation layer.

[0078] In some embodiments, the display substrate further comprises an auxiliary electrode AE ​​located at a different layer from the second electrode E2, and the auxiliary electrode AE ​​is electrically connected to the second electrode E2. Optionally, the connection structure CS electrically connects the auxiliary electrode AE ​​and the second electrode E2.

[0079] In some embodiments, the planarization layer PLN is a layer of insulating material that is in direct contact with at least a portion of the first electrode E1. By planarizing the surface of the substrate before forming each layer on the planarization layer PLN, it is facilitated to form each layer on the planarization layer PLN. The planarization layer PLN extends at least partially in the sub-pixel region SR. Optionally, the planarization layer PLN extends at least partially in the sub-pixel region SR and at least partially in the inter-sub-pixel region ISR.

[0080] Various suitable insulating materials and various suitable manufacturing methods can be used to manufacture the planarization layer PLN. For example, the insulating material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process or a sputtering process (e.g., a magnetron sputtering process). Examples of suitable insulating materials include various suitable resin materials, polyimide, silicon oxide (SiOy), silicon nitride (SiNy, such as Si3N4), and silicon oxynitride (SiOxNy).

[0081] Figure 3 Schematic diagram showing the structure of a connection structure according to some embodiments of the present disclosure. Figure 3 In some embodiments, the connection structure includes a first connection electrode CE1, a second connection electrode CE2, and a third connection electrode CE3 stacked in sequence. In one example, the first connection electrode CE1 is in direct contact with the second connection electrode CE2, and the second connection electrode CE2 is in direct contact with the third connection electrode CE3. The second connection electrode CE2 connects the first connection electrode CE1 and the third connection electrode CE3.

[0082] Various suitable conductive electrode materials and various suitable manufacturing methods can be used to manufacture the connecting electrode. For example, the conductive electrode material can be deposited on the substrate by, for example, sputtering or vapor deposition, and patterned by, for example, photolithography (such as a wet etching process) to form a connecting electrode. Examples of suitable conductive electrode materials include, but are not limited to, metal conductive electrode materials and non-metallic conductive electrode materials. Examples of suitable metal conductive electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates thereof. Examples of suitable non-metallic conductive electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide.

[0083] In one example, the first connection electrode CE1 and the third connection electrode CE3 are made of indium tin oxide. In another example, the second connection electrode CE2 is made of a reflective electrode material such as aluminum alloy.

[0084] Various suitable conductive electrode materials and various suitable manufacturing methods can be used to manufacture the first electrode E1. For example, the conductive electrode material can be deposited on the substrate by, for example, sputtering or vapor deposition, and patterned by, for example, photolithography (such as a wet etching process) to form a connecting electrode. Examples of suitable conductive electrode materials include, but are not limited to, metal conductive electrode materials and non-metallic conductive electrode materials. Examples of suitable metal conductive electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates thereof. Examples of suitable non-metallic conductive electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide.

[0085] In some embodiments, the first electrode E1 includes a plurality of sub-layers. Optionally, the first electrode E1 includes a first sub-layer SUB1, a second sub-layer SUB2 and a third sub-layer SUB3 stacked in sequence.

[0086] In one example, the first sublayer SUB1 and the third sublayer SUB3 are made of indium tin oxide. In another example, the second sublayer SUB2 is made of a reflective electrode material (eg, aluminum alloy).

[0087] In some embodiments, the first sublayer SUB1 and the first connection electrode CE1 are located in the same layer; the second sublayer SUB2 and the second connection electrode CE2 are located in the same layer; and the third sublayer SUB3 and the third connection electrode CE3 are located in the same layer. Optionally, the first sublayer SUB1 and the first connection electrode CE1 are separated from each other, for example, by a pixel defining layer PDL; the second sublayer SUB2 and the second connection electrode CE2 are separated from each other, for example, by a pixel defining layer PDL; and the third sublayer SUB3 and the third connection electrode CE3 are separated from each other, for example, by a pixel defining layer PDL.

[0088] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the first sublayer SUB1 and the first connection electrode CE1 are formed due to one or more steps of the same patterning process performed in the same material layer deposited in the same deposition process, the first sublayer SUB1 and the first connection electrode CE1 are located in the same layer. In another example, the first sublayer SUB1 and the first connection electrode CE1 may be formed in the same layer by simultaneously performing the step of forming the first sublayer SUB1 and the step of forming the first connection electrode CE1. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0089] Various suitable conductive electrode materials and various suitable manufacturing methods can be used to manufacture the second electrode E2. For example, the conductive electrode material can be deposited on the substrate by, for example, sputtering or vapor deposition, and patterned by, for example, photolithography (such as a wet etching process) to form a connecting electrode. Examples of suitable conductive electrode materials for manufacturing the second electrode E2 include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide. In one example, the second electrode E2 is made of indium zinc oxide.

[0090] In some embodiments, the second electrode E2 is in direct contact with at least one of the first connection electrode CE1, the second connection electrode CE2, or the third connection electrode CE3. In one example, the second electrode E2 is in direct contact with the first connection electrode CE1. In another example, the second electrode E2 is in direct contact with the second connection electrode CE2. In another example, the second electrode E2 is in direct contact with the first connection electrode CE1 and the second connection electrode CE2. In another example, the second electrode E2 is in direct contact with the second connection electrode CE2 and the third connection electrode CE3. In another example, the second electrode E2 is in direct contact with the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3.

[0091] In some embodiments, reference Figure 2 and Figure 3 The auxiliary electrode AE ​​is located at a side of the first connection electrode CE1 away from the second connection electrode CE2. In one example, the auxiliary electrode AE ​​is located in the same layer as the source S and the drain D of the transistor in the display substrate.

[0092] In some embodiments, the display substrate includes a base substrate BS; a shading layer LSL located on the base substrate, which includes a shading member LS; a buffer layer BUF located on a side of the shading layer LSL away from the base substrate BS; an active layer ACT located on a side of the buffer layer BUF away from the base substrate BS, wherein the orthographic projection of the shading member LS on the base substrate BS at least partially overlaps with the orthographic projection of the active layer ACT on the base substrate BS (for example, the orthographic projection of the shading member LS on the base substrate BS completely covers the orthographic projection of the active layer ACT on the base substrate BS); The invention comprises a gate insulating layer GI on one side of the substrate BS; a gate layer CT including a gate G, which is located on the side of the gate insulating layer GI away from the substrate BS; an interlayer dielectric layer ILD, which is located on the side of the gate layer CT away from the substrate BS; a signal line layer SL including a source electrode S, a drain electrode D and an auxiliary electrode AE, which is located on the side of the interlayer dielectric layer ILD away from the substrate BS; a passivation layer PVX, which is located on the side of the signal line layer SL away from the substrate BS; a planarization layer PLN, which is located on the side of the passivation layer PVX away from the substrate BS; a pixel defining layer PDL, a light emitting element LE and a connection structure CS, which are located on the side of the planarization layer PLN away from the substrate BS. The pixel defining layer PDL defines a sub-pixel opening for accommodating at least one sub-layer (e.g., a light emitting layer) of the organic layer OL.

[0093] Reference Figure 2 and Figure 3 In some embodiments, the connection structure CS further includes at least one of: a remaining organic layer ROL stacked on a side of the third connection electrode CE3 away from the second connection electrode CE2; or a remaining second electrode RE2 stacked on a side of the remaining organic layer ROL away from the third connection electrode CE3. Figure 2 and Figure 3 In an example depicted in , the connection structure CS includes a structure stacked in sequence, which includes a first connection electrode CE1, a second connection electrode CE2 located on the first connection electrode CE1, a third connection electrode CE3 located on a side of the second connection electrode CE2 away from the first connection electrode CE1, a remaining organic layer ROL located on a side of the third connection electrode CE3 away from the second connection electrode CE2, and a remaining second electrode RE2 located on a side of the remaining organic layer ROL away from the third connection electrode CE3.

[0094] In some embodiments, the remaining organic layer ROL is located in the same layer as the organic layer OL and is at least partially (e.g., completely) separated from the organic layer OL. Optionally, at least one sublayer of the remaining organic layer ROL and at least one sublayer of the organic layer OL are located in the same layer. In one example, the remaining organic layer ROL includes a remaining hole transport layer located in the same layer as the hole transport layer of the organic layer OL. In another example, the remaining organic layer ROL includes a remaining hole injection layer located in the same layer as the hole injection layer of the organic layer OL. In one example, the remaining organic layer ROL includes a remaining electron transport layer located in the same layer as the electron transport layer of the organic layer OL. In another example, the remaining organic layer ROL includes a remaining electron injection layer located in the same layer as the electron injection layer of the organic layer OL.

[0095] In some embodiments, the remaining second electrode RE2 is located in the same layer as the second electrode E2 and is at least partially (eg, completely) separated from the second electrode E2.

[0096] Reference Figure 2 and Figure 3 In some embodiments, the first connection electrode CE1 extends through the via hole to be connected to the auxiliary electrode AE. Figure 2 and Figure 3 In one example depicted in FIG, the via extends through the planarization layer PLN and the passivation layer PVX. Figure 2 and Figure 3 As shown, in some embodiments, the orthographic projection of the planarization layer PLN on the substrate BS completely covers the orthographic projection of the first connecting electrode CE1 on the substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate BS completely covers the orthographic projection of the second connecting electrode CE2 on the substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate BS completely covers the orthographic projection of the third connecting electrode CE3 on the substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate BS completely covers the orthographic projection of the connecting structure CS on the substrate BS.

[0097] In some embodiments, the connection structure CS further includes at least one of the remaining organic layer ROL or the remaining second electrode RE2. Optionally, the orthographic projection of the planarization layer PLN on the base substrate BS completely covers the orthographic projection of the remaining organic layer ROL on the base substrate BS, and completely covers the orthographic projection of the remaining second electrode RE2 on the base substrate BS.

[0098] The connection structure CS (e.g., the layers of the connection structure CS) is formed on the planarized surface by making the orthographic projection of the planarization layer PLN on the base substrate BS completely cover the orthographic projection of the connection structure CS on the base substrate BS. The connection structure CS can have a substantially flat morphology, avoiding damage to the organic layer OL caused by the protrusion of the connection structure CS.

[0099] Figure 4 is a cross-sectional view of a display substrate in some embodiments according to the present disclosure. Figure 5 Schematic diagram showing the structure of the connection structure according to some embodiments of the present disclosure. Figure 4 and Figure 5 In some embodiments, the first connection electrode CE1 extends through the via hole to be connected to the auxiliary electrode AE. Figure 4 In one example depicted in FIG, the via extends through the passivation layer PVX but not through the planarization layer PLN. Figure 4 and Figure 5 As shown, in some embodiments, the orthographic projection of the planarization layer PLN on the substrate substrate BS does not overlap with the orthographic projection of the first connecting electrode CE1 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS does not overlap with the orthographic projection of the second connecting electrode CE2 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS does not overlap with the orthographic projection of the third connecting electrode CE3 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS does not overlap with the orthographic projection of the connecting structure CS on the substrate substrate BS.

[0100] In some embodiments, the connection structure CS further includes at least one of the remaining organic layer ROL or the remaining second electrode RE2. Optionally, the orthographic projection of the planarization layer PLN on the base substrate BS does not overlap with the orthographic projection of the remaining organic layer ROL on the base substrate BS, and does not overlap with the orthographic projection of the remaining second electrode RE2 on the base substrate BS.

[0101] By making the orthographic projection of the planarization layer PLN on the base substrate BS not overlap with the orthographic projection of the connection structure CS on the base substrate BS, a connection structure CS (e.g., each layer of the connection structure CS) having a relatively small height relative to the base substrate BS is formed. When the substrate is subjected to brushing during the manufacturing process, the edge of the connection structure CS is not easily damaged. The intact edge of the connection structure CS can ensure the separation of the remaining organic layer ROL from the organic layer OL, and the separation of the remaining second electrode RE2 from the second electrode E2.

[0102] Figure 6 is a cross-sectional view of a display substrate in some embodiments according to the present disclosure. Figure 7Schematic diagram showing the structure of the connection structure according to some embodiments of the present disclosure. Figure 6 and Figure 7 , the first connection electrode CE1 extends through the via hole to be connected to the auxiliary electrode AE. Figure 6 and Figure 7 In one example depicted in FIG, the via extends through the passivation layer PVX but not through the planarization layer PLN. Figure 6 and Figure 7 As shown, in some embodiments, the orthographic projection of the planarization layer PLN on the substrate substrate BS only partially overlaps with the orthographic projection of the first connecting electrode CE1 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS only partially overlaps with the orthographic projection of the second connecting electrode CE2 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS only partially overlaps with the orthographic projection of the third connecting electrode CE3 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS only partially overlaps with the orthographic projection of the connecting structure CS on the substrate substrate BS.

[0103] In some embodiments, the connection structure CS further includes at least one of the remaining organic layer ROL or the remaining second electrode RE2. Optionally, the orthographic projection of the planarization layer PLN on the base substrate BS only partially overlaps with the orthographic projection of the remaining organic layer ROL on the base substrate BS, and only partially overlaps with the orthographic projection of the remaining second electrode RE2 on the base substrate BS.

[0104] By making the orthographic projection of the planarization layer PLN on the base substrate BS only partially overlap with the orthographic projection of the connection structure CS on the base substrate BS, the edge of the connection structure CS can remain substantially intact when the base substrate is brushed during manufacturing, thereby ensuring that the remaining organic layer ROL is separated from the organic layer OL, and the remaining second electrode RE2 is separated from the second electrode E2. At the same time, the connection structure CS can be manufactured without large protrusions that may damage the organic layer OL.

[0105] Figure 8 Schematic diagram showing the structure of a connection structure according to some embodiments of the present disclosure. Figure 8 , Figure 2 , Figure 4 and Figure 6 In some embodiments, the second connection electrode CE2 includes an upper surface in contact with the third connection electrode CE3 and a lower surface in contact with the first connection electrode CE1 and opposite to the upper surface. In some embodiments, a cross section along a plane intersecting the first connection electrode CE1, the second connection electrode CE2 and the third connection electrode CE3 and perpendicular to the main surface of the substrate substrate BS (for example, as Figures 2 to 7The cross section shown in any of the figures in the drawings) includes a top edge located in the upper surface and a bottom edge located in the lower surface, and the orthographic projection of the bottom edge on the substrate base plate BS covers the orthographic projection of the top edge on the substrate base plate BS.

[0106] By providing the auxiliary electrode AE, the voltage drop on the extension path of the second electrode E2 when the display substrate is in operation is further reduced. Therefore, the second electrode can be made relatively thin, thereby increasing the transmittance of the display substrate. In the present display substrate, the orthographic projection of the bottom side of the cross section of the second connection electrode CE2 on the base substrate BS covers the orthographic projection of the top side of the cross section of the second connection electrode CE2 on the base substrate BS. In some embodiments, the second connection electrode CE2 has a slope structure located between its upper surface and lower surface, as further described below, and this slope structure helps to achieve a larger contact area between the second electrode E2 and the connection structure CS, thereby reducing the contact resistance between the second electrode E2 and the connection structure CS, thereby further effectively reducing the voltage drop on the extension path of the second electrode E2 during the operation of the display substrate. Therefore, an excessive voltage drop on the second electrode E2 can be avoided, and the transmittance of the display substrate can be further improved by making the second electrode E2 thinner, further enhancing the brightness uniformity of the image displayed by the display substrate.

[0107] As described above, the orthographic projection of the auxiliary electrode AE ​​on the base substrate BS does not overlap with the orthographic projection of the sub-pixel region SR on the base substrate BS, thereby minimizing the effect of the auxiliary electrode AE ​​on the luminescence of the sub-pixel region SR. The auxiliary electrode AE ​​and the connection structure CS may have various appropriate relative positional relationships. In one example, the orthographic projection of the auxiliary electrode AE ​​on the base substrate BS does not overlap with the orthographic projection of the connection structure CS on the base substrate BS. In another example, the orthographic projection of the auxiliary electrode AE ​​on the base substrate BS at least partially overlaps with the orthographic projection of the connection structure CS on the base substrate BS to increase the aperture ratio of the display substrate. The layer where the auxiliary electrode AE ​​is located (e.g., the signal line layer SL) is located on the side of the organic layer OL close to the base substrate BS to avoid the adverse effect of the auxiliary electrode AE ​​on the light-emitting layer of the organic layer OL.

[0108] In some embodiments, the orthographic projection of the first connection electrode CE1 on the base substrate BS completely covers the orthographic projection of the third connection electrode CE3 on the base substrate BS; the orthographic projection of the second connection electrode CE2 on the base substrate BS does not exceed the orthographic projection of the third connection electrode CE3 on the base substrate BS. In one example, in a cross section along a plane intersecting the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 and perpendicular to the main surface of the base substrate BS (for example, as Figures 2 to 8In any cross section shown in FIG. 1 , the first connection electrode CE1, the second connection electrode CE2 and the third connection electrode CE3 have an I-shape, which helps to form a stable and effective connection between the second electrode E2 and the connection structure CS.

[0109] In some embodiments, the second connection electrode CE2 includes an upper surface in contact with the third connection electrode CE3, and a lower surface in contact with the first connection electrode CE1 and opposite to the upper surface. In some embodiments, a cross section along a plane intersecting the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 and perpendicular to the main surface of the substrate substrate BS (for example, as shown in FIG. Figures 2 to 7 The cross section shown in any one of the above) includes a top edge located in the upper surface, a bottom edge located in the lower surface, and a side edge connecting the top edge and the bottom edge. The side edge and the lower surface intersect at an intersection in the lower surface. The angle between the line from any point on the side edge to the intersection and the lower surface is less than or equal to 90 degrees, wherein the opening of the angle faces the second connection electrode CE2. The slope structure of the second connection electrode CE2 with the angle helps to allow the material of the second electrode E2 to diffuse to the side edge of the second connection electrode CE2 during the manufacturing process of the display substrate, thereby facilitating a larger contact area between the second electrode E2 and the second connection electrode CE2.

[0110] Fig. 9A is a cross-sectional view of a connection structure according to some embodiments of the present disclosure. Fig. 9A The second connection electrode CE2 has a cross section perpendicular to its upper and lower surfaces, and the height of the cross section along the vertical direction is H. The cross section of the second connection electrode CE2 includes a top edge located in the upper surface, a bottom edge located in the lower surface, and a side edge connecting the top edge to the bottom edge. The side edge and the bottom edge intersect to form an acute angle α. Fig. 9A The acute angle α shown is an example of the above-mentioned angle.

[0111] The side of the second connection electrode CE2 may have any suitable shape. In one example, the side may be substantially flat. In another example, the side may be uneven or irregular. Fig. 9B is a cross-sectional view of a connection structure according to some embodiments of the present disclosure. Fig. 9B , the side is not flat. The side intersects the lower surface at an acute angle β.

[0112] The inventors of the present disclosure have found through extensive experiments that the degree of the angle affects the effective connection between the second electrode E2 and the second connection electrode CE2. A relatively small angle may cause a protrusion to appear on the second connection electrode CE2, thereby preventing or reducing the effective connection between the second electrode E2 and the second connection electrode CE2. The inventors of the present disclosure have found through a large number of experiments that an angle within a range between 45 degrees and 70 degrees is optimal for avoiding a protrusion on the second connection electrode CE2 and forming an effective connection between the second electrode E2 and the second connection electrode CE2.

[0113] The cross section of the second connection electrode CE2 may have various appropriate shapes. Fig. 9A In one example shown, the cross section of the second connection electrode CE2 has a trapezoidal shape.

[0114] Reference Figure 2 , Figure 4 and Figure 6 In some embodiments, the display substrate further includes a pixel defining layer PDL surrounding the sub-pixel region SR. Optionally, the orthographic projection of the planarization layer PLN on the base substrate BS overlaps at least partially with the orthographic projection of the pixel defining layer PDL on the base substrate BS (for example, overlapping by at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95% or at least 99%). Optionally, the orthographic projection of the pixel defining layer PDL on the base substrate BS does not overlap with the orthographic projection of the second connection electrode CE2 on the base substrate BS, and does not overlap with the orthographic projection of the third connection electrode CE3 on the base substrate BS.

[0115] In some embodiments, the second electrode E2 extends from the sub-pixel region SR across the pixel defining layer PDL to the inter-sub-pixel region ISR to directly contact at least one of the first connection electrode CE1 , the second connection electrode CE2 , or the third connection electrode CE3 .

[0116] In some embodiments, at least one sub-layer of the organic layer OL extends from the sub-pixel region SR, across the pixel defining layer PDL, to the inter-sub-pixel region ISR.

[0117] In some embodiments, the display substrate includes a stacked structure, which includes a pixel defining layer PDL; a portion of at least one sublayer of the organic layer OL, which is located on the pixel defining layer PDL and in direct contact with the pixel defining layer PDL; and a portion of the second electrode E2, which is located on a side of a portion of at least one sublayer of the organic layer OL away from the pixel defining layer PDL and in direct contact with a portion of at least one sublayer of the organic layer OL. Optionally, the orthographic projection of the second electrode E2 on the base substrate BS at least partially overlaps with the orthographic projection of the pixel defining layer PDL on the base substrate BS (for example, the orthographic projection of the second electrode E2 on the base substrate BS completely covers the orthographic projection of the pixel defining layer PDL on the base substrate BS). Optionally, the orthographic projection of at least one sublayer of the organic layer OL on the base substrate BS at least partially overlaps with the orthographic projection of the pixel defining layer PDL on the base substrate BS (for example, the orthographic projection of at least one sublayer of the organic layer OL on the base substrate BS completely covers the orthographic projection of the pixel defining layer PDL on the base substrate BS).

[0118] In some embodiments, reference Figure 8 The connection structure CS has an open groove GV formed between the first connection electrode CE1, the second connection electrode CE2 and the third connection electrode CE3. The second electrode E2 at least partially extends into the open groove GV to directly contact at least one of the first connection electrode CE1, the second connection electrode CE2 or the third connection electrode CE3.

[0119] In some embodiments, the orthographic projection of the third connection electrode CE3 on the substrate substrate BS covers the orthographic projection of the open groove GV on the substrate substrate BS, and at least partially overlaps with the orthographic projection of the second connection electrode CE2 on the substrate substrate BS (for example, the orthographic projection of the third connection electrode CE3 on the substrate substrate BS completely covers the orthographic projection of the second connection electrode CE2 on the substrate substrate BS). Optionally, the orthographic projection of the first connection electrode CE1 on the substrate substrate BS covers the orthographic projection of the open groove GV on the substrate substrate BS, and at least partially overlaps with the orthographic projection of the second connection electrode CE2 on the substrate substrate BS (for example, the orthographic projection of the first connection electrode CE1 on the substrate substrate BS completely covers the orthographic projection of the second connection electrode CE2 on the substrate substrate BS). Optionally, the orthographic projection of the third connection electrode CE3 on the substrate substrate BS partially overlaps with the orthographic projection of the second electrode E2 on the substrate substrate BS.

[0120] In some embodiments, reference Figure 2 , Figure 4 , Figure 6 and Figure 8The open groove GV has an opening side opened toward the pixel defining layer PDL. The second electrode E2 extends through the opening side into the open groove GV to directly contact at least one of the first connection electrode CE1, the second connection electrode CE2 or the third connection electrode CE3.

[0121] In some embodiments, the open groove has an upper wall, a lower wall and a side wall. The upper wall of the open groove GV is formed by a portion of the third connection electrode CE3 that extends toward the pixel defining layer PDL and is not in direct contact with the second connection electrode CE2. The lower wall is formed by a portion of the first connection electrode CE1 that extends toward the pixel defining layer PDL and is not in direct contact with the second connection electrode CE2. The side wall is formed by a portion of the second connection electrode CE2. The upper wall extends a first length in a horizontal direction parallel to the main surface of the substrate substrate BS, and the lower wall extends a second length in a horizontal direction parallel to the main surface of the substrate substrate BS. Optionally, the second length is greater than the first length.

[0122] Reference Fig. 9A and Fig. 9B The first length is represented as D1 and the second length is represented as D2. The presence of the open groove GV in the connection structure helps the material of the second electrode E2 to extend into the open groove GV and directly contact the third connection electrode CE3 during the manufacture of the display substrate, thereby further reducing the voltage drop on the second electrode E2 during the operation of the display substrate.

[0123] In some embodiments, the second length D2 is 4 to 10 times the first length D1. In one example, the second length D2 is about 5 μm, while the first length D1 is between 0.5 μm and 1.2 μm. The inventors of the present disclosure have found that these ranges ensure that the second electrode E2 can extend within the open groove GV to directly contact at least one of the lower wall and the side wall of the open groove GV, thereby increasing the contact area between the second electrode E2 and the first connection electrode CE1 or between the second electrode E2 and the second connection electrode CE2, thereby reducing the voltage drop on the extension path of the second electrode E2 during operation of the display substrate.

[0124] In some embodiments, the third connection electrode CE3 extends a third length D3 along a horizontal direction parallel to a surface direction of the substrate BS. Optionally, the third length D3 is in a range between 12 μm and 14 μm.

[0125] In some embodiments, the first length D1 is 1 to 2 times the height of the second connection electrode CE2 in the second direction, where the second direction is a vertical direction perpendicular to the horizontal direction. This can help in the process of manufacturing the display substrate by preventing too much material of the light emitting layer EL from entering the open groove GV. The height of the second connection electrode CE2 in the second direction is Fig. 9A and Fig. 9BIn some embodiments, the height H is between 0.5 μm and 0.6 μm, and the height d2 of the organic layer OL in the second direction is approximately like Fig. 9A and Fig. 9B As shown, at least a portion of the organic layer OL located in the sub-pixel region may extend beyond the pixel defining layer PDL to extend to the auxiliary electrode connection region. Optionally, a height H of the second connection electrode CE2 in the second direction is 1.5 to 2 times a height d2 of the organic layer OL in the second direction.

[0126] Fig. 10A The structure of a portion of a display substrate in some embodiments of the present disclosure is shown. Fig. 10B Shows Fig. 10A The structure of the light shielding layer in a portion of the display substrate shown in FIG. Fig. 10C Shows Fig. 10A The structure of the semiconductor material layer in a portion of the display substrate is shown in FIG. Fig. 10D Shows Fig. 10A The structure of the gate layer in a portion of the display substrate is shown in FIG. Fig. 10E Shows Fig. 10A The structure of the signal line layer in a portion of the display substrate shown in FIG. Fig.10F Shows Fig. 10A The structure of the planarization layer in a portion of the display substrate is shown in FIG. Figure 10G Shows Fig. 10A The structure of the first conductive layer in a portion of the display substrate is shown in FIG. Fig. 10H Shows Fig. 10A The structure of the second conductive layer in a portion of the display substrate is shown in FIG. Fig.10I Shows Fig. 10A . The structure of the third conductive layer in a portion of the display substrate is shown in FIG. Fig.10J Shows Fig. 10A The structure of a pixel defining layer in a portion of a display substrate shown in FIG. Figure 10K Shows Fig. 10A The structure of the black matrix layer in a portion of the display substrate shown in FIG. FIG. 10A to FIG. 10K The display substrate includes a sub-pixel region SR and an inter-sub-pixel region outside the sub-pixel region SR. Each individual sub-pixel region corresponds to an individual sub-pixel. In the inter-sub-pixel region, the display substrate also includes a transparent region TR that allows an observer to view through it.

[0127] like FIG. 10A to FIG. 10K As shown, in some embodiments, the auxiliary electrode AE ​​at least partially extends in one or more sub-pixels. Optionally, the auxiliary electrode AE ​​at least partially extends in a plurality of sub-pixels located in a plurality of sub-pixel regions, such as Fig. 10Ashown. Fig.11A Shows Fig. 10A The structure of the planarization layer and the signal line layer in a portion of the display substrate shown in FIG. Fig.11A In some embodiments, the orthographic projection of the planarization layer PLN on the base substrate at least partially overlaps with the orthographic projection of the auxiliary electrode AE ​​on the base substrate. FIG. 10A to FIG. 10K and Fig.11A In the display substrate shown, the orthographic projection of the planarization layer PLN on the base substrate completely covers the orthographic projection of the auxiliary electrode AE ​​on the base substrate.

[0128] Fig. 12A The structure of a planarization layer in a portion of a display substrate in some embodiments according to the present disclosure is shown. Fig. 12B The structure of a planarization layer and a signal line layer in a portion of a display substrate in some embodiments according to the present disclosure is shown. Fig.13A The structure of a planarization layer in a portion of a display substrate in some embodiments according to the present disclosure is shown. Fig. 13B The structure of a planarization layer and a signal line layer in a portion of a display substrate in some embodiments of the present disclosure is shown. Fig. 12A , Fig. 12B , Fig.13A as well as Fig. 13B In some embodiments, the orthographic projection of the planarization layer PLN on the base substrate only partially overlaps with the orthographic projection of the auxiliary electrode AE ​​on the base substrate.

[0129] Fig. 11B The structure of the auxiliary electrode in some embodiments of the present disclosure is shown. Fig. 11B In some embodiments, the auxiliary electrode includes an auxiliary electrode line AEL extending through a plurality of sub-pixels along a first direction DR1; and a branch line BL extending from the auxiliary electrode line AEL along a second direction DR2. The second direction DR2 is different from the first direction DR1.

[0130] Reference Figure 2 , Figure 4 , Figure 6 , FIG. 10A to FIG. 10K , Fig.11A and Fig. 11B In some embodiments, the first connection electrode CE1 extends through the via hole to be connected to the branch line BL. Optionally, the orthographic projection of the first connection electrode CE1 on the base substrate BS partially overlaps with the orthographic projection of the branch line BL on the base substrate BS, and does not overlap with the orthographic projection of the auxiliary electrode line AEL on the base substrate BS.

[0131] In some embodiments, the auxiliary electrode further comprises one or more auxiliary electrode blocks AEB located in a different layer from the auxiliary electrode line AEL. In one example, the one or more auxiliary electrode blocks AEB are in the gate layer, and the auxiliary electrode line AEL is in the signal line layer. Fig. 11C Shows Fig. 10A The structure of the gate layer and the signal line layer in a portion of the display substrate shown in FIG. Fig.11D 2 shows the structure of the auxiliary electrode in some embodiments of the present disclosure. Fig. 11C and Fig.11D , the auxiliary electrode line AEL is connected to one or more auxiliary electrode blocks AEB through one or more vias v1. Optionally, the one or more auxiliary electrode blocks AEB are arranged along the first direction DR1. Optionally, the orthographic projection of the auxiliary electrode line AEL on the base substrate at least partially overlaps with the orthographic projection of the one or more auxiliary electrode blocks AEB on the base substrate.

[0132] Reference Figure 2 , Figure 4 , Figure 6 and Fig.11D In some embodiments, the display substrate includes an interlayer dielectric layer ILD between the gate layer CT and the signal line layer SL. Optionally, the auxiliary electrode line AEL is located on a side of the interlayer dielectric layer ILD away from the one or more auxiliary electrode blocks AEB. Optionally, the auxiliary electrode line AEL is connected to the one or more auxiliary electrode blocks AEB through one or more vias v1 extending through the interlayer dielectric layer ILD.

[0133] Fig.11E Schematic diagram showing the structure of the pixel defining layer and the auxiliary electrode in some embodiments of the present disclosure. Fig.11E , Figure 2 , Figure 4 and Figure 6 In some embodiments, the orthographic projection of the pixel defining layer PDL on the substrate partially overlaps with the orthographic projection of the auxiliary electrode line AEL on the substrate BS, and does not overlap with the orthographic projection of the first connection electrode CE1 on the substrate BS. Optionally, the orthographic projection of the pixel defining layer PDL on the substrate partially overlaps with the orthographic projection of one or more auxiliary electrode blocks AEB on the substrate BS. Optionally, the orthographic projection of the pixel defining layer PDL on the substrate substrate does not at least partially overlap with the orthographic projection of the branch line on the substrate BS.

[0134] Fig.11F The structure of the auxiliary electrode in some embodiments of the present disclosure is shown. Fig.11FThe auxiliary electrode includes an auxiliary electrode line AEL extending through a plurality of sub-pixels along a first direction DR1; and a plurality of branch lines BLS extending from the auxiliary electrode line AEL along a second direction DR2, the second direction DR2 being different from the first direction DR1. Optionally, the plurality of branch lines BLS include one or more first branch lines BL1 and one or more second branch lines BL2.

[0135] Fig.11G The structure of the auxiliary electrode and multiple connection structures in some embodiments of the present disclosure are shown. Fig.11G In some embodiments, the display substrate includes a plurality of connection structures CSS, each connection structure CSS electrically connecting the auxiliary electrode to the second electrode. Optionally, the plurality of connection structures CSS include one or more first connection structures CS1 and one or more second connection structures CS2. Fig.11G As shown, each of the one or more first branch lines BL1 connects the corresponding first connection structure in the one or more first connection structures CS1 to the auxiliary electrode line AEL. Each of the one or more second branch lines BL2 connects the corresponding second connection structure in the one or more second connection structures CS2 to the auxiliary electrode line AEL. Each of the one or more first branch lines BL1 extends a first length along the second direction DR2. Each of the one or more second branch lines BL2 extends a second length along the second direction DR2, respectively. The first length is greater than each of the second lengths.

[0136] Fig.11H The structure of the planarization layer, the auxiliary electrode, and the multiple connection structures in some embodiments of the present disclosure are shown. Fig.11H In some embodiments, the orthographic projection of the planarization layer PLN on the base substrate does not overlap at all with the orthographic projection of one or more first connection structures CS1 on the base substrate. Optionally, the orthographic projection of the planarization layer PLN on the base substrate at least partially overlaps with the orthographic projection of one or more second connection structures CS2 on the base substrate. Fig.11H In one example shown, the orthographic projection of the planarization layer PLN on the base substrate covers the orthographic projection of one or more second connection structures CS2 on the base substrate.

[0137] Fig. 12C The structure of the planarization layer, the auxiliary electrode, and the multiple connection structures in some embodiments of the present disclosure are shown. Fig. 12C In some embodiments, the orthographic projection of the planarization layer PLN on the base substrate does not overlap at all with the orthographic projection of one or more first connection structures CS1 on the base substrate, and does not overlap at all with the orthographic projection of one or more second connection structures CS2 on the base substrate.

[0138] Fig. 13C The structure of the planarization layer, the auxiliary electrode, and the multiple connection structures in some embodiments of the present disclosure are shown. Fig. 13C In some embodiments, the orthographic projection of the planarization layer PLN on the base substrate does not overlap at all with the orthographic projection of one or more first connection structures CS1 on the base substrate. Optionally, the orthographic projection of the planarization layer PLN on the base substrate only partially overlaps with the orthographic projection of one or more second connection structures CS2 on the base substrate. Fig. 13C In one example shown, the orthographic projection of the planarization layer PLN on the base substrate only partially overlaps each of the orthographic projections of the one or more second connection structures CS2 on the base substrate.

[0139] Reference Figure 10G In some embodiments, the display substrate includes a repair structure RPS. The repair structure connects the first conductive portion EC1 and the second conductive portion EC2 together. In some embodiments, the first conductive portion EC1 and the second conductive portion EC2 are first electrodes (eg, Figure 2 Optionally, the first conductive portion EC1 and the second conductive portion EC2 are portions of the first electrode located in the same sub-pixel region (eg, Figure 1 , Figure 2 , Figure 4 and Fig. 10A Optionally, the first electrode includes a plurality of sub-layers. For example, see Figure 2 and Figure 4 In some embodiments, the first electrode E1 includes a first sublayer SUB1, a second sublayer SUB2, and a third sublayer SUB3 stacked in sequence. Optionally, the first conductive portion EC1 and the second conductive portion EC2 are part of one of the plurality of sublayers of the first electrode. Figure 10G In some embodiments, the first conductive portion EC1 and the second conductive portion EC2 are parts of the first sub-layer SUB1 of the first electrode E1.

[0140] In some embodiments, the first conductive portion EC1 and the second conductive portion EC2 are at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) located on the first side S1 of the virtual line VL, and the repair structure RPS is at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) located on the second side S2 of the virtual line VL. In one example, the first conductive portion EC1 and the second conductive portion EC2 are completely located on the first side S1 of the virtual line VL, and the repair structure RPS is completely located on the second side S2 of the virtual line VL. Optionally, the virtual line VL is a boundary line that separates the repair structure RPS from the first conductive portion EC1 and separates the repair structure RPS from the second conductive portion EC2.

[0141] Fig.14 is a circuit diagram of a pixel driving circuit in a portion of a display substrate according to some embodiments of the present disclosure. Fig.14 , each pixel driving circuit is connected to a corresponding light emitting element LE. In some embodiments, each pixel driving circuit includes a storage capacitor Cst having a first capacitor electrode coupled to a first node N1 and a second capacitor electrode coupled to a second node N2; a driving transistor T1 having a source coupled to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, a drain coupled to the second node N2, and a gate coupled to the first node N1; a switching transistor T2 having a source coupled to a corresponding data line among a plurality of data lines (including a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4), a drain coupled to the first node N1, and a gate coupled to a corresponding first gate line among a plurality of first gate lines GL1; and a sensing transistor T3 having a source coupled to a corresponding sensing line among a plurality of sensing lines SL, a drain coupled to the second node N2, and a gate coupled to a corresponding second gate line among a plurality of second gate lines GL2. The first node N1 is coupled to the gate of the driving transistor T1, the source of the switching transistor T2, and the first capacitor electrode of the storage capacitor Cst. The second node N2 is coupled to the drain of the driving transistor T1, the drain of the sensing transistor T3, the second capacitor electrode of the storage capacitor Cst, and the anode of the light emitting element LE. Various suitable light emitting elements can be used in the present array substrate. Examples of suitable light emitting elements include organic light emitting diodes, quantum dot light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is a micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.

[0142] Fig.14Four pixel driving circuits configured to drive four sub-pixels (such as a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel) to emit light are shown. In one example, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are sub-pixels in the same pixel. In another example, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. In some embodiments, a plurality of data lines include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4 configured to provide data signals to the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, respectively.

[0143] In some embodiments, the display substrate includes one or more first connection structures CS1 and one or more second connection structures CS2. Each of the one or more first connection structures CS1 connects the auxiliary electrode AE ​​to the second electrode of the light-emitting element. Each of the one or more second connection structures CS2 connects the auxiliary electrode AE ​​to the second electrode of the light-emitting element. In some embodiments, each of the first connection structures and each of the second connection structures have different structures.

[0144] Fig.15 is a schematic diagram showing the structure of a corresponding first connection structure in some embodiments of the present disclosure. Fig.15 In some embodiments, each first connection structure includes a connection electrode CE and at least one of: a portion of the organic layer OL on the connection electrode CE or a portion of the second electrode E2 on the connection electrode CE. Fig.15 In one example shown, each first connection structure includes a structure stacked in sequence, including a connection electrode CE, a portion of the organic layer OL on the connection electrode CE, and a portion of the second electrode E2 located on a side of the portion of the organic layer OL away from the connection electrode CE. In some embodiments, the auxiliary electrode AE ​​is located on a side of the connection electrode CE away from the portion of the organic layer OL. In one example, the auxiliary electrode AE ​​is located in the same layer as the source and drain of a transistor (e.g., a driving transistor T1, a switching transistor T2, and / or a sensing transistor T3) in the display substrate. In one example, the connection electrode CE is in direct contact with the auxiliary electrode AE, the portion of the organic layer OL is in direct contact with the connection electrode CE, and the portion of the second electrode E2 is in direct contact with the portion of the organic layer OL.

[0145] In some embodiments, at least a portion of the connection electrode CE is located in the same layer as the first connection electrode CE1. In some embodiments, at least a portion of the connection electrode CE is located in the same layer as the second connection electrode CE2. In some embodiments, at least a portion of the connection electrode CE is located in the same layer as the third connection electrode CE3. In some embodiments, the connection electrode CE includes a plurality of sublayers, and a corresponding sublayer of the plurality of sublayers is located in the same layer as one of the first connection electrode CE1, the second connection electrode CE2, or the third connection electrode CE3. In a specific example, the connection electrode CE is located in the same layer as the first connection electrode CE1.

[0146] In some embodiments, each first connection structure further comprises a conductive channel CC, which comprises a sintered conductive material, which comprises at least one of the following: an organic material of the portion of the organic layer OL, a conductive material of the connection electrode CE, or a conductive material of the portion of the second electrode E2. Optionally, the conductive channel CC comprises a sintered conductive material, which comprises an organic material of the portion of the organic layer OL, a conductive material of the connection electrode CE, and a conductive material of the portion of the second electrode E2. The second electrode E2 is connected to the connection electrode CE through the conductive channel CC, and is connected to the auxiliary electrode AE ​​through the connection electrode CE.

[0147] In some embodiments, the orthographic projection of the planarization layer PLN on the base substrate BS does not overlap with the orthographic projection of the conductive channel CC on the base substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the base substrate BS does not overlap with the orthographic projection of the corresponding first connection structure on the base substrate BS.

[0148] In some embodiments, the conductive channel CC can be formed by, for example, laser sintering the organic layer OL, the connecting electrode CE, and the portion of the second electrode E2. In some embodiments, the second electrode E2 is electrically connected to the auxiliary electrode AE ​​by sintering the organic layer OL, the connecting electrode CE, and the portion of the second electrode E2. Alternatively, the sintering can be performed by laser. The conductive channel CC is at least partially sintered so that the conductive channel CC is conductive, thereby electrically connecting the second electrode E2 to the connecting electrode CE.

[0149] Fig.16 Schematic diagrams showing the structures of corresponding second connection structures in some embodiments of the present disclosure. Each second connection structure has a different structure from each first connection structure. Fig.16 and Figures 2 to 8In some embodiments, each second connection structure includes a first connection electrode CE1, a second connection electrode CE2, and a third connection electrode CE3 stacked in sequence. In one example, the first connection electrode CE1 is in direct contact with the second connection electrode CE2, and the second connection electrode CE2 is in direct contact with the third connection electrode CE3. The second connection electrode CE2 connects the first connection electrode CE1 and the third connection electrode CE3. In some embodiments, the auxiliary electrode AE ​​is located on a side of the first connection electrode CE1 away from the second connection electrode CE2. In one example, the auxiliary electrode AE ​​is located in the same layer as the source and drain of the transistor (e.g., the driving transistor T1, the switching transistor T2, and / or the sensing transistor T3) in the display substrate.

[0150] In some embodiments, the first sublayer SUB1 and the first connection electrode CE1 are located in the same layer; the second sublayer SUB2 and the second connection electrode CE2 are located in the same layer; and the third sublayer SUB3 and the third connection electrode CE3 are located in the same layer. Optionally, the first sublayer SUB1 and the first connection electrode CE1 are separated from each other, for example, by a pixel defining layer PDL; the second sublayer SUB2 and the second connection electrode CE2 are separated from each other, for example, by a pixel defining layer PDL; and the third sublayer SUB3 and the third connection electrode CE3 are separated from each other, for example, by a pixel defining layer PDL.

[0151] In some embodiments, the second electrode E2 is in direct contact with at least one of the first connection electrode CE1, the second connection electrode CE2, or the third connection electrode CE3. In one example, the second electrode E2 is in direct contact with the first connection electrode CE1. In another example, the second electrode E2 is in direct contact with the second connection electrode CE2. In another example, the second electrode E2 is in direct contact with the first connection electrode CE1 and the second connection electrode CE2. In another example, the second electrode E2 is in direct contact with the second connection electrode CE2 and the third connection electrode CE3. In another example, the second electrode E2 is in direct contact with the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3.

[0152] In some embodiments, each second connection structure further includes at least one of: a remaining organic layer ROL stacked on a side of the third connection electrode CE3 away from the second connection electrode CE2; or a remaining second electrode RE2 stacked on a side of the remaining organic layer ROL away from the third connection electrode CE3. Fig.16In an example depicted in , each second connection structure includes a structure stacked in sequence, which includes a first connection electrode CE1, a second connection electrode CE2 located on the first connection electrode CE1, a third connection electrode CE3 located on a side of the second connection electrode CE2 away from the first connection electrode CE1, a remaining organic layer ROL located on a side of the third connection electrode CE3 away from the second connection electrode CE2, and a remaining second electrode RE2 located on a side of the remaining organic layer ROL away from the third connection electrode CE3.

[0153] In some embodiments, the remaining organic layer ROL is located in the same layer as the organic layer OL and is at least partially (e.g., completely) separated from the organic layer OL. Optionally, at least one sublayer of the remaining organic layer ROL and at least one sublayer of the organic layer OL are located in the same layer. In one example, the remaining organic layer ROL includes a remaining hole transport layer located in the same layer as the hole transport layer of the organic layer OL. In another example, the remaining organic layer ROL includes a remaining hole injection layer located in the same layer as the hole injection layer of the organic layer OL. In one example, the remaining organic layer ROL includes a remaining electron transport layer located in the same layer as the electron transport layer of the organic layer OL. In another example, the remaining organic layer ROL includes a remaining electron injection layer located in the same layer as the electron injection layer of the organic layer OL.

[0154] In some embodiments, the remaining second electrode RE2 is located in the same layer as the second electrode E2 and is at least partially (eg, completely) separated from the second electrode E2.

[0155] Fig.16 Embodiments of corresponding second connection structures are depicted. Various alternative embodiments may be implemented. For example, each second connection structure may adopt Figures 2 to 9B The structure of any connection structure shown in .

[0156] In some embodiments, the orthographic projection of the planarization layer PLN on the substrate substrate BS at least partially overlaps with the orthographic projection of the first connection electrode CE1 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS at least partially overlaps with the orthographic projection of the second connection electrode CE2 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS at least partially overlaps with the orthographic projection of the third connection electrode CE3 on the substrate substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate substrate BS at least partially overlaps with the orthographic projection of the corresponding second connection structure on the substrate substrate BS.

[0157] Fig.17 is a schematic diagram of a portion of a display substrate according to some embodiments of the present disclosure. Fig.17In some embodiments, the display substrate includes a light-emitting region LER and a transparent region TR. The light-emitting region LER refers to a region configured to emit light, for example, a region corresponding to a pixel electrode in a liquid crystal display or a region corresponding to a light-emitting layer in an organic light-emitting display. The transparent region refers to a region configured to allow light from the background of the display substrate to be transmitted through the display substrate, such as a region that is substantially free of any light-emitting elements and substantially opaque components (for example, thin-film transistors associated with the light-emitting elements, signal lines, and other non-transparent layers or elements). Optionally, the layer in the transparent region is substantially transparent, and therefore, the transparent region is also substantially transparent.

[0158] In some embodiments, one or more first connection structures CS1 and one or more second connection structures CS2 are located in the transparent region TR. Each of the one or more first connection structures CS1 is connected to the auxiliary electrode line AEL through a corresponding first branch line in one or more first branch lines BL1. Each of the one or more second connection structures CS2 is connected to the auxiliary electrode line AEL through a corresponding second branch line in one or more second branch lines BL2.

[0159] Fig.17 Four sub-pixels are shown, including a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, and a fourth sub-pixel sp4. In one example, Fig.17 Shown corresponding to Fig.14 A portion of a display substrate of a pixel driving circuit shown in FIG. Fig.14 The four pixel drive circuits shown in FIG. 1 are configured to drive Fig.17 In one example, the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 are sub-pixels in the same pixel. In another example, the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. In some embodiments, the plurality of data lines include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4, which are configured to provide data signals to the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4, respectively.

[0160] The inventors of the present disclosure have found that by providing one or more first connection structures CS1 and one or more second connection structures CS2, the connection between the second electrode and the auxiliary electrode can be optimized, thereby effectively reducing the voltage drop on the extension path of the second electrode during operation of the display substrate.

[0161] In some embodiments, each of the one or more first connection structures CS1 is spaced apart from the light emitting region LER by a first shortest distance d1; each of the one or more second connection structures CS2 is spaced apart from the light emitting region LER by a second shortest distance d2. In some embodiments, the first shortest distance d1 is greater than the second shortest distance d2. Optionally, the first shortest distance d1 is at least 10% greater than the second shortest distance d2, for example, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190% or at least 200%.

[0162] In some embodiments, the orthographic projection of the planarization layer PLN on the substrate BS does not overlap with the orthographic projection of the corresponding first connection structure on the substrate BS; the orthographic projection of the planarization layer PLN on the substrate BS at least partially overlaps with the orthographic projection of the corresponding second connection structure on the substrate BS. Optionally, the orthographic projection of the planarization layer PLN on the substrate BS does not overlap with the orthographic projection of the conductive channel CC of each first connection structure on the substrate BS; the orthographic projection of the planarization layer PLN on the substrate BS at least partially overlaps with the orthographic projection of at least one of the first connection electrode CE1, the second connection electrode CE2 or the third connection electrode CE3 on the substrate BS.

[0163] Fig.18 is a circuit diagram of a pixel driving circuit in a portion of a display substrate according to some embodiments of the present disclosure. Fig.18 In some embodiments, the display substrate includes one or more dummy structures DS and one or more second connection structures CS2. In each of the one or more dummy structures DS, the auxiliary electrode AE ​​is not connected to the second electrode of the light emitting element. Each of the one or more second connection structures CS2 connects the auxiliary electrode AE ​​to the second electrode of the light emitting element. In some embodiments, the dummy structure and each second connection structure have different structures.

[0164] Fig.19 is a schematic diagram showing the structure of corresponding dummy structures in some embodiments of the present disclosure. Each dummy structure has a structure different from each first connection structure. Fig.19 In some embodiments, each dummy structure includes a connection electrode CE, and at least one of: a portion of the organic layer OL on the connection electrode CE or a portion of the second electrode E2 on the connection electrode CE. Fig.19In one example shown, each dummy structure includes a structure stacked in sequence, including a connection electrode CE, a portion of the organic layer OL on the connection electrode CE, and a portion of the second electrode E2 located on a side of the portion of the organic layer OL away from the connection electrode CE. In some embodiments, the auxiliary electrode AE ​​is located on a side of the connection electrode CE away from the portion of the organic layer OL. In one example, the auxiliary electrode AE ​​is located in the same layer as the source and drain of a transistor (e.g., a driving transistor T1, a switching transistor T2, and / or a sensing transistor T3) in the display substrate. In one example, the connection electrode CE is in direct contact with the auxiliary electrode AE, the portion of the organic layer OL is in direct contact with the connection electrode CE, and the portion of the second electrode E2 is in direct contact with the portion of the organic layer OL.

[0165] In some embodiments, at least a portion of the connection electrode CE is located in the same layer as the first connection electrode CE1. In some embodiments, at least a portion of the connection electrode CE is located in the same layer as the second connection electrode CE2. In some embodiments, at least a portion of the connection electrode CE is located in the same layer as the third connection electrode CE3. In some embodiments, the connection electrode CE includes a plurality of sublayers, and a corresponding sublayer of the plurality of sublayers is located in the same layer as one of the first connection electrode CE1, the second connection electrode CE2, or the third connection electrode CE3. In a specific example, the connection electrode CE is located in the same layer as the first connection electrode CE1.

[0166] Each dummy structure is different from each first connection structure in that there is no conductive path in each dummy structure. In each dummy structure, the portion of the second electrode E2 is separated from the connection electrode CE by the portion of the organic layer OL. In the absence of a conductive path, the portion of the second electrode E2 is electrically isolated from the auxiliary electrode AE.

[0167] In some embodiments, an orthographic projection of the planarization layer PLN on the base substrate BS does not overlap with an orthographic projection of the corresponding dummy structure DS on the base substrate BS.

[0168] Fig. 20 is a schematic diagram showing the structure of a corresponding second connection structure in some embodiments of the present disclosure. Fig. 20 Each second connection structure shown in Fig.16 The structure shown in is very similar to the structure shown in. Fig. 20 Various alternative embodiments may be implemented. For example, each second connection structure may be implemented as Figures 2 to 9B The structure of any connection structure shown in .

[0169] Fig.21is a schematic diagram of a portion of a display substrate according to some embodiments of the present disclosure. Fig.21 In some embodiments, the display substrate includes a light emitting region LER and a transparent region TR. In some embodiments, one or more dummy structures DS and one or more second connection structures CS2 are located in the transparent region TR.

[0170] The inventors of the present disclosure have found that by providing one or more first connection structures CS1 and one or more dummy structures DS, the density of one or more first connection structures can be adjusted. Therefore, the connection between the second electrode and the auxiliary electrode can be optimized, effectively reducing the voltage drop on the extension path of the second electrode during the operation of the display substrate.

[0171] In some embodiments, each of the one or more dummy structures DS is spaced apart from the light emitting region LER by a third shortest distance d3; each of the one or more second connection structures CS2 is spaced apart from the light emitting region LER by a second shortest distance d2. In some embodiments, the third shortest distance d3 is greater than the second shortest distance d2. Optionally, the third shortest distance d3 is at least 10% greater than the second shortest distance d2, for example, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190% or at least 200%.

[0172] In some embodiments, the orthographic projection of the planarization layer PLN on the substrate BS does not overlap with the orthographic projection of each dummy structure on the substrate BS; the orthographic projection of the planarization layer PLN on the substrate BS at least partially overlaps with the orthographic projection of each second connection structure on the substrate BS.

[0173] In some embodiments, the display substrate includes a plurality of first repeating units. Each of the plurality of first repeating units has Fig.17 In some embodiments, each first repeating unit includes at least one first connection structure among the one or more first connection structures and at least one second connection structure among the one or more second connection structures. In one example, each first repeating unit includes a first connection structure and a second connection structure, such as Fig.17 As shown. Optionally, a plurality of first repeating units are arranged in an array in the display substrate. Optionally, each first repeating unit includes a plurality of sub-pixels and a portion of the transparent region TR. Each first repeating unit includes the conductive channel as described above.

[0174] In some embodiments, the display substrate further comprises a plurality of second repeating units. Each of the plurality of second repeating units has Fig.21 In some embodiments, each second repeating unit includes at least one dummy structure of the one or more dummy structures and at least one second connecting structure of the one or more second connecting structures. In one example, the second repeating unit includes a dummy structure and a second connecting structure, such as Fig.21 As shown. Optionally, a plurality of second repeating units are arranged in an array in the display substrate. Optionally, each second repeating unit includes a plurality of sub-pixels and a portion of the transparent region TR. The plurality of second repeating units do not include a conductive channel.

[0175] In some embodiments, the display substrate includes a plurality of first repeating units and does not include any second repeating units in the plurality of second repeating units. In an alternative embodiment, the display substrate includes a plurality of first repeating units and a plurality of second repeating units.

[0176] In some embodiments, each first repeating unit includes a pixel, and the pixel includes a plurality of sub-pixels (e.g., a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, and a fourth sub-pixel sp4). In some embodiments, each second repeating unit includes a pixel, and the pixel includes a plurality of sub-pixels (e.g., a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, and a fourth sub-pixel sp4).

[0177] In some embodiments, the ratio of the number of one or more second connection structures to the number of one or more first connection structures is greater than or equal to 0.9:1.0, for example, 0.9:1.0 to 1.0:0.9, 1.8:1.0 to 2.0:0.8, 2.8:1.0 to 3.0:0.8, 3.8:1.0 to 4.0:0.8, 4.8:1.0 to 5.0:0.8, 5.8:1.0 to 6.0:0.8, 6.8:1.0 to 7.0:0.8, 7.8:1.0 to 8.0:0.8, 8.8:1.0 to 9.0:0.8 or 9.8:1.0 to 10.0:0.8. In one example, the ratio of the number of one or more second connection structures to the number of one or more first connection structures is 1:1. In another example, the ratio of the number of one or more second connection structures to the number of one or more first connection structures is 2:1. In another example, the ratio of the number of the one or more second connection structures to the number of the one or more first connection structures is 4: 1. In another example, the ratio of the number of the one or more second connection structures to the number of the one or more first connection structures is 9:1.

[0178] In some embodiments, a ratio of the number of the one or more second connection structures to the sum of the number of the one or more first connection structures and the number of the one or more dummy structures is in the range of 0.9:1.0, for example 1:1.

[0179] In some embodiments, the ratio of the number of pixels to the number of one or more first connection structures is greater than or equal to 0.9:1.0, for example, 0.9:1.0 to 1.0:0.9, 1.8:1.0 to 2.0:0.8, 2.8:1.0 to 3.0:0.8, 3.8:1.0 to 4.0:0.8, 4.8:1.0 to 5.0:0.8, 5.8:1.0 to 6.0:0.8, 6.8:1.0 to 7.0:0.8, 7.8:1.0 to 8.0:0.8, 8.8:1.0 to 9.0:0.8 or 9.8:1.0 to 10.0:0.8. In one example, the ratio of the number of pixels to the number of one or more first connection structures is 1:1. In another example, the ratio of the number of pixels to the number of one or more first connection structures is 2:1. In another example, the ratio of the number of pixels to the number of one or more first connection structures is 4:1. In another example, a ratio of the number of pixels to the number of the one or more first connection structures is 9:1.

[0180] Fig. 22 The values ​​of the voltage drop in the display substrate with different ratios of the number of second connection structures to the number of first connection structures according to some embodiments of the present disclosure are shown. The voltage drop varies with the change of the sheet resistance of the second electrode. The larger the sheet resistance of the second electrode, the larger the value of the voltage drop. Curve "A" represents the change of the voltage drop in the second electrode in the display substrate, wherein the ratio of the number of one or more second connection structures to the number of one or more first connection structures is 1:1. Curve "B" represents the change of the voltage drop in the second electrode in the display substrate, wherein the ratio of the number of one or more second connection structures to the number of one or more first connection structures is 2:1. Curve "C" represents the change of the voltage drop in the second electrode in the display substrate, wherein the ratio of the number of one or more second connection structures to the number of one or more first connection structures is 4:1. Curve "D" represents the change of the voltage drop in the second electrode in the display substrate, wherein the ratio of the number of one or more second connection structures to the number of one or more first connection structures is 9:1.

[0181] like Fig. 22 As shown, at the same sheet resistance, curve A and curve B have substantially the same voltage drop value. The voltage drop value of curve C is greater than the voltage drop values ​​of curve A and curve B, and the voltage drop value of curve D is greater than the voltage drop values ​​of curve A, curve B, and curve C. The ratio can be determined based on the manufacturing process to achieve optimal display uniformity in the display substrate.

[0182] Fig.23 Schematic diagram showing the layout of a display substrate in some embodiments of the present disclosure. Fig.23 In some embodiments, the display substrate includes a plurality of first repeating units RU1, but does not include any second repeating units. The ratio of the number of the one or more second connection structures to the number of the one or more first connection structures is in the range of 0.9:1.0 to 1.0:0.9, for example 1:1. The ratio of the number of pixels to the number of the one or more first connection structures is in the range of 0.9:1.0 to 1.0:0.9, for example 1:1.

[0183] Fig.24 Schematic diagram showing the layout of a display substrate in some embodiments of the present disclosure. Fig.24 In some embodiments, the display substrate includes a plurality of first repeating units RU1 and a plurality of second repeating units RU2. The conductive channel CC exists in each first repeating unit in the plurality of first repeating units RU1, but does not exist in each second repeating unit in the plurality of second repeating units RU2. The ratio of the number of one or more second connection structures to the number of one or more first connection structures is in the range of 1.8:1.0 to 2.0:0.8, for example, 2:1. The ratio of the number of pixels to the number of one or more first connection structures is in the range of 1.8:1.0 to 2.0:0.8, for example, 2:1. The plurality of first repeating units RU1 are arranged into a plurality of first rows, the plurality of second repeating units RU2 are arranged into a plurality of second rows, and the plurality of first rows and the plurality of second rows are arranged alternately. The inventors of the present disclosure have found that the structure helps to reduce any potential mura (display unevenness) caused by the conductive channel in the display substrate, thereby achieving a high degree of display uniformity in the display substrate.

[0184] Fig.25 Schematic diagram showing the layout of a display substrate in some embodiments of the present disclosure. Fig.25In some embodiments, the display substrate includes a plurality of first repeating units RU1 and a plurality of second repeating units RU2. The conductive channel CC exists in each of the plurality of first repeating units RU1, but does not exist in each of the plurality of second repeating units RU2. The ratio of the number of the one or more second connection structures to the number of the one or more first connection structures is in the range of 1.8:1.0 to 2.0:0.8, for example, 2:1. The display substrate includes a plurality of pixels PX and a plurality of dummy pixels DPX. As used herein, the term "dummy" refers to a pixel having a structure that is the same or similar to an active pixel, but the structure is only used for a configuration that exists as a pattern, and does not actually perform a function in the display substrate. Therefore, an electrical signal may not be applied to a "dummy" pixel, or even in the case where an electrical signal is applied to a "dummy" pixel, the "dummy" pixel may not perform an electrically equivalent function. Optionally, the ratio of the sum of the number of the pixels and the number of the dummy pixels to the number of the one or more first connection structures is in the range of 1.8:1.0 to 2.0:0.8, for example, 2:1. Each of the first repeating units may include a pixel or a dummy pixel. Each of the second repeating units may include a pixel or a dummy pixel.

[0185] In some embodiments, see Fig.25 In one row of repeating units, the first repeating units and the second repeating units are arranged alternately. Alternatively, in one column of repeating units, the first repeating units and the second repeating units are arranged alternately.

[0186] In some embodiments, the dummy pixels are arranged in a plurality of rows. In a row of repeating units including the dummy pixels, a first repeating unit including the dummy pixels and a second repeating unit including the dummy pixels are alternately arranged.

[0187] In another aspect, the present disclosure provides a display device, comprising a display substrate as described herein or manufactured by a method as described herein, and one or more integrated circuits connected to an array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0188] On the other hand, the present invention provides a method for manufacturing a display substrate. In some embodiments, the method includes forming a light-emitting element on a planarization layer, the light-emitting element including a first electrode, an organic layer located on the first electrode, and a second electrode located on a side of the organic layer away from the first electrode; forming an auxiliary electrode, which is located in a different layer from the second electrode; forming one or more first connection structures, which electrically connect the auxiliary electrode to the second electrode respectively; and forming one or more second connection structures, which electrically connect the auxiliary electrode to the second electrode respectively. Optionally, forming each of the one or more first connection structures includes forming a conductive path, the conductive path including a sintered conductive material. Optionally, the conductive path is not included in the one or more second connection structures.

[0189] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A display substrate, comprising: planarization layer; a light emitting element located on the planarization layer, comprising a first electrode, an organic layer located on the first electrode, and a second electrode located on a side of the organic layer away from the first electrode; an auxiliary electrode, which is located in a different layer from the second electrode; one or more first connection structures, which respectively electrically connect the auxiliary electrode to the second electrode; as well as one or more second connection structures, which respectively electrically connect the auxiliary electrode to the second electrode; wherein each of the one or more first connection structures comprises a conductive path, and the conductive path comprises a sintered conductive material; as well as The one or more second connection structures do not include the conductive path.

2. The display substrate according to claim 1, comprising a light emitting area and a transparent area; in, The one or more first connection structures and the one or more second connection structures are located in the transparent area.

3. The display substrate according to claim 2, wherein: Each first connection structure is spaced apart from the light emitting area by a first shortest distance; Each of the one or more second connection structures is spaced apart from the light emitting region by a second shortest distance; and The first shortest distance is greater than the second shortest distance.

4. The display substrate according to claim 3, further comprising a planarization layer extending at least partially in the light emitting area; in, The orthographic projection of the planarization layer on the base substrate does not overlap with the orthographic projection of each first connection structure on the base substrate, but at least partially overlaps with the orthographic projection of each second connection structure on the base substrate.

5. The display substrate according to any one of claims 1 to 4, wherein: Each first connection structure includes a sequentially stacked structure including a connection electrode, a portion of the organic layer located on the connection electrode, and a portion of the second electrode located on a side of the portion of the organic layer away from the connection electrode.

6. The display substrate according to claim 5, wherein: The sintered conductive material includes at least one of an organic material of the portion of the organic layer, a conductive material of the connection electrode, or a conductive material of the portion of the second electrode.

7. The display substrate according to claim 5, wherein: The sintered conductive material includes the organic material of the portion of the organic layer, the conductive material of the connection electrode, and the conductive material of the portion of the second electrode.

8. The display substrate according to claim 5, wherein: The auxiliary electrode is located at a side of the connecting electrode away from the organic layer; The second electrode is connected to the connecting electrode through the conductive path, and further connected to the auxiliary electrode through the connecting electrode; and The auxiliary electrode at least partially extends in one or more sub-pixels.

9. The display substrate according to any one of claims 1 and 5 to 8, wherein: Each of the one or more second connection structures comprises a first connection electrode, a second connection electrode and a third connection electrode stacked in sequence; The second electrode is in direct contact with at least one of the first connecting electrode, the second connecting electrode or the third connecting electrode.

10. The display substrate according to claim 9, wherein: The auxiliary electrode is located at a side of the first connecting electrode away from the second connecting electrode; The first connecting electrode extends through the via hole to be connected to the auxiliary electrode; and The auxiliary electrode at least partially extends in one or more sub-pixels.

11. The display substrate according to claim 10, further comprising a pixel defining layer surrounding the sub-pixel area; The orthographic projection of the planarization layer on the base substrate at least partially overlaps with the orthographic projection of the pixel defining layer on the base substrate; and The orthographic projection of the pixel defining layer on the base substrate does not overlap with the orthographic projection of the second connection electrode on the base substrate, and does not overlap with the orthographic projection of the third connection electrode on the base substrate.

12. The display substrate according to claim 11, wherein: The second electrode extends from the light emitting region, across the pixel defining layer, into the transparent region to directly contact at least one of the first connection electrode, the second connection electrode, or the third connection electrode.

13. The display substrate according to any one of claims 9 to 12, wherein: Each second connection structure further includes at least one of the following: a remaining organic layer, which is stacked on a side of the third connection electrode away from the second connection electrode, the remaining organic layer being located in the same layer as the organic layer and at least partially separated from the organic layer; or The remaining second electrode is stacked on a side of the remaining organic layer away from the third connecting electrode. The remaining second electrode is located in the same layer as the second electrode and is at least partially separated from the second electrode.

14. The display substrate according to any one of claims 9 to 13, wherein: The first electrode comprises a first sublayer, a second sublayer and a third sublayer stacked in sequence; The first sublayer and the first connecting electrode are located in the same layer and are separated from each other by a pixel defining layer; The second sublayer and the second connecting electrode are located in the same layer and are separated from each other by the pixel defining layer; as well as The third sublayer and the third connecting electrode are located in the same layer and are separated from each other by the pixel defining layer.

15. The display substrate according to any one of claims 1 to 4 and 9 to 14, further comprising one or more dummy structures; in, Each of the one or more dummy structures comprises a structure stacked in sequence, which includes a connecting electrode, a portion of the organic layer located on the connecting electrode, and a portion of the second electrode located on a side of the portion of the organic layer away from the connecting electrode; Each dummy structure does not include a conductive path connecting the portion of the second electrode and the auxiliary electrode; as well as The portion of the second electrode is electrically isolated from the auxiliary electrode.

16. The display substrate according to any one of claims 1 to 15, wherein: In the display substrate, a ratio of the number of the one or more second connection structures to the number of the one or more first connection structures is greater than or equal to 0.9:1.

0.

17. The display substrate according to any one of claims 1 to 15, wherein: A ratio of the number of the one or more second connection structures to the number of the one or more first connection structures in the display substrate is in a range of 0.9:1.0 to 1.0:0.

9.

18. The display substrate according to any one of claims 1 to 14, comprising a plurality of first repeating units and a plurality of second repeating units; Each first repeating unit of the plurality of first repeating units comprises at least one first connecting structure of the one or more first connecting structures and at least one second connecting structure of the one or more second connecting structures; Each second repeating unit includes at least one dummy structure of the one or more dummy structures and at least one second connecting structure of the one or more second connecting structures; Each of the plurality of first repeating units includes the conductive path, while each of the plurality of second repeating units does not include the conductive path.

19. The display substrate according to claim 18, wherein: In a row of repeating units, the first repeating units and the second repeating units are arranged alternately; and In one column of repeating units, the first repeating units and the second repeating units are arranged alternately.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

Images