Controller and system for state compression in a storage unit

Abstract

A controller and system for state compression in a storage cell are disclosed. The controller includes a processor. In one embodiment, the processor is configured to set a value of D bits based on a value of M bits. M is an integer greater than 0 and D is an integer greater than 0. The controller is configured to write the value of D bits and the value of M bits into a storage cell of a non-volatile memory. In another embodiment, the controller is configured to read the value of M bits and the value of D bits from a storage cell of a non-volatile memory and the controller includes a processor configured to determine the value of M bits based on the value of D bits.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to state compression in a storage unit. BACKGROUND

[0002] With the continuous development of solid state drive (SSD) technology, different types of storage units have been developed to store data, including single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), and even penta-level cell (PLC).

[0003] For the storage unit of an SSD, different states are defined by a read reference voltage Vth. For example, in the case of SLC, a single read reference voltage Vth is used to define one bit (or one level) with two states "1" and "0". In the case of MLC, three read reference voltages Vth0, Vth1 and Vth2 are used to define two bits (or two levels) with four states "11", "10", "01" and "00". In the case of TLC, seven read reference voltages are used to define three bits (or three levels) with eight states "111", "110", "101", "100", "011", "010", "001" and "000". And, in the case of QLC, by utilizing fifteen read reference voltages, four bits (or four levels) with sixteen states "1111", "1110", "1101", "1100", "1011", "1010", "1001", "1000", "0111", "0110", "0101", "0100", "0011", "0010", "0001" and "0000" are defined. The case of PLC follows a similar pattern.

[0004] SLC cells store one bit of data per cell, providing high performance, endurance and reliability. They have faster read and write speeds, but are more expensive and have lower capacity compared to other cell types.

[0005] In an SSD, static data such as log files, system configuration data and firmware are stored in SLC cells. These data are written once, rarely changed, and require high reliability. Therefore, they are stored in SLC cells to reduce wear and maintain reliability.

[0006] In addition to these static data, a mapping table of logical addresses to physical addresses can be written to SLC cells when a power outage occurs. When power is restored, the firmware will read the mapping table from the SLC cells to rebuild the table.

[0007] The SLC cell can be used as a program data buffer. In this use case, the data to be programmed is first written to the SLC cell and then moved to the TLC cell during background programming operations.

[0008] Because SLC cells have a lower raw bit error rate and are more reliable than MLC / TLC / QLC cells, SLC cells are typically used to store the aforementioned critical data.

[0009] TLC / QLC can be used as SLC cells or TLC / QLC cells. For example, 20% of all cells in an SSD can be used as SLC cells.

[0010] If the number of SLC cells (including TLC / QLC cells used as SLC cells) can be reduced, the supply of TLC / QLC cells will increase. Therefore, the write amplification factor can be reduced, and the performance and lifespan of the SSD can be improved.

[0011] Reducing the number of SLC cells may be helpful while still meeting the data storage requirements previously met by SLC cells.

[0012] Although this disclosure uses SSDs to explain state compression, state compression can be applied to other types of storage. Summary of the Invention

[0013] In one embodiment, the controller has a processor configured to set the value of the D bit based on the value of the M bit. M is an integer greater than 0, and D is an integer greater than 0. The controller is configured to write the values ​​of the D bit and the M bit into a storage cell of non-volatile memory.

[0014] In another embodiment, the controller is configured to read the values ​​of M bits and D bits from a storage cell in non-volatile memory. M is an integer greater than 0, and D is an integer greater than 0. The controller has a processor configured to determine the value of the M bits based on the value of the D bits.

[0015] In yet another embodiment, the system includes a controller. The system is a solid-state drive (SSD), flash memory drive, motherboard, processor, computer, server, gaming device, or mobile device.

[0016] The foregoing, provided in a general manner, is not intended to limit the scope of the claims of this invention. The described embodiments, along with further advantages, will be best understood by referring to the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figure 1 A system according to one embodiment is illustrated schematically.

[0018] Figure 2 An example of state compression for a TLC cell is illustrated schematically.

[0019] Figure 3 An example of state compression for a QLC cell is illustrated schematically.

[0020] Figure 4 The Gray code state representation in normal TLC mode is shown.

[0021] Figure 5 The 8-to-4 compression state representation of TLC Example 1 is shown.

[0022] Figure 6 The state representation in normal TLC mode is shown.

[0023] Figure 7 The shift of the read reference voltage for read retry of UP is schematically shown.

[0024] Figure 8 The 8-to-4 compression state representation of TLC Example 2 is shown.

[0025] Figure 9 This shows the Gray code state representation in another normal TLC mode.

[0026] Figures 10-13 Four compression schemes for 8 to 4TLC states are shown.

[0027] Figure 14 The Gray code state representation in normal QLC mode is shown.

[0028] Figure 15 The 16-to-8 compression state representation of QLC Example 1 is shown.

[0029] Figure 16 The 16-to-4 compression state representation of QLC Example 2 is shown.

[0030] Figure 17 This is a schematic flowchart of the word line programming operations of the fully protected state compression scheme disclosed herein.

[0031] Figure 18 This is a schematic flowchart of the word line reading operation of the fully protected state compression scheme disclosed herein.

[0032] Figure 19 The illustration schematically shows a portion of page usage in the state compression scheme within a TLC block. Detailed Implementation

[0033] Embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same reference numerals for consistency.

[0034] This disclosure proposes a state compression scheme that can provide better reliability for data storage in SSDs. The state compression scheme can be used to reduce the number of SLC blocks in an SSD, thereby increasing the SSD's lifespan.

[0035] State compression schemes use fewer states for data storage compared to the physical number of states in a non-volatile memory (NVM) cell. For example, a TLC cell physically has 8 states, but under a state compression scheme, only 2 or 4 states are used for data storage. That is, under a state compression scheme, a TLC cell is used as an SLC cell or an MLC cell. Similarly, a QLC cell physically has 16 states, but under a state compression scheme, only 2, 4, or 8 states are used for data storage. That is, under a state compression scheme, a QLC cell is used as an SLC cell, an MLC cell, or a TLC cell.

[0036] In other words, although TLC has 8 states and QLC has 16 states, state compression can be achieved by applying an encoding scheme to the programming data. This reduces the number of states on the word lines in TLC or QLC, and due to fine-grained programming operations, the margin between two adjacent states is greater than that of normal TLC / QLC word lines. Therefore, state-compressed word lines may have better reliability and a lower raw bit error rate (BER).

[0037] Similarly, the proposed solution can also be applied to MLC and PLC.

[0038] Figure 1 A system according to one embodiment is illustrated schematically.

[0039] In some embodiments, the system is a solid-state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

[0040] System 100 may include controller 102 and nonvolatile storage device (NVM) 104. In some embodiments, system 100 may function as a storage system and provide data storage and / or access to stored data to a host when connected to a host.

[0041] Storage device 104 may be non-volatile memory (NVM), such as a NAND device. System 100 may include multiple non-volatile storage devices, and storage device 104 may be represented as a representative of multiple non-volatile storage devices.

[0042] The controller 102 includes a processor 106. The processor 106 may be a computer processor, such as, but not limited to, a microprocessor or a microcontroller.

[0043] The controller 102 can write data to the storage device 104 and read data from the storage device 104. The processor 106 can perform some processing on some data to be written to the storage cells of the storage device 104 or some data to be read from the storage cells of the storage device 104.

[0044] A storage cell is the smallest physical storage unit in storage device 104. In some embodiments, a storage cell may be a NAND cell. In the cases of SLC, MLC, TLC, QLC, and PLC, a storage cell is configured to store 1, 2, 3, 4, and 5 bits of data, respectively, by defining 2, 4, 8, 16, and 32 states using 1, 3, 7, 15, and 31 read reference voltages. Data is written to the storage cell by programming voltages within a range corresponding to the bit values ​​of the data into the storage cell, and data is read from the storage cell by comparing a threshold voltage of the storage cell with a read reference voltage.

[0045] The term "bit" refers to a binary digit, which is the basic unit of information in computing, digital communication, and data storage. It is usually represented by 0 or 1, corresponding to two possible states of a digital signal or two values ​​in binary code.

[0046] Assume the storage unit is initially configured to store N bits of data, with 2 N There are several states. Here, N is an integer greater than 1. For example, N=2 represents MLC mode; N=3 represents TLC mode; N=4 represents QLC mode; and N=5 represents PLC mode.

[0047] The MLC cell is configured to store 2 bits of data, which can be mapped to 2 pages: a next page "LP" and a previous page "UP". The TLC cell is configured to store 3 bits of data, which can be mapped to 3 pages: a next page "LP", a previous page "UP", and an extra page "XP". The QLC cell is configured to store 4 bits of data, which can be mapped to 4 pages: a next page "LP", a middle page "MP", a previous page "UP", and a top page "TP".

[0048] Under the state compression scheme, 2 N The states can be compressed into 2. M There are M states, corresponding to M bits. In other words, the data expected to be written to the memory unit has M bits. Here, M is an integer greater than 0, for example, M=1, M=2, M=3, or M=4. The M bits of data can be the data expected to be written to the memory unit.

[0049] Since memory cells are initially designed and configured for N bits—for example, in TLC mode with N=3 bits or QLC mode with N=4 bits—the word lines connected to the memory cell are configured for N bits (or N pages). Under state compression schemes, there are still D=NM bits (pages) of data needed for programming; these can be referred to as "redundant bits" or "redundant pages." Here, D is an integer greater than 0. For example, D=1 or D=2.

[0050] With D=1, M=1 for MLC mode; M=2 for TLC mode; M=3 for QLC mode; and M=4 for PLC mode.

[0051] With D=2, M=1 for TLC mode; M=2 for QLC mode; and M=3 for PLC mode.

[0052] The controller 102 can perform write and / or read operations on the storage cells of the non-volatile memory (NVM) 104, which may be referred to as a "write embodiment" or a "read embodiment". It should be understood that when the controller 102 is configured to read data from the non-volatile memory (NVM) 104, this does not mean that the data in the non-volatile memory (NVM) 104 is written by the controller 102.

[0053] In the implementation of the write operation, processor 106 is configured to set the value of bit D based on the value of bit M. For example, processor 106 is configured to set the value of bit D using the result of one or more logical operations (e.g., AND, disjunction, NOT, XOR) performed on one or more values ​​of bit M.

[0054] In some embodiments, the processor 106 is configured to set the value of at least one bit in the D bit based on the value of only one bit in the M bit.

[0055] In some other embodiments, the processor 106 is configured to set the value of at least one bit in the D bit based on the value of only two bits in the M bit.

[0056] The controller 102 is configured to write the values ​​of the D bits and the M bits into the storage cells of the non-volatile memory (NVM) 104.

[0057] In some cases, D-bit data derived from the value of M bits can be used to recover or correct one or more missing or erroneous bits in the M bits. This can be performed when checking, recovering, or correcting one or more bits in the M bits.

[0058] In the reading embodiment, controller 102 is configured to read the values ​​of M bits and D bits from the storage cells of non-volatile memory (NVM) 104, and processor 106 is configured to determine the value of M bits based on the value of D bits.

[0059] In some embodiments, the processor 106 is configured to determine the value of at least one bit in the M bits based on the value of only one bit in the D bits.

[0060] In some other embodiments, the processor 106 is configured to determine the value of at least one bit in the M bits based on the value of only two bits in the D bits.

[0061] In the above embodiments and examples, N = M + D. It should be understood that in some other embodiments, N = M + D + E is also possible. Here, E is an integer greater than 0. The D redundant bits are set based on the value of the M bits of data expected to be written to the memory cell, while the further E bits can be set in any other suitable manner. The controller 102 is configured to write the values ​​of the E bits, the D bits, and the M bits into the memory cell of the non-volatile memory (NVM) 104.

[0062] The following sections will describe some schemes for setting the value of the D bit or determining the value of the M bit. Logical operations such as NOT, decomposition, and XOR will be used in the setting schemes.

[0063] The "invert" operation, also known as the logical "NOT" operation, is sometimes represented by the simple "~" and is used to flip or reverse the state of a bit value. For example, the inverted value of bit 0 is 1, and the inverted value of bit 1 is 0.

[0064] The "disjunction" of two bits, also known as the logical "OR" operation, is sometimes represented by the symbol "|". It returns 1 if at least one bit is 1. Otherwise, it returns 0.

[0065] The following is the truth table for disjunction:

[0066] Bit A Bit B A OR B 0 0 0 0 1 1 1 0 1 1 1 1

[0067] As shown in the truth table, if bit A or bit B (or both) is 1, the result of the disjunction operation will be 1. The result is 0 only when both bits are 0.

[0068] The "exclusive OR" operation on two bits, also known as the logical "XOR" operation, returns 1 if the two bits have different values. Otherwise, it returns 0.

[0069] The following is the truth table for the XOR operation:

[0070] Bit A Bit B A XOR B 0 0 0 0 1 1 1 0 1 1 1 0

[0071] As shown in the truth table, the XOR operation results in 1 when two bits have different values ​​(one is 0 and the other is 1). If the two bits are the same (either both are 0 or both are 1), the result is 0.

[0072] In the writing embodiment, the processor is configured to set the value of at least one bit in the D bits to the value of one bit in the M bits.

[0073] For example, for a TLC cell, if LP and UP are designed to store M (M=2) bits of data and XP is designed to store one of D (D=1) bits, then the value of XP can be set to the value of UP or LP, i.e., XP=UP or XP=LP.

[0074] Accordingly, in the reading embodiment, the processor is configured to determine the value of one bit in the D bits as the value of at least one bit in the M bits.

[0075] For example, in a TLC cell, LP and UP are designed to store M (here M = 2) bits of data, and XP is designed to store one bit out of D (here D = 1) bits. The value of XP is set to the value of UP (or LP), that is, when data is written to the memory cell, XP = UP (or XP = LP). If, when reading the value of the bit written to the memory cell, UP (or LP) cannot be decoded, but XP can be decoded, then the value of UP (or LP) can be determined as the value of XP.

[0076] In another implementation of the write operation, the processor is configured to set the value of at least one bit in the D bits to the XOR NOT of the values ​​of the two bits in the M bits.

[0077] For example, for a TLC cell, if LP and UP are designed to store M (here M=2) bits of data, and XP is designed to store one of D (here D=1) bits, then the value of XP can be set to XP=NOT(UP XOR LP).

[0078] Alternatively, if LP and XP are designed to store M (M=2) bits of data, and UP is designed to store one of D (D=1) bits, then the value of UP can be set to UP=NOT(XP XOR LP).

[0079] Accordingly, in the reading embodiment, the processor is configured to determine the value of at least one of the M bits as the XOR of the value of another of the M bits and the inverse of the value of one of the D bits, or is configured to determine the value of at least one of the M bits as the XOR of the value of one of the D bits and the inverse of the value of another of the M bits.

[0080] For example, for a TLC cell, LP and UP are designed to store M (here M = 2) bits of data, and XP is designed to store one bit out of D (here D = 1) bits, and the value of XP is set to XP = NOT (UP XOR LP). If XP and UP can be decoded from the storage cell but LP cannot be decoded, LP can be determined based on LP = (NOT XP) XOR UP. If XP and LP can be decoded but UP cannot be decoded, UP can be determined based on UP = (NOT XP) XOR LP.

[0081] In another example, LP and XP are designed to store M (here M = 2) bits of data, and UP is designed to store one bit out of D (here D = 1) bits. The value of UP is set to UP = NOT(XP XOR LP). If UP and LP can be decoded from the memory location, but XP cannot be decoded, XP can be determined based on XP = (NOT UP) XOR LP. If UP and XP can be decoded, but LP cannot be decoded, LP can be determined based on LP = (NOT UP) XOR XP.

[0082] In another example, UP and XP are designed to store M (here M = 2) bits of data, and LP is designed to store one bit out of D (here D = 1) bits. The value of LP is set to LP = NOT(XP XOR UP). If LP and UP can be decoded from the memory location, but XP cannot be decoded, XP can be determined based on XP = (NOT LP) XOR UP. If LP and XP can be decoded, but UP cannot be decoded, UP can be determined based on UP = (NOT LP) XOR XP.

[0083] In another implementation of the write operation, the processor is configured to set the value of at least one bit in the D bits to the disjunction of the inverse of one bit in the M bits and the inverse of the other bit in the M bits.

[0084] For example, for a TLC cell, if LP and UP are designed to store (here M=2) bits of data, and XP is designed to store one bit of (here D=1) bits, then the value of XP can be set to XP=(~LP)|(~UP), that is, XP=(NOT LP)OR(NOT UP).

[0085] In another implementation of the write operation, the processor is configured to set the value of at least one bit in the D bits to a disjunction of the value of one bit in the M bits and the inverse of the value of the other bit in the M bits.

[0086] For example, for a TLC cell, if LP and UP are designed to store (here M=2) bits of data, and XP is designed to store one bit of (here D=1) bits, then the value of XP can be set to XP=LP|(~UP), that is, XP=(LP)OR(NOT UP).

[0087] In another implementation of the write operation, the processor is configured to set the value of at least one bit in the D bits to the XOR of the values ​​of the two bits in the M bits.

[0088] For example, for a TLC cell, if LP and XP are designed to store (here M=2) bits of data, and UP is designed to store one bit of (here D=1) bits, then the value of UP can be set to UP = XP XOR LP.

[0089] In another implementation of the write operation, the processor is configured to set the value of at least one of the D bits to the XOR result of the values ​​of the second and third bits and the XOR result of the value of the first bit, wherein the first, second, and third bits are three of the M bits.

[0090] For example, for a QLC cell, if LP, MP, and UP are designed to store (here M=3) bits of data, and TP is designed to store one bit of (here D=1) bits, then the value of TP can be set to TP = LP XOR MP XOR UP.

[0091] It should be understood that if M is greater than 3, then the first, second, and third bits can be any three bits from the M bits. The first, second, and third bits do not imply any specific bit. For example, the first bit is not necessarily the most significant bit.

[0092] The state compression effect produced by the scheme of this disclosure will be described below with some examples.

[0093] According to the scheme disclosed herein, although TLC has 8 states and QLC has 16 states, state compression can be achieved by applying an encoding scheme to the programming data. This reduces the number of word line states in TLC or QLC, and due to fine-grained programming operations, the margin between two adjacent states is greater than that of normal TLC / QLC word lines. Therefore, state-compressed word lines have better reliability and lower raw BER.

[0094] Similarly, the proposed solution can also be applied to MLC and PLC.

[0095] Figure 2 An example of state compression for a TLC cell is illustrated schematically.

[0096] like Figure 2As shown, in normal TLC mode, eight states T0, T1, T2, T3, T4, T5, T6, and T7 are defined using seven read reference voltages Vth (as indicated by seven upward arrows). Each word line has three data pages and zero redundant pages.

[0097] When the TLC cell applies the 8-to-4 state compression scheme, the four non-adjacent states (e.g., T0, T2, T5, T7) in the original list of eight states are retained. Each word line has two data pages and one redundant page.

[0098] When the TLC cell applies the 8-to-2 state compression scheme, two non-adjacent states (e.g., T0 and T7) from the original 8-state list are retained. Each word line has 1 data page and 2 redundant pages.

[0099] Figure 3 An example of state compression for a QLC cell is illustrated schematically.

[0100] like Figure 3 As shown, in normal QLC mode, 16 states Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, and Q15 are defined using 15 read reference voltages Vth (as indicated by 15 upward arrows). Each word line has 4 data pages and 0 redundant pages.

[0101] When the QLC cell applies a 16-to-8 state compression scheme, the eight non-adjacent states (e.g., Q0, Q2, Q4, Q6, Q8, Q10, Q12, and Q15) in the original list of 16 states are retained. Each word line has three data pages and one redundant page.

[0102] When the QLC cell applies a 16-to-4 state compression scheme, the four non-adjacent states (e.g., Q0, Q5, Q10, Q15) in the original list of 16 states are retained. Each word line has two data pages and two redundant pages.

[0103] When the QLC cell applies a 16-to-2 state compression scheme, two non-adjacent states (e.g., Q0 and Q15) in the original list of 16 states are retained. Each word line has one data page and three redundant pages.

[0104] As can be seen from the above description, the state compression scheme provides a trade-off between data reliability and the overhead of SSD storage of critical data.

[0105] In traditional SSDs with TLC flash NAND without state compression, the blocks used as SLC regions comprise approximately 20% of the entire flash NAND block. If we replace the SLC regions with 4-state compressed TLC, only 10% of the entire block is needed. The remaining 10% can be used as TLC regions to provide more reserved space. Therefore, the overhead of storing critical data and the overhead of data buffering are half that of traditional SSDs.

[0106] In some embodiments, state-compressed MLC can be used to store critical data instead of SLC.

[0107] A TLC cell stores eight states, which can be represented by eight three-bit binary codes. The correspondence between the eight three-bit binary codes and the eight states can be established using different sorting methods.

[0108] Gray code is a binary number system that represents consecutive values ​​in such a way that only one bit changes between consecutive values.

[0109] In Gray code state representation, each state is encoded using a binary code, where adjacent states differ by only one bit. This helps reduce the likelihood of errors due to noise or signal distortion during transmission or processing.

[0110] For a given Gray code state representation, there are multiple state compression schemes, some of which (which can be called "fully protected state compression schemes") provide better data protection than others.

[0111] Several examples of state compression schemes will be described in more detail below.

[0112] TLC Example 1

[0113] This is an example of compressing the 8 states of a TLC cell into 4 states.

[0114] Figure 4 The Gray code state representation in normal TLC mode is shown and can be used in this example.

[0115] like Figure 4 As shown, in this Gray coding rule, the eight states T0, T1, T2, T3, T4, T5, T6, and T7 are mapped to eight three-bit binary codes: 111, 011, 001, 101, 100, 000, 010, and 110, respectively. As mentioned earlier, the first bit (left) corresponds to XP (extra page), the middle bit corresponds to UP (previous page), and the last bit (right) corresponds to LP (next page).

[0116] The eight states are defined by seven read reference voltages V1 to V7.

[0117] LP can be determined by a single read reference voltage V4, as indicated by the longest upward arrow.

[0118] UP can be determined by two read reference voltages, V2 and V6, as shown by the medium-length upward arrow. If the cell's threshold voltage is between V2 and V6, then UP = 0. If the cell's threshold voltage is not between V2 and V6, then UP = 1.

[0119] XP can be determined by four read reference voltages V1, V3, V5, and V7, as shown by the shortest upward arrow.

[0120] By setting XP=LP, only four states are retained: 111, 001, 000, and 110. Therefore, the eight states of the normal TLC mode are compressed into four states.

[0121] In this example, the extra page (XP) data is encoded to be identical to the previous page (UP) data (XP = LP), which results in state compression.

[0122] Figure 5 The 8-to-4 compression state representation of TLC Example 1 is shown.

[0123] With state compression, TLC mode storage cells can now be used in MLC mode.

[0124] In TLC Example 1, the UP bit is protected. If UP cannot be decoded when reading the value of the bit written to the memory cell, but XP can be decoded, then UP can be restored by UP = XP.

[0125] Figure 6 The state representation in normal MLC mode is shown.

[0126] Compare Figure 5 and Figure 6 The difference between TLC 8-to-4 state compression and normal MLC can be seen. Although Figure 5 and Figure 6 Each cell has four states, but the MLC states are closer together, while the TLC 8-to-4 state compression has a wider valley window between the states. The wider valley window can provide a lower RBER (raw bit error rate).

[0127] The dual-encoded unit distribution in TLC mode (e.g.) Figure 5 As shown) compared to MLC mode (e.g.) Figure 6 (As shown) This is much better because NAND uses a fine-grained programming mode for TLC operations, rather than MLC programming operations. This ensures more reliable data and a lower RBER, thus providing another way to store critical data and reduce the number of SLC blocks required.

[0128] In addition, extra pages (XP) provide another layer of protection for the previous page (UP).

[0129] If the previous page (UP) cannot be decoded, but the extra page (XP) can be decoded, the data of the previous page (UP) can be recovered by decoding the extra page (XP).

[0130] However, the data on the next page (LP) is not protected by the XP and UP data. Therefore, this scheme is not a fully protected state compression scheme.

[0131] Use such as Figure 5 The state compression scheme shown can be used to read the UP bit using the voltage between V1 and V2, or V2 (preferably) or V1.

[0132] In TLC Example 1, the probability of a next page (LP) error is very low for the following reasons.

[0133] First, unlike the previous page (UP) and extra page (XP), which apply two internal reads, the next page (LP) only applies a single read, resulting in a lower error rate.

[0134] Secondly, since the proposed scheme does not have T3 and T4 states, the margin of the read reference voltage Vref4 (V4) is greatly increased relative to the adjacent states, and the RBER is greatly reduced.

[0135] On the other hand, while the read margin for the next page (LP) Vref is improved on both sides of the adjacent state, the read margin for the UP and XP Vref is improved on only one side.

[0136] For example, XP Vref(V1, V3, V5, and V7) gains increased read margin to the right of states T1 and T3 and to the left of states T4 and T6.

[0137] UP Vref(V2 and V6) gains an increased read margin to the right of state T6 and to the left of state T1.

[0138] like Figure 5 As shown, in Example 1, the default Vrefs for UP and XP are no longer aligned with the center of the new valley window.

[0139] Now that the narrow margin point is known, read retry in UECC can apply a shifted Vref to the center of the new valley window to obtain a smaller RBER and a higher probability of successful decoding, such as... Figure 5 As shown.

[0140] Figure 7 The shift of the read reference voltage for the UP read retry is schematically shown.

[0141] like Figure 7As shown, the read reference voltage V2 used to read UP can be shifted from the right side of the valley window between T0 and T2 to the middle of the valley window, i.e., V'2, and the read reference voltage V6 used to read UP can be shifted from the left side of the valley window between T5 and T7 to the middle of the valley window, i.e., V'6.

[0142] TLC Example 2

[0143] In TLC Example 2, using and Figure 4 The same Gray coding rules shown are used for normal TLC mode.

[0144] In this example, the XP page is set to XP = NOT (UP XOR LP).

[0145] Figure 8 The 8-to-4 compression state representation of TLC Example 2 is shown.

[0146] like Figure 8 As shown, the remaining 4 states are T0(111), T2(001), T4(100) and T6(010).

[0147] When reading from a storage unit, if only one page cannot be decoded, it can be recovered using the data from the other two pages.

[0148] Therefore, the extra page (XP) provides another layer of protection for the previous page (UP) and the next page (LP).

[0149] Therefore, the state compression scheme in this example is a fully protected state compression scheme.

[0150] It should be noted that for the 8-to-4 state compressed TLC scheme, although there are only four states after programming, representing two pages of user data, three pages of data are still required for programming because the word line is in TLC mode. The remaining pages are used as redundant pages.

[0151] In some embodiments, any two of the three pages may be used for user data, while the remaining page may be used as a redundant page. In some embodiments, it may be preferred or less preferred to allocate some of the three pages to the data page and the redundant page.

[0152] For based on Figure 4 The TLC example 1 for the Gray coding rules of the states shown in the figure illustrates an 8 to 4 state compression scheme that can use (UP, LP) or (XP, LP) to store two pages of user data, but using (XP, UP) is not preferred.

[0153] For (UP, LP), XP will be a redundant page, providing another copy of UP.

[0154] Similarly, if (XP, LP) is used, UP will be a redundant page, providing another copy of XP.

[0155] However, since LP has a lower decoding failure probability compared to UP and XP, using LP as a redundant page is not preferred. One of UP and XP can be used as a redundant page to protect the other.

[0156] For the 8-to-4 state compression scheme shown in TLC Example 2, data pages can be any two pages: (LP, UP), (LP, XP), or (UP, XP). The remaining pages are redundant pages.

[0157] To reduce read latency, (LP, UP) will be used as the data page, and XP will be used as a redundant page because LP only requires one read reference voltage Vref (V4), UP requires two read reference voltages Vref (V2, V6), while XP requires four read reference voltages Vref (V1, V3, V5, V7).

[0158] TLC Example 3

[0159] The Gray code state representation used for TLC in this example is different from that in TLC Examples 1 and 2.

[0160] Figure 9 The Gray code state representation in another normal TLC mode used in TLC Example 3 is shown.

[0161] like Figure 9 As shown, in this Gray coding rule, the eight states T0, T1, T2, T3, T4, T5, T6 and T7 are mapped to eight three-bit binary codes 111, 110, 100, 000, 010, 011, 001 and 101, respectively.

[0162] The eight states are defined by seven read reference voltages V1 to V7.

[0163] Specifically, LP requires two read reference voltages Vref (V1, V5); XP requires two read reference voltages Vref (V3, V7); and UP requires three read reference voltages Vref (V2, V4, V6). The read reference voltages for each page are schematically indicated by upward arrows of varying lengths.

[0164] and Figure 4 The Gray code state representation shown is similar, for Figure 9 The Gray code state representation shown can be implemented in various ways from 8 to 4 TLC state compression.

[0165] Figures 10-13 Four compression schemes for 8 to 4TLC states are shown.

[0166] Figure 10 The first scheme is achieved by setting XP = (~LP)|(~UP), i.e., XP = (NOT LP) OR (NOT UP). The remaining four states are T1 (110), T2 (100), T5 (011), and T7 (101).

[0167] Figure 11 This is achieved through the second scheme, which sets XP = LP | (~UP), i.e., XP = LP OR (NOT UP). The remaining four states are T0 (111), T2 (100), T4 (010), and T7 (101).

[0168] Figure 12 The third approach is implemented by setting XP = NOT (UP XOR LP). The remaining four states are T0 (111), T2 (100), T4 (010), and T6 (001).

[0169] exist Figures 10-12 Of the schemes shown, only Figure 12 The third scheme shown provides a large margin between two adjacent states while protecting for extra pages (XP) and the next page (LP). Therefore, Figure 12 The third scheme shown is a fully protected 8-to-4 state compression scheme, and provides better performance than... Figure 10 and Figure 11 The first and second schemes shown are better 8-to-4 state compression schemes.

[0170] for Figure 12 In the third scheme, to reduce read latency, XP and LP are used for data pages; UP is used for redundant pages. This is because, as mentioned above, in Figure 9 In the Gray code state representation shown, UP uses 3 read reference voltages, while XP and LP use 2 read reference voltages.

[0171] If one of the data pages cannot be decoded, a redundant page will be read and decoded. If the redundant page can be decoded, the other data page and the redundant page can be used to recover the data page that failed to be decoded.

[0172] Specifically, if in Figure 12 In the third scheme shown, data is written to the storage unit, which can decode LP and UP, but cannot decode XP. Therefore, XP can be determined by XP = (NOT UP) XOR LP.

[0173] Similarly, Figure 13 based on Figure 9 The same Gray code state representation shown provides another fully protected 8-to-4 state compression scheme. Figure 13This is achieved through the fourth scheme, which sets UP = (XP XOR LP). The remaining four states are T1 (110), T3 (000), T5 (011), and T7 (101).

[0174] QLC Example 1

[0175] This is an example of compressing the 16 states of a QLC cell into 8 states.

[0176] Figure 14 The Gray code state representation in normal QLC mode is shown and can be used in this example.

[0177] like Figure 14 As shown, in this Gray coding rule, the 16 states T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, and T15 are mapped to 16 four-bit binary codes: 1111, 1110, 1100, 1101, 1001, 0001, 0000, 1000, 1010, 0010, 0110, 0100, 0101, 0111, 0011, and 1011, respectively. As mentioned earlier, the first bit (left) corresponds to TP (top page), the second bit corresponds to UP (previous page), the third bit corresponds to MP (middle page), and the last bit (right) corresponds to LP (next page).

[0178] The 16 states consist of 15 read reference voltages V1 to V2. 15 definition.

[0179] Specifically, LP requires four read reference voltages Vref (V1, V3, V6, V...). 12 MP requires four read reference voltages Vref (V2, V8, V...). 11 V 13 ); The UP requires three read reference voltages Vref(V4, V); 10 V 14 ); TP requires four read reference voltages Vref (V5, V7, V9, V... 15 The reference voltage for each page is schematically indicated by upward arrows of varying lengths.

[0180] In this example, LP, MP, and UP can be used as three data pages to store user data, while TP can be used as a redundant page.

[0181] A 16-to-8 fully protected state compression scheme for QLC is achieved by setting TP=LP XOR MP XOR UP.

[0182] Figure 15 The 16-to-8 compression state representation of QLC Example 1 is shown.

[0183] like Figure 15 As shown, the remaining 8 states are T0(1111), T2(1100), T4(1001), T6(0000), T8(1010), T10(0110), T12(0101) and T14(0011).

[0184] When reading data from a storage unit, if any of the data pages LP, MP, and UP cannot be decoded, the successfully decoded TP can be used to recover the failed page.

[0185] QLC Example 2

[0186] Figure 16 This illustrates a 16-to-4 compression state representation for QLC Example 2. QLC Example 2 is based on... Figure 14 The same Gray code state representation is shown.

[0187] For Gray code state representations, there may not be a fully protected 16-to-4 state compression scheme. For example, for Figure 14 The Gray code states shown indicate that there is no fully protected 16-to-4 state compression.

[0188] For this state compression scheme, (T0, T5, T10, T15) will be selected to increase the margin between any two adjacent states.

[0189] Furthermore, in this example, TP and UP will be used as data pages. For this state compression scheme, LP and MP can be used as redundant pages to provide additional data protection for the data in TP.

[0190] The above describes several examples of state compression schemes for TLC and QLC.

[0191] In a TLC cell, if no two adjacent states in the 8-to-4 state compression scheme satisfy one of the following two fully protected 8-to-4 state compression scheme coding rules: XP = NOT (UP XOR LP) or XP = UP XOR LP, then one of the pages with the maximum number of Vrefs (LP, UP, and XP) can be used as a redundant page, and the other two pages can be used as data pages.

[0192] In a QLC unit, a fully protected 16-to-8 state compression scheme is defined by one of the coding rules: TP = NOT(UP XOR MP XOR LP) and TP = UP XOR MP XOR LP. The page with the largest number of Vrefs among LP, MP, UP, and TP can be used as a redundant page, while the other three pages can be used as data pages.

[0193] Figure 17This is a schematic flowchart of the programming operations for word lines with the state compression scheme of this disclosure.

[0194] Programming operations can be performed by Figure 1 The controller 102 of the system 100 shown is executed.

[0195] like Figure 17 As shown, in step S110, the data page is prepared.

[0196] Then, in step S120, redundant pages are generated (or set) based on the corresponding encoding rules.

[0197] As described in this disclosure, redundant pages may be based on at least one page of data pages.

[0198] Then, in step S130, all data pages and redundant pages are programmed to word lines to be written to the memory cell.

[0199] If the data stored in the state-compressed storage unit is programmed with a fully protected state compression scheme, then when reading the data stored in the storage unit, failed data page decoding can be recovered with the help of redundant pages.

[0200] Figure 18 This is a schematic flowchart of the word line reading operation of the fully protected state compression scheme disclosed herein.

[0201] Read operations can be performed by Figure 1 The controller 102 of the system 100 shown is executed.

[0202] Figure 18 An example of reading a data page from a state-compressed storage unit with multiple pages is shown.

[0203] like Figure 18 As shown, in step S210, a data page is read from the storage cell, for example, by using a read reference voltage corresponding to this data page.

[0204] In step S220, it is checked whether the data page can be decoded. For example, the page can be decoded using an ECC decoder.

[0205] If decoding is successful, the process proceeds to step S230, where the page data is output as the result. The process then ends.

[0206] If decoding fails, the process proceeds to step S240, where all other pages are read from the storage unit.

[0207] In step S250, it is checked whether all other pages in the same word line can be decoded.

[0208] If all other pages in the same word line can be decoded, the process proceeds to step S260, where data from all these other pages is used to recover the data for that page and output that page data as the result. The process then ends.

[0209] If any of the other pages cannot be successfully decoded, the process proceeds to step S270, where another advanced error recovery scheme can be attempted.

[0210] The state compression scheme proposed in this disclosure can be used by various parts of the word line.

[0211] Figure 19 The illustration schematically shows a portion of page usage in the state compression scheme within a TLC block.

[0212] like Figure 19 As shown, a portion of the TLC block (e.g., the first four bytes of three pages (LP, UP, and XP) of the TLC word line) is encoded using a state compression scheme. The remaining portion of the TLC block (e.g., the remaining bytes of the word line) is programmed in the normal manner.

[0213] Some 64-bit attribute data (such as the programming temperature of the current word line) can be stored in the state-compressed portion (e.g., the first four bytes of three pages) using a fully protected 8-to-4 state compression scheme. The remaining space in the word line reserved for normal mode can be used to store uncompressed main data.

[0214] Even if word line decoding attempts using the default Vref fail, the property data stored using the 8-to-4 state compression scheme can still be retrieved correctly due to its enhanced reliability and additional protection, and can be used to select the best Vref for the next read retry.

[0215] If you wish to further improve the reliability of attribute data, you can use an 8-to-2 state compression scheme by providing a trade-off between data size and reliability.

[0216] Using the new best Vref, uncompressed master data can be successfully decoded.

[0217] Therefore, the state compression scheme proposed in this disclosure provides better reliability than normal TLC or QLC modes. Some critical data previously stored in SLC blocks can now be stored in state-compressed TLC or QLC storage cells.

[0218] Therefore, state compression schemes can be used to reduce the number of blocks used for SLC in an SSD, thereby increasing the lifespan of the SSD.

[0219] As mentioned above, for 8 to 4TLC state compression schemes and 16 to 8QLC state compression schemes, fully protected state compression schemes can be found and used to provide additional data protection.

[0220] For 16 to 4QLC state compression schemes, a (T0, T5, T10, T15) state compression scheme will be used to provide better reliability.

[0221] In order to use the state compression scheme proposed in this disclosure, the data randomization after the ECC encoding engine is disabled should be performed.

[0222] Furthermore, the state compression scheme proposed in this disclosure can be used by the entire word line or a portion of the word line.

[0223] The state compression scheme presented in this disclosure can be dynamically applied to portions of a block without converting the entire block to a more reliable state (such as SLC). For example, when the host notifies the SSD of data of critical nature (e.g., using a write FUA (Forced Cell Access) command), the device can write this data to a word line using the state compression scheme.

[0224] While various aspects and embodiments have been disclosed, those skilled in the art will appreciate other aspects and embodiments. The various aspects and embodiments disclosed herein are for illustrative purposes only and are not intended to be limiting; the true scope and spirit of protection are indicated by the claims.

Claims

1. A controller, characterized in that, include: The processor is configured to set the value of the D bits based on the value of the M bits, where M is a positive integer and D is a positive integer; The controller is configured to write the values ​​of the D bits and the M bits into the storage cells of the non-volatile memory; the controller is also configured to program a first part of the block using a state compression scheme to store attribute data, and to program a second part of the block in normal mode to store uncompressed master data; the attribute data is used to select a read reference voltage for read retry when the master data decoding fails.

2. The controller according to claim 1, characterized in that, The processor is configured to set the value of the D bit using one or more results of one or more logical operations performed on one or more of the values ​​of the M bits.

3. The controller according to claim 1, characterized in that, D=1, D=2, or D=3.

4. The controller according to claim 1, characterized in that, M=1, M=2, M=3 or M=4.

5. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one of the D bits to the value of one of the M bits.

6. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one of the D bits to the XOR NOT of the values ​​of the two M bits.

7. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one of the D bits to the disjunction of the inverse of the value of one of the M bits and the inverse of the value of the other of the M bits.

8. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one of the D bits to the disjunction of the value of one of the M bits and the inverse of the value of the other of the M bits.

9. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one of the D bits to the XOR of the values ​​of the two M bits.

10. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one of the D bits to the XOR result of the values ​​of the second and third bits and the XOR result of the value of the first bit, wherein the first, second, and third bits are any three of the M bits.

11. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one bit in the D bits based on the value of only one bit in the M bits.

12. The controller according to claim 1, characterized in that, The processor is configured to set the value of at least one bit in the D bit based on the value of only two bits in the M bit.

13. A system, characterized in that, Includes the controller according to claim 1, wherein the system is a solid-state drive, flash drive, motherboard, processor, computer, server, gaming device, or mobile device.

14. A controller configured to read M-bit values ​​and D-bit values ​​from a storage cell of a non-volatile memory, wherein M is an integer greater than 0 and D is an integer greater than 0; in, The controller includes a processor configured to determine the value of the M bit based on the value of the D bit; the controller is also configured to program a first portion of the block using a state compression scheme to store attribute data, and to program a second portion of the block in normal mode to store uncompressed master data; The attribute data is used to select a read reference voltage for read retry when the master data decoding fails.

15. The controller according to claim 14, characterized in that, D=1, D=2, or D=3.

16. The controller according to claim 14, characterized in that, M=1, M=2, M=3 or M=4.

17. The controller according to claim 14, characterized in that, The processor is configured to determine the value of at least one of the M bits as the value of one of the D bits.

18. The controller according to claim 14, characterized in that, The processor is configured to determine the value of at least one of the M bits as the inverse of the value of one of the D bits and the XOR of the value of the other of the M bits, or is configured to determine the value of at least one of the M bits as the inverse of the value of the other of the M bits and the XOR of the value of one of the D bits.

19. The controller according to claim 14, characterized in that, The processor is configured to determine the value of at least one bit in the M bits based on the value of only one bit in the D bits.

20. The controller according to claim 14, characterized in that, The processor is configured to determine the value of at least one bit in the M bits based on the value of only two bits in the D bits.

21. A system comprising the controller of claim 14, wherein the system is a solid-state drive, a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

Images