Fixed floating point hybrid processing circuit

Abstract

The application provides a fixed-point floating-point mixed processing circuit, which comprises a multiplication-addition auxiliary calculation module, a floating-point addition-subtraction shift preprocessing module, a fixed-point multiplication module, a fixed-point addition-subtraction and logical operation module, a lookup table module, an inverse interpolation module, an exponential compensation module, a fine-grained normalization module and a coarse-grained normalization module, the multiplication-addition auxiliary calculation module comprises a * / +ACU1 module for processing an exponential correlation operation and a * / +ACU2 module for processing an effective bit correlation operation of a source operand, the * / +ACU1 module is connected with the floating-point addition-subtraction shift preprocessing module, and the * / +ACU2 module is connected with the exponential compensation module; the coarse-grained normalization module shifts a mantissa of a calculation result into a redundant space according to an effective bit estimation of the exponential compensation module; and the source operand is stored in an MFP data format. The application reuses hardware resources by configuring a data flow and a module connection mode, so that the consumption of hardware resources is reduced.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design technology, and more specifically, to a fixed-point / floating-point mixed processing circuit. Background Technology

[0002] Neural network inference requires enormous computing power. Currently, when deploying neural networks on edge devices, fixed-point data is mainly used for neural network inference. However, fixed-point operations only exhibit good properties in convolution operations; the implementation of other operators still requires floating-point operations to improve precision. Therefore, how to implement a hybrid precision computing framework that combines the large dynamic range and lack of online quantization of floating-point operations with the low power consumption and high speed of fixed-point operations is a current research hotspot in the industry. Summary of the Invention

[0003] The purpose of this invention is to provide a data structure MFP that is compatible with both fixed-point and floating-point operations, simplifying common arithmetic operations through redundant carry; based on this data structure, hardware implementation methods for various corresponding operations are proposed; and a complete vector processor microarchitecture is also provided. The hardware resource overhead and computational energy consumption of the MFP-based microarchitecture proposed in this invention are superior to traditional fixed-point and floating-point separated processing architecture designs.

[0004] To achieve the above-mentioned objective, this invention discloses a fixed-point / floating-point mixed-signal processing circuit, comprising:

[0005] The system includes a multiplication and addition auxiliary calculation module, a floating-point addition and subtraction shift preprocessing module, a fixed-point multiplication module, a fixed-point addition and subtraction and logical operation module, a lookup table module, a reciprocal interpolation module, an exponent compensation module, a fine-grained normalization module, and a coarse-grained normalization module.

[0006] The multiplication and addition auxiliary calculation module includes a * / +ACU1 module for handling exponent-related operations and a * / +ACU2 module for handling valid bit-related operations of the source operands. The * / +ACU1 module is connected to the preprocessing module for floating-point addition, subtraction and shifting, and the * / +ACU2 module is connected to the exponent compensation module.

[0007] The floating-point addition and subtraction shift preprocessing module is connected to the fixed-point addition and subtraction and logic operation module and the lookup table module. It is used to shift the mantissa with the smaller exponent operand in addition and subtraction mode so that the exponents of the two source operands are the same.

[0008] The fixed-point multiplication module connects the fine-grained normalization module and the coarse-grained normalization module, and is used to perform multiplication operations on the source operands;

[0009] The fixed-point addition and subtraction method and logic operation module are connected to the fine-grained normalization module and the coarse-grained normalization module, and are used to perform logical operations and fixed-point addition and subtraction;

[0010] The lookup table module is connected to the reciprocal interpolation module and is used to realize the collaborative reuse of positive and negative numbers in the lookup table;

[0011] The reciprocal interpolation module combines the reciprocal values ​​of two adjacent points output by the lookup table and performs interpolation based on the weights of the input values ​​that are close to the two points, thereby obtaining the accurate value of the reciprocal operation.

[0012] The exponent compensation module connects the fine-grained normalization module and the coarse-grained normalization module, and is used to compensate the exponent part of the floating-point number.

[0013] The fine-grained normalization module is used to convert floating-point numbers according to a specified format;

[0014] The coarse-grained normalization module shifts the mantissa of the calculation result to the redundancy space based on the effective bit estimation of the exponential compensation module.

[0015] The source operands are stored in MFP data format.

[0016] The initial goal of this invention was to reduce hardware resource consumption and power consumption by sacrificing a small amount of computational precision. Ultimately, this invention achieves the goal of reducing hardware resource consumption by reusing hardware resources through configured data flow and module connection methods; and by using the coarse-grained normalization "cg_norm" module to reduce normalization shift operations, thereby lowering power consumption. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a fixed-point / floating-point mixed processing circuit structure provided in one embodiment of the present invention;

[0018] Figure 2 This is a periodic layout diagram of a fixed-floating-point mixed-signal processing circuit provided in one embodiment of this disclosure;

[0019] Figure 3 This is a diagram of the MFP data representation format provided in one embodiment of this disclosure;

[0020] Figure 4 This is a circuit diagram of the * / +ACU1 module provided in one embodiment of this disclosure;

[0021] Figure 5 This is a circuit diagram of the * / +ACU2 module provided in one embodiment of this disclosure;

[0022] Figure 6 This is a circuit diagram of a preprocessing module for floating-point addition, subtraction, and shifting provided in one embodiment of this disclosure;

[0023] Figure 7 This is a circuit diagram of a fixed-point multiplication module provided in one embodiment of this disclosure;

[0024] Figure 8 This is a circuit diagram of a valid bit detection module provided in one embodiment of this disclosure;

[0025] Figure 9 This is a circuit diagram of a fixed-point addition and subtraction and logic operation module provided in one embodiment of this disclosure;

[0026] Figure 10 This is a circuit diagram of a valid bit estimation module specific to addition and subtraction provided in one embodiment of this disclosure;

[0027] Figure 11 This is a circuit diagram of a valid bit estimation module for addition, subtraction, and multiplication provided in one embodiment of this disclosure;

[0028] Figure 12 This is an additional circuit diagram required for power saving provided in one embodiment of this disclosure;

[0029] Figure 13 This is a diagram showing the arrangement of the last digits of the lookup table provided in one embodiment of this disclosure;

[0030] Figure 14 This is a circuit diagram of an index compensation module for LUT mode provided in one embodiment of this disclosure;

[0031] Figure 15 This is a coarse-grained normalized through-bypass circuit diagram provided in one embodiment of this disclosure;

[0032] Figure 16 This is a circuit diagram of a coarse-grained normalization module provided in one embodiment of this disclosure;

[0033] Figure 17 This is a diagram illustrating the application of the fixed-floating-point mixed processing circuit provided in one embodiment of this disclosure in a vector processor;

[0034] Figure 18 This is a pipeline diagram of a vector processor provided in one embodiment of the present disclosure. Detailed Implementation

[0035] The following is in conjunction with the appendix Figures 1 to 18 The embodiments of the present invention will be described in detail below. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Those skilled in the art should understand that the following specific embodiments or implementation methods are a series of optimized configurations listed to further explain the specific content of the invention. These configurations can be combined or used in conjunction with each other, unless the invention explicitly states that some or a specific embodiment or implementation method cannot be associated with or used in conjunction with other embodiments or implementation methods. Furthermore, the following specific embodiments or implementation methods are merely optimized configurations and are not intended to limit the scope of protection of the invention.

[0037] See Figure 1 In one embodiment, the present invention discloses a fixed-point / floating-point mixed processing circuit, including a multiplication and addition auxiliary calculation module, a floating-point addition and subtraction shift preprocessing module, a fixed-point multiplication module, a fixed-point addition and subtraction and logical operation module, a lookup table module, a reciprocal interpolation module, an exponent compensation module, a fine-grained normalization module, and a coarse-grained normalization module, characterized in that...

[0038] The multiplication and addition auxiliary calculation module includes a * / +ACU1 module for handling exponent-related operations and a * / +ACU2 module for handling valid bit-related operations of the source operands. The * / +ACU1 module is connected to the preprocessing module for floating-point addition, subtraction and shifting, and the * / +ACU2 module is connected to the exponent compensation module.

[0039] The floating-point addition and subtraction shift preprocessing module is connected to the fixed-point addition and subtraction and logic operation module and the lookup table module. It is used to shift the mantissa with the smaller exponent operand in addition and subtraction mode so that the exponents of the two source operands are the same.

[0040] The fixed-point multiplication module connects the fine-grained normalization module and the coarse-grained normalization module, and is used to perform multiplication operations on the source operands;

[0041] The fixed-point addition and subtraction method and logic operation module are connected to the fine-grained normalization module and the coarse-grained normalization module, and are used to perform logical operations and fixed-point addition and subtraction;

[0042] The lookup table module is connected to the reciprocal interpolation module and is used to realize the collaborative reuse of positive and negative numbers in the lookup table;

[0043] The reciprocal interpolation module combines the reciprocal values ​​of two adjacent points output by the lookup table and performs interpolation based on the weights of the input values ​​that are close to the two points, thereby obtaining the accurate value of the reciprocal operation.

[0044] The exponent compensation module connects the fine-grained normalization module and the coarse-grained normalization module, and is used to compensate the exponent part of the floating-point number.

[0045] The fine-grained normalization module is used to convert floating-point numbers according to a specified format;

[0046] The coarse-grained normalization module shifts the mantissa of the calculation result to the redundancy space based on the effective bit estimation of the exponential compensation module.

[0047] The source operands are stored in MFP data format.

[0048] In this embodiment, the periodic arrangement of the fixed-point / floating-point mixed processing circuit is as follows: Figure 2 As shown, the horizontal axis to the right is the time axis T, which is divided into three clock cycles by dashed lines. The modules and operations used by this circuit are arranged on the time axis as follows: Figure 2 As shown, the horizontal length of a module represents the time required to operate that module.

[0049] To enable the aforementioned circuitry to accommodate operations of varying precision (e.g., fixed-point, floating-point) and different types (e.g., addition, subtraction, multiplication, and division), we utilize configuration parameters and control signals to manage the switching of different modules and their inter-module combinations and connections. This guides the data flow through the various modules, ensuring the successful completion of diverse computational requirements. Table 1 provides the symbol conventions for the control signals and input / output data streams involved.

[0050] symbol Number of bits Meaning and Explanation <![CDATA[X1,X2]]> 32 Mantissa of two source operands <![CDATA[E1,E2]]> 8 Exponent of two source operands <![CDATA[X o ]]> 32 The mantissa of the output result <![CDATA[E o ]]> 8 The exponential part of the output result fp_en 1 Floating-point precision enabled (0: fixed-point arithmetic; 1: floating-point arithmetic) <![CDATA[S + / * ]]> 1 Addition / multiplication control signals (0: addition / subtraction; 1: multiplication) <![CDATA[S + / - ]]> 1 Addition / subtraction control signals (0: addition; 1: subtraction) lut_sel 1 Lookup table control signals (0: other operations; 1: lookup table) lg_crtl 3 Logic selection and control signals

[0051] Table 1

[0052] The first four rows in the table represent input and output data flows, while the last five rows represent control flows. If a control flow signal appears in a submodule, its value will directly determine the module's function and role.

[0053] The fractional part of the MFP format involved in this technical solution includes an 8-bit integer and a 24-bit fractional part. The position of the decimal point can be changed to achieve better performance for specific datasets, and the length of the fractional part can be changed (e.g., 16 bits, 24 bits) to achieve a balance between computational precision and resource consumption. This technical solution is applied to the implementation of arithmetic circuits in very large-scale integrated circuits.

[0054] The fixed-point / floating-point mixed-signal processing circuit also includes a CLZ high-order bit detection module, a general-purpose module used to detect which bit is the most significant bit of the data. This module... Figure 1 The identifier "clz_src" indicates the highest bit of the source operand.

[0055] In another embodiment, the data in the MFP data format is represented as x = {S, I, D; E}, where S is the sign bit, I is the integer bit, D is the decimal bit, and E is the exponent bit.

[0056] In this embodiment, the complement operation means: if {S, X} represents a signed binary number x, where S is the sign bit and X is the remaining numerical bits. The conversion between sign-magnitude and complement representation requires the complement operation. The complement operation is represented in the following form:

[0057]

[0058] Use (X) C This represents the complement operation on X. If S = 1, the number is negative. When complementing, the numerical part X needs to be inverted bit by bit and incremented by one; ~X represents the bit-inverting operation. If S = 0, complementing X will still result in X.

[0059] Therefore, if x = {S, X} is a signed number represented in fixed-point two's complement, then its value can be written as: x = (-1) S ·(X) C .

[0060] For standard floating-point data formats like FP32, 32 bits are used to store a single data value, including a 1-bit sign bit, an 8-bit exponent, and a 23-bit mantissa. When the floating-point number is a regular number, the most significant bit of the mantissa is padded with a 1; when the floating-point number is irregular, the most significant bit of the mantissa is padded with a 0, forming the fractional part of the floating-point number. All 24 bits of the fractional part are significant bits, making full use of every bit of storage space to improve precision. However, this standard data format requires multiple rounding operations on the calculation result during computation to ensure that the result does not overflow and fully utilizes the mantissa precision, thus meeting the standard for regular numbers.

[0061] However, the normalization part of floating-point operations consumes a significant amount of energy and space, prolonging the computational pipeline. Other related standard floating-point data formats are the same as FP32, requiring multiple normalization operations to maintain the full significant bit of the mantissa during computation. Therefore, the standard floating-point data format can be considered a data format with high storage density but poor computational efficiency.

[0062] To minimize normalization operations and thus reduce power consumption and area overhead of the computing unit, this solution proposes a new data representation format called MFP format. Its definition and concept are as follows: during computation, each data point is allocated a certain number of extra redundant bits, called the data redundancy space. If the most significant bit of the data falls within the redundancy space, the data is considered computationally valid and can be stored on-chip and participate in subsequent calculations. Only when a calculation result is the final output or needs to be stored in memory is it normalized to a standard floating-point data format.

[0063] In this way, using the MFP format for computation avoids a large number of meaningless normalization operations. Furthermore, this format uses two's complement to represent the mantissa, making it compatible with fixed-point arithmetic.

[0064] MFP Format: In this solution, improvements are made to the standard FP32, and a unified data representation format is used for both fixed-point and floating-point data, such as... Figure 3 As shown. Let the mantissa portion of the data be X = {S, I, D}, and the data x can be represented as x = {S, I, D; E} or x = {X; E}. The mantissa portion X is stored uniformly, occupying 32 bits. In the mantissa portion X, S (sign) is the sign bit, 1 bit occupying the 31st position; I (integer) is the integer part, 7 bits occupying [30:24]; D (decimal) is the decimal part, 24 bits occupying [23:0]. The exponent E (expoent) is 8 bits and stored separately.

[0065] The mantissa X = {S, I, D} is represented in two's complement form, with the decimal point fixed between 23 and 24 bits. The range is from -2... 31-24 to (2) 31 -1)·2 -24 With a precision of 2 -24 The independently stored E is an 8-bit shift code. When using it, it needs to be shifted down by 127 numbers, that is, [0, 255] is used to represent [-127, 128], and 127 represents the exponent 0.

[0066] Therefore, the value of data x can be denoted as:

[0067] x = (-1) S ·(I, D) C ·2 E-127-24

[0068] If x is specified as floating-point data, then the numerical representation of x is as shown in the above formula. If x is specified as fixed-point signed data, then the exponent is fixed at E = 151. Therefore, the representation of a signed integer can be expressed as follows:

[0069] x = (-1) s ·(I, D) C

[0070] Its range is: [-2 31 ,2 31 -1].

[0071] If x is specified as an unsigned integer, the sign bit participates in the counting, and the value of x can be represented as:

[0072] x = (S, I, D)

[0073] Its range is: [0, 2] 32 -1].

[0074] In another embodiment, the integer bit I is a redundant carry space. As long as the most significant bit of the data falls within the range of the redundant carry space, the data is stored on-chip and participates in subsequent calculations. Only when a calculation result is the final output or needs to be stored in memory is the data normalized.

[0075] In this embodiment, the integer part I is the number of redundant bits compared to the FP32 format. I or X [30:24] is called the redundant carry space. Data is valid as long as its most significant bit falls within the redundant carry space. If the estimated most significant bit of the result still falls within this range, the regularization operation can be omitted. When I equals 1 or -1, the data is called a fully normalized number.

[0076] In another embodiment, the * / +ACU1 module includes a Max module, a + / - module, and a multiplexer mux. The Max module compares the magnitudes of two inputs and outputs the larger term number, the larger exponent term, and the smaller exponent term. The + / - module is an 8-bit adder used to add or subtract the two inputs and output the result. The multiplexer mux selects the base exponent E. b And output it.

[0077] In this embodiment, the * / +ACU has a special structure; it performs different calculations and undertakes different functions when the processor executes multiplication, addition, and lookup table operations. For example... Figure 1 As shown, * / +ACU will be instantiated into two modules, * / +ACU1 and * / +ACU2, which will have slight differences.

[0078] The ACU module primarily handles exponent-related operations. According to the design principles of this device, when calculating multiplication, subsequent modules will use the multiplication base exponent E. b = The value of E1 + E2. However, when calculating addition and subtraction, the base exponent E is... b =E max =max{E1, E2}, no exponent addition is needed. However, compared to multiplication, the subsequent modules of addition and subtraction use the absolute value of the exponent difference |E1-E2| for mantissa shifting. To address these requirements, a collaborative reuse design for the multiplication and addition auxiliary calculation modules is proposed. Its circuit implementation is as follows... Figure 4 As shown. The inputs include: the exponent bits E1 and E2 of two 8-bit source operands; and the multiplication / addition control signal S. + / * The output includes: the index of the larger exponent, max_index; the ACU calculation term, ACU_out1; and the benchmark exponent, E.b .

[0079] Figure 4 In the code, the "max" module can compare the size of two inputs and output the index of the larger term (max_index) and the index of the larger term (E). max ), the smaller term of the exponent (E) min The "+ / -" module is an 8-bit adder that adds or subtracts two inputs and outputs the result. The multiplication / addition control signal S... + / * This is used to indicate whether the arithmetic unit is performing addition, subtraction, or multiplication. In addition / subtraction mode, S... + / * =0, controls "+ / -" for subtraction, the output is: ACU_out1 = |E1-E2|; in multiplication mode, S + / * =1, controlling "+ / -" to perform addition, the output is: ACU_out1 = E1 + E2. Note that since the exponent is calculated using shift code, the addition here must satisfy the shift code arithmetic rules. At the end of the circuit, a multiplexer (mux) is used to select the reference exponent E. b And output it.

[0080] In another embodiment, the * / +ACU2 module includes a Max module, a + / - module, and a multiplexer mux. The inputs of the * / +ACU2 module are the significant bit values ​​C1 and C2 of two 5-bit source operands, and the multiplication / addition control signal S. + / * The output of the * / +ACU2 module is the base valid bit C and the ACU calculation item ACU_out2.

[0081] In this embodiment, the * / +ACU2 module primarily handles operations related to the significant bits of the source operands. The computational unit design of this device employs a result significant bit estimation technique, requiring auxiliary calculations of the significant bits C1 and C2 of the two source operands. This significant bit estimation technique will be detailed in the exponent compensation module (compensation_E). According to the design principles of this device, when calculating multiplication, subsequent modules will use the value of the multiplication reference significant bit C = C1 + C2. When calculating addition and subtraction, the addition / subtraction reference significant bit C = C... max =max{C1, C2}, no significant bits need to be added. However, compared to multiplication, subsequent modules for addition and subtraction will use the absolute value of the significant bits |C1-C2| for coarse-grained regularization. To address these requirements, a collaborative reuse design for the multiplication and addition auxiliary calculation modules is presented. Its circuit implementation is as follows... Figure 5 As shown. The inputs include: the significant bit values ​​C1 and C2 of two 5-bit source operands, generated by the pre-amplifier module; and the multiplication / addition control signal S. + / * The output is: reference valid bit C; ACU calculation item ACU_out2.

[0082] and Figure 4 resemblance, Figure 5 In the code, the "max" module can compare the size of two inputs and output the term with the larger significant digit (C). max ), the smaller of the significant digits (C) min The "+ / -" module here is a 5-bit adder that adds or subtracts two inputs before outputting the result. The multiplication / addition control signal S... + / * This is used to indicate whether the arithmetic unit is performing addition, subtraction, or multiplication. In addition / subtraction mode, S... + / * =0, controls "+ / -" for subtraction, the output is: ACU_out2 = |C1-C2|; in multiplication mode, S + / * =1, controlling "+ / -" to perform addition, calculating the output: ACU_out2 = C1 + C2. At the end of the circuit, a multiplexer (mux) is used to select the reference exponent C and output it.

[0083] In another embodiment, the floating-point addition / subtraction shift preprocessing module includes a Shift_r module and a multiplexer mux. The Shift_r module right-shifts the input by a specified number of bits, and the multiplexer mux selects an input signal as the output based on the sel selection signal 0 / 1. The inputs of the floating-point addition / subtraction shift preprocessing module are the mantissa portions X1 and X2 of the source operands, the output ACU_out1 of the * / +ACU1 module, the source operand number max_index with the larger exponent, the selection signal lut_sel of the lookup table module, and the valid bit C1 of the source operand 1. The output of the floating-point addition / subtraction shift preprocessing module is the preprocessed mantissa X1 of the two source operands. 1_s and X 2_s .

[0084] In this embodiment, this module is only used in S + / * Enabled when `lut_sel = 0`. Primarily used in addition and subtraction modes to shift the mantissa of operands with smaller exponents, ensuring both source operands have the same exponent. Additionally, in LUT mode (`lut_sel = 1`), the lookup table number needs to be shifted and normalized before the lookup. Therefore, in LUT mode, with slight configuration, module reuse can be achieved to preprocess the lookup table number. Note that in the control logic of the arithmetic unit, when `lut_sel = 1`, `S` must be configured. + / * =0.

[0085] The specific circuit implementation of this module Figure 6As shown. The inputs are: the mantissas X1 and X2 of the source operands; the ACU1 calculation term ACU_out1, which is always |E1-E2|; the source operand number max_index with the larger exponent; the lookup table module selection signal lut_sel; and the valid bit C1 of the source operand 1. The output is: the preprocessed mantissas X1 and X2 of the two source operands. 1_s and X 2_s .

[0086] Additionally, the "shift_r" module shifts the input to the right by a specified number of bits. In non-LUT mode, when lut_sel = 0, the shift number is |E1-E2|; in LUT mode, when lut_sel = 1, the shift number is C1[2:0], which will shift the most significant bit of X1 to the 23rd bit.

[0087] Figure 6 The upper and middle sections, with their three "mux" and "shift_r" combinations, perform the following function: Select the source operand with the smaller exponent from X1 and X2, and shift it into shift_r. For output, X... 1_s X 2_s These correspond to the processing outputs of X1 and X2, respectively. The output mux logic is as follows: if the exponent of the source operand is smaller, the shifted data is selected for output. If the exponent of the source operand is larger, the source operand is directly selected for output.

[0088] In LUT mode, this module preprocesses the lookup table data. The lookup table number is used as the first source operand, with its mantissa and exponent as inputs X1 and E1, respectively. E2 is configured to its maximum value, and lut_sel = 1. This module then selects the smaller exponent's mantissa X1 and right-shifts it by C1[2:0] bits, with lut_sel selecting this as the shift position. The most significant bit of X1 is shifted to the 23rd bit. Thus, the lookup table module can reuse this module to normalize the lookup number. Figure 6 In this diagram, "mux" stands for multiplexer, which selects an input signal as its output based on the sel selection signal (0 / 1). Some mux modules in the diagram have input 0 / 1 markings. In this article, unmarked mux modules default to having the upper input signal marked as 0 and the lower input signal marked as 1.

[0089] In another embodiment, the fixed-point multiplication module is as follows: Figure 7 As shown, the high 16 bits of X1 and X2 are multiplied respectively. This is a standard 16-bit fixed-point multiplier that supports both signed and unsigned multiplication, outputting a 32-bit result. Finally, the multiplication / addition selection signal S is used. + / - To select the base mantissa X of the result bFinally, this mux is the same mux as the last mux in the "+logic" module; here, it's assumed that the base mantissa X is obtained directly. b Clz_src is the high-order detection module, such as... Figure 8 As shown, this is used to detect the significant number of bits in two source operands. When the measured number is positive, it counts the number of 0s from the highest bit; when the measured number is negative, it counts the number of 1s from the highest bit. `Sat` is for data saturation detection; when the calculated result exceeds the maximum value, it assigns the maximum value; when the data result is less than the minimum value, it assigns the minimum value. `fg_norm` is the fine-grained normalization module, which is the same as the normalization module for standard floating-point operations.

[0090] In another embodiment, the fixed-point addition, subtraction, and logic operation module includes an integrated logic operation module (logic), a fixed-point adder, and a multiplexer (mux). The input of the fixed-point addition, subtraction, and logic operation module is the preprocessed mantissa X of the two source operands. 1_s and X 2_s and the addition / subtraction control signal S + / - Addition control signal S + / * The output of the fixed-point addition / subtraction and logic operation module is the reference mantissa X, and the logic control signal lg_crtl. b .

[0091] In this embodiment, the input to the fixed-point addition / subtraction and logic operation module is: the mantissa X of the two processed 32-bit source operands. 1_s and X 2_s Add / subtract control signal S + / - ; Multiplication control signal S + / * The logic control signal is lg_crtl. The output is: a 32-bit mantissa processing result X. b The specific circuit implementation of this module. Figure 9 As shown. "logic" is an integrated logic unit capable of performing logical operations such as AND, OR, XOR, and shift. "+ / -" is a 32-bit fixed-point adder, outputting a 32-bit result. The lg_ctrl option selects whether the logical operation or addition / subtraction is performed. Finally, the multiplication / addition selection signal S is used. + / * To select the base mantissa X of the result b Finally, this mux is the same mux as the last mux in the "*" module; here, it's assumed that the base mantissa X is obtained directly. b .

[0092] In another embodiment, the LUT lookup module and INPLT interpolation module are tightly coupled in this design. The lookup function is specifically designed for even or odd functions, significantly reducing the number of items in the lookup table. In this example, it can be used to perform reciprocal operations on inverse proportional functions, assisting in division operations.

[0093] In another embodiment, the reciprocal interpolation module (Intplt) combines the reciprocal values ​​of two adjacent points output by the lookup table and interpolates according to the weights of the input values ​​that are close to the two points, thereby obtaining the accurate value of the reciprocal operation.

[0094] In another embodiment, the exponent compensation module includes a valid digit estimation module SBE shared by addition, subtraction and multiplication, a valid digit estimation module +SBE specific to addition and subtraction, and an exponent compensation module lut_E dedicated to LUT mode.

[0095] In this embodiment, the exponent compensation module is divided into three parts: a significant bit estimation module "SBE" shared by addition, subtraction, and multiplication; a significant bit estimation module "+SBE" specific to addition and subtraction; and an exponent compensation module "lut_E" dedicated to LUT mode. Before floating-point operations, significant bit estimation technology can be used to coarsely estimate the number of significant bits in the result. In this way, based on the estimated significant bits of the result, the arithmetic unit can compensate for the exponent portion of the floating-point operation even before the decimal operations are completed.

[0096] In this way, the calculation of the decimal part of the data and the exponent compensation can be performed simultaneously. Furthermore, based on the exponent compensation, we can choose whether to further normalize the calculation results with precise normalization, coarse-grained normalization, or skip the normalization step altogether. This not only reduces the pipeline cycle count of the computing unit but also reduces power consumption by conditionally shutting down the normalization module. Figure 10 This generates the control flow required to refine the coarse-grained classification table. The symbols "==1?" and "==0?" indicate whether the input is equal to 1 or 0.

[0097] In coarse-grained normalization, there are many cases where multiple coarse-grained normalization options can be satisfied. For example, if the estimated result has 25 significant bits, regardless of whether the mantissa is passed through or shifted left by 4 bits, the result will fall within the redundancy range and will not result in an error. The detailed table above is designed to maximize the number of pass-through options. Adding a pass-through option can directly disable the subsequent cg_norm module to reduce power consumption. If power consumption is not considered, to achieve the simplest circuit, it can be simplified to the following coarse classification table 2.

[0098] C Straight Left 4 Left 8 Right 4 [18：21] 0 0 1 0 [22：25] 0 1 0 0 [26：30] 1 0 0 0 31 0 0 0 1

[0099] Table 2

[0100] Table 2 is used under the premise that fg_sel = 0. The effective bit estimation circuit designed according to Table 2 is implemented as follows: Figure 11 As shown.

[0101] If power saving is required, it needs to be used. Figure 10 The output results are then combined with additional circuitry. Compared to Figure 11 Additional circuit design such as Figure 12 As shown. This additional power-saving design will normalize the original enablers c1, c2, c3, and C. 25 Update c1′, c2′, c3′, and c4′. This enables more direct routes to be selected after the update and normalization.

[0102] LUT_E Principle Derivation and Implementation: The exponent in LUT mode also needs compensation. The output of the LUT module is LUT_out, which has 10 bits, with the highest bit being the sign bit and 9 bits being the significant bits. From LUT_out to output X o The settings are as follows:

[0103] X o ={(7){S}, lut_out[8:0], (16){0}}

[0104] Arrange the most significant bit of the LUT output in the 24th bit, such as... Figure 13 As shown. The resulting exponent shift change is as follows: pre-normalization right shift by C1[2:0] bits, and the most significant bit of the mantissa moves to the 23rd bit. After looking up the table, the most significant bit of the mantissa is reduced by 1 bit, and the most significant bit is the 22nd bit. Now, the most significant bit of the result needs to be set to the 24th bit, and the mantissa needs to be shifted left by 2 bits, so the exponent needs to be reduced by 2 bits.

[0105] Accordingly, the formula for calculating the exponential output in LUT mode is:

[0106] E o =- s (E min +C1[2:0])-2

[0107] =127-(E min +C1[2:0]-127)-2

[0108] =252-E min -C1[2:0]

[0109] In the formula, - s This represents the negation rule for shift code operations. The Lut_E module consistently executes the result of the above expression, which can be implemented using an adder with a fixed offset. The specific circuit implementation of this module... Figure 14As shown.

[0110] In another embodiment, the inputs to the coarse-grained normalization module are coarse-grained selection signals c1, c2, c3, c4, and the reference exponent E. b and the base number X b The output of the coarse-grained normalization module is the exponent E of the final calculation result. o Sum of last digits X o .

[0111] In this embodiment, based on the effective bit estimation of the preceding module compensation_E, the mantissa of the calculation result is shifted to the redundancy space. The inputs to the coarse-grained normalization module are: coarse-grained selection signals c1, c2, c3, c4, and the reference exponent E. b Benchmark Index X b The output includes: the exponent and mantissa E of the final calculation result. o and X o .

[0112] like Figure 15 As shown, when the coarse-grained pass-through selection signal c3 is high, this module is turned off, and the reference tail number X... b and benchmark index E b It is used directly as the final output.

[0113] Internally, `cg_norm` performs a three-choice execution expression, with each execution unit performing a fixed shift of the mantissa and a fixed addition of the exponent. The specific circuit implementation of the coarse-grained normalization module is as follows. Figure 16 As shown.

[0114] In another embodiment, the circuit switches between different operating modes by configuring different control signals.

[0115] In this embodiment, as Figure 2 The illustrated mixed-signal processing circuit can perform fixed-point and floating-point addition and subtraction, fixed-point and floating-point multiplication, division, reciprocal calculation, and logical operations. This embodiment describes the collaborative usage method between modules that can perform these operations.

[0116] This fixed-point / floating-point mixed-signal processing circuit switches between different operation modes by configuring different control signals. There are five control signals in total, and their names and explanations are detailed in Table 1. The values ​​of these signals that need to be configured in different operation modes are shown in Table 3 below.

[0117] Operation type fp_en <![CDATA[S + / * ]]> <![CDATA[S + / - ]]> lut_sel lg_ctrl Floating-point addition 1 0 0 0 000 Floating-point subtraction 1 0 1 0 000 Floating-point multiplication 1 1 d 0 d Reverse lookup table 1 0 d 1 000 fixed point addition 0 0 0 0 000 Fixed-point subtraction 0 0 1 0 000 Fixed-point multiplication 0 1 d 0 d Logical operations 0 0 d 0 001～111

[0118] Table 3

[0119] In Table 3, a signal value of 'd' indicates that the enable of the module controlled by this signal is disabled in this mode. At this time, the control signal has no control function, and the signal value can be any value. In logic operation mode, S... + / * =0 and lg_ctrl≠0, lg_ctrl can be configured to implement 7 logical operations.

[0120] Under different operating modes, the modules inside the fixed-float mixed-signal processing circuit also have different states. Table 4 lists all the sub-modules contained in the fixed-float mixed-signal processing circuit, and the enable configuration of each sub-module and their on state in different operating modes.

[0121] Module Name Enable each module Fixed point + / - Fixed-point multiplication logic floating point + / - Floating-point multiplication Lookup table + / *ACU1 fp_en √ √ √ +pre_shift <![CDATA[fp_en&(~S + / * )]]> √ √ +logic <![CDATA[~(S + / * ||lut_sel)]]> √ √ √ clz_src fp_en √ √ √ * <![CDATA[S + / * ]]> √ √ + / *ACU2 fp_en&(~lut_sel) √ √ SEB fp_en&(~lut_sel) √ √ +SEB <![CDATA[fp en &~(s + / * ||lut sel )]]> √ lut_E lut_sel √ lut lutsel √ intplt lutsel √ cg_norm <![CDATA[~(fg_sel||c3)]]> √(？) √(？) fg_norm fg_sel √(？) sat ~(lut_sel||(|lg_ctrl)) √ √ √ √

[0122] Table 4

[0123] The first column in Table 4 lists all the sub-modules involved in the fixed-to-floating-point mixed-signal processing circuit. The SAT (Simplified Data Set) module is typically configured during the processor's write-back phase. Figure 2 The schematic diagram for the computation phase is not shown. The second column of the table shows the enable configurations for the sub-modules. Except for the two normalization modules fg_norm and cg_norm, all enable functions are only related to control signals. The remaining columns in the table show the computation modes that the device can execute. In Table 4, those marked with a "√" indicate that the module will be used in that mode. The two normalization modules marked with "√(?)" are both placed in the third cycle of the computation. Their enable signals are only generated when the computation reaches the second cycle, at which point it can be determined whether they are enabled, so it indicates that their enabled state is marked with (?).

[0124] In another embodiment, a fixed-floating-point mixed processing circuit is used in a vector processor.

[0125] Vector coprocessors have the following characteristics: 1. Control flow is implemented in a scalar processor, therefore vector processors do not perform jump checks, and all instructions are executed sequentially. 2. The data processing bit width is 16 elements, and the data bit width represented by the instruction is 64 elements. Therefore, each instruction requires 4 cycles to complete the calculation, and there is a 4-clock-cycle interval between every two instructions, which can achieve step-by-step pipelined processing.

[0126] Based on the characteristics of vector processors described above, the application of fixed-point / floating-point mixed-signal processing circuits in vector processors is as follows: Figure 17As shown. In a vector processor, the fixed-point / floating-point mixed-signal processing circuit serves as the computational unit of the entire processor, capable of performing fixed-point / floating-point addition, subtraction, multiplication, division, logical operations, and backward lookup table operations. Vector instructions, after entering the vector processor's "instruction queue," await activation. The "scoreboard" controls the activation of vector instructions in the vector queue. If the activated instruction is a load or store instruction, the "Read / Store Vector Instruction" module below will configure the corresponding control flow to complete the read or store operation. Specifically, when a load instruction is received, the "on-chip memory" will transfer the specified data to the "Vector Register File (VRF)" through the "Data Format Conversion" module. When a store instruction is received, the "Vector Register File (VRF)" will transfer the specified data to the "on-chip memory" through the "Data Format Conversion" module.

[0127] We use such as Figure 3 The data is in a proprietary data format, therefore the data in the vector "register file" is all generated by... Figure 3 The data is stored in the format shown. The "on-chip memory" stores data in a universal standard format that can interact with external systems. Therefore, a "data format conversion" module is needed when transferring data between the on-chip memory and the vector register file. If the wake-up command is a register read command, it will directly control the "vector register file" to send data to the "fixed-floating-point mixed processing circuit." This part of the instruction relates to the application of this fixed-floating-point mixed processing circuit. The data sent is a pair of source operands, including the mantissas X1 and X2 of the two source operands; and the exponents E1 and E2 of the two source operands. The calculation result is returned as the exponent and mantissa E of the calculated result. o and X o Meanwhile, the "Instruction Parsing and Parameter Configuration" module configures the parameters required by the "Fixed-to-Floating Point Mixed Processing Circuit". The parameters to be configured follow the pipeline flow, and include: the multiplication / addition control signal S. + / * Add / subtract control signal S + / - The lookup table control signal is lut_sel; the logic operation control signal is lg_ctrl. See Table 1 for a detailed explanation of the data and control signals for the fixed-point and floating-point processing unit.

[0128] Vector Processor Pipeline Description: The vector processor contains 16 parallel fixed-point / floating-point mixed-signal processing circuits. The usage of each fixed-point / floating-point mixed-signal processing circuit in the vector processor is as follows... Figure 17 As shown, it can only process one pair of data. A vector instruction contains 64 data items to be processed, represented by Item[63:0]. Therefore, four inputs are required to complete the calculation of one vector instruction. The pipeline design of the vector processor is as follows: Figure 18As shown. The vertical axis points downwards, representing the time direction. The length of each small square in the vertical axis represents one cycle, and the same color represents the same instruction. As shown, in cycle 1, input Item[15:0]. In cycle 2, input Item[31:16]. At this point, inputting Item[15:0] in cycle 1 enters the second cycle of the calculation. In the description of fixed-point floating-point computing devices, all types of calculations are arranged to be completed within 3 cycles, such as... Figure 2 In vector processors, a fourth cycle is added as a write-back cycle, resulting in a pipeline of depth 4 cycles for each computation. In cycle 4, the last element of the first instruction, Item[63:48], is input, while in cycle 1, Item[15:0] has already been computed and entered the write-back phase. The advantage of this pipeline design is that if there are dependencies between instructions, such as between Item0[15:0] and Item1[15:0], when Item1[15:0] is input, Item0[15:0] has already been computed, resolving the dependency issue. In other words, even if there are dependencies between corresponding elements of instructions, computation can still be performed back-to-back, reducing runtime instruction bubbles and improving computational efficiency.

[0129] In another embodiment, a specific implementation of various operations is carried out using a fixed-to-floating-point mixed-signal processing circuit. The following calculation steps are all based on... Figure 17 For reference, the step definition rules are as follows: the first two bits in S100 indicate that Step1 is the first step; the last two bits (00) indicate the specific operations within the current step. These operations can be executed in parallel if they have no dependencies.

[0130] First, implement floating-point addition and subtraction operations using a fixed-point / floating-point mixed-signal processing circuit. The steps are as follows:

[0131] S100: Instruction parsing and preparation phase. This phase reads the source operands and configures the control signals. The configuration method for the control signals is shown in Table 3. The input of the control signals will not be repeated in later steps.

[0132] S200: Cycle 1 phase. At the start of cycle 1, modules "+ / *ACU1" and "clz_src" begin working. In the middle of cycle 1, modules "+ / *ACU1" and "clz_src" complete their calculations. Modules "+pre_shift" and "+ / *ACU2" begin working. At the end of cycle 1, modules "+pre_shift" and "+ / *ACU2" complete their calculations.

[0133] S201: At the start of cycle 1, the exponents E1 and E2 are input to the "+ / *ACU1" module. Half a cycle later, at the midpoint of cycle 1, the output max_index is obtained. b ,ACU_out1.

[0134] S202: At the beginning of cycle 1, the last two digits X1 and X2 are input into the "clz_src" module. Half a cycle later, at the middle of cycle 1, the outputs C1 and C2 are obtained.

[0135] S203: During the middle of cycle 1, the last two digits X1 and X2, the result of S201 (max_index), ACU_out1, and the result of S202 (C1) are input into the "+pre_shift" module. Half a cycle later, at the end of cycle 1, the output X is obtained. 1_s X 2_s .

[0136] S204: Midway through cycle 1, the results of S202, C1 and C2, are input to the "+ / *ACU2" module. After half a cycle, when cycle 1 ends, the outputs C and ACU_out2 are obtained.

[0137] S300: Cycle 2 phase. At the start of cycle 2, modules "+logic", "SEB", and "+SEB" begin operation. In the middle of cycle 2, module "SEB" completes its calculations. At the end of cycle 2, modules "+logic" and "+SEB" complete their calculations.

[0138] S301: At the start of cycle 2, the result C from S204 is input into module "SEB". During the middle of cycle 2, outputs c1, c2, c3, and c4 are obtained.

[0139] S302: At the start of cycle 2, the result X of S203... 1_s X 2_s Input module "+logic". At the end of cycle 2, output X is obtained. b .

[0140] S303: At the beginning of cycle 2, the sign bits S1, S2, and S204 result ACU_out2 input module "+SEB". In the middle of cycle 2, the outputs fg_sel, c, and a are obtained. To implement a power-saving circuit design, in the middle of cycle 2, the results c1, c2, c3, and c4 of S301 are input to the "+SEB" module in an additional circuit (…). Figure 12 (Circuit), at the end of cycle 2, the corrected coarse-grained selection outputs c1′, c2′, c3′, and c4′ are obtained.

[0141] S400: Cycle 3 stage. Using the results fg_sel and c3(c3′) from S303, calculate the enable signals for modules "fg_norm" and "cg_norm" in Table 4. If fg_en = 1, execute S401; if cg_en = 1, execute S402; otherwise, skip the cycle 3 stage and directly output the result X from S302. b And S201 result E b For the final result X o E o .

[0142] S401: Perform standard fine-grained normalization operation. At the start of cycle 3, the result X of S401 is... b And S201 result E b Input the "fg_norm" module. At the end of cycle 3, the final result X is obtained. o E o .

[0143] S402: Perform coarse-grained normalization. At the start of cycle 3, the results of S303 (c1, c2, c3, c4) or their corrections (c1′, c2′, c3′, c4′) and the result of S301 (X) are... b S201 Result E b Input the "cg_norm" module. At the end of cycle 3, the final result X is obtained. o E o .

[0144] S500: Final Result X o E o Perform SAT saturation detection and write back.

[0145] Second, use a mixed-signal and floating-point processing circuit to implement floating-point multiplication operations. The steps are as follows:

[0146] S100: Instruction parsing and preparation phase. This phase reads the source operands and configures the control signals. The configuration method for the control signals is shown in Table 3. The input of the control signals will not be repeated in later steps.

[0147] S200: Cycle 1 phase. At the start of cycle 1, modules "+ / *ACU1", "*", and "clz_src" begin working. In the middle of cycle 1, modules "+ / *ACU1" and "clz_src" complete their calculations. Module "+ / *ACU2" begins working. At the end of cycle 1, module "+ / *ACU2" completes its calculations. At the end of cycle 2, module "*" completes its calculations.

[0148] S201: At the start of cycle 1, the exponents E1 and E2 are input to the "+ / *ACU1" module. Half a cycle later, at the midpoint of cycle 1, the output E is obtained. b .

[0149] S202: At the beginning of cycle1, the last two digits X1 and X2 are input to the "clz_src" module. Half a cycle later, at the middle of cycle1, the outputs C1 and C2 are obtained.

[0150] S203: At the start of cycle 1, the last two digits X1 and X2 are input into the "*" module. After two cycles, at the end of cycle 2, the output X is obtained. b .

[0151] S204: Mid-cycle of cycle 1. The result of S202, C1 and C2, is input to the "+ / *ACU2" module. After half a cycle, when cycle 1 ends, the output C is obtained.

[0152] S300: Cycle 2 phase. At the start of cycle 2, the result C from S204 is input into module "SEB". In the middle of cycle 2, "SEB" completes the calculation and outputs c1, c2, c3, and c4.

[0153] S400: Cycle 3 stage. Based on the result c3 from S300 and Table 4, determine the enable signal of module "cg_norm". If cg_en = 1, execute S401; otherwise, skip the cycle 3 stage and directly output the result X from S203. b And S201 result E b For the final result X o E o .

[0154] S401: Perform coarse-grained normalization operation. At the start of cycle 3, the results of S301 are c1, c2, c3, c4, and the result of S203 is X. b S201 Result E b Input the "cg_norm" module. At the end of cycle 3, the final result X is obtained. o E o .

[0155] S500: Final Result X o E o Perform SAT saturation detection and write back.

[0156] Third, implement the reciprocal lookup table using a mixed-signal and floating-point processing circuit, as follows:

[0157] S100: Instruction parsing and preparation stage. Configure the lookup table number as operand 1, and configure the exponent of operand 2 as the maximum value of E2 = {(8){1′b1}}. The configuration method of the control signals is shown in Table 3. The input of the control signals will not be mentioned again in the following steps.

[0158] S200: Cycle 1 phase. At the start of cycle 1, modules "+ / *ACU1" and "clz_src" begin working. In the middle of cycle 1, modules "+ / *ACU1" and "clz_src" complete their calculations. Module "+pre_shift" begins working. At the end of cycle 1, module "+pre_shift" completes its calculations.

[0159] S201: At the beginning of cycle 1, the exponents E1 and E2 are input into the "+ / *ACU1" module. Half a cycle later, at the middle of cycle 1, the outputs max_index and ACU_out1 are obtained.

[0160] S202: At the beginning of cycle 1, the last digit X1 is input into the "clz_src" module. Half a cycle later, at the middle of cycle 1, the output C1 is obtained.

[0161] S203: In the middle of cycle 1, the last digit X1, the result max_index of S201, ACU_out1, and the result C1 of S202 are input into the "+pre_shift" module. Half a cycle later, at the end of cycle 1, the output X is obtained. 1_s .

[0162] S300: Cycle 2 phase. At the start of cycle 2, modules "LUT" and "lut_E" begin working. At the end of cycle 2, modules "LUT" and "lut_E" complete their calculations.

[0163] S301: At the start of cycle 2, the exponent E1 is input into module "lut_E". At the end of cycle 2, the final exponent result E is obtained. o .

[0164] S302: At the start of cycle 2, sign bit S1, result X of S203. 1_s [23:16] Input module "LUT". At the end of cycle 2, outputs A and B are obtained.

[0165] S400: Cycle 3 phase. At the start of cycle 3, the sign bits S1 and S203 result X. 1_s[15:14], S303 results A and B are input to module "intplt". At the end of cycle 3, the output LUT_out is obtained.

[0166] S500: Write-back phase, the result of S400, LUT_out, is processed according to... Figure 13 The final digit X is obtained by rearranging the last digits. o , and S301 result E o Both are output as the final result.

[0167] Fourth, use a mixed-signal (fixed-point and floating-point) processing circuit to implement division and other operations. Division needs to be broken down into two instructions: first, calculate the reciprocal of the divisor, and then perform a floating-point multiplication of the reciprocal and the dividend. The steps are as follows:

[0168] S100: Use a fixed-point / floating-point mixed-signal processing circuit to find the reciprocal of the divisor. The reciprocal is found using the steps and methods described in section three.

[0169] S200: Use a fixed-to-floating-point mixed processing circuit to calculate the floating-point multiplication of the reciprocal of the divisor and the dividend. The floating-point multiplication is performed using the steps and methods described in section two.

[0170] Other operations, such as fixed-point + / - and logical operations, only require enabling the corresponding arithmetic module, and will not be elaborated further.

[0171] Although embodiments of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, and not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of the present invention, and all of these are within the scope of protection of the present invention.

Claims

1. A fixed-point / floating-point mixed-signal processing circuit, comprising: The system includes a multiplication and addition auxiliary calculation module, a floating-point addition and subtraction shift preprocessing module, a fixed-point multiplication module, a fixed-point addition and subtraction and logical operation module, a lookup table module, a reciprocal interpolation module, an exponent compensation module, a fine-grained normalization module, and a coarse-grained normalization module. The multiplication and addition auxiliary calculation module includes a * / +ACU1 module for handling exponent-related operations and a * / +ACU2 module for handling valid bit-related operations of the source operands. The * / +ACU1 module is connected to the preprocessing module for floating-point addition, subtraction and shifting, and the * / +ACU2 module is connected to the exponent compensation module. The floating-point addition and subtraction shift preprocessing module is connected to the fixed-point addition and subtraction and logic operation module and the lookup table module. It is used to shift the mantissa with the smaller exponent operand in addition and subtraction mode so that the exponents of the two source operands are the same. The fixed-point multiplication module connects the fine-grained normalization module and the coarse-grained normalization module, and is used to perform multiplication operations on the source operands; The fixed-point addition and subtraction method and logic operation module are connected to the fine-grained normalization module and the coarse-grained normalization module, and are used to perform logical operations and fixed-point addition and subtraction; The lookup table module is connected to the reciprocal interpolation module and is used to realize the collaborative reuse of positive and negative numbers in the lookup table; The reciprocal interpolation module combines the reciprocal values ​​of two adjacent points output by the lookup table and performs interpolation based on the weights of the input values ​​that are close to the two points, thereby obtaining the accurate value of the reciprocal operation. The exponent compensation module connects the fine-grained normalization module and the coarse-grained normalization module, and is used to compensate the exponent part of the floating-point number. The fine-grained normalization module is used to convert floating-point numbers according to a specified format; The coarse-grained normalization module shifts the mantissa of the calculation result to the redundancy space based on the effective bit estimation of the exponential compensation module. The source operands are stored in MFP data format.

2. The circuit according to claim 1, wherein, The data in the MFP data format is represented as follows: ,in, For the sign bit, For integer digits, For decimal places, For the exponent.

3. The circuit according to claim 2, wherein, The integer part It is a redundant carry space. As long as the most significant bit of the data falls within the range of this redundant carry space, the data is stored on-chip and participates in subsequent calculations. Only when a certain calculation result is the final output result or needs to be stored in memory, it is normalized.

4. The circuit according to claim 1, wherein, The * / +ACU1 module includes a Max module, a + / - module, and a multiplexer mux. The Max module compares the magnitudes of two inputs and outputs the larger term number, the term with the larger exponent, and the term with the smaller exponent. The + / - module is an 8-bit adder used to add or subtract the two inputs and output the result. The multiplexer mux selects the base exponent. And output it.

5. The circuit according to claim 1, wherein, The * / +ACU2 module includes a Max module, a + / - module, and a multiplexer mux. The input of the * / +ACU2 module is the significant bit value of two 5-bit source operands. and and multiplication control signals The output of the * / +ACU2 module is the reference valid bit. And the ACU calculation item ACU_out2.

6. The circuit according to claim 1, wherein, The preprocessing module for floating-point addition, subtraction, and shifting includes a Shift_r module and a multiplexer mux. The Shift_r module shifts the input to the right by a specified number of bits, and the multiplexer mux... The selection signal 0 / 1 selects a specific input signal as the output; the input to the floating-point addition, subtraction, and shift preprocessing module is the mantissa of the source operand. and The output ACU_out1 of the * / +ACU1 module has a source operand number with a large exponent. The selection signal of the lookup table module ; Valid bits of source operand 1 The output of the preprocessing module for floating-point addition, subtraction, and shifting is the preprocessed mantissa of the two source operands. and .

7. The circuit according to claim 1, wherein, The fixed-point addition, subtraction, and logic operation module includes an integrated logic operation module (logic), a fixed-point adder, and a multiplexer (mux). The input to the fixed-point addition, subtraction, and logic operation module is the preprocessed mantissa of the two source operands. and and addition / subtraction control signals Addition control signal and logic control signals The output of the fixed-point addition / subtraction and logic operation module is the base mantissa. .

8. The circuit according to claim 1, wherein the exponent compensation module includes a valid digit estimation module SBE shared by addition, subtraction and multiplication, a valid digit estimation module +SBE specific to addition and subtraction, and an exponent compensation module lut_E dedicated to LUT mode.

9. The circuit according to claim 1, wherein, The input to the coarse-grained normalization module is the coarse-grained selection signal. benchmark index and base tail number The output of the coarse-grained normalization module is the exponent of the final calculation result. Sum of last digits .

10. The circuit according to claim 1, wherein, The circuit switches between different operating modes by configuring different control signals.

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