Deep sleep wake-up control method and system for multi-mode SoC master chip

Abstract

The present invention relates to the technical field of SoC main control chips, and discloses a deep sleep wake-up control method and system for a multi-mode SoC main control chip. The method includes: collecting voltage and current data and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain a chip monitoring data set; constructing a functional module topology map and mapping it as a potential feature to obtain a deep sleep state criterion for each functional module; establishing a hierarchical Bayesian model to identify the state transition probability and EOC influencing factors of each functional module to obtain a combination scheme of deep sleep functional modules; determining a collaborative sleep control sequence; inputting a hierarchical Bayesian model to generate a wake-up voltage and clock sequence, and monitoring the power consumption response of each functional module in real time through a dynamic graph neural network, and outputting a safe wake-up control result. The present invention reduces mutual interference between functional modules and improves the overall power consumption management efficiency of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of SoC master control chips, and in particular to a deep sleep wake-up control method and system for a multi-mode SoC master control chip. Background Art

[0002] With the development of integrated circuit technology, the integration of multi-mode SoC main control chips continues to increase, and the functional modules are becoming increasingly complex, resulting in severe challenges in chip power management. Traditional power management methods use fixed threshold judgment and preset voltage timing control, which cannot effectively cope with the dynamic power consumption changes of various functional modules under different environments and operating conditions, and are prone to power waste or module operation abnormalities.

[0003] Existing deep sleep wake-up control methods are mainly based on single functional modules for control, lack consideration of the relationship between modules, and are difficult to achieve coordinated control of multi-functional modules. At the same time, due to the complex data dependencies and thermal coupling relationships between functional modules, simple sequential control strategies are prone to cause working conflicts and temperature accumulation between functional modules, affecting the reliability and stability of the chip. In addition, traditional wake-up control methods lack the ability to monitor and dynamically adjust the status of functional modules in real time, and are unable to promptly detect and handle abnormal situations during the wake-up process. In a complex working environment, the wake-up characteristics of the functional modules will change with the environment and load conditions, and a fixed wake-up strategy is difficult to ensure the safe and reliable operation of the chip. Summary of the invention

[0004] The present invention provides a deep sleep wake-up control method and system for a multi-mode SoC main control chip, which reduces mutual interference between functional modules and improves the overall power consumption management efficiency of the chip.

[0005] In a first aspect, the present invention provides a deep sleep wakeup control method for a multi-mode SoC main control chip, the deep sleep wakeup control method for the multi-mode SoC main control chip comprising:

[0006] Collect voltage, current and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain the chip monitoring data set;

[0007] Inputting the chip monitoring data set into a dynamic graph neural network, constructing a dynamic adjacency matrix, and extracting the dynamic features and spatial correlation of each functional module to obtain a functional module topology map;

[0008] The functional module topology map is mapped into potential features through the encoder in the dynamic graph neural network, and the power consumption timing features and spatial distribution features are reconstructed and the error is calculated to obtain the deep sleep state criterion of each functional module;

[0009] A hierarchical Bayesian model is established according to the deep sleep state criterion to identify the state transition probability and EOC influencing factors of each functional module, and obtain a combination scheme of deep sleep functional modules;

[0010] Determine a collaborative sleep control sequence based on a combination scheme of the deep sleep function modules;

[0011] The collaborative sleep control sequence is input into the hierarchical Bayesian model to generate a wake-up voltage and clock sequence, and the power consumption response of each functional module is monitored in real time through the dynamic graph neural network to output a safe wake-up control result.

[0012] In a second aspect, the present invention provides a deep sleep wake-up control system for a multi-mode SoC main control chip, wherein the deep sleep wake-up control system for the multi-mode SoC main control chip comprises:

[0013] The acquisition module is used to collect the voltage and current data and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain a chip monitoring data set;

[0014] A construction module is used to input the chip monitoring data set into a dynamic graph neural network, construct a dynamic adjacency matrix, and extract the dynamic features and spatial correlation of each functional module to obtain a functional module topology map;

[0015] A mapping module, used to map the functional module topology map into potential features through the encoder in the dynamic graph neural network, and to reconstruct the power consumption timing features and spatial distribution features and calculate the errors, so as to obtain the deep sleep state criterion of each functional module;

[0016] An identification module is used to establish a hierarchical Bayesian model according to the deep sleep state criterion, identify the state transition probability and EOC influencing factors of each functional module, and obtain a combination scheme of the deep sleep functional modules;

[0017] A processing module, configured to determine a collaborative sleep control sequence based on a combination scheme of the deep sleep function modules;

[0018] The output module is used to input the collaborative sleep control sequence into the hierarchical Bayesian model, generate a wake-up voltage and clock sequence, and monitor the power consumption response of each functional module in real time through the dynamic graph neural network to output a safe wake-up control result.

[0019] The third aspect of the present invention provides a deep sleep wake-up control device for a multi-mode SoC main control chip, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the deep sleep wake-up control device for the multi-mode SoC main control chip executes the above-mentioned deep sleep wake-up control method for the multi-mode SoC main control chip.

[0020] A fourth aspect of the present invention provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is run on a computer, the computer executes the deep sleep wake-up control method for the multi-mode SoC master control chip.

[0021] In the technical solution provided by the present invention, by combining the dynamic graph neural network and the hierarchical Bayesian model, the accurate extraction of the state characteristics of the multifunctional module and the accurate modeling of the state transition probability are realized, and the accuracy of the deep sleep state judgment is improved. Based on the functional module topology diagram and the dynamic adjacency matrix, the spatial correlation and temporal correlation between the functional modules are established, the collaborative control of the multifunctional modules is realized, and the working conflict between the modules is avoided. The reconfigurable intelligent control strategy is adopted to optimize the control parameters on the long time scale and the short time scale respectively, so as to improve the flexibility and adaptability of the sleep-wake-up process. Through real-time power consumption monitoring and reconstruction error analysis, a complete protection mechanism is established to ensure the safety and reliability of the functional module during the wake-up process. The hierarchical Bayesian model is introduced to model the influence of the environment and operating conditions, so as to improve the adaptability of the control strategy to different working scenarios. Based on dynamic feature extraction and spatial distribution feature reconstruction, the accurate identification and prediction of the functional module state are realized, and the intelligent level of deep sleep control is improved. Through the optimization design of the collaborative sleep control sequence, the mutual interference between the functional modules is reduced, and the overall power consumption management efficiency of the chip is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 A schematic flow chart of a deep sleep wake-up control method for a multi-mode SoC master chip provided in an embodiment of the present application;

[0024] Figure 2 A schematic block diagram of the structure of a deep sleep wake-up control system of a multi-mode SoC main control chip provided in an embodiment of the present application;

[0025] Figure 3 A schematic block diagram of the structure of a deep sleep wake-up control device for a multi-mode SoC master chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change based on actual conditions.

[0028] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0029] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0030] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0031] See also Figure 1 , Figure 1 A flowchart of a deep sleep wakeup control method for a multi-mode SoC master chip provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the deep sleep wake-up control method of the multi-mode SoC master chip provided in the embodiment of the present application includes steps S100 to S600.

[0032] Step S100, collecting voltage and current data and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain a chip monitoring data set;

[0033] It is understandable that the execution subject of the present invention can be a deep sleep wake-up control system of a multi-mode SoC main control chip, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0034] Specifically, a deep sleep monitoring (DSM) system is deployed in the multi-mode SoC main control chip, and a power consumption monitor array and a temperature sensor array are set for the power supply path of each functional module inside the chip to comprehensively monitor the power consumption and temperature data. The power consumption monitor array captures the voltage and current data of each functional module in real time, while the temperature sensor array is used to collect the temperature distribution information of each area of ​​the chip. By connecting the power consumption monitor array to the SCADA monitoring system, the voltage and current data of each functional module are sampled in real time, and these sampled values ​​are recorded as the original power consumption data. At the same time, the temperature distribution data collected by the temperature sensor array is input into the SCADA monitoring system to form the original temperature data corresponding to the power consumption data. The original power consumption data and the original temperature data are digitally filtered to eliminate random noise and unstable factors in the sampling process. Through the filtering algorithm, smoother and more accurate monitoring data are obtained. The filtered data is classified according to different environments and operating conditions (EOC), where EOC includes four types: normal working state, light load state, heavy load state and standby state. The classification process can make subsequent analysis more targeted. Different environments and load conditions have significant differences in the power consumption and temperature distribution of the chip. Classification can more clearly show the characteristics under these states. After the classification is completed, the classified data set is preprocessed, including data format unification, outlier detection and correction, and missing value filling. Feature extraction is performed on the preprocessed data set to mine deep patterns and characteristics in the data. The feature extraction process comprehensively considers the timing characteristics of power consumption and the spatial distribution characteristics of temperature to generate a representative chip monitoring data set that reflects the operating status of the multi-mode SoC master chip under different environments and operating conditions.

[0035] Step S200: Input the chip monitoring data set into the dynamic graph neural network, construct a dynamic adjacency matrix, and extract the dynamic features and spatial correlation of each functional module to obtain a functional module topology map;

[0036] Specifically, the chip monitoring data set is constructed into an initial node matrix according to the physical position relationship of the functional modules, and on this basis, a unique identifier is assigned to each functional module node in the initial node matrix to form a functional module identification matrix. The identification matrix provides a unified indexing mechanism for the statistical analysis of the relationship between the subsequent functional modules, ensuring the consistency and traceability in the data processing process. The data transmission volume between adjacent functional modules in the functional module identification matrix is ​​statistically analyzed to quantify the degree of interaction between them. According to the statistical results and the size of the data transmission volume, connection weights are assigned between the functional modules to generate a weighted connection matrix. After the weighted connection matrix is ​​input into the dynamic graph neural network, the weighted connection matrix is ​​decomposed by the orthogonal decomposition processor. The dynamic features hidden in the matrix are extracted through the decomposition process to generate a dynamic adjacency matrix. The dynamic adjacency matrix is ​​a quantitative expression of the time-varying relationship between the functional modules, which can capture the characteristics of the interaction relationship between the functional modules over time during the operation of the chip. Based on the dynamic adjacency matrix, the temporal correlation of each functional module is calculated. The timing correlation reflects the synergy between functional modules in the time dimension. By setting a reasonable threshold, the functional modules with timing correlation exceeding the threshold are dynamically connected to form a timing feature matrix. Based on the timing feature matrix, the power consumption data and temperature data of the functional modules are analyzed in the time domain to extract the dynamic feature matrix. The dynamic feature matrix can describe the time-varying operation characteristics of the functional modules, and provide support for the overall power consumption analysis of the chip in combination with the changes in its internal state. At the same time, the spatial distance and thermal conductivity coefficient between the functional modules are calculated based on the dynamic feature matrix to generate a spatial correlation matrix to characterize the interaction between the functional modules in the spatial dimension, such as the heat transfer path and the impact of the physical distance on the module operation state. The dynamic feature matrix and the spatial correlation matrix are fused to form a fused feature matrix. On the basis of the fused feature matrix, the topological diagram of the functional modules is obtained by constructing the topological connection relationship between the modules.

[0037] Step S300, mapping the functional module topology map into potential features through the encoder in the dynamic graph neural network, and reconstructing the power consumption timing features and spatial distribution features and calculating the errors to obtain the deep sleep state criterion of each functional module;

[0038] Specifically, the functional module topology map is used as input, and the node features and edge features in the map are subjected to graph convolution operation through the encoder of the dynamic graph neural network. By aggregating the feature information of adjacent nodes, the structural relationship and interaction characteristics between modules are extracted, and a first-order feature mapping matrix is ​​generated to reflect the direct association between the functional modules and their neighborhood features. The first-order feature mapping matrix is ​​transformed and deep features are extracted through a multi-layer perceptron. The multi-layer perceptron can perform nonlinear mapping on the first-order feature mapping matrix, mine the complex relationship between features, and generate a potential feature vector. The potential feature vector is the representation of the functional module topology map in a high-dimensional feature space, and has concentrated time series dynamic characteristics and spatial distribution information. The potential feature vector is input into the first decoder, and the power consumption time series characteristics of the functional module are reconstructed through the deconvolution layer in the decoder. The core of the power consumption time series reconstruction process is to restore the power consumption variation law of the functional module at different time points and generate a power consumption time series reconstruction result. At the same time, the same potential feature vector is input into the second decoder, and the spatial distribution characteristics of the functional module are reconstructed using the deconvolution layer in the second decoder, and the physical layout characteristics of the functional module and its corresponding temperature distribution state are restored to generate a spatial distribution reconstruction result. The error between the power consumption timing reconstruction result and the original power consumption data is calculated. The power consumption timing reconstruction result is compared with the original power consumption data, and the power consumption reconstruction error matrix is ​​calculated to reflect the degree of fit of the reconstruction model to the actual power consumption timing characteristics. Similarly, the spatial distribution reconstruction result is compared with the original temperature distribution data, and the spatial reconstruction error matrix is ​​calculated. The spatial reconstruction error matrix describes the reconstruction accuracy of the model for the spatial distribution characteristics. The power consumption reconstruction error matrix and the spatial reconstruction error matrix are weighted and fused to generate a comprehensive error index. The comprehensive error index can uniformly evaluate the reconstruction performance of the module in both the timing and spatial dimensions. Based on the comprehensive error index, a deep sleep judgment threshold is set, which is used to distinguish whether the functional module meets the conditions for entering deep sleep. On this basis, by comparing the power consumption reconstruction error matrix and the spatial reconstruction error matrix with the threshold respectively, a clear deep sleep state judgment criterion is generated for each functional module.

[0039] Step S400, establishing a hierarchical Bayesian model according to the deep sleep state criterion, identifying the state transition probability and EOC influencing factors of each functional module, and obtaining a combination scheme of the deep sleep functional modules;

[0040] Specifically, the deep sleep state criteria are input into the hierarchical Bayesian model, which is established based on the power consumption reconstruction error matrix and the spatial reconstruction error matrix, and fully reflects the specific state characteristics of the functional modules in terms of dynamic characteristics and physical distribution. In the initial stage of the model, the state transition probability of the functional modules is calculated by analyzing these criteria, and the first-layer Bayesian parameters are generated to describe the transition trend of each module from the active state to the sleep state. Based on the first-layer Bayesian parameters, the state sequence of each functional module under different EOC (operating conditions) is analyzed to establish the correlation mapping relationship between the state transition probability and the EOC parameters. This analysis captures the impact of EOC changes (such as load type and ambient temperature) on the module state and generates the second-layer Bayesian parameters. The first-layer Bayesian parameters and the second-layer Bayesian parameters are input into the hierarchical Bayesian reasoner in the hierarchical Bayesian model, and the state transition matrix between the functional modules is calculated by the joint probability reasoning method. The state transition matrix is ​​a global description of the dynamic interaction between modules, which can reveal the steady-state behavior and transition law in the operation of the system. Based on the state transition matrix, the steady-state probability distribution of the functional modules in different states is calculated to identify the behavior patterns of the functional modules in long-term operation, providing a theoretical basis for determining the critical points of the module's state transition. Through the analysis of the steady-state probability distribution, the state transition boundaries are obtained, which define the conditions for the functional modules to enter different operating modes. Based on the state transition boundaries, the state space is refined and divided into active areas and sleep areas through threshold segmentation. In this process, a reasonable deep sleep threshold is set in combination with the state distribution characteristics of the functional modules to form a sleep condition set that describes the conditions for each module to enter the sleep state. This set clarifies the specific parameter range for each module to meet the deep sleep requirements. The functional modules are preliminarily grouped according to the sleep condition set. The grouping process fully considers the state correlation between the functional modules to ensure that the modules in the group can cooperate with each other in state transition. Based on this correlation, the modules in the initial grouping set are combined and matched to generate an initial combination set. Based on the initial combination set, the combination of each group of functional modules is scored, and the scoring criteria comprehensively consider factors such as power consumption reduction effect, module interaction characteristics, and sleep stability. After calculating the scores of all combinations, the combination with the highest score is selected as the final combination scheme for the deep sleep functional module.

[0041] Step S500, determining a collaborative sleep control sequence based on a combination scheme of deep sleep function modules;

[0042] Specifically, by analyzing the state stability of each functional module in the combination scheme of deep sleep functional modules in a long time scale, the state statistical matrix is ​​calculated. The state statistical matrix records the state characteristics of the functional modules in different time periods, including the duration distribution and frequency of the active state and the sleep state, and provides the dynamic behavior basis of each module in power consumption optimization. According to the state statistical matrix, the state correlation analysis of the functional modules is carried out to capture the interaction rules and interdependence between the functional modules. On this basis, according to the degree of synchronization of state transfer between functional modules, the module dependency matrix is ​​constructed. The module dependency matrix quantifies the collaborative relationship between modules, such as whether the state change of some modules requires the support of other modules or is affected by other modules. The module dependency matrix is ​​topologically sorted to generate a long-time scale sleep order. The sorting reflects the order in which the modules are controlled in the sleep operation, thereby ensuring the logical consistency of the state transfer between modules. In order to optimize the control process, the sleep order of the long time scale is correlated and analyzed. By evaluating the voltage demand change trend of the module, the supply voltage of each functional module is adjusted in a piecewise linear manner to generate a voltage adjustment sequence. This adjustment method minimizes power consumption while ensuring a smooth transition of the module and avoiding functional abnormalities caused by voltage fluctuations. Based on the voltage regulation sequence, the clock gating strategy of the functional module is constructed. The clock gating strategy generates a clock control sequence by performing hierarchical shutdown control on the clock tree. Hierarchical shutdown gradually turns off unnecessary clock signals according to the importance and dependency of the modules, thereby reducing power consumption. In order to ensure the coordination between the voltage regulation sequence and the clock control sequence, the two are aligned in the time domain so that the voltage adjustment and clock operation of the module can be completed synchronously to form an initial control sequence. The initial control sequence is verified for timing integrity. By checking the control signal transmission and response time of each functional module, it is ensured that all modules can complete the state transition according to the expected control logic and time sequence. The verified sequence is calibrated as a calibration control sequence, and its reliability and consistency can meet the operation requirements of complex chip systems. According to the physical connection relationship between the calibration control sequence and each functional module, the transmission path of the control signal is analyzed to optimize the efficiency and stability of signal transmission, and the final collaborative sleep control sequence is obtained. In actual operation, the collaborative sleep control sequence can perform deep sleep control of the module in an efficient and accurate manner, providing comprehensive support for the power consumption optimization of multi-mode SoC chips, while ensuring the fast response and functional integrity of the chip when waking up.

[0043] Step S600: Input the collaborative sleep control sequence into the hierarchical Bayesian model to generate a wake-up voltage and clock sequence, and monitor the power consumption response of each functional module in real time through a dynamic graph neural network to output a safe wake-up control result.

[0044] Specifically, the collaborative sleep control sequence is input into the hierarchical Bayesian model, and the state transition probability of each functional module is calculated by the first-layer Bayesian parameters. The influencing factors of the environment and operating conditions (EOC) are analyzed by combining the second-layer Bayesian parameters to generate the wake-up state probability distribution. The wake-up state probability distribution reflects the possibility of each functional module being successfully awakened in the current environment. Based on the wake-up state probability distribution, the functional modules are sorted according to priority, and the physical connection relationship and data transmission dependency between modules are considered to generate the wake-up sequence of the functional modules. Priority sorting ensures that key modules enter the active state first, avoiding state inconsistency caused by data transmission dependency, thereby improving the overall coordination of the wake-up process. After determining the wake-up sequence, a specific voltage regulation curve is designed for each functional module. The design of the voltage regulation curve includes determining the slope of the voltage ramp and the voltage holding time to ensure a smooth transition of the module when switching from the sleep state to the active state, forming a voltage wake-up sequence. A clock enable control scheme is constructed based on the voltage wake-up sequence. In the clock enable design, the clock wake-up sequence of the module is formulated through the hierarchical opening strategy. The hierarchical opening can gradually activate the clock signal according to the importance and dependency of the module, thereby avoiding the power consumption peak problem caused by the simultaneous awakening of too many modules. The voltage wake-up sequence and the clock wake-up sequence are wired and planned according to the spatial distribution of the functional modules to form a complete wake-up control network. The wake-up control network ensures the rationality and timing consistency of signal transmission. During the wake-up process, in order to monitor the power consumption changes and state stability in real time, the power consumption data of each functional module in the wake-up control network is collected in real time and input into the dynamic graph neural network for feature extraction and reconstruction analysis. By analyzing the power consumption reconstruction results, the error between the actual power consumption and the prediction model, that is, the power consumption reconstruction error, can be obtained. The power consumption reconstruction error directly reflects the execution effect of the current wake-up control strategy. When the power consumption reconstruction error exceeds the preset protection threshold, the compensation adjustment amount is calculated based on the error size to generate the protection control parameters. The role of the protection control parameters is to dynamically adjust the key control variables in the wake-up process, including the ramp slope in the voltage wake-up sequence and the specific timing of the clock enable. By correcting these parameters, the power consumption error is effectively reduced, and the module is prevented from being in an unstable state or power consumption fluctuations beyond the safe range during the wake-up process. The corrected voltage wake-up sequence and clock wake-up sequence are combined with the spatial distribution characteristics of the module to be reintegrated into an optimized safe wake-up control result. This result ensures that the functional modules can complete the switch from deep sleep state to normal working state under the optimal power consumption and time conditions, while avoiding system instability caused by error accumulation.

[0045] In the embodiment of the present invention, by combining the dynamic graph neural network and the hierarchical Bayesian model, the accurate extraction of the state characteristics of the multifunctional module and the accurate modeling of the state transition probability are realized, and the accuracy of the deep sleep state judgment is improved. Based on the functional module topology diagram and the dynamic adjacency matrix, the spatial correlation and temporal correlation between the functional modules are established, the collaborative control of the multifunctional modules is realized, and the working conflict between the modules is avoided. The reconfigurable intelligent control strategy is adopted to optimize the control parameters on the long time scale and the short time scale respectively, so as to improve the flexibility and adaptability of the sleep-wake-up process. Through real-time power consumption monitoring and reconstruction error analysis, a complete protection mechanism is established to ensure the safety and reliability of the functional module during the wake-up process. The hierarchical Bayesian model is introduced to model the influence of the environment and operating conditions, so as to improve the adaptability of the control strategy to different working scenarios. Based on dynamic feature extraction and spatial distribution feature reconstruction, the accurate identification and prediction of the state of the functional module are realized, and the intelligent level of deep sleep control is improved. Through the optimization design of the collaborative sleep control sequence, the mutual interference between the functional modules is reduced, and the overall power consumption management efficiency of the chip is improved.

[0046] In a specific embodiment, the process of executing step S100 may specifically include the following steps:

[0047] Deploy a deep sleep monitoring DSM system in the multi-mode SoC main control chip, and set up a power consumption monitor array and a temperature sensor array for the power supply path of each functional module;

[0048] The power consumption monitor array is connected to the SCADA monitoring system, and the voltage and current data of each functional module are sampled in real time to obtain the original power consumption data, and the temperature distribution data collected by the temperature sensor array is input into the SCADA monitoring system to obtain the original temperature data;

[0049] The original power consumption data and the original temperature data are digitally filtered to obtain the filtered monitoring data, and the filtered monitoring data are classified according to different environments and operating conditions EOC to obtain a classified data set, where EOC includes four types: normal working state, light load state, heavy load state and standby state;

[0050] The classification data set is preprocessed to obtain a preprocessed data set, and features are extracted from the preprocessed data set to obtain a chip monitoring data set.

[0051] Specifically, by setting power consumption monitor arrays and temperature sensor arrays in the power supply path of each functional module, the ability to perceive core physical parameters is established. The power consumption monitor array is used to capture the voltage and current information of the functional module. The temperature sensor array is used to record the temperature distribution of different areas of the chip in real time. These data reflect the thermal characteristics and cooling requirements of the chip operation. After connecting the power consumption monitor array to the SCADA monitoring system, the system can sample the voltage and current data of each functional module in real time at a high frequency to form an original power consumption data set. Assume that the voltage and current of a functional module are and , then the instantaneous power consumption of the module is expressed as:

[0052] ;

[0053] in, Indicates at time The measured voltage in volts (V); is the current at the corresponding moment, in ampere (A); is the instantaneous power consumption in watts (W). The original power consumption data set consists of instantaneous power consumption data of multiple modules, reflecting the dynamic energy consumption characteristics of the chip during operation. At the same time, the temperature sensor array inputs the collected temperature distribution data into the SCADA system to form the original temperature data set. Assume that the temperature sensor is located at the chip The temperature recorded at the coordinate position is , then the temperature distribution of the entire chip at a certain moment is expressed as:

[0054] ;

[0055] in, yes Coordinates at time The temperature value is in degrees Celsius (°C); ChipArea represents the physical area of ​​the chip. The raw power consumption data and temperature data are digitally filtered to improve the data quality. By applying a digital filtering algorithm, such as a low-pass filter, high-frequency noise is removed and the data is smoothed. The filtered power consumption data is expressed as:

[0056] ;

[0057] in, It is the impulse response function of the filter, which determines the characteristics of the filter; It is the power consumption data after filtering. The filtered temperature data is processed similarly to ensure that the temperature value at each time point is smoother and more reliable. These data are classified according to different environmental and operating conditions (EOC). EOC includes four types: normal working state, light load state, heavy load state and standby state. For example, when the chip is running, its total power consumption When the following conditions are met, it is classified into the corresponding EOC category:

[0058] Normal: , Idle: ;

[0059] in, and They are the lower and upper limits of the power consumption range in normal state, in watts; is the typical power consumption value in the standby state. After the data classification is completed, the classified data set is preprocessed, including steps such as outlier detection, missing value filling and data normalization. Outlier detection uses statistical methods, such as the triple standard deviation method, to identify and process abnormal points in power consumption and temperature data. Missing value filling uses time series interpolation methods to ensure the continuity and integrity of the data. Normalization maps the data to the range of [0,1] through linear transformation to eliminate the influence between different feature dimensions. After completing the data preprocessing, feature extraction is performed on the preprocessed data set to generate a chip monitoring data set. Feature extraction is completed by combining statistical features (such as mean, variance) and frequency domain features (such as power spectral density). For example, for the power consumption data of a functional module, its mean feature is expressed as:

[0060] ;

[0061] in, Indicates the time mean of power consumption; is the total duration of the monitoring period. Similarly, the feature extraction of temperature data is completed based on the spatial mean and time change rate to generate a comprehensive index describing the thermal characteristics of the module.

[0062] In a specific embodiment, the process of executing step S200 may specifically include the following steps:

[0063] The chip monitoring data set is used to construct an initial node matrix according to the physical position relationship of the functional modules, and a unique identifier is assigned to each functional module node in the initial node matrix to obtain a functional module identification matrix;

[0064] Performing statistical analysis on the data transmission volume between adjacent functional modules in the functional module identification matrix, and determining the connection weights between the functional modules according to the data transmission volume, to obtain a weighted connection matrix;

[0065] The weighted connection matrix is ​​input into the dynamic graph neural network, and the weighted connection matrix is ​​decomposed by the orthogonal decomposition POD processor to obtain a dynamic adjacency matrix;

[0066] The temporal correlation of each functional module is calculated according to the dynamic adjacency matrix, and a dynamic connection relationship is established between pairs of functional modules whose temporal correlation exceeds a threshold value to obtain a temporal feature matrix;

[0067] Based on the time series feature matrix, the power consumption data and temperature data of each functional module are analyzed in the time domain to obtain a dynamic feature matrix, and the spatial distance and thermal conductivity coefficient between the functional modules are calculated based on the dynamic feature matrix to obtain a spatial correlation matrix;

[0068] The dynamic feature matrix and the spatial correlation matrix are fused to obtain a fused feature matrix, and the topological connection relationship between modules is constructed based on the fused feature matrix to obtain a functional module topology map.

[0069] Specifically, the chip monitoring data set is constructed according to the physical layout of the functional modules in the chip to construct the initial node matrix. The initial node matrix defines each functional module as a node in the graph structure and clarifies its coordinates in the physical space. For example, suppose the chip has Functional modules, the physical coordinates of each module are Indicates that the initial node matrix is ​​expressed in the following form:

[0070] ;

[0071] in, and Respectively represent modules Each row of the matrix corresponds to a functional module. Assign a unique identifier to each module in the initial node matrix , get the functional module identification matrix The result of this step is expressed as follows:

[0072] ;

[0073] Based on the functional module identification matrix, the communication intensity between modules is quantified by statistically analyzing the data transmission volume between adjacent functional modules. and modules The average data transfer volume between , whose value is based on the total amount of data in the sampling period and sampling duration calculate:

[0074] ;

[0075] in, From the module To module The total amount of data transferred, is the sampling time. Based on the statistical analysis results, the transmission volume is mapped to the connection weight between functional modules. . Weighted connection matrix It is expressed as:

[0076] ;

[0077] in, The value of reflects the module and modules The communication strength between them; the diagonal elements are 0 because the module does not communicate with itself. Input the dynamic graph neural network and perform decomposition operations on it through the orthogonal decomposition processor to extract dynamic characteristics. Decompose the matrix into a combination of basis vectors in a low-dimensional subspace to capture the main change trends of module interactions. Assume that the matrix The decomposition result is:

[0078] ;

[0079] in, and is an orthogonal matrix, representing the left and right singular vectors; It is a diagonal matrix whose diagonal elements are singular values, indicating the weight strength. The decomposed dynamic adjacency matrix It follows from this that:

[0080] ;

[0081] Based on the dynamic adjacency matrix, the temporal dependency between modules is captured by calculating the temporal correlation of each functional module. and The temporal correlation It is expressed by the cross-correlation function of its time series data:

[0082] ;

[0083] in, and It is a module and Power consumption time series; and is its mean. The module pairs whose timing correlation exceeds the threshold are defined as dynamic connection relationships, and a timing feature matrix is ​​generated. Using the timing feature matrix, the power consumption data and temperature data of the functional modules are analyzed in the time domain to extract the dynamic feature matrix. At the same time, the spatial distance between modules is calculated and thermal conductivity , and obtain the spatial correlation matrix The spatial distance formula is:

[0084] ;

[0085] The formula for thermal conductivity is:

[0086] ;

[0087] in, is the thermal conductivity of the material. By transforming the dynamic characteristic matrix and the spatial correlation matrix Perform feature fusion to generate a fusion feature matrix Based on the fusion feature matrix, the topological connection relationship between modules is constructed to obtain the functional module topology map, which can reflect the spatial and temporal characteristics of the module.

[0088] In a specific embodiment, the process of executing step S300 may specifically include the following steps:

[0089] The functional module topology graph is input into the encoder of the dynamic graph neural network, and the node features and edge features of the functional module topology graph are subjected to graph convolution operation to obtain a first-order feature mapping matrix;

[0090] Perform multi-layer perceptron transformation and deep feature extraction on the first-order feature mapping matrix to obtain the potential feature vector;

[0091] Inputting the potential feature vector into the first decoder, reconstructing the power consumption timing characteristics of the functional module through the deconvolution layer in the first decoder, and obtaining the power consumption timing reconstruction result;

[0092] Inputting the potential feature vector into the second decoder, reconstructing the spatial distribution features of the functional module through the deconvolution layer in the second decoder, and obtaining a spatial distribution reconstruction result;

[0093] The error between the power consumption time series reconstruction result and the original power consumption data is calculated to obtain a power consumption reconstruction error matrix, and the error between the spatial distribution reconstruction result and the original temperature distribution data is calculated to obtain a spatial reconstruction error matrix;

[0094] The power consumption reconstruction error matrix and the space reconstruction error matrix are weightedly fused to obtain a comprehensive error index, and the deep sleep judgment threshold is set according to the comprehensive error index. The thresholds are compared based on the power consumption reconstruction error matrix and the space reconstruction error matrix to obtain the deep sleep state judgment criteria of each functional module.

[0095] Specifically, the topological graph of the functional modules is input into the encoder of the dynamic graph neural network. The functional module topological graph is represented in the form of a graph structure, where each node represents a functional module and the edge reflects the interaction between modules. Each node and edge contains multi-dimensional features, for example, the node feature is the power consumption and temperature status of the module, and the edge feature is the communication strength and distance between modules. The graph convolution operation is the process of aggregating the features of the node and its neighborhood. Assume that the node The eigenvector of , the set of neighboring nodes is , then the update formula of graph convolution is expressed as:

[0096] ;

[0097] in, It is Node after layer graph convolution The characteristic vector of and Is a node and neighbor nodes The degree of is the number of connected edges; It is The weight matrix of the layer, is the bias term; is an activation function, such as ReLU. Through the above graph convolution operation, node features are propagated layer by layer and fused with their neighborhood features to generate a first-order feature mapping matrix , whose dimensions are ,in Indicates the number of nodes, is the feature dimension of each node. The first-order feature mapping matrix Input the multi-layer perceptron for nonlinear transformation and deep feature extraction to generate potential feature vectors :

[0098] ;

[0099] in, is a nonlinear activation function (such as ReLU), and are the weight matrices of the first and second layer perceptrons, respectively. and is the bias term. The latent feature vector is a low-dimensional representation that contains the deep semantic information of the node. The potential feature vector is input into two decoders. The first decoder reconstructs the power consumption timing characteristics of the functional module through the deconvolution layer. Assume that the timing representation of the original power consumption data is , then the reconstructed power consumption timing characteristics are , the formula is:

[0100] ;

[0101] in, is the weight of the deconvolution kernel, is the first Quantity, is the reconstruction error. The second decoder similarly reconstructs the spatial distribution characteristics of the functional module through the deconvolution layer. Assuming that the original temperature distribution data is , then the reconstructed spatial distribution characteristics are , the formula is:

[0102] ;

[0103] in, is the convolution kernel weight for spatial reconstruction, is the reconstruction error of the spatial feature. After the reconstruction is completed, the error matrix between the power consumption timing feature and the original data is calculated. :

[0104] ;

[0105] Similarly, the error matrix of the spatial distribution characteristics is calculated :

[0106] ;

[0107] in, is the spatial area of ​​the module, is the area of ​​the region. The power consumption is reconstructed into the error matrix And the spatial reconstruction error matrix Perform weighted fusion to obtain the comprehensive error index :

[0108] ;

[0109] in, and is a weighting coefficient used to adjust the contribution ratio of power consumption and spatial characteristics to the comprehensive error. Set the deep sleep judgment threshold according to the comprehensive error index .when , the module meets the conditions to enter deep sleep, otherwise it keeps the current state.

[0110] In a specific embodiment, the process of executing step S400 may specifically include the following steps:

[0111] The deep sleep state criterion is used as input, and a hierarchical Bayesian model is constructed based on the power consumption characteristics and temperature characteristics of each functional module;

[0112] The state transition probability is calculated according to the power consumption reconstruction error matrix and the space reconstruction error matrix in the deep sleep state criterion, and the first-layer Bayesian parameters are obtained;

[0113] According to the first-layer Bayesian parameters, the state sequences of each functional module under different EOCs are analyzed, and the association mapping between the state transition probability and the EOC parameters is established to obtain the second-layer Bayesian parameters;

[0114] Inputting the first layer Bayesian parameters and the second layer Bayesian parameters into the hierarchical Bayesian reasoner in the hierarchical Bayesian model, performing joint probability reasoning on the state transition characteristics of the functional modules, and obtaining a state transition matrix;

[0115] Based on the state transfer matrix, the steady-state probability distribution of each functional module in different states is calculated, and the state transfer critical point of the functional module is determined according to the steady-state probability distribution to obtain the state transfer boundary;

[0116] Perform threshold segmentation on the state transition boundary, divide the state space into active area and sleep area, and determine the deep sleep threshold based on the state distribution characteristics of the functional module to obtain the sleep condition set;

[0117] The functional modules are grouped according to the sleep condition set, and combined and matched based on the state correlation between the functional modules to obtain an initial combination set. The combination score is calculated for each group of functional modules in the initial combination set, and the combination with the highest score is selected as the combination scheme of the deep sleep functional module.

[0118] Specifically, the deep sleep state criterion is based on the power consumption reconstruction error matrix And the spatial reconstruction error matrix The result reflects the possibility of the functional module entering the deep sleep state. Based on the deep sleep state criterion, the basic framework of the hierarchical Bayesian model is constructed by statistically analyzing the state change law of each functional module under different operating conditions (EOC, Environment and Operating Conditions). In the first layer of the Bayesian model, the error matrix is ​​reconstructed based on the power consumption And the spatial reconstruction error matrix , calculate the state transition probability of the functional module. Assume that the functional module The state is active (Active, denoted as ) or Sleep (Sleep, denoted as ), state transition probability Calculated by the following formula:

[0119] ;

[0120] in, Indicates that the module is in state Transfer to state Count Indicates that the module is in state Taking the power consumption reconstruction error matrix as an example, if the module The power consumption error is lower than a certain threshold , then the probability of entering the sleep state These state transition probabilities constitute the parameters of the first-level Bayesian model In the second-level Bayesian model, the impact of EOC on state transition is considered. EOC includes light load, heavy load, standby and other situations, and each situation has a different impact on the state transition probability. By analyzing the state sequence of the functional module under different EOCs, an association mapping between the state transition probability and the EOC parameters is established. For example, the EOC parameter Indicates environmental conditions The influence weight on state transfer is as follows:

[0121] ;

[0122] in, To indicate the function, when the module In time In the environment The value is 1 when it is, otherwise it is 0; is the number of modules, is the length of observation time. In this way, the second-level Bayesian parameter It can describe how environmental factors affect state transition. and the second-layer Bayesian parameters Input the hierarchical Bayesian reasoner to perform joint probability reasoning on the state transition characteristics of the module and generate a state transition matrix In the state transfer matrix, the element Indicates that the module is in state Transfer to state The joint probability of:

[0123] ;

[0124] in, It is in the environment The conditional probability under It’s the environment After obtaining the state transfer matrix, the steady-state probability distribution of the module under different states is calculated through steady-state analysis. The following equilibrium equation is satisfied:

[0125] ;

[0126] in, Indicates that the module is in state The long-term stability probability of . Through the steady-state probability distribution, the critical point of the state transition of the functional module is determined. For example, when When the module is more inclined to enter the deep sleep state. Based on these critical points, the active area and the sleep area in the state space are divided. The specific threshold of deep sleep is determined based on the state distribution characteristics, and a set of conditions describing the functional module entering sleep is generated. These conditions include power consumption, temperature, and ranges of environmental parameters, such as W . Group the functional modules according to the sleep condition set, combine the state correlation matching between modules, and generate the initial combination set For each group of functional modules, calculate the combined score :

[0127] ;

[0128] in, It is a module The weight of indicates its importance; is the distance penalty coefficient; d It is a module and The combination with the highest score is selected as the final deep sleep function module combination solution.

[0129] In a specific embodiment, the process of executing step S500 may specifically include the following steps:

[0130] Based on the combination scheme of deep sleep functional modules, the state stability of each functional module in a long time scale is analyzed to obtain the state statistical matrix;

[0131] According to the state statistics matrix, the state correlation analysis of the functional modules is carried out, and the module dependency matrix is ​​constructed according to the degree of state transfer synchronization between the functional modules;

[0132] The module dependency matrix is ​​topologically sorted to obtain the long-time sleep order, and the long-time sleep order is correlated and analyzed. The power supply voltage of each functional module is piecewise linearly regulated to obtain the voltage regulation sequence.

[0133] The clock gating strategy of the functional module is constructed based on the voltage regulation sequence. The clock control sequence is generated by performing hierarchical shutdown control on the clock tree, and the voltage regulation sequence and the clock control sequence are aligned in the time domain to obtain the initial control sequence.

[0134] The timing integrity of the initial control sequence is verified to obtain a calibration control sequence, and the transmission path of the control signal is analyzed based on the physical connection relationship between the calibration control sequence and each functional module to obtain a collaborative sleep control sequence.

[0135] Specifically, according to the combination scheme of deep sleep functional modules, the state of each functional module during long-term operation is counted to calculate its stability index. The state of the functional module is represented as two discrete modes: active state (Active, denoted as ) and sleep state (Sleep, denoted as ). Assume that at time Internal, module The state sequence is , its stability Calculated by the ratio of active and sleeping time:

[0136] ;

[0137] Among them, Count Representation Module In time In-state The number of times yes or By counting the state stability of all modules, a state statistics matrix is ​​generated, in which each element Describing the Module The long-term proportion in a certain state. Based on the state statistical matrix, the state correlation between functional modules is analyzed to identify the linkage between modules. For example, if two modules and The state changes of Transfer to ), then the correlation is high. State correlation is expressed as mutual information Indicates that the calculation formula is:

[0138] ;

[0139] in, It is a module and At the same time and The joint probability of and Modules and By analyzing the correlation between modules, the module dependency matrix is ​​constructed. , where the elements Representation Module For modules The module dependency matrix Perform topological sorting to generate a long-term sleep order. Topological sorting arranges the order of modules according to dependencies, so that the logic of shutting down high-dependency modules first and then shutting down low-dependency modules is met. Assume that the topological sorting result is ,in It is According to the sleep order, the supply voltage of each functional module is adjusted in a piecewise linear manner to generate a voltage adjustment sequence. The voltage change curve is , its piecewise linear form is expressed as:

[0140] ;

[0141] in, is the initial voltage, is the target voltage, is the voltage ramp slope, is the ramp time. Based on the voltage regulation sequence, the clock gating strategy of the functional module is constructed. Clock gating achieves energy saving by shutting down the clock tree in a hierarchical manner. , the clock control strategy uses the enable function express:

[0142] ;

[0143] in, It is a module The clock shutdown time is controlled by hierarchical control, and the clock control sequence is generated. . The voltage regulation sequence and clock control sequence Perform time domain alignment to ensure the consistency of the two in the time dimension and obtain the initial control sequence. The initial control sequence needs to be verified for timing integrity to ensure that the signal transmission between modules meets the logical dependency. For example, if the module Dependency modules output, you must ensure that the module The clock and voltage in the module It remains stable before switching to sleep. By verifying and correcting the inconsistent timing, a calibration control sequence is generated. According to the physical connection relationship between the calibration control sequence and the functional modules, the transmission path of the control signal is analyzed, the signal distribution is optimized, and the final coordinated sleep control sequence is obtained. For example, in a chip example, suppose three modules The dependency is , the sleep order is determined by topological sorting: Module Voltage change Set to linearly decrease from 1.2V to 0V, clock control It is turned off at 10ms. After aligning the voltage and clock sequences of all modules, a coordinated control sequence is obtained.

[0144] In a specific embodiment, the process of executing step S600 may specifically include the following steps:

[0145] The collaborative sleep control sequence is input into the hierarchical Bayesian model, the state transition probability of each functional module is calculated based on the first-layer Bayesian parameters, and the EOC influencing factors are analyzed in combination with the second-layer Bayesian parameters to obtain the probability distribution of the wake-up state;

[0146] Prioritize the functional modules according to the probability distribution of wake-up states, and generate a wake-up sequence for the functional modules based on the physical connection relationships and data transmission dependencies between the functional modules;

[0147] For each functional module in the functional module wake-up sequence, a voltage regulation curve is designed according to the wake-up timing, and the voltage ramp slope and holding time are determined to obtain a voltage wake-up sequence. A clock enable control scheme is constructed based on the voltage wake-up sequence, and a hierarchical start-up timing is designed to obtain a clock wake-up sequence.

[0148] The voltage wake-up sequence and the clock wake-up sequence are wired and planned according to the spatial distribution of the functional modules to obtain the wake-up control network. The power consumption data of each functional module in the wake-up control network is collected in real time and input into the dynamic graph neural network for feature extraction and reconstruction analysis to obtain the power consumption reconstruction error.

[0149] The power consumption reconstruction error is compared with the preset protection threshold. When the reconstruction error exceeds the threshold, the compensation adjustment amount is calculated based on the error size and the protection control parameters are generated. The voltage wake-up sequence and clock wake-up sequence are corrected according to the protection control parameters, and the voltage climbing slope and clock enable timing are adjusted to obtain a safe wake-up control result.

[0150] Specifically, the collaborative sleep control sequence is input into the hierarchical Bayesian model, and the wake-up state of the functional module is inferred by combining the first and second layer Bayesian parameters. The collaborative sleep control sequence provides the specific operation information of the functional module entering deep sleep, including the voltage, clock and state changes of each module. It is the state transition probability obtained based on historical data statistics, describing the module from sleep state To active state The basic probability distribution of the second-level Bayesian parameters It is used to model the impact of environment and operating conditions (EOC) on the wake-up process. Combining the two, the probability distribution of wake-up state is calculated through the hierarchical Bayesian model :

[0151] ;

[0152] in, represents the impact factor of EOC, is the conditional state transition probability, is the prior probability distribution of EOC. According to the probability distribution of wake-up state, the functional modules are sorted according to the wake-up priority. The priority is determined by two main factors: the urgency of wake-up and the dependency between functional modules. For example, some modules have higher priority during system startup because the normal operation of other modules depends on their active state. Priority It is expressed as:

[0153] ;

[0154] in, It is a module The probability of awakening state, Is a dependent module A collection of modules, It is a module and The dependency weight between and is a weight factor used to adjust the relative importance of these two factors. Based on the sorting results, a wake-up sequence for the functional modules is generated and a voltage regulation curve is designed for each module. Assuming the module The target voltage is , the initial voltage is The slope of the voltage ramp is , then its voltage regulation curve is expressed as:

[0155] ;

[0156] in, The unit is V / s. For modules with faster wake-up process, If the setting is large and the module has high temperature control requirements, it is necessary to reduce On the basis of voltage regulation, a clock enable control scheme is constructed to realize the gradual wake-up of the module by hierarchical opening of the clock tree. The clock enable opening strategy uses the enable function express:

[0157] ;

[0158] in, It is a module The clock enable time is consistent with the voltage regulation curve. The voltage wake-up sequence of all modules and clock wake-up sequence According to the spatial distribution of functional modules, wiring planning is performed to form a complete wake-up control network. During the wake-up process, the power consumption data of each functional module in the wake-up control network is collected in real time, and these data are input into the dynamic graph neural network (DGN) for feature extraction and reconstruction analysis. The real-time power consumption is , the reconstruction result of DGN is , then the power consumption reconstruction error It is expressed as:

[0159] ;

[0160] When the reconstruction error Exceeds the preset protection threshold The wake-up process needs to be corrected. According to the error size, calculate the compensation adjustment amount and adjust the clock enable time :

[0161] ;

[0162] in, and is the proportional adjustment coefficient, which is used to convert the error into compensation. After the compensation parameters are updated, the voltage wake-up sequence and clock wake-up sequence are corrected to adjust the voltage ramp slope. and clock enable time , ensuring that the module completes wakeup within a safe range. The generated safe wakeup control result is optimized through dynamic real-time adjustment.

[0163] See also Figure 2 , Figure 2A schematic block diagram of the structure of a deep sleep wake-up control system 200 of a multi-mode SoC main control chip provided in an embodiment of the present application, such as Figure 2 As shown, the deep sleep wake-up control system 200 of the multi-mode SoC main control chip includes:

[0164] The acquisition module 210 is used to collect the voltage and current data and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain a chip monitoring data set;

[0165] A construction module 220 is used to input the chip monitoring data set into the dynamic graph neural network, construct a dynamic adjacency matrix, and extract the dynamic features and spatial correlation of each functional module to obtain a functional module topology map;

[0166] A mapping module 230 is used to map the functional module topology map into potential features through an encoder in a dynamic graph neural network, and to reconstruct the power consumption timing features and spatial distribution features and calculate the error to obtain the deep sleep state criterion of each functional module;

[0167] The identification module 240 is used to establish a hierarchical Bayesian model according to the deep sleep state criterion, identify the state transition probability and EOC influencing factors of each functional module, and obtain a combination scheme of the deep sleep functional modules;

[0168] A processing module 250, configured to determine a collaborative sleep control sequence based on a combination scheme of the deep sleep function modules;

[0169] The output module 260 is used to input the collaborative sleep control sequence into the hierarchical Bayesian model, generate the wake-up voltage and clock sequence, and monitor the power consumption response of each functional module in real time through the dynamic graph neural network, and output the safe wake-up control result.

[0170] Through the collaboration of the above components, the combination of dynamic graph neural network and hierarchical Bayesian model realizes the accurate extraction of state features of multifunctional modules and the precise modeling of state transition probability, which improves the accuracy of deep sleep state judgment. Based on the functional module topology graph and dynamic adjacency matrix, the spatial correlation and temporal correlation between functional modules are established, the collaborative control of multifunctional modules is realized, and the working conflict between modules is avoided. The reconfigurable intelligent control strategy is adopted to optimize the control parameters on long time scale and short time scale respectively, which improves the flexibility and adaptability of the sleep-wake-up process. Through real-time power consumption monitoring and reconstruction error analysis, a complete protection mechanism is established to ensure the safety and reliability of functional modules during the wake-up process. The hierarchical Bayesian model is introduced to model the impact of environmental and operating conditions, which improves the adaptability of the control strategy to different working scenarios. Based on dynamic feature extraction and spatial distribution feature reconstruction, the accurate identification and prediction of the state of functional modules is realized, and the intelligent level of deep sleep control is improved. Through the optimization design of collaborative sleep control sequence, the mutual interference between functional modules is reduced, and the overall power consumption management efficiency of the chip is improved.

[0171] See also Figure 3 , Figure 3 A schematic block diagram of the structure of a deep sleep wake-up control device 300 for a multi-mode SoC master chip provided in an embodiment of the present application, wherein the deep sleep wake-up control device 300 for the multi-mode SoC master chip includes a processor 301 and a memory 302, wherein the processor 301 and the memory 302 are connected via a device bus 303, wherein the memory 302 may include a non-volatile storage medium and an internal memory.

[0172] The non-volatile storage medium can store a computer program. The computer program includes program instructions, and when the program instructions are executed by the processor 301, the processor 301 can execute any of the above-mentioned deep sleep wake-up control methods for the multi-mode SoC main control chip.

[0173] The processor 301 is used to provide computing and control capabilities to support the operation of the deep sleep wake-up control device 300 of the entire multi-mode SoC main control chip.

[0174] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor 301, the processor 301 can execute any of the above-mentioned deep sleep wake-up control methods for the multi-mode SoC master chip.

[0175] Those skilled in the art will understand that Figure 3The structure shown in the figure is only a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the deep sleep wake-up control device 300 of the multi-mode SoC main control chip involved in the scheme of the present application. The specific deep sleep wake-up control device 300 of the multi-mode SoC main control chip may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0176] It should be understood that the processor 301 may be a central processing unit (CPU), and the processor 301 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0177] It should be noted that technical personnel in the relevant field can clearly understand that, for the convenience and conciseness of description, the specific working process of the deep sleep wake-up control device 300 of the multi-mode SoC master control chip described above can refer to the corresponding process of the deep sleep wake-up control method of the aforementioned multi-mode SoC master control chip, and will not be repeated here.

[0178] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by one or more processors, the one or more processors implement the deep sleep wake-up control method of the multi-mode SoC master control chip provided in the embodiment of the present application.

[0179] The computer-readable storage medium may be an internal storage unit of the deep sleep wake-up control device 300 of the multi-mode SoC main control chip in the aforementioned embodiment, such as a hard disk or memory of the deep sleep wake-up control device 300 of the multi-mode SoC main control chip. The computer-readable storage medium may also be an external storage device of the deep sleep wake-up control device 300 of the multi-mode SoC main control chip, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc., equipped with the deep sleep wake-up control device 300 of the multi-mode SoC main control chip.

[0180] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0181] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0182] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A deep sleep wake-up control method for a multi-mode SoC master chip, characterized in that: include: Collect voltage, current and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain a chip monitoring data set; Inputting the chip monitoring data set into a dynamic graph neural network, constructing a dynamic adjacency matrix, and extracting the dynamic features and spatial correlation of each functional module to obtain a functional module topology map; The functional module topology map is mapped into potential features through the encoder in the dynamic graph neural network, and the power consumption timing features and spatial distribution features are reconstructed and the error is calculated to obtain the deep sleep state judgment criteria of each functional module; specifically including: inputting the functional module topology map into the encoder of the dynamic graph neural network, performing graph convolution operation on the node features and edge features of the functional module topology map to obtain a first-order feature mapping matrix; performing multi-layer perceptron transformation and deep feature extraction on the first-order feature mapping matrix to obtain a potential feature vector; inputting the potential feature vector into the first decoder, reconstructing the power consumption timing features of the functional module through the deconvolution layer in the first decoder, and obtaining the power consumption timing reconstruction result; The potential feature vector is input into the second decoder, and the spatial distribution characteristics of the functional module are reconstructed through the deconvolution layer in the second decoder to obtain a spatial distribution reconstruction result; the error calculation is performed on the power consumption time series reconstruction result and the original power consumption data to obtain a power consumption reconstruction error matrix, and the error calculation is performed on the spatial distribution reconstruction result and the original temperature distribution data to obtain a spatial reconstruction error matrix; the power consumption reconstruction error matrix and the spatial reconstruction error matrix are weightedly fused to obtain a comprehensive error index, and a deep sleep judgment threshold is set according to the comprehensive error index, and a threshold comparison is performed based on the power consumption reconstruction error matrix and the spatial reconstruction error matrix to obtain a deep sleep state judgment criterion for each functional module; A hierarchical Bayesian model is established according to the deep sleep state criterion, the state transition probability and EOC influencing factors of each functional module are identified, and a combination scheme of the deep sleep functional modules is obtained; specifically, the deep sleep state criterion is used as input, and a hierarchical Bayesian model is constructed based on the power consumption characteristics and temperature characteristics of each functional module; the state transition probability is calculated according to the power consumption reconstruction error matrix and the space reconstruction error matrix in the deep sleep state criterion, and the first layer of Bayesian parameters are obtained; according to the first layer of Bayesian parameters, the state sequence of each functional module under different EOC is analyzed, and the association mapping between the state transition probability and the EOC parameters is established to obtain the second layer of Bayesian parameters; the first layer of Bayesian parameters and the second layer of Bayesian parameters are input into the hierarchical Bayesian model The inference engine performs joint probability reasoning on the state transfer characteristics of the functional modules to obtain a state transfer matrix; based on the state transfer matrix, the steady-state probability distribution of each functional module in different states is calculated, and the state transfer critical point of the functional module is determined according to the steady-state probability distribution to obtain a state transfer boundary; the state transfer boundary is threshold segmented to divide the state space into an active area and a sleep area, and the deep sleep threshold is determined based on the state distribution characteristics of the functional modules to obtain a sleep condition set; the functional modules are grouped according to the sleep condition set, and combination matching is performed based on the state correlation between the functional modules to obtain an initial combination set, and a combination score is calculated for each group of functional modules in the initial combination set, and the combination with the highest score is selected as the combination scheme of the deep sleep functional module; Determine a collaborative sleep control sequence based on a combination scheme of the deep sleep function modules; The collaborative sleep control sequence is input into the hierarchical Bayesian model to generate a wake-up voltage and clock sequence, and the power consumption response of each functional module is monitored in real time through the dynamic graph neural network to output a safe wake-up control result.

2. The deep sleep wake-up control method of the multi-mode SoC master chip according to claim 1 is characterized in that: The collecting of voltage and current data and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain a chip monitoring data set includes: A deep sleep monitoring DSM system is deployed in the multi-mode SoC main control chip, and a power consumption monitor array and a temperature sensor array are set for the power supply path of each functional module; The power consumption monitor array is connected to a SCADA monitoring system, and the voltage and current data of each functional module are sampled in real time to obtain original power consumption data, and the temperature distribution data collected by the temperature sensor array is input into the SCADA monitoring system to obtain original temperature data; Performing digital filtering on the original power consumption data and the original temperature data to obtain filtered monitoring data, and classifying the filtered monitoring data according to different environments and operating conditions EOC to obtain a classified data set, wherein the EOC includes four types: normal working state, light load state, heavy load state and standby state; The classified data set is preprocessed to obtain a preprocessed data set, and feature extraction is performed on the preprocessed data set to obtain a chip monitoring data set.

3. The deep sleep wake-up control method of the multi-mode SoC master chip according to claim 2 is characterized in that: The chip monitoring data set is input into a dynamic graph neural network, a dynamic adjacency matrix is ​​constructed, and the dynamic features and spatial correlation of each functional module are extracted to obtain a functional module topology map, including: Constructing an initial node matrix based on the chip monitoring data set according to the physical position relationship of the functional modules, and assigning a unique identifier to each functional module node in the initial node matrix to obtain a functional module identification matrix; Performing statistical analysis on the data transmission volume between adjacent functional modules in the functional module identification matrix, and determining the connection weights between the functional modules according to the data transmission volume, to obtain a weighted connection matrix; Inputting the weighted connection matrix into a dynamic graph neural network, performing a decomposition operation on the weighted connection matrix through an orthogonal decomposition POD processor to obtain a dynamic adjacency matrix; Calculate the temporal correlation of each functional module according to the dynamic adjacency matrix, and establish a dynamic connection relationship between pairs of functional modules whose temporal correlation exceeds a threshold value to obtain a temporal feature matrix; Based on the timing characteristic matrix, the power consumption data and temperature data of each functional module are analyzed in the time domain to obtain a dynamic characteristic matrix, and the spatial distance and thermal conductivity coefficient between the functional modules are calculated based on the dynamic characteristic matrix to obtain a spatial correlation matrix; The dynamic feature matrix and the spatial correlation matrix are subjected to feature fusion to obtain a fused feature matrix, and a topological connection relationship between modules is constructed based on the fused feature matrix to obtain a functional module topology map.

4. The deep sleep wake-up control method of the multi-mode SoC master chip according to claim 1, characterized in that: The determining of the collaborative sleep control sequence based on the combination scheme of the deep sleep function modules includes: Analyze the state stability of each functional module on a long time scale based on the combination scheme of the deep sleep functional module to obtain a state statistical matrix; Performing state correlation analysis on the functional modules according to the state statistical matrix, and constructing a module dependency matrix according to the degree of state transfer synchronization between the functional modules; Topologically sorting the module dependency matrix to obtain a long-time-scale sleep order, performing correlation analysis on the long-time-scale sleep order, performing piecewise linear regulation on the power supply voltage of each functional module to obtain a voltage regulation sequence; Building a clock gating strategy for a functional module based on the voltage regulation sequence, generating a clock control sequence by performing hierarchical shutdown control on a clock tree, and aligning the voltage regulation sequence and the clock control sequence in the time domain to obtain an initial control sequence; The initial control sequence is verified for timing integrity to obtain a calibration control sequence, and a transmission path analysis of the control signal is performed based on the calibration control sequence and the physical connection relationship between each functional module to obtain a collaborative sleep control sequence.

5. The deep sleep wake-up control method of the multi-mode SoC master chip according to claim 4 is characterized in that: The step of inputting the collaborative sleep control sequence into the hierarchical Bayesian model, generating a wake-up voltage and clock sequence, and monitoring the power consumption response of each functional module in real time through the dynamic graph neural network, and outputting a safe wake-up control result includes: The collaborative sleep control sequence is input into the hierarchical Bayesian model, the state transition probability of each functional module is calculated based on the first layer Bayesian parameters, and the EOC influencing factors are analyzed in combination with the second layer Bayesian parameters to obtain the probability distribution of the awakening state; Prioritize the functional modules according to the wake-up state probability distribution, and generate a functional module wake-up sequence based on the physical connection relationship and data transmission dependency between the functional modules; For each functional module in the functional module wake-up sequence, a voltage regulation curve is designed according to the wake-up timing, and the voltage ramp slope and holding time are determined to obtain a voltage wake-up sequence, a clock enable control scheme is constructed based on the voltage wake-up sequence, and a hierarchical start timing is designed to obtain a clock wake-up sequence; The voltage wake-up sequence and the clock wake-up sequence are wired and planned according to the spatial distribution of the functional modules to obtain a wake-up control network, power consumption data of each functional module in the wake-up control network is collected in real time, and input into a dynamic graph neural network for feature extraction and reconstruction analysis to obtain a power consumption reconstruction error; The power consumption reconstruction error is compared with a preset protection threshold. When the reconstruction error exceeds the threshold, a compensation adjustment amount is calculated based on the error size and a protection control parameter is generated. The voltage wake-up sequence and the clock wake-up sequence are corrected according to the protection control parameter, and the voltage ramp slope and the clock enable timing are adjusted to obtain a safe wake-up control result.

6. A deep sleep wake-up control system for a multi-mode SoC main control chip, characterized in that: A deep sleep wake-up control method for executing a multi-mode SoC master control chip according to any one of claims 1 to 5, comprising: The acquisition module is used to collect the voltage and current data and temperature distribution data of each functional module of the multi-mode SoC main control chip under different environments and operating conditions EOC to obtain a chip monitoring data set; A construction module is used to input the chip monitoring data set into a dynamic graph neural network, construct a dynamic adjacency matrix, and extract the dynamic features and spatial correlation of each functional module to obtain a functional module topology map; A mapping module is used to map the functional module topology map into potential features through the encoder in the dynamic graph neural network, and reconstruct the power consumption timing features and spatial distribution features and calculate errors to obtain the deep sleep state judgment criteria of each functional module; specifically comprising: inputting the functional module topology map into the encoder of the dynamic graph neural network, performing graph convolution operations on the node features and edge features of the functional module topology map to obtain a first-order feature mapping matrix; performing multi-layer perceptron transformation and deep feature extraction on the first-order feature mapping matrix to obtain a potential feature vector; inputting the potential feature vector into the first decoder, reconstructing the power consumption timing features of the functional module through the deconvolution layer in the first decoder, and obtaining a power consumption timing reconstruction Result; input the potential feature vector into the second decoder, reconstruct the spatial distribution characteristics of the functional module through the deconvolution layer in the second decoder, and obtain the spatial distribution reconstruction result; perform error calculation on the power consumption time series reconstruction result and the original power consumption data to obtain the power consumption reconstruction error matrix, and perform error calculation on the spatial distribution reconstruction result and the original temperature distribution data to obtain the spatial reconstruction error matrix; perform weighted fusion on the power consumption reconstruction error matrix and the spatial reconstruction error matrix to obtain a comprehensive error index, and set a deep sleep judgment threshold according to the comprehensive error index, perform threshold comparison based on the power consumption reconstruction error matrix and the spatial reconstruction error matrix to obtain the deep sleep state judgment criterion of each functional module; The identification module is used to establish a hierarchical Bayesian model according to the deep sleep state criterion, identify the state transition probability and EOC influencing factors of each functional module, and obtain a combination scheme of the deep sleep functional modules; specifically includes: taking the deep sleep state criterion as input, and constructing a hierarchical Bayesian model based on the power consumption characteristics and temperature characteristics of each functional module; calculating the state transition probability according to the power consumption reconstruction error matrix and the space reconstruction error matrix in the deep sleep state criterion, and obtaining the first layer of Bayesian parameters; analyzing the state sequence of each functional module under different EOC according to the first layer of Bayesian parameters, establishing an association mapping between the state transition probability and the EOC parameters, and obtaining the second layer of Bayesian parameters; inputting the first layer of Bayesian parameters and the second layer of Bayesian parameters into the hierarchical Bayesian model; A hierarchical Bayesian reasoner performs joint probability reasoning on the state transition characteristics of the functional modules to obtain a state transition matrix; based on the state transition matrix, the steady-state probability distribution of each functional module in different states is calculated, and the state transition critical point of the functional module is determined according to the steady-state probability distribution to obtain a state transition boundary; threshold segmentation is performed on the state transition boundary to divide the state space into an active area and a sleep area, and a deep sleep threshold is determined based on the state distribution characteristics of the functional modules to obtain a sleep condition set; each functional module is grouped according to the sleep condition set, and combination matching is performed based on the state correlation between the functional modules to obtain an initial combination set, a combination score is calculated for each group of functional modules in the initial combination set, and the combination with the highest score is selected as the combination scheme of the deep sleep functional module; A processing module, configured to determine a collaborative sleep control sequence based on a combination scheme of the deep sleep function modules; The output module is used to input the collaborative sleep control sequence into the hierarchical Bayesian model, generate a wake-up voltage and clock sequence, and monitor the power consumption response of each functional module in real time through the dynamic graph neural network to output a safe wake-up control result.

7. A deep sleep wake-up control device for a multi-mode SoC main control chip, characterized in that: The deep sleep wake-up control device of the multi-mode SoC main control chip comprises: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instruction in the memory so that the deep sleep wake-up control device of the multi-mode SoC main control chip executes the deep sleep wake-up control method of the multi-mode SoC main control chip as described in any one of claims 1-5.

8. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instruction is executed by the processor, a deep sleep wake-up control method for a multi-mode SoC master control chip as described in any one of claims 1-5 is implemented.

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