Cache strategy verification method, device, equipment and readable storage medium

Abstract

The embodiment of the present invention provides a cache strategy verification method, device, equipment and readable storage medium, the method comprising: constructing an initial state machine model based on a state set cached in a data interaction process; triggering a transfer of the state in the initial state machine model when the corresponding operating condition is realized; configuring a time condition in the state migration path of the initial state machine model to obtain an updated state machine model; triggering a transfer of the state in the updated state machine model when the corresponding operating condition and time condition are realized; constructing functional features corresponding to the state according to multiple states and state migration paths in the initial state machine model, and constructing performance features corresponding to the state according to the time condition; searching and verifying the updated state machine model, and respectively determining a functional verification result corresponding to the functional feature and a performance verification result corresponding to the performance feature. The present invention can improve the accuracy of cache strategy verification.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a cache strategy verification method, device, electronic device and computer-readable storage medium. Background Art

[0002] In a multi-core system, multiple cores can have their own caches to increase data access speed, but this can easily lead to data inconsistency. To ensure data accuracy, cache consistency technology is used to coordinate data states between different caches. Different cache strategies can be used to achieve cache consistency, but the cache strategy needs to be verified to avoid problems with the cache strategy that lead to the failure to achieve cache consistency.

[0003] In the related art, a state machine model is constructed based on the various states and state transitions of the cache during the data interaction process of a specific cache strategy, and the state machine model is verified to confirm whether the current cache strategy has the relevant functions.

[0004] However, in the related art, only the function of the cache strategy is verified, and the verification dimension is single, resulting in insufficient accuracy of the cache strategy verification. Summary of the invention

[0005] The embodiments of the present invention provide a cache policy verification method, device, electronic device and readable storage medium, which can solve the problem in related technologies that the applicability of an instruction set cannot be determined.

[0006] In order to solve the above problem, an embodiment of the present invention discloses a cache policy verification method, which includes:

[0007] Based on the state set cached in the data interaction process, an initial state machine model is constructed; the initial state machine model includes multiple states and state transition paths between states; each state transition path has a corresponding operating condition; the state in the initial state machine model triggers the transition when the corresponding operating condition is achieved;

[0008] In the state transition path of the initial state machine model, a time condition is configured to obtain an updated state machine model; the state in the updated state machine model triggers the transition when the corresponding operation condition and time condition are achieved;

[0009] According to the multiple states and state transition paths in the initial state machine model, construct functional characteristics corresponding to the states, and according to the time conditions, construct performance characteristics corresponding to the states;

[0010] The updated state machine model is searched and verified to respectively determine a function verification result corresponding to the function feature and a performance verification result corresponding to the performance feature.

[0011] On the other hand, an embodiment of the present invention discloses a cache policy verification device, the device comprising:

[0012] An initial model module is used to construct an initial state machine model based on a state set cached in the data interaction process; the initial state machine model includes multiple states and state transition paths between states; each state transition path has a corresponding operating condition; the state in the initial state machine model triggers the transition when the corresponding operating condition is achieved;

[0013] An update model module, configured to configure a time condition in the state transition path of the initial state machine model to obtain an updated state machine model; the state in the updated state machine model triggers the transition when the corresponding operation condition and time condition are achieved;

[0014] A feature construction module, used to construct functional features corresponding to the states according to the multiple states and state transition paths in the initial state machine model, and to construct performance features corresponding to the states according to the time conditions;

[0015] The feature verification module is used to search and verify the updated state machine model, and respectively determine the function verification results corresponding to the functional features and the performance verification results corresponding to the performance features.

[0016] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned cache policy verification method.

[0017] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned cache policy verification method.

[0018] The embodiment of the present invention has the following advantages: by constructing an initial state machine model based on a state set cached in a data interaction process, the initial state machine model includes multiple states and state transition paths; each state transition path has a corresponding operation condition, the state in the initial state machine model triggers a transfer when the operation condition is realized, in the state transition path of the initial state machine model, a time condition is configured to obtain an updated state machine model, the state in the updated state machine model is used to trigger a transfer when the operation condition and the time condition are met, according to the multiple states and state transition paths in the initial state machine model, a functional feature corresponding to the state is constructed, according to the time condition, a performance feature corresponding to the state is constructed, the updated state machine model is searched and verified, and the functional verification result corresponding to the functional feature and the performance verification result corresponding to the performance feature are determined respectively, on the basis of constructing a state machine model including states and state transition paths based on a state set, the time condition can be further configured on the state transition path to obtain an updated state machine model, and then the functional verification result and the performance verification result can be verified, and the cache strategy is verified from the two dimensions of function and performance, which increases the verification dimension of the cache and improves the accuracy of the cache strategy verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figure 1 It is a flowchart of the steps of a cache strategy verification method provided by an example of the present invention;

[0021] Figure 2 is a schematic diagram of an initial state machine model provided by an example of the present invention;

[0022] Figure 3 is a schematic diagram of an update state machine model provided by an example of the present invention;

[0023] Figure 4 is a flowchart of another cache strategy verification method provided by an example of the present invention;

[0024] Figure 5 is a structural block diagram of a cache strategy verification device provided by an example of the present invention;

[0025] Figure 6 It is a structural block diagram of an electronic device for cache policy verification provided by an example of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0028] Method Embodiment

[0029] Reference Figure 1 , shows a flowchart of a cache strategy verification method embodiment of the present invention, the method may specifically include the following steps:

[0030] Step 101, construct an initial state machine model based on a set of states cached in the data interaction process; the initial state machine model includes multiple states and state transition paths between states; each state transition path has a corresponding operating condition; the state in the initial state machine model triggers a transfer when the corresponding operating condition is achieved.

[0031] In the embodiment of the present invention, the cache may have multiple states during the data interaction process, and the multiple states are referred to as a state set. When different cache strategies are adopted, the states in the state set may be different. Each state of the cache may be migrated from one state to another state if the migration condition is met, that is, there may be a state migration path between the states.

[0032] Taking a relatively simple elevator control system as an example, the states may include "stationary on the 1st floor", "ascending", "stationary on the 5th floor", etc. The transition between states is that the elevator switches from one state to another according to different input conditions (such as a passenger pressing a floor button).

[0033] The system that needs to be verified (such as hardware circuits, software programs, communication protocols, etc.) can be established as a state transition system model, which contains a series of states and the migration paths between states.

[0034] In an embodiment of the present invention, the migration conditions in the state migration path may be operation conditions, such as operations such as Acquire, Release, and Probe. For example, the AcquireBlock.NtoT operation is performed to obtain specific permissions for a cache block and convert its state from an initial state to a target state, which may be a conversion from an unauthorized or low-authorized state to a target permission state that can read or write the cache block; the GrantData operation is performed to grant data to the requester and set the data state to the target state, as well as other operations and corresponding state migrations, which are not limited here.

[0035] In the initial state machine model constructed based on the cached state set, each state can be connected to other states through a state transition path, and each state can be migrated to the state at the other end of the state transition path when the operating conditions in the corresponding state transition path are realized.

[0036] Step 102, in the state transition path of the initial state machine model, configure the time condition to obtain an updated state machine model; the state in the updated state machine model triggers the transition when the corresponding operation condition and time condition are achieved.

[0037] In the embodiment of the present invention, the existing state transition path of the initial state machine model may mainly include operating conditions, that is, when the corresponding operating conditions are realized, it is possible to transition from one state to another state.

[0038] Figure 2 is a schematic diagram of an initial state machine model provided by an embodiment of the present invention; Figure 2 The state 201, the state 202, the state 203 and the state 204 are included;

[0039] State 201 may be the N (None) state, indicating that there is no valid data in the cache block. In this state, the cache block is invalid and does not contain a copy of the data that should be used by the processor.

[0040] State 202 may be a B (Busy) state, indicating that the cache block is being operated, and may be in the process of data transmission or consistency maintenance operation;

[0041] State 203 may be a TTC (Touched-To-Clean) state, which means that the cache block has been accessed and the data is dirty (inconsistent with the data in the main memory), and needs to be written back to the main memory at some point to maintain data consistency;

[0042] State 204 may be a TTD (Touched-To-Dirty) state, which means that the cache block has been accessed and modified and has become dirty data. It is also necessary to handle the consistency issue with the main memory data at an appropriate time.

[0043] The operation condition from state 202 to state 201 can be a probe operation or a release operation, which can be expressed as "ProbetoN / Release"; the operation condition from state 201 to state 203 can be acquiring data (AcquireData) and performing authorization cleanup (GrantClean) operations, which can be expressed as "AcquireDataTTC&GrantClean"; the operation condition from state 203 to state 204 can be a probe operation, and the operation conditions for other state transitions are similar and will not be repeated. Figure 2 The process and relationship of operations such as data acquisition, permission acquisition, detection and release between a small number of states are schematically shown. The actual state machine can be more complex.

[0044] On the basis of the existing state transition path, a time condition can be added, which means that in the case of being in the current state, the time condition in the state transition path corresponding to the current state needs to be met before the next state can be migrated. It can be understood that if the existing state transition path already includes the operation condition, if the state transition is to occur, both the operation condition and the time condition need to be met.

[0045] Figure 3 is a schematic diagram of an update state machine model provided by an embodiment of the present invention; Figure 3 State 301 in the data transmission may be the TTD state; state 302 may be TTD1, which may be a sub-state of the TTD state and may be used to further subdivide operations after the data becomes dirty; state 303 may be ERR_TTD (a sub-state of TTD), and when an error occurs, the ERR_TTD state may be entered, which may be used for an error handling and recovery mechanism so that the system can identify and correct problems during the transmission process; state 304 may be TTDTTD1 (a sub-state of TTD), and state 305 may be TTDTTD2 (a sub-state of TTD).

[0046] For the transition from state 302 to state 301, operation condition 1 may be “l2_l3_ReleaseAck!”; for the transition from state 301 to state 302, operation condition 2 may be “l2_l3_Release_BtoN?”; for the transition from state 301 to state 303, operation condition 3 may be “l2_l3_Release_TtoN?”; for the transition from state 301 to state 304, operation condition 4 may be “l2_l3_AcquireBlock_NtoB?” and time condition 1 may be “clk_l3=0”; for the transition from state 304 to state 305, operation condition 5 may be “l3_l2_GrantData_toT!” and time condition 2 may be “clk_l3>=39”. In addition, state 304 itself may also correspond to time condition 3 “clk_l3<=39”, indicating that the stay time in state 304 may be less than or equal to 39 time units.

[0047] Understandably, Figure 3 These are only some examples of updating the state machine model. The actual state machine model can be more complex, including more states and state transition paths.

[0048] Step 103: construct functional characteristics corresponding to the states according to the multiple states and state transition paths in the initial state machine model, and construct performance characteristics corresponding to the states according to the time conditions.

[0049] In an embodiment of the present invention, the features may include features for describing the reachability, security, activity, etc. of the state machine model, such as whether a certain state can be reached, whether a deadlock exists, and whether a certain state will eventually be accessed.

[0050] Functional features can be set according to the existing states and state transition paths in the initial state machine model. For example, for the above elevator system, a functional feature may be "when the elevator is ascending, it will not suddenly descend". The functional features of the embodiments of the present invention represent the specific functions that the cache strategy corresponding to the initial state machine model needs to implement.

[0051] For example, the constructed functional feature may be A[]notdeadlock, which indicates that deadlock should not occur. In the cache strategy, deadlock may mean that the system is stuck in an infinite waiting state when waiting for certain resources, making it impossible to continue running.

[0052] Functional features related to state transition requirements may also be included, for example, including "11d_ctl.NTTC3-->11d_ctl.TTD", indicating correct transition from state NTTC3 (TTC-related state) to TTD.

[0053] The performance characteristics may be set according to time conditions. For example, the time condition for a state to migrate to another state may be to migrate within 341 time units. Then the performance characteristics may include A[]11d_ctl.NTTC2imply11d_ctl.clk<=341, indicating that in state NTTC2, the state stay time should be less than or equal to 341 time units. The content of the functional characteristics and performance characteristics is not specifically limited here.

[0054] The above functional characteristics and performance characteristics limit the cache strategy to avoid deadlock during operation and ensure that the migration between various states complies with the logic and timing requirements of the system design, thereby ensuring the correctness and stability of the cache operation.

[0055] Step 104 , searching and verifying the updated state machine model, and determining the function verification results corresponding to the function characteristics and the performance verification results corresponding to the performance characteristics.

[0056] In an embodiment of the present invention, the update state machine model includes multiple states and state transition paths, so the update state machine model may include a state space, and the state space of the update state machine model may be traversed. The traversal process may start from the initial state and gradually generate all possible state sequences according to the state transition path. In this process, the information of each state and the conversion relationship between states are recorded. For each generated state sequence, check whether the relevant functional characteristics and performance characteristics are met.

[0057] If the updated state machine model meets all functional characteristics, the functional verification result can be passed; if not all functional characteristics are met, the functional verification result can list the functional characteristics that failed. The performance characteristics are similar. If the updated state machine model meets all performance characteristics, the performance verification result can be passed; if not all performance characteristics are met, the functional verification result can list the performance characteristics that failed.

[0058] The embodiment of the present invention has the following advantages: by constructing an initial state machine model based on a state set cached in a data interaction process, the initial state machine model includes multiple states and state transition paths; each state transition path has a corresponding operating condition, the state in the initial state machine model triggers a transfer when the operating condition is realized, in the state transition path of the initial state machine model, a time condition is configured to obtain an updated state machine model, the state in the updated state machine model is used to trigger a transfer when the operating condition and the time condition are met, according to the multiple states and state transition paths in the initial state machine model, a functional feature corresponding to the state is constructed, according to the time condition, a performance feature corresponding to the state is constructed, the updated state machine model is searched and verified, and the functional verification result corresponding to the functional feature and the performance verification result corresponding to the performance feature are determined respectively, on the basis of constructing a state machine model including states and state transition paths based on a state set, the time condition can be further configured in the state transition path to obtain an updated state machine model, and then the functional verification result and the performance verification result can be verified, and the cache strategy is verified from the two dimensions of function and performance, which increases the verification dimension of the cache and improves the accuracy of the cache strategy verification.

[0059] Reference Figure 4 , shows a flowchart of another cache strategy verification method embodiment of the present invention, the method may specifically include the following steps:

[0060] Step 401, constructing an initial state machine model based on a state set cached in the data interaction process; the initial state machine model includes multiple states and state transition paths between states; each state transition path has a corresponding operating condition; the state in the initial state machine model triggers a transition when the corresponding operating condition is achieved;

[0061] Step 402, in the state transition path of the initial state machine model, a time condition is configured to obtain an updated state machine model; the state in the updated state machine model triggers the transition when the corresponding operation condition and time condition are achieved;

[0062] Step 403, constructing functional characteristics corresponding to the states according to the multiple states and state transition paths in the initial state machine model, and constructing performance characteristics corresponding to the states according to the time conditions;

[0063] Step 404: Search and verify the updated state machine model to respectively determine a function verification result corresponding to the function feature and a performance verification result corresponding to the performance feature.

[0064] The contents of steps 401-404 can refer to the above Figure 1 The embodiments are not described in detail here.

[0065] Optionally, the step 402 of configuring a time condition in the state transition path of the initial state machine model to obtain an updated state machine model includes:

[0066] Sub-step 4021, determining a hardware configuration and an operation strategy corresponding to a cache system including the cache;

[0067] Sub-step 4022, determining a target state transition path corresponding to the hardware configuration and the operation strategy according to a correspondence relationship between the preset hardware configuration, the operation strategy and the state transition path;

[0068] Sub-step 4023, configuring a time condition in the target state transition path to obtain an updated state machine model; the time condition defines a size relationship with a preset duration.

[0069] In the embodiment of the present invention, the specific content of the time condition may be determined according to the hardware configuration and operation strategy of the cache system where the cache is located. The hardware configuration may include a cache, a buffer, a register, and a storage structure, and the operation strategy may include merging requests to read together, merging requests to write together, and other operation strategies.

[0070] Among them, there is a hierarchical storage structure in the cache system, such as a cache (Cache)-main memory is a random access memory (RAM) structure. If the data is not in the cache (cache miss), it is necessary to obtain the data from the RAM. Since the cache uses a higher-speed storage medium such as static random access memory (SRAM), and RAM is usually a slower dynamic random access memory (DRAM), the access switch from the cache to the main memory will cause delays. For example, the access speed of the cache may be within a few clock cycles, while the access speed of the main memory is relatively slow and may take dozens of clock cycles.

[0071] Different hardware configurations and operating strategies will cause delays in specific state migration paths. When the cache strategy is designed, the correspondence between the hardware configuration, operating strategy and the affected state migration path can be determined, so that the corresponding target state migration path can be determined based on the current hardware configuration and operating strategy.

[0072] Furthermore, specific time conditions may be set based on the specific conditions of the hardware configuration and operation strategy. For example, if the hardware configuration and operation strategy may cause a large delay, a longer time length may be set in the time condition. Figure 3The clk_l3<=39 corresponding to the state 304 indicates that the stay time in the TTDTTD1 state is less than or equal to 39 time units. The time delay is mainly caused by operation strategies such as table lookup and write-back update state.

[0073] Each time condition may include a preset time length and a size relationship with the preset time length. For example, clk_l3<=39 indicates that it is less than or equal to 39 time units, and clk_l3>=39 indicates that it is greater than or equal to 39 time units.

[0074] In implementing the embodiments of the present invention, by determining the hardware configuration and operating strategy corresponding to the cache system including the cache, determining the target state migration path corresponding to the hardware configuration and operating strategy according to the correspondence between the preset hardware configuration, operating strategy and the state migration path, configuring the time condition in the target state migration path to obtain an updated state machine model, it is possible to determine the target state migration path that will cause delay based on the actual hardware configuration and operating strategy, and set the time condition of the corresponding size, thereby being able to accurately verify the performance of the cache strategy, thereby improving the verification accuracy.

[0075] Optionally, the step 401 of constructing an initial state machine model based on the state set cached in the data interaction process includes:

[0076] Sub-step 4011, determining the target protocol type based on which the cache is used in the data interaction process, and determining the target cache level of the cache in the multi-level cache system; different protocol types correspond to different state sets; different cache levels correspond to different state sets;

[0077] Sub-step 4012, determining a state set of the cache according to the target protocol type and the target cache level, and constructing an initial state machine model based on the state set.

[0078] In the embodiment of the present invention, it can be understood that different cache strategies can be designed based on different consistency protocols to achieve cache consistency (CC, Cache Coherency).

[0079] The cache coherence protocol may include, for example, a coherent hub interface (CHI)-based protocol. CHI is mainly used for data consistency maintenance between multiple caches and main memory in a system on chip (SOC). It is a high-performance, scalable interface protocol suitable for complex system-on-chip architectures such as multi-core processors. CHI specifies the Invalid state, Shared state, Exclusive state, Modified state, and Forward state.

[0080] The cache consistency protocol can also include the MESI protocol, which specifies four states: Modified, Exclusive, Shared, and Invalid. For the open source instruction set architecture of the fifth-generation reduced instruction set computer (RISC-V, Reduced Instruction Set Computer Five), the TileLink protocol can be used.

[0081] In addition, caches at different levels in the cache system, such as the first-level cache L1, the second-level cache L2 or the third-level cache L3, may have different states and state migration paths, so the state machines of caches at different levels may also be different.

[0082] It is necessary to determine the target protocol type that the cache is based on during data interaction, as well as the target cache level in the multi-level cache system, so that the state set of the current cache can be determined and the initial state machine model can be further constructed.

[0083] Optionally, the step 4012 of determining a state set of the cache according to the target protocol type and the target cache level, and constructing an initial state machine model based on the state set includes:

[0084] Step A1, determining a state set corresponding to each cache level in the multi-level cache system according to the target protocol type;

[0085] Step A2, determining a target state set corresponding to the target cache level from the state sets corresponding to each cache level, wherein there is an association relationship between the states in the state set; the states in different state sets and the association relationships between the states are different;

[0086] Step A3: constructing an initial state machine model of the cache according to the multiple states in the target state set and the association relationship between the states.

[0087] In an embodiment of the present invention, after determining the target protocol type currently used to achieve cache consistency, the state sets corresponding to different cache levels can be obtained according to the protocol specification. There is an association relationship between the states in each state set, and the states in different state sets and the association relationships between states are different.

[0088] For example, the association between states can be that in a multi-core processor system, processor A reads data block X in the main memory. At this time, the cache line corresponding to the data block in the cache of processor A changes from an invalid state to an exclusive state, because no other processor has a copy of data block X. If other processors already have a copy of the data, then the cache line that reads the data enters the shared state. For example, processor B reads data block Y in the main memory, and processor C already has a copy of data block Y and is in a shared state. At this time, the cache line corresponding to data block Y in the cache of processor B enters the shared state.

[0089] Furthermore, according to the target state set corresponding to the target cache level and according to the multiple states in the target state set and the association relationship between the states, an initial state machine model of the cache is constructed.

[0090] Optionally, the functional feature includes a deadlock-free feature; the step of searching and verifying the updated state machine model to respectively determine a functional verification result corresponding to the functional feature and a performance verification result corresponding to the performance feature comprises:

[0091] Based on a preset feature verification sequence, searching and verifying the updated state machine model; the feature verification sequence includes functional features and performance features, and the first feature of the feature verification sequence is the deadlock-free feature;

[0092] If it is determined that the updated state machine model does not have the deadlock-free feature, stop searching and verifying other functional features and performance features, and adjust the updated state machine model until the updated state machine model has the deadlock-free feature;

[0093] When it is determined that the updated state machine model has the deadlock-free feature, continue searching and verifying other functional features and performance features, and respectively determine the functional verification results corresponding to the functional features and the performance verification results corresponding to the performance features.

[0094] In the embodiment of the present invention, for the constructed functional features and performance features, a feature verification sequence can be pre-generated, in which each feature is arranged in sequence, and the feature verification sequence can be used to control the feature verification order. Among them, the deadlock-free feature can be used as the first feature to be verified in the feature verification sequence, so that when verifying the cache strategy, the deadlock-free feature is verified first.

[0095] By first verifying the deadlock-free feature, it is possible to determine whether there is a deadlock in the state space. Since the existence of a deadlock indicates that there is a major problem with the cache strategy, even if the verification of other features is passed, it cannot indicate the effectiveness of the cache strategy.

[0096] The deadlock-free feature is verified. When it is determined that the updated state machine model does not have the deadlock-free feature, stop searching and verifying other functional features and performance features, that is, do not continue to verify subsequent features of the feature verification sequence, but adjust the updated state machine model, and then re-verify the deadlock-free feature until the updated state machine model has the deadlock-free feature.

[0097] When adjusting the state machine model, since the problem may exist in the cache strategy itself, it is necessary to adjust the cache strategy first and then rebuild the corresponding state machine model; it may also be that the state machine model does not match the actual cache strategy, or the state machine model is too abstract, in which case the model can be modified directly.

[0098] When it is determined that the updated state machine model has a deadlock-free feature, continue searching and verifying other functional features and performance features, and respectively determine the functional verification results corresponding to the functional features and the performance verification results corresponding to the performance features.

[0099] In the implementation of the embodiment of the present invention, based on the preset feature verification sequence, the update state machine model is searched and verified. When it is determined that the update state machine model does not have the deadlock-free feature, the search and verification of other functional features and performance features are stopped, and the update state machine model is adjusted until the update state machine model has the deadlock-free feature. When it is determined that the update state machine model has the deadlock-free feature, the search and verification of other functional features and performance features continues, and the functional verification results and performance verification results are determined respectively. The core features can be verified first, avoiding the cost of verifying other minor features when there are major problems, and the verification efficiency can be improved.

[0100] Optionally, the step of searching and verifying the updated state machine model to respectively determine a function verification result corresponding to the function feature and a performance verification result corresponding to the performance feature includes:

[0101] Inputting the functional characteristics, the performance characteristics and the updated state machine model into a preset model verification tool; the model verification tool is used to search the state space of the updated state machine model to determine the characteristic compliance of the updated state machine model;

[0102] Acquire the function verification result corresponding to the function feature and the performance verification result corresponding to the performance feature output by the model verification tool.

[0103] In an embodiment of the present invention, functional characteristics, performance characteristics and an updated state machine model may be input into a preset model verification tool, which may include a Simple Promela Interpreter (SPIN), a Process Analysis Toolkit (PAT), a Bounded Model Checker for C and C++ (CBMC) and other model verification tools.

[0104] Model verification tools can use various algorithms to traverse all possible states of the system based on defined models and features. Algorithms may include breadth-first search, depth-first search, symbolic execution, etc. to search the state space. In the process of traversing the state, the model verification tool can check whether the features are satisfied in each state according to the defined features. For a finite state space, if all states are traversed and the features are established in each state, it can be proved that the model meets the given features; if the features are not satisfied in a certain state, the model verification tool can record and generate corresponding counterexamples to locate the problem.

[0105] Among them, when the verification result indicates that some features have not passed, that is, the state machine model not only has the corresponding functions, the state machine model can be adjusted. Similarly, since the problem may exist in the cache strategy itself, the cache strategy can be adjusted first, and then the state machine model can be rebuilt; it may also be that the state machine model and the actual cache strategy do not match, or the state machine model is too abstract, then the model can be modified directly.

[0106] Optionally, the step of constructing functional characteristics corresponding to the states according to the multiple states and state transition paths in the initial state machine model, and constructing performance characteristics corresponding to the states according to the time conditions, includes:

[0107] Acquire function description information and performance description information input by a user, and determine corresponding feature format information according to the model verification tool; wherein there is a mapping relationship between the model verification tool and the feature format information;

[0108] Inputting the function description information, the performance description information and the feature format information into a text parser; the text parser is used to convert the function description information into a function feature and convert the performance description information into a performance feature according to the feature format information;

[0109] The functional characteristics and the performance characteristics output by the text parser are obtained; the formats of the functional characteristics and the performance characteristics correspond to the characteristic format information.

[0110] In an embodiment of the present invention, the features used by a model verification tool such as UPPAAL (an integrated tool) may be mainly written based on computation tree logic (CTL) and linear temporal logic (LTL). Based on these logic languages, various behaviors in the state migration process can be expressed, and the corresponding feature format may be CTL format or LTL format. The features in CTL format may be expressed as "11d_ctl.NTTC3-->11d_ctl.TTD". It may also include state machine attribute format, invariant format, and other formats.

[0111] Therefore, it is necessary to obtain feature format information, which may be determined based on a specific model verification tool type, such as UPPAAL corresponding to CTL format or LTL format.

[0112] The text parser can be used to convert the natural language description information input by the user into a formal language. For some natural language descriptions with clear semantics and relatively simple structures, they can be converted into a formal language through the parser combined with the rule definition, i.e., the feature format information. For example, the logical proposition "If it rains today, the ground will be wet" can be identified by the parser as a conditional relationship and converted into a formal logical expression "Raining > Wet Ground".

[0113] The function description information and performance description information input by the user are converted according to the feature format information through the text parser to obtain the function characteristics and performance characteristics output by the text parser. The model verification tool can directly use the function characteristics and performance characteristics output by the text parser to verify the state machine model.

[0114] The embodiment of the present invention is implemented by obtaining the function description information and performance description information input by the user, and determining the feature format information according to the model verification tool, inputting the function description information, performance description information and feature format information into the text parser, and the text parser is used to convert the description information into the model features in the format corresponding to the feature format information according to the feature format information, and obtaining the function features and performance features output by the text parser. The process of constructing the function features and performance features can be simplified, the time cost of feature construction can be reduced, and the verification efficiency of the cache can be improved.

[0115] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0116] Device Embodiment

[0117] Reference Figure 5 , shows a structural block diagram of a cache strategy verification device of the present invention, the device 50 comprises:

[0118] The initial model module 501 is used to construct an initial state machine model based on the state set cached in the data interaction process; the initial state machine model includes multiple states and state transition paths between states; each state transition path has a corresponding operating condition; the state in the initial state machine model triggers the transition when the corresponding operating condition is achieved;

[0119] An update model module 502, configured to configure a time condition in the state transition path of the initial state machine model to obtain an updated state machine model; the state in the updated state machine model triggers the transition when the corresponding operation condition and time condition are achieved;

[0120] A feature construction module 503 is used to construct functional features corresponding to the states according to the multiple states and state transition paths in the initial state machine model, and to construct performance features corresponding to the states according to the time conditions;

[0121] The feature verification module 504 is used to search and verify the updated state machine model, and respectively determine the function verification results corresponding to the function features and the performance verification results corresponding to the performance features.

[0122] Optionally, update the model module, including:

[0123] An influencing factor submodule, used to determine a hardware configuration and an operation strategy corresponding to a cache system including the cache;

[0124] A target path submodule, used to determine a target state migration path corresponding to the hardware configuration and the operation strategy according to a correspondence relationship between the preset hardware configuration, the operation strategy and the state migration path;

[0125] The time configuration submodule is used to configure the time condition in the target state transition path to obtain an updated state machine model; the time condition defines the size relationship with the preset duration.

[0126] Optional, initial model module, including:

[0127] A type level submodule, used to determine the target protocol type based on which the cache is based during the data interaction process, and to determine the target cache level of the cache in the multi-level cache system; different protocol types correspond to different state sets; different cache levels correspond to different state sets;

[0128] The set determination submodule is used to determine the state set of the cache according to the target protocol type and the target cache level, and to construct an initial state machine model based on the state set.

[0129] Optionally, the set determines the submodules, including:

[0130] A protocol set unit, used to determine a state set corresponding to each cache level in the multi-level cache system according to the target protocol type;

[0131] A level set unit, used to determine a target state set corresponding to the target cache level from the state sets corresponding to the cache levels, wherein there is an association relationship between the states in the state sets; the states in different state sets and the association relationships between the states are different;

[0132] The set construction unit is used to construct the initial state machine model of the cache according to the multiple states in the target state set and the association relationship between the states.

[0133] Optionally, the functional feature includes a deadlock-free feature; and the feature verification module includes:

[0134] A sequence verification submodule, used for searching and verifying the updated state machine model based on a preset feature verification sequence; the feature verification sequence includes functional features and performance features, and the first feature of the feature verification sequence is the deadlock-free feature;

[0135] A verification suspension submodule, configured to stop searching and verifying other functional features and performance features when determining that the update state machine model does not have the deadlock-free feature, and adjust the update state machine model until the update state machine model has the deadlock-free feature;

[0136] The verification continuation submodule is used to continue searching and verifying other functional characteristics and performance characteristics when it is determined that the updated state machine model has the deadlock-free feature, and to respectively determine the functional verification results corresponding to the functional characteristics and the performance verification results corresponding to the performance characteristics.

[0137] Optional, feature verification module, including:

[0138] An information input submodule, used for inputting the functional characteristics, the performance characteristics and the updated state machine model into a preset model verification tool; the model verification tool is used for searching the state space of the updated state machine model to determine the characteristic compliance of the updated state machine model;

[0139] The result acquisition submodule is used to acquire the function verification results corresponding to the function characteristics and the performance verification results corresponding to the performance characteristics output by the model verification tool.

[0140] Optional, feature building blocks, including:

[0141] An information acquisition submodule, used to acquire the function description information and performance description information input by the user, and determine the corresponding feature format information according to the model verification tool; wherein there is a mapping relationship between the model verification tool and the feature format information;

[0142] A data conversion submodule, used for inputting the function description information, the performance description information and the feature format information into a text parser; the text parser is used for converting the function description information into function features and converting the performance description information into performance features according to the feature format information;

[0143] The feature acquisition submodule is used to acquire the functional features and the performance features output by the text parser; the formats of the functional features and the performance features correspond to the feature format information.

[0144] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0145] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0146] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0147] Reference Figure 6 , is a structural block diagram of an electronic device for cache strategy verification provided by an embodiment of the present invention. Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the cache policy verification method of the aforementioned embodiment.

[0148] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor.

[0149] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, and a control bus. For ease of representation, Figure 4 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0150] The memory can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be an EEPROM (Electrically ErasableProgrammable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, and an optical data storage device.

[0151] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 2 The cache policy validation method shown.

[0152] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0153] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0154] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0155] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0156] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable terminal device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0157] Although the preferred embodiments of the present invention are described, those skilled in the art will recognize the basic creative concept and may make other changes and modifications to these embodiments. The appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0158] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0159] The above is a detailed introduction to a cache policy verification method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A cache strategy verification method, characterized in that: The method comprises: Based on the state set cached in the data interaction process, an initial state machine model is constructed; the initial state machine model includes multiple states and state transition paths between states; each state transition path has a corresponding operating condition; the state in the initial state machine model triggers the transition when the corresponding operating condition is achieved; In the state transition path of the initial state machine model, a time condition is configured to obtain an updated state machine model; the state in the updated state machine model triggers the transition when the corresponding operation condition and time condition are achieved; According to the multiple states and state transition paths in the initial state machine model, construct functional characteristics corresponding to the states, and according to the time conditions, construct performance characteristics corresponding to the states; Searching and verifying the updated state machine model, and respectively determining a function verification result corresponding to the function feature and a performance verification result corresponding to the performance feature; The step of configuring a time condition in the state transition path of the initial state machine model to obtain an updated state machine model comprises: Determining a hardware configuration and an operation strategy corresponding to a cache system including the cache; According to the correspondence between the preset hardware configuration, the operation strategy and the state transition path, determining the target state transition path corresponding to the hardware configuration and the operation strategy; A time condition is configured in the target state transition path to obtain an updated state machine model; the time condition defines a size relationship with a preset duration.

2. The method according to claim 1, characterized in that The step of constructing an initial state machine model based on the state set cached in the data interaction process includes: Determine the target protocol type based on which the cache is to be used in the data interaction process, and determine the target cache level of the cache in the multi-level cache system; different protocol types correspond to different state sets; different cache levels correspond to different state sets; According to the target protocol type and the target cache level, a state set of the cache is determined, and an initial state machine model is constructed based on the state set.

3. The method according to claim 2, characterized in that The step of determining the state set of the cache according to the target protocol type and the target cache level, and constructing an initial state machine model based on the state set includes: Determining, according to the target protocol type, a state set corresponding to each cache level in the multi-level cache system; In the state sets corresponding to each cache level, a target state set corresponding to the target cache level is determined; there is an association relationship between the states in the state set; the states in different state sets and the association relationships between the states are different; An initial state machine model of the cache is constructed according to the multiple states in the target state set and the association relationship between the states.

4. The method according to claim 1, characterized in that: The functional features include a deadlock-free feature; The step of searching and verifying the updated state machine model to respectively determine a function verification result corresponding to the function feature and a performance verification result corresponding to the performance feature comprises: Based on a preset feature verification sequence, searching and verifying the updated state machine model; the feature verification sequence includes functional features and performance features, and the first feature of the feature verification sequence is the deadlock-free feature; If it is determined that the updated state machine model does not have the deadlock-free feature, stop searching and verifying other functional features and performance features, and adjust the updated state machine model until the updated state machine model has the deadlock-free feature; When it is determined that the updated state machine model has the deadlock-free feature, continue searching and verifying other functional features and performance features, and respectively determine the functional verification results corresponding to the functional features and the performance verification results corresponding to the performance features.

5. The method according to claim 1, characterized in that The step of searching and verifying the updated state machine model to respectively determine a function verification result corresponding to the function feature and a performance verification result corresponding to the performance feature comprises: Inputting the functional characteristics, the performance characteristics and the updated state machine model into a preset model verification tool; the model verification tool is used to search the state space of the updated state machine model to determine the characteristic compliance of the updated state machine model; Acquire the function verification result corresponding to the function feature and the performance verification result corresponding to the performance feature output by the model verification tool.

6. The method according to claim 5, characterized in that The step of constructing functional features corresponding to the states according to the multiple states and state transition paths in the initial state machine model, and constructing performance features corresponding to the states according to the time conditions, comprises: Acquire function description information and performance description information input by a user, and determine corresponding feature format information according to the model verification tool; wherein there is a mapping relationship between the model verification tool and the feature format information; Inputting the function description information, the performance description information and the feature format information into a text parser; the text parser is used to convert the function description information into a function feature and convert the performance description information into a performance feature according to the feature format information; The functional characteristics and the performance characteristics output by the text parser are obtained; the formats of the functional characteristics and the performance characteristics correspond to the characteristic format information.

7. A cache strategy verification device, characterized in that: The device comprises: An initial model module is used to construct an initial state machine model based on a state set cached in the data interaction process; the initial state machine model includes multiple states and state transition paths between states; each state transition path has a corresponding operating condition; the state in the initial state machine model triggers the transition when the corresponding operating condition is achieved; An update model module, configured to configure a time condition in the state transition path of the initial state machine model to obtain an updated state machine model; the state in the updated state machine model triggers the transition when the corresponding operation condition and time condition are achieved; A feature construction module, used to construct functional features corresponding to the states according to the multiple states and state transition paths in the initial state machine model, and to construct performance features corresponding to the states according to the time conditions; A feature verification module, used to search and verify the updated state machine model, and respectively determine a function verification result corresponding to the function feature and a performance verification result corresponding to the performance feature; The updating model module comprises: An influencing factor submodule, used to determine a hardware configuration and an operation strategy corresponding to a cache system including the cache; A target path submodule, used to determine a target state migration path corresponding to the hardware configuration and the operation strategy according to a correspondence relationship between the preset hardware configuration, the operation strategy and the state migration path; The time configuration submodule is used to configure the time condition in the target state transition path to obtain an updated state machine model; the time condition defines the size relationship with the preset duration.

8. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the cache policy verification method as described in any one of claims 1 to 6.

9. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the cache policy verification method as described in any one of claims 1 to 6.

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