Display substrate, display device and working method

Abstract

The invention provides a display substrate, a display device and a working method. Specifically, the display substrate is characterized by comprising a plurality of pixel driving circuits and a plurality of light-emitting elements connected with the plurality of pixel driving circuits respectively, and the plurality of pixel driving circuits are arranged to drive the plurality of light-emitting elements to emit light. At least one pixel driving circuit comprises a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, a write-in sub-circuit, a driving sub-circuit and a light-emitting sub-circuit. According to the technical scheme, the defect that gray scale display of the display substrate is not uniform is overcome.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display device, and a working method. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device, which is widely used in various electronic devices. It has the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, high response speed, light weight and low cost.

[0003] In the related art, each pixel of an OLED product is independently controlled, and its control circuit includes a thin film transistor (TFT). However, different thin film transistors usually have different characteristics, which inevitably leads to the problem of insufficient display uniformity. Summary of the invention

[0004] In view of this, an object of the present disclosure is to provide a display substrate, a display device and a working method.

[0005] Based on the above purpose, the present disclosure provides a display substrate, comprising a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one pixel driving circuit comprises a first reset subcircuit, a second reset subcircuit, a compensation subcircuit, a writing subcircuit, a driving subcircuit and a light-emitting subcircuit; wherein,

[0006] The first reset subcircuit is connected to the first initial signal line, the fourth node, and the reset signal line, respectively, and is configured to write the first initial signal of the first initial signal line into the fourth node under the control of the reset signal line;

[0007] The second reset subcircuit is connected to the second initial signal line, the reset signal line, and the first node respectively; and is configured to write the second initial signal of the second initial signal line into the first node under the control of the reset signal line; wherein the second initial signal is determined based on the gray scale of the light emitting element;

[0008] The compensation subcircuit is connected to the first power line, the scan signal line, the first node, the third node N3, and the fourth node respectively, and is configured to provide the signal of the third node to the fourth node under the control of the scan signal line;

[0009] The writing subcircuit is connected to the scanning signal line, the data signal line and the second node respectively, and is configured to write the data signal of the data signal line into the second node under the control of the scanning signal line; and couple the signal of the second node to the first node in the data writing phase;

[0010] The driving subcircuit is connected to the first node, the second node and the third node respectively, and is configured to write the data signal of the second node to the third node in the data writing phase, and to provide a driving current to the third node according to the signals of the first node and the second node in the light emitting phase;

[0011] The light-emitting subcircuit is respectively connected to the first power line, the second node, the third node, the first light-emitting signal line, the second light-emitting signal line and the first pole of the light-emitting element, and is configured to write the signal of the first power line into the second node under the control of the first light-emitting signal line, and write the signal of the third node into the first pole of the light-emitting element under the control of the second light-emitting signal line.

[0012] Based on the same inventive concept, an embodiment of the present disclosure further provides a working method of a display substrate, wherein the display substrate comprises a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one pixel driving circuit comprises a first reset subcircuit, a compensation subcircuit, a write subcircuit, a second reset subcircuit, a driving subcircuit and a light-emitting subcircuit, and the working method of the display substrate comprises:

[0013] Under the control of the reset signal line, the first reset subcircuit writes the first initial signal of the first initial signal line into the fourth node;

[0014] Under the control of the reset signal line, the second reset subcircuit provides a second initial signal of the second initial signal line to the first node; wherein the second initial signal is determined based on the gray scale of the light emitting element;

[0015] Under the control of the scanning signal line, the writing subcircuit writes the data signal of the data signal line into the second node; in the data writing phase, the signal of the second node is coupled to the first node;

[0016] The driving subcircuit provides a driving current to a third node according to signals of the first node and the second node;

[0017] Under the control of the first light-emitting signal line, the light-emitting subcircuit writes the signal of the first power line into the second node, and under the control of the second light-emitting signal line, the light-emitting subcircuit writes the signal of the third node into the first pole of the light-emitting element.

[0018] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, comprising any one of the display substrates described above.

[0019] From the above description, it can be seen that the present disclosure provides a display substrate, a display device and a working method, wherein the display substrate includes multiple pixel driving circuits, and at least one pixel driving circuit writes a second initial signal of a second initial signal line into the first node through a second reset subcircuit during a reset phase; wherein the second initial signal is determined based on the grayscale of the light-emitting element, so that the signal after the first node is coupled with the data signal is adjusted with the grayscale of the light-emitting element, which helps to improve the defect of uneven grayscale display of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic structural diagram of a display substrate is shown;

[0022] Figure 2 A schematic diagram of a planar structure of a display substrate is shown;

[0023] Figure 3 A schematic cross-sectional structure diagram of a display substrate is shown;

[0024] Figure 4A A schematic diagram of an equivalent circuit of a pixel driving circuit is shown;

[0025] Figure 4B Show Figure 4A Working diagram of the equivalent circuit in the reset phase;

[0026] Figure 4C Show Figure 4A Working diagram of the equivalent circuit in the data writing stage;

[0027] Figure 4D Show Figure 4A Working diagram of the equivalent circuit in the light-emitting stage;

[0028] Figure 5A shows the Id-Vg curve of low temperature polysilicon type TFT;

[0029] Figure 5B Schematic diagram showing the deviation of Vgs of different TFTs at different currents;

[0030] Fig. 6AA schematic diagram showing the structure of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure is shown;

[0031] Figure 6B A schematic diagram showing an equivalent circuit of a pixel driving circuit provided by an embodiment of the present disclosure is shown;

[0032] Figure 6C A schematic diagram showing a top view of a pixel driving circuit provided in an embodiment of the present disclosure is shown;

[0033] Figure 7 A working timing diagram of a display substrate provided by an embodiment of the present disclosure is shown;

[0034] Fig. 8A A working diagram of an equivalent circuit provided by an embodiment of the present disclosure in a reset phase is shown;

[0035] Figure 8B A working diagram of an equivalent circuit provided by an embodiment of the present disclosure during a data writing phase is shown;

[0036] Figure 8C The working diagram of the equivalent circuit provided by the embodiment of the present disclosure in the light-emitting stage is shown. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0038] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes a state where the angle is greater than 85° and less than 95°. "Film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0039] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in the present disclosure, the channel region refers to a region through which current mainly flows.

[0040] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged. In the embodiments of the present disclosure, the gate electrode may be referred to as a control electrode.

[0041] Figure 1 FIG. 2 shows a schematic diagram of the structure of a display substrate. Figure 1As shown, the display substrate 100 may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver and a pixel array, and the timing controller is connected to the data signal driver, the scan signal driver and the light emitting signal driver respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), and the light emitting signal driver is connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels P xij , i and j can be natural numbers, at least one sub-pixel P xij A circuit unit and a light-emitting device connected to the circuit unit may be included, and the circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data signal driver to the data signal driver, a clock signal suitable for the specifications of the scan signal driver, a scan start signal, etc. may be provided to the scan signal driver, and a clock signal suitable for the specifications of the light-emitting signal driver, an emission stop signal, etc. may be provided to the light-emitting signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal, and m may be a natural number. The light-emitting signal driver may generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting signal driver may sequentially provide an emission signal having an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner that sequentially transmits an emission stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal, and o may be a natural number.

[0042] Figure 2 FIG. 1 shows a schematic diagram of a planar structure of a display substrate. Figure 2 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0043] In an exemplary embodiment, a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel may be included in the pixel unit P. The present disclosure does not limit the shape and arrangement of the sub-pixels in the pixel unit.

[0044] Figure 3 A schematic cross-sectional structure diagram of a display substrate is shown. Figure 3 The structure of three sub-pixels of an OLED display substrate is shown in FIG. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 302 disposed on a substrate 301, and a light emitting structure layer 303 and an encapsulation layer 304 disposed sequentially on a side of the driving circuit layer 302 away from the substrate 301. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.

[0045] In some embodiments, the substrate 301 may be a flexible substrate, or may be a rigid substrate, which is not limited in the present disclosure. The driving circuit layer 302 of each sub-pixel may include a plurality of transistors (e.g., 3021) and a storage capacitor constituting a pixel driving circuit. The light-emitting structure layer 303 may include an anode 3031, a pixel definition layer 3034, an organic light-emitting layer 3032, and a cathode 3033, wherein the anode 3031 is connected to the drain electrode of the driving transistor 3021 through a via, the organic light-emitting layer 3032 is connected to the anode 3031, and the cathode 3033 is connected to the organic light-emitting layer 3032, and the organic light-emitting layer 3032 emits light of corresponding colors under the drive of the anode 3031 and the cathode 3033. The encapsulation layer 304 may include a plurality of stacked encapsulation layers, such as a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The encapsulation layer 304 can ensure that external water vapor cannot enter the light-emitting structure layer 303, thereby ensuring the performance and service life of the display substrate.

[0046] In some embodiments, the organic light-emitting layer 3032 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL).

[0047] In some embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4A FIG. 1 shows an equivalent circuit diagram of a pixel driving circuit. Figure 4AAs shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C1, and the pixel driving circuit may be connected to 7 signal lines (data signal line Vdata, reset signal line Reset, scan signal line Gate, light emitting signal line EM, initial signal line Initial, first power line Vdd and second power line Vss). Here, the data signal line Vdata may be selected from one or more of the aforementioned D1, D2...Dn; the reset signal line Reset and the scan signal line Gate are independently selected from one or more of the aforementioned S1, S2...Sm; the light emitting signal line EM is selected from one or more of the aforementioned E1, E2...Eo. It should be understood that the 7 signal lines of different sub-pixels may specifically correspond to different signal lines, for example, the data signal line Vdata corresponding to some sub-pixels is D1, and the data signal line Vdata corresponding to some sub-pixels is D2; the reset signal line Reset corresponding to some sub-pixels is S2, and the reset signal line Reset corresponding to some sub-pixels is S3, which are not listed again.

[0048] Exemplarily, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the first node N1 is respectively connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C1, and the third node N3 is respectively connected to the first electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0049] Further, a first end of the storage capacitor C1 is connected to the first power line Vdd, and a second end of the storage capacitor C1 is connected to the first node N1, that is, the second end of the storage capacitor C1 is connected to the control electrode of the third transistor T3.

[0050] Further, the control electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the initial signal line Initial, and the second electrode of the first transistor is connected to the first node N1. When the on-level scanning signal is applied to the reset signal line Reset, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0051] Further, the control electrode of the second transistor T2 is connected to the scanning signal line Gate, the second electrode of the second transistor T2 is connected to the first node N1, and the first electrode of the second transistor T2 is connected to the third node N3. When the on-level scanning signal is applied to the scanning signal line Gate, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0052] Further, the control electrode of the third transistor T3 is connected to the first node N1, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line Vdd and the second power line Vss according to the potential difference between its control electrode and the first electrode.

[0053] Further, the control electrode of the fourth transistor T4 is connected to the scanning signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Vdata, and the second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be called a switching transistor, a scanning transistor, etc. When the on-level scanning signal is applied to the scanning signal line Gate, the fourth transistor T4 inputs the data voltage of the data signal line Vdata into the pixel driving circuit.

[0054] Further, the control electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line Vdd, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line EM, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line Vdd and the second power line Vss to make the light emitting device emit light.

[0055] Further, the control electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the initial signal line Initial, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scanning signal is applied to the reset signal line Reset, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize the charge accumulated in the first electrode of the light emitting device or release the charge accumulated in the first electrode of the light emitting device.

[0056] In some embodiments, the second electrode of the light emitting device is connected to the second power line Vss, the signal of the second power line Vss is a low level signal, and the signal of the first power line Vdd is a continuously provided high level signal.

[0057] Optionally, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some alternative embodiments, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0058] In some embodiments, the light emitting device may be an organic light emitting diode (OLED), including a stacked first electrode (corresponding to an anode), an organic light emitting layer, and a second electrode (corresponding to a cathode).

[0059] Below through Figure 4A The operation process of the exemplary pixel driving circuit is described in detail. Figure 4A The pixel driving circuit includes 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C1 and 7 signal lines (data signal line Vdata, reset signal line Reset, scan signal line Gate, light emitting signal line EM, initial signal line Initial, first power line Vdd and second power line Vss), and all 7 transistors are N-type transistors.

[0060] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0061] like Figure 4B As shown, in the first stage, called the reset stage, the first transistor T1 is turned on, and the signal of the initial signal line Initial is provided to the first node N1 to initialize the storage capacitor C1 and clear the original data voltage in the storage capacitor. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.

[0062] like Figure 4CAs shown, the second stage is called the data writing stage or the threshold compensation stage. The fourth transistor T4, the third transistor T3, and the second transistor T2 are turned on, and the data signal line Vdata outputs the data voltage. The data voltage output by the data signal line Vdata is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage (Vd) output by the data signal line Vdata and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1. The voltage at the second end (first node N1) of the storage capacitor C1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Vdata, and Vth is the threshold voltage of the third transistor T3.

[0063] like Figure 4D As shown, in the third stage, called the light-emitting stage, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage Vdd output by the first power line Vdd provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0064] The third transistor T3 is subjected to Vth compensation so that the pixel gate voltage is set to Vd-|Vth|. According to the current formula, the driving current of the third transistor T3 is I∝[(Vdd-Vd)] 2 , ensuring that the current between pixels is not affected by Vth, achieving the technical effect of improving display uniformity.

[0065] However, Vd is usually short in the writing phase, and the writing current decreases when Vgs>Vth, so the Vth usually compensated at 60Hz (in a pixel circuit with a writing time of 5-6μs) is about the Vgs corresponding to the TFT when I≈1nA. Here, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0066] Figure 5A The Id-Vg curve of the low temperature polysilicon (LTPS) TFT is shown; Figure 5B Schematic diagram showing the deviation of Vgs of different TFTs under different currents. Figure 5A As shown, the driving current 501 of the third transistor T3 corresponding to grayscale 255 is about 1nA, while the driving current 501' of the third transistor T3 corresponding to grayscale 0-5 is about 1pA. In other words, for different grayscales, the driving current of the third transistor T3 is significantly different, resulting in different corresponding Vgs. Figure 5BAs shown, the Id-Vg curves of the two third transistors T3 are shown, which are 502 and 502'. Considering that the initial signal of the initial signal line Initial is a constant value, the corresponding compensation current is I (in the related art, the compensation current can be 1nA), the driving current is close to I under high grayscale, the difference between the driving current and the compensation current of the two third transistors T3 is small, and the Vgs corresponding to the compensation current is close to the Vgs corresponding to the driving current, which can have good uniformity; however, the driving current is II (for example, 1pA) under low grayscale, and the difference between the driving current (1pA) and the compensation current (1nA) of the third transistor T3 is large. Under the control of the initial signal of the initial signal line Initial, the difference between the compensated Vgs and the driving Vgs is large. Since the slopes of the two Id-Vg curves (502 and 502') are different, the deviation between the two third transistors T3 is different, so it is difficult to ensure grayscale uniformity.

[0067] In view of this, an embodiment of the present disclosure provides a display substrate, which includes multiple pixel driving circuits, at least one pixel driving circuit writes a second initial signal of a second initial signal line into the first node through a second reset sub-circuit during a reset phase; wherein the second initial signal is determined based on the grayscale of the light-emitting element, so that the signal after the first node is coupled with the data signal is adjusted with the grayscale of the light-emitting element, which helps to improve the defect of uneven grayscale display of the display substrate.

[0068] Fig. 6A The schematic diagram of the structure of the pixel driving circuit in the display substrate provided by the embodiment of the present disclosure is shown. The display substrate may include multiple pixel driving circuits and multiple light-emitting elements (such as OLED) respectively connected to the multiple pixel driving circuits, and the multiple pixel driving circuits are configured to drive the multiple light-emitting elements to emit light. Fig. 6A As shown, at least one pixel driving circuit includes a first reset subcircuit 601 , a second reset subcircuit 602 , a compensation subcircuit 603 , a writing subcircuit 604 , a driving subcircuit 605 and a light emitting subcircuit 606 .

[0069] The first reset sub-circuit 601 is respectively connected to the first initial signal line Initial 1, the fourth node N4, and the reset signal line Reset, and is configured to write the first initial signal of the first initial signal line Initial 1 into the fourth node N4 under the control of the reset signal line Reset;

[0070] The second reset subcircuit 602 is connected to the second initial signal line Initial 2, the reset signal line Reset, and the first node N1 respectively; it is configured to write the second initial signal of the second initial signal line Initial 2 into the first node N1 under the control of the reset signal line Reset; wherein the second initial signal is determined based on the gray scale of the light emitting element;

[0071] The compensation sub-circuit 603 is respectively connected to the first power line Vdd, the scan signal line Gate, the first node N1, the third node N3, and the fourth node N4, and is configured to provide the signal of the third node N3 to the fourth node N4 under the control of the scan signal line Gate;

[0072] The writing sub-circuit 604 is connected to the scanning signal line Gate, the data signal line Vdata and the second node N2 respectively, and is configured to write the data signal of the data signal line Vdata into the second node N2 under the control of the scanning signal line Gate; and couple the signal of the second node N2 to the first node N1 in the data writing phase;

[0073] The driving sub-circuit 605 is connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to write the data signal of the second node N2 to the third node N3 in the data writing phase, and to provide a driving current to the third node N3 according to the signals of the first node N1 and the second node N2 in the light emitting phase;

[0074] The light-emitting sub-circuit 606 is respectively connected to the first power line Vdd, the second node N2, the third node N3, the first light-emitting signal line, the second light-emitting signal line and the first pole of the light-emitting element, and is configured to write the signal of the first power line Vdd into the second node N2 under the control of the first light-emitting signal line, and write the signal of the third node N3 into the first pole of the light-emitting element under the control of the second light-emitting signal line.

[0075] It can be seen that the display substrate provided by the embodiment of the present disclosure introduces the second initial signal line Initial2 to pre-charge the first node N1, so that the working interval of T3 is pulled to a lower current state in advance to start data writing. The bootstrap effect of the compensation subcircuit 603 will cause the potential of the first node N1 to change, and finally the voltage of the first node N1 is closer to Vd+Vgs (I=1pA), so that the light-emitting element has better uniformity at low grayscale. In addition, different second initial signals can be written based on different grayscale requirements, so that the voltage of the first node N1 is compensated for the Vgs voltage value that better matches the grayscale. It should be noted that the second initial signal can be determined in the grayscale definition stage of the module, which is not described in detail in the present disclosure.

[0076] Optionally, the scanning signal line Gate can be the scanning signal line in the pixel driving circuit of the current display row, and the reset signal line Reset can be the scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the scanning signal line Gate is S(n), and the reset signal line Reset is S(n-1). The reset signal line Reset of the current display row is the same signal line as the scanning signal line Gate in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0077] It should be noted that the first light-emitting signal line and the second light-emitting signal line may be two different branches of the same light-emitting signal line, which is not limited in the present disclosure.

[0078] Figure 6B FIG. 1 is a schematic diagram showing an equivalent circuit of a pixel driving circuit provided by an embodiment of the present disclosure. Figure 6B As shown, the second reset subcircuit 602 includes an eighth transistor T8; a control electrode of the eighth transistor T8 is connected to the reset signal line Reset, a first electrode of the eighth transistor T8 is connected to the second initial signal line Initial 2, and a second electrode of the eighth transistor T8 is connected to the first node N1.

[0079] In some embodiments, Figure 6B As shown, the compensation sub-circuit 603 includes a second transistor T2, a first capacitor C1 and a second capacitor C2;

[0080] The control electrode of the second transistor T2 is connected to the scanning signal line Gate, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the fourth node N4;

[0081] A first plate of the first capacitor C1 is connected to the first power line Vdd, and a second plate of the first capacitor C1 is connected to the first node N1;

[0082] A first plate of the second capacitor C2 is connected to the first node N1 , and a second plate of the second capacitor C2 is connected to the fourth node N4 .

[0083] In some embodiments, Figure 6B As shown, the writing sub-circuit 604 includes a fourth transistor T4;

[0084] A control electrode of the fourth transistor T4 is connected to the scan signal line Gate, a first electrode of the fourth transistor T4 is connected to the data signal line Vdata, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0085] In some embodiments, Figure 6B As shown, the light emitting sub-circuit 606 includes a fifth transistor T5 and a sixth transistor T6;

[0086] The control electrode of the fifth transistor T5 is connected to the first light emitting signal line, the first electrode of the fifth transistor T5 is connected to the first power line Vdd, and the second electrode of the fifth transistor T5 is connected to the second node N2;

[0087] The control electrode of the sixth transistor T6 is connected to the second light emitting signal line, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element.

[0088] It should be noted that the first luminous signal line and the second luminous signal line can be two signal lines or the same luminous signal line EM, which is not limited in the present disclosure. In other words, the luminous signal line EM can control the fifth transistor T5 and the sixth transistor T6 at the same time.

[0089] In some embodiments, Figure 6B As shown, the first reset sub-circuit 601 includes a first transistor T1;

[0090] A control electrode of the first transistor T1 is connected to the reset signal line Reset, a first electrode of the first transistor T1 is connected to the first initial signal line Initial 1, and a second electrode of the first transistor T1 is connected to the fourth node N4.

[0091] In some embodiments, Figure 6B As shown, the driving sub-circuit 605 includes a third transistor T3;

[0092] A control electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0093] In some embodiments, Fig. 6A As shown, it also includes a third reset subcircuit 607, which is respectively connected to the first initial signal line Initial 1, the reset signal line Reset and the first pole of the light-emitting element, and is configured to write the initial signal of the first initial signal line Initial 1 into the first pole of the light-emitting element under the control of the reset signal line Reset.

[0094] In some embodiments, Figure 6B As shown, the third reset sub-circuit includes a seventh transistor T7;

[0095] A control electrode of the seventh transistor T7 is connected to the reset signal line Reset, a first electrode of the seventh transistor T7 is connected to the first initial signal line Initial 1, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element.

[0096] In some embodiments, Figure 6B As shown, the first reset subcircuit 601 includes a first transistor T1; the compensation subcircuit 603 includes a second transistor T2, a first capacitor C1 and a second capacitor C2; the driving subcircuit 605 includes a third transistor T3; the writing subcircuit 604 includes a fourth transistor T4; the light emitting subcircuit 606 includes a fifth transistor T5 and a sixth transistor T6; the third reset subcircuit includes a seventh transistor T7; the second reset subcircuit 602 includes an eighth transistor T8;

[0097] A control electrode of the first transistor T1 is connected to a reset signal line Reset, a first electrode of the first transistor T1 is connected to a first initial signal line Initial 1, and a second electrode of the first transistor T1 is connected to a fourth node N4;

[0098] The control electrode of the second transistor T2 is connected to the scanning signal line Gate, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the fourth node N4;

[0099] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3;

[0100] A control electrode of the fourth transistor T4 is connected to the scan signal line Gate, a first electrode of the fourth transistor T4 is connected to the data signal line Vdata, and a second electrode of the fourth transistor T4 is connected to the second node N2;

[0101] A first electrode of the fifth transistor T5 is connected to the first power line Vdd, and a second electrode of the fifth transistor T5 is connected to the second node N2;

[0102] The control electrode of the sixth transistor T6 is connected to the second light emitting signal line, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element;

[0103] The control electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the first initial signal line Initial 1, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element;

[0104] The control electrode of the eighth transistor T8 is connected to the reset signal line Reset, the first electrode of the eighth transistor T8 is connected to the second initial signal line Initial 2, and the second electrode of the eighth transistor T8 is connected to the first node N1;

[0105] A first plate of the first capacitor C1 is connected to the first power line Vdd, and a second plate of the first capacitor C1 is connected to the first node N1;

[0106] A first plate of the second capacitor C2 is connected to the first node N1 , and a second plate of the second capacitor C2 is connected to the fourth node N4 .

[0107] In some embodiments, the first to eighth transistors T1 to T8 are low temperature polysilicon transistors.

[0108] Figure 6C FIG. 1 is a schematic diagram showing a top view of a pixel driving circuit provided by an embodiment of the present disclosure. Figure 6C It can be seen that the scanning signal line Gate, the reset signal line Reset, the luminous signal line EM and the first initial signal line Initial 1 and the second initial signal line Initial 2 extend in the horizontal direction, and the first power line Vdd and the second power line Vss ( Figure 6C The first initial signal line Initial 1 and the second initial signal line Initial 2 can be arranged in the same layer as the first gate layer 701; the scanning signal line Gate, the reset signal line Reset, and the light emitting signal line EM can be arranged in the same layer as the second gate layer 702; the first power line Vdd can be arranged in the same layer as the first source and drain layer 703; the data signal line Vdata can be arranged in the same layer as the second source and drain layer 704; the active layer 705 can be arranged separately; and the through-hole column 706 can be used to realize the conductive connection between different layers.

[0109] Figure 7 FIG. 1 shows a working timing diagram of a display substrate provided by an embodiment of the present disclosure, wherein the structure of the display substrate is as follows: Figure 6B As shown, all eight transistors are P-type transistors. Fig. 8A A working diagram of an equivalent circuit provided by an embodiment of the present disclosure in a reset phase is shown; Figure 8B A working diagram of an equivalent circuit provided by an embodiment of the present disclosure during a data writing phase is shown; Figure 8C FIG. 2 shows a working diagram of the equivalent circuit provided by the embodiment of the present disclosure in the light-emitting stage. Figure 7 and Figure 8A to Figure 8C As shown, the working process of the display substrate may include a first stage A1, a second stage A2 and a third stage A3.

[0110] The first stage A1: It can be called the reset stage or the initialization stage. The signals of the luminous signal line EM and the scanning signal line Gate are at a high level, and the signal of the reset signal line Reset is at a low level. Fig. 8AAs shown, since the reset signal line Reset is at a low level, the first transistor T1, the seventh transistor T7 and the eighth transistor T8 are turned on, and the initial voltage V1 output by the first initial signal line Initial 1 is provided to the fourth node N4 through the first transistor T1, and the fourth node N4 is at a low level (the initial voltage V1 output by the first initial signal line Initial 1, for example, V1 = Vss = -3V); the initial voltage V1 output by the first initial signal line Initial 1 is also provided to the first electrode of the light-emitting element through the seventh transistor T1. The initial voltage V2 output by the second initial signal line Initial 2 is provided to the first node N1 through the eighth transistor T8. Reference Figure 5A and Figure 5B Since the working Vgs of the driving circuit is different at different grayscales, and the slopes of the Id-Vg curves of different pixels are different, different Initial 2s need to be used at different grayscales to obtain more accurate compensation for pixels at different grayscales. The initial voltage V2 output by the second initial signal line Initial 2 depends on the grayscale corresponding to the light-emitting element, and the corresponding relationship between the initial voltage V2 and the grayscale can be determined in the grayscale definition stage. Figure 7 As shown, the initial voltage V2 output by the second initial signal line Initial 2 is higher at low grayscale than at high grayscale, so as to have a higher Vgs at low grayscale after supplementation, which is suitable for a lower operating current, such as 1pA. Since the signals of the luminous signal line EM and the scanning signal line Gate are at a high level, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are disconnected, and the data voltage output by the data signal line Vdata cannot be written into the second node N2 via the fourth transistor T4; the signal of the first power line Vdd cannot provide a driving voltage to the first electrode of the OLED via the fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the OLED does not emit light at this stage.

[0111] The second stage A2: can be called the data writing stage or the compensation stage, the signals of the luminous signal line EM and the reset signal line Reset are at a high level, and the signal of the scanning signal line Gate is at a low level. Figure 8BAs shown, since the signal of the scanning signal line Gate is at a low level, the fourth transistor T4 and the second transistor T2 are turned on. Considering that the initial voltage V2 is input to the first node N1, in order to ensure that the third transistor T3 is turned on, the data voltage Vdata output by the data signal line data can be appropriately increased. Exemplarily, Vdd = 4.6V, Vss = -3V, taking the picture with a grayscale of 3 as an example, the normal data voltage Vdata can be 3V, and the increased data voltage Vdata can be ~6-7V, thereby turning on the third transistor T3, and since the Vds of the third transistor T3 is 9-10V, the larger Vds can ensure the normal flow of current between the N2-N4 nodes. The data voltage Vdata output by the data signal line data is written into the second node N2 via the fourth transistor T4, and the potential of the second node N2 becomes the data voltage Vdata, and then affects the fourth node N4 via the third transistor T3 and the fourth transistor T4, and the voltage of the fourth node N4 rises. Based on the bootstrap effect of the second capacitor C2, the voltage of the first node N1 increases with the voltage of the fourth node N4, until N1-N2<Vgs, and finally the voltage of the first node N1=Vdata+Vgs. Here, the initial voltage V2 output by the second initial signal line Initial 2 determines Vgs. If the initial voltage V2 is based on a low grayscale setting, Vgs corresponds to Vgs at a low grayscale operating current of 1pA. If the initial voltage V2 is based on a high grayscale setting, Vgs corresponds to Vgs at a high grayscale operating current of 1nA. Combined with Figure 5A The Vgs corresponding to the low grayscale working current is greater than the Vgs corresponding to the high grayscale working current. Therefore, the voltage of the first node N1 is greater than the voltage at the high grayscale at the low grayscale, which helps to make the Vgs compensated for each pixel in the low grayscale picture more accurate and more in line with the working voltage requirements, so that each pixel has better uniformity during the light-emitting stage.

[0112] Since the signals of the light emitting signal line EM and the reset signal line Reset are at high level, the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. Since the fifth transistor T5 and the sixth transistor T6 are turned off, the signal of the first power line Vdd cannot provide a driving voltage to the first electrode of the OLED via the fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the OLED does not emit light at this stage.

[0113] The third stage A3: can be called the light-emitting stage, the signals of the scanning signal line Gate and the reset signal line Reset are at a high level, and the signal of the light-emitting signal line EM is at a low level. Figure 8CAs shown, the signal of the reset signal line Reset is at a high level, and the eighth transistor T8 is turned off. Since the signal of the luminous signal line EM is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first power supply voltage Vdd output by the first power supply line Vdd provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0114] Based on the same inventive concept, corresponding to any of the above embodiments, the present disclosure also provides a working method of a display substrate. Fig. 6A The implemented display substrate includes a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, at least one pixel driving circuit includes a first reset subcircuit 601, a compensation subcircuit 603, a writing subcircuit 604, a second reset subcircuit 602, a driving subcircuit 605 and a light-emitting subcircuit 606, and the working method of the display substrate includes:

[0115] Under the control of the reset signal line Reset, the first reset sub-circuit 601 writes the first initial signal (eg, initial voltage V1) of the first initial signal line Initial1 into the fourth node;

[0116] Under the control of the reset signal line Reset, the second reset sub-circuit 602 provides a second initial signal of the second initial signal line Initial2 to the first node N1; wherein the second initial signal is determined based on the gray scale of the light emitting element;

[0117] Under the control of the scan signal line Gate, the write sub-circuit 604 writes the data signal of the data signal line Vdata into the second node N2; in the data writing phase, the signal of the second node N2 is coupled to the first node N1;

[0118] According to the signals of the first node N1 and the second node N2, the driving sub-circuit 605 provides a driving current to the third node N3;

[0119] Under the control of the first light-emitting signal line, the light-emitting subcircuit 606 writes the signal of the first power line Vdd into the second node N2, and under the control of the second light-emitting signal line, the light-emitting subcircuit writes the signal of the third node N3 into the first electrode of the light-emitting element. It should be noted that the first light-emitting signal line and the second light-emitting signal line can be the same light-emitting signal EM.

[0120] In some embodiments, the pixel driving circuit further includes a third resetting subcircuit 607; and the working method further includes:

[0121] Under the control of the reset signal line Reset, the third reset sub-circuit 607 writes the first initial signal (eg, V1 ) of the first initial signal line Initial1 into the first electrode of the light emitting element.

[0122] The working method of the above embodiment is applied to the corresponding display substrate in any of the above embodiments, and has the beneficial effects of the corresponding display substrate embodiment, which will not be described in detail here.

[0123] Based on the same inventive concept, corresponding to the display substrate of any of the above embodiments, an embodiment of the present disclosure further provides a display device, comprising any of the above display substrates.

[0124] The device of the above embodiment includes a display substrate for realizing the corresponding display substrate in any of the above embodiments, and has the beneficial effects of the corresponding display substrate embodiment, which will not be described in detail here.

[0125] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0126] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: It includes a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one pixel driving circuit includes a first reset subcircuit, a second reset subcircuit, a compensation subcircuit, a writing subcircuit, a driving subcircuit and a light-emitting subcircuit; wherein, The first reset subcircuit is connected to the first initial signal line, the fourth node, and the reset signal line, respectively, and is configured to write the first initial signal of the first initial signal line into the fourth node under the control of the reset signal line; The second reset subcircuit is connected to the second initial signal line, the reset signal line, and the first node respectively; and is configured to write the second initial signal of the second initial signal line into the first node under the control of the reset signal line; wherein the second initial signal is determined based on the gray scale of the light emitting element; The compensation subcircuit is connected to the first power line, the scan signal line, the first node, the third node N3, and the fourth node respectively, and is configured to provide the signal of the third node to the fourth node under the control of the scan signal line; The writing subcircuit is connected to the scanning signal line, the data signal line and the second node respectively, and is configured to write the data signal of the data signal line into the second node under the control of the scanning signal line; and couple the signal of the second node to the first node in the data writing phase; The driving subcircuit is connected to the first node, the second node and the third node respectively, and is configured to write the data signal of the second node to the third node in the data writing phase, and to provide a driving current to the third node according to the signals of the first node and the second node in the light emitting phase; The light-emitting subcircuit is respectively connected to the first power line, the second node, the third node, the first light-emitting signal line, the second light-emitting signal line and the first pole of the light-emitting element, and is configured to write the signal of the first power line into the second node under the control of the first light-emitting signal line, and write the signal of the third node into the first pole of the light-emitting element under the control of the second light-emitting signal line.

2. The display substrate according to claim 1, characterized in that: The second reset subcircuit comprises an eighth transistor; A control electrode of the eighth transistor is connected to the reset signal line, a first electrode of the eighth transistor is connected to the second initial signal line, and a second electrode of the eighth transistor is connected to the first node.

3. The display substrate according to claim 1, characterized in that: The compensation subcircuit includes a second transistor, a first capacitor and a second capacitor; The control electrode of the second transistor is connected to the scanning signal line, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the fourth node; The first plate of the first capacitor is connected to the first power line, and the second plate of the first capacitor is connected to the first node; The first plate of the second capacitor is connected to the first node, and the second plate of the second capacitor is connected to the fourth node.

4. The display substrate according to claim 1, characterized in that: The writing subcircuit includes a fourth transistor; A control electrode of the fourth transistor is connected to the scanning signal line, a first electrode of the fourth transistor is connected to the data signal line, and a second electrode of the fourth transistor is connected to the second node.

5. The display substrate according to claim 1, characterized in that: The light emitting subcircuit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected to the first light emitting signal line, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the second node; The control electrode of the sixth transistor is connected to the second light emitting signal line, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the first electrode of the light emitting element.

6. The display substrate according to claim 1, characterized in that: The first reset subcircuit includes a first transistor; A control electrode of the first transistor is connected to the reset signal line, a first electrode of the first transistor is connected to the first initial signal line, and a second electrode of the first transistor is connected to the fourth node.

7. The display substrate according to claim 1, characterized in that: The driving subcircuit includes a third transistor; A control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node.

8. The display substrate according to claim 1, characterized in that: It also includes a third reset subcircuit, which is respectively connected to the first initial signal line, the reset signal line and the first pole of the light-emitting element, and is configured to write the initial signal of the first initial signal line into the first pole of the light-emitting element under the control of the reset signal line.

9. The display substrate according to claim 8, characterized in that: The third reset subcircuit includes a seventh transistor; The control electrode of the seventh transistor is connected to the reset signal line, the first electrode of the seventh transistor is connected to the first initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light emitting element.

10. The display substrate according to claim 8, characterized in that: The first reset subcircuit includes a first transistor; the compensation subcircuit includes a second transistor, a first capacitor and a second capacitor; the drive subcircuit includes a third transistor; the write subcircuit includes a fourth transistor; the light emitting subcircuit includes a fifth transistor and a sixth transistor; the third reset subcircuit includes a seventh transistor; and the second reset subcircuit includes an eighth transistor; The control electrode of the first transistor is connected to the reset signal line, the first electrode of the first transistor is connected to the first initial signal line, and the second electrode of the first transistor is connected to the fourth node; The control electrode of the second transistor is connected to the reset signal line, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the fourth node; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; The control electrode of the fourth transistor is connected to the scanning signal line, the first electrode of the fourth transistor is connected to the data signal line, and the second electrode of the fourth transistor is connected to the second node; A first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the second node; The control electrode of the sixth transistor is connected to the second light emitting signal line, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the first electrode of the light emitting element; The control electrode of the seventh transistor is connected to the reset signal line, the first electrode of the seventh transistor is connected to the first initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light emitting element; The control electrode of the eighth transistor is connected to the reset signal line, the first electrode of the eighth transistor is connected to the second initial signal line, and the second electrode of the eighth transistor is connected to the first node; The first plate of the first capacitor is connected to the first power line, and the second plate of the first capacitor is connected to the first node; The first plate of the second capacitor is connected to the first node, and the second plate of the second capacitor is connected to the fourth node.

11. The display substrate according to claim 10, characterized in that: The first to eighth transistors are low temperature polysilicon transistors.

12. A method for operating a display substrate, characterized in that: The display substrate comprises a plurality of pixel driving circuits and a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, the plurality of pixel driving circuits being configured to drive the plurality of light emitting elements to emit light, at least one pixel driving circuit comprising a first resetting subcircuit, a compensation subcircuit, a writing subcircuit, a second resetting subcircuit, a driving subcircuit and a light emitting subcircuit, and the working method of the display substrate comprises: Under the control of the reset signal line, the first reset subcircuit writes the first initial signal of the first initial signal line into the fourth node; Under the control of the reset signal line, the second reset subcircuit provides a second initial signal of the second initial signal line to the first node; wherein the second initial signal is determined based on the gray scale of the light emitting element; Under the control of the scanning signal line, the writing subcircuit writes the data signal of the data signal line into the second node; in the data writing phase, the signal of the second node is coupled to the first node; The driving subcircuit provides a driving current to a third node according to signals of the first node and the second node; Under the control of the first light-emitting signal line, the light-emitting subcircuit writes the signal of the first power line into the second node, and under the control of the second light-emitting signal line, the light-emitting subcircuit writes the signal of the third node into the first pole of the light-emitting element.

13. The working method according to claim 12, characterized in that: The pixel driving circuit further includes a third resetting subcircuit; and the working method further includes: Under the control of the reset signal line, the third reset subcircuit writes the first initial signal of the first initial signal line into the first electrode of the light emitting element.

14. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 11.

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