Signal processing method and related equipment based on memristor array

Abstract

This application provides one or more embodiments of a signal processing method and related device based on a memristor array. The method includes: mapping an input signal to an input voltage signal, and inputting the input voltage signal to the mapped memristor array; the mapped memristor array obtaining an output current based on the input voltage signal; wherein the mapped memristor array is obtained through the following steps: determining the discrete Fourier transform expression X = W for the signal conversion. N x, where x represents the input signal, X represents the output signal, and W N The rotation factor is represented; it is converted into a complex matrix-vector multiplication expression; Re() represents the real part of the complex number, and Im() represents the imaginary part of the complex number; the operation matrix is ​​mapped to the memristor array to obtain the mapped memristor array. This application can improve the computational efficiency of the DFT or IDFT module and further improve the efficiency of signal processing.

Description

Technical Field

[0001] One or more embodiments of this application relate to the field of signal analysis and signal processing technology, and in particular to a signal processing method and related equipment based on memristor arrays. Background Technology

[0002] With the introduction of massive MIMO and the increase in RF bandwidth, the energy efficiency of baseband signal processing has become one of the key challenges in 5G / 6G systems. Orthogonal Frequency Division Multiplexing (OFDM) technology is an important component of the physical layer, a standard modulation choice for 5G NR systems, and will continue to be used in 6G. In OFDM, the Discrete Fourier Transform (DFT) is the most resource-intensive module because it needs to continuously process the entire operating frequency band. Currently, 5G bandwidth has reached 400MHz, and the bandwidth will be even higher in future 6G. The complexity and high computational latency of DFT have become major limiting factors for the development of high-speed, low-latency communication.

[0003] The Fast Fourier Transform (FFT), as an efficient algorithm for the Distributed Fourier Transform (DFT), significantly improves computation speed. However, with the increase in the number of computation points, the implementation of the Cooley-Tukey algorithm, one of the most commonly used methods in FFT, faces scalability challenges. Although related technologies propose using hardware acceleration platforms (such as graphics processing units, FPGAs, and field-programmable gate arrays) to accelerate FFT computation, these platforms may also introduce energy consumption and latency issues during computation. Summary of the Invention

[0004] In view of this, the purpose of one or more embodiments of this application is to provide a signal processing method and related device based on a memristor array to solve the problems in the background art.

[0005] To achieve the above objectives, one or more embodiments of this application provide a signal processing method based on a memristor array, including:

[0006] The input signal is mapped to an input voltage signal, and the input voltage signal is input to the mapped memristor array;

[0007] The mapped memristor array obtains the output current based on the input voltage signal;

[0008] The mapped memristor array is obtained through the following steps:

[0009] Determine the discrete Fourier transform expression for signal conversion: X = W N x, where x represents the input signal, X represents the output signal, and W N Indicates the rotation factor;

[0010] Convert it into a complex matrix-vector multiplication expression;

[0011]

[0012] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0013] Operation matrix The mapped memristor array is obtained by mapping the mapped memristor array.

[0014] Optionally, the operation matrix G X Mapping to the memristor array includes:

[0015] According to the operation matrix The calculated value of the element is obtained by calculating the conductance of the memristor in the memristor array using the following formula;

[0016]

[0017] Where B represents the conductance array of the memristor array, and λ1 represents the scaling factor used to map the operation matrix to the memristor conductance range. Φ represents the movement matrix, used to indicate the movement distance of each element in the operation matrix. B max and B min G represents the conductance range of the memristors in the memristor array. max and G min This represents the maximum and minimum element values ​​of the operation matrix.

[0018] Optionally, the input signal may include a time-domain signal or a frequency-domain signal.

[0019] Optionally, mapping the input signal to an input voltage signal includes:

[0020] Based on the input signal, the input voltage signal is obtained using the following formula;

[0021]

[0022] Where x represents the input signal, λ2 represents the mapping scaling factor, and N represents the numerical range of the input signal.

[0023] Optionally, the mapped memristor array obtains the output current based on the input voltage signal, including:

[0024] The mapped memristor array obtains the output current based on the input voltage signal using the following formula;

[0025]

[0026] Optionally, mapping the input signal to an input voltage signal includes:

[0027] Based on the input signal, the input voltage signal is obtained using the following formula;

[0028] V in =λ2(xx min );

[0029] Where, x min This represents the minimum value of the input voltage.

[0030] Optionally, the mapped memristor array obtains the output current based on the input voltage signal, including:

[0031] The mapped memristor array obtains the output current based on the input voltage signal using the following formula;

[0032]

[0033] Optionally, mapping the input signal to an input voltage signal includes:

[0034] The input signal is equalized using a contraction coefficient to obtain an equalized input signal.

[0035] The equalized input signal is mapped to an input voltage signal;

[0036] The shrinkage coefficient is obtained through the following steps:

[0037] Receive pilot signals;

[0038] Based on the pilot signal, the shrinkage coefficient is calculated using the following formula, where the shrinkage coefficient includes a horizontal axis shrinkage coefficient and a vertical axis shrinkage coefficient.

[0039]

[0040] Among them, e I e represents the horizontal axis shrinkage coefficient. Q The vertical axis contraction coefficient is represented by i, the number of known pilot points is represented by j, and the number of pilot signals received at each known pilot point is represented by s. i,Is represents the I-axis coordinate of the i-th sample of a known pilot point received by the receiver. i,Q Let represent the Q-axis coordinate of the i-th sample of the known pilot point received by the receiver, a represent the correct I-axis coordinate of the known pilot point, and c represent the correct Q-axis coordinate of the known pilot point.

[0041] Based on the same inventive concept, one or more embodiments of this application also provide a signal processing device based on a memristor array, including:

[0042] The first mapping module is used to map the input signal into an input voltage signal, and input the input voltage signal to the mapped memristor array;

[0043] The mapped memristor array is used to obtain the output current based on the input voltage signal;

[0044] The mapped memristor array is obtained through the following steps:

[0045] Determine the discrete Fourier transform expression for signal conversion: X = W N x, where x represents the input signal, X represents the output signal, and W N Indicates the rotation factor;

[0046] Convert it into a complex matrix-vector multiplication expression;

[0047]

[0048] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0049] Operation matrix The mapped memristor array is obtained by mapping the mapped memristor array.

[0050] Optionally, it also includes:

[0051] A signal conversion module is used to convert the output current into a voltage signal;

[0052] A signal output module is used to modulate the voltage signal into an output voltage signal.

[0053] As can be seen from the above, the signal processing method based on a memristor array provided in one or more embodiments of this application maps an input signal to an input voltage signal and inputs the input voltage signal to the mapped memristor array; the mapped memristor array obtains an output current based on the input voltage signal. The mapped memristor array is obtained through the following steps: determining the discrete Fourier transform expression X = W for signal conversion. N x, where x represents the input signal, X represents the output signal, and W NRepresent the rotation factor; convert it into a complex matrix-vector multiplication expression; Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number; the operation matrix... Mapping to a memristor array yields the mapped memristor array.

[0054] The technical solutions provided in one or more embodiments of this application convert the calculation expression of DFT into the expression form of complex matrix-vector multiplication, convert the rotation factor of DFT into an operation matrix and map it to a memristor array, make full use of the matrix operation capability of the memristor array, integrate the memristor module circuit, improve the operation efficiency of the DFT module, and further improve the efficiency of signal processing.

[0055] The signal processing device based on a memristor array provided in this application can implement the steps of the above-mentioned signal processing method based on a memristor array, and therefore also has the beneficial effects of the above-mentioned signal processing method based on a memristor array. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in one or more embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic flowchart illustrating a signal processing method based on a memristor array according to one or more embodiments of this application.

[0058] Figure 2 This is a schematic diagram of the structure of a signal processing device based on a memristor array according to one or more embodiments of this application;

[0059] Figure 3 This is a schematic diagram of the mapping of pilot signals for one or more embodiments of this application;

[0060] Figure 4 This is a schematic diagram of the computing unit circuit structure based on a memristor array according to one or more embodiments of this application;

[0061] Figure 5 This is a schematic diagram of the programmable memristor unit structure for one or more embodiments of this application;

[0062] Figure 6 This application provides an embodiment of the overall circuit architecture for one or more DFT (or IDFT) devices.

[0063] Figure 7This is a schematic diagram of the hardware structure of one or more electronic devices in this application. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0065] It should be noted that, unless otherwise defined, the technical or scientific terms used in one or more embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in one or more embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0066] As mentioned in the background section, improving the computational efficiency of DFT is a pressing technical problem that needs to be solved. However, no effective technical solution has yet been proposed in the relevant technologies.

[0067] Memristors (e.g., resistive random access memory, phase-change memory, bridged memory, etc.) are non-volatile devices whose conductance can be adjusted by applying external stimuli. As a two-terminal device, memristors possess adjustable and non-volatile resistance, making them widely used in in-memory computing. According to Kirchhoff's current law and Ohm's law, arrays of memristors can perform multiplication-accumulation calculations in parallel, with both storage and computation occurring within the array's individual devices. Based on this computing architecture, in-memory computing can be implemented without requiring extensive data movement.

[0068] In the process of developing this disclosure, the applicant discovered that memory computing architectures, represented by cross-switch memristor arrays, have significant advantages in performing VMM operations and can be considered an ideal choice for solving the aforementioned problems.

[0069] refer to Figure 1 The signal processing method based on memristor array according to one or more embodiments of this application includes the following steps:

[0070] Step S101: Map the input signal to an input voltage signal and input the above input voltage signal to the mapped memristor array.

[0071] Step S102: The mapped memristor array obtains the output current based on the input voltage signal.

[0072] The mapped memristor array is obtained through the following steps:

[0073] Step S201: Determine the discrete Fourier transform expression X = W for the signal conversion. N x, where x represents the input signal, X represents the output signal, and W N This represents the rotation factor.

[0074] Step S202: Convert it into a complex matrix-vector multiplication expression.

[0075]

[0076] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0077] Step S203: Perform the operation matrix Mapping onto the memristor array above, we obtain the mapped memristor array.

[0078] The expression for the DFT algorithm is:

[0079]

[0080] in, Indicates the rotation factor.

[0081] The matrix form of the above expression can be represented as:

[0082] X = W N x;

[0083] in,

[0084] It's understandable that a larger N value means a larger Fourier transform, which in turn means more complex matrix operations are required. In traditional computer systems, matrix operations typically consume a lot of resources.

[0085] In related technologies, the FFT algorithm is mainly used for computation. FFT is an efficient DFT algorithm. Its basic idea is to use the periodicity, symmetry and reducibility of the twitch factor to decompose the long sequence DFT operation into multiple short sequence DFT operations.

[0086] The calculation process of the FFT algorithm includes:

[0087] From a discrete signal sequence of length N, one point is extracted every n points to form n new sequences;

[0088]

[0089] in,

[0090] Substitute it into the expression of the DFT algorithm:

[0091]

[0092] After simplification, we get:

[0093]

[0094] According to this formula, the N-point DFT is decomposed into n smaller-point DFTs of length N / n according to the basis n. After calculation, n frequency domain sequences of length N / n are obtained, represented as X1[m], X2[m], ..., X n [m](m=0,1,2,…,N / n-1), the above formula can be simplified to:

[0095]

[0096] make Based on the periodicity of the twitch factor:

[0097]

[0098] We can obtain:

[0099]

[0100] The matrix expression of the above formula is:

[0101]

[0102] in X N It is an n-dimensional column vector.

[0103] The second to nth level operations follow the same process as described above.

[0104] Similarly, the IDFT algorithm expression is:

[0105]

[0106] The matrix form is as follows:

[0107]

[0108] Its calculation process is the same as that of DFT calculation.

[0109] In related technologies, the Cooley-Tukey algorithm is used to reduce complex matrix operations, and a radix-2 butterfly operation is employed to avoid matrix multiplication. However, for large-scale FFT operations, the number of stages increases significantly, requiring the circuit to have strong temporary data storage and scheduling capabilities.

[0110] In implementing this application, the applicant discovered that high-radix FFT operations can be divided into two parts: smaller-radix operations after radix n decomposition and radix composition operations. Both of these vector-matrix operations can be efficiently performed using a memristor cross array. The radix size of the decomposition depends on the size of the memristor array. Therefore, the applicant proposes to implement the DFT module using a memristor array.

[0111] Considering that the input and output data types of the DFT module are combinations of complex numbers, and complex matrix-vector multiplication can be represented as:

[0112]

[0113] Combining the expression of complex matrix-vector multiplication, this application transforms the algorithmic expression of DFT into:

[0114]

[0115] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number.

[0116] Through the above transformation, the twitch factor in the DFT algorithm can be mapped to the memristor array, realizing the integration of memristors and effectively utilizing the matrix operation capabilities of memristors, thereby improving the computational efficiency of the DFT module.

[0117] Due to the properties of the rotation factor, W N and The real parts are the same, and the imaginary parts are opposites of each other. Since the rotation factor matrix is ​​a symmetric matrix, Therefore, the IDFT algorithm can be expressed as:

[0118]

[0119] It is understood that the computation of an IDFT module for a signal sequence can be regarded as the conjugate computation of the DFT module for the same signal sequence, and the forward and inverse Fourier transforms can be performed in the same circuit computation unit. Those skilled in the art will readily understand that the signal processing method based on memristor arrays in this application can be used for both DFT and IDFT operations.

[0120] In step S101, the input signal can be a time-domain signal or a frequency-domain signal. When the input signal is a time-domain signal, the corresponding output signal is a frequency-domain signal; when the input signal is a frequency-domain signal, the corresponding output signal is a time-domain signal.

[0121] According to the formula above In this step, the input signal x is mapped to a voltage signal. Specifically, in this application, the real and imaginary parts of the input signal x are mapped to voltage signals and then input in parallel to the memristor array.

[0122] The mapped memristor array in step S101 is mapped with a matrix. The matrix Related to the rotation factor. Considering that the rotation factor involved in each calculation is different, and that using memristors for storage and calculation may result in a large amount of time and energy consumption due to frequent resistance changes, in the embodiments of this application, memory can be used to store all the basic rotation factors.

[0123] In a 1T1R (transistor-resistor) structure of a memristor array, the drain current is controlled by the gate-source voltage to achieve a switching function. The input numerical vector used for matrix calculations has positive and negative values. If the positive and negative voltages correspond to the positive and negative values ​​in the numerical matrix, respectively, then the input voltage vector will consist of both positive and negative voltages. In embodiments of this application, to avoid gate-source voltage confusion, the input signal can be mapped to a positive voltage value.

[0124] Therefore, in the embodiments of this application, when the amplitude of the input signal is known (such as the input signal at the transmitting end), the mapping expression of the input voltage signal can be:

[0125]

[0126] Where x represents the input signal, λ2 represents the mapping scaling factor, and N represents the numerical range of the input signal. In embodiments of this application, the input signal can be a numerical vector of length n. When the amplitude of the input signal is known, the amplitude range of the computational data is known, and mapping it to the corresponding constellation points results in a positive-negative symmetric amplitude range. In the above formula, a value is added to the numerical vector. The purpose is to ensure that the values ​​of the input vector remain non-negative.

[0127] In this case, the output current vector can be expressed as:

[0128]

[0129] The result of matrix operations can be represented by the output value of the current circuit as follows:

[0130]

[0131] The result of matrix operations is obtained by adding or subtracting the three components α, β, and γ. Here, α is related to the output current and can be determined by the gain. The transimpedance amplifier is implemented; all parameters in β are fixed values, where I is a unit vector, calculated once after each change in the resistance of the memristor array; γ is composed of the sum of the input numerical vectors.

[0132] In the embodiments of this application, when the amplitude of the input signal is unknown (such as the input signal at the receiving end), the mapping expression of the input voltage signal can be:

[0133] V in =λ2(a n×1 -a min );

[0134] In this case, the output current vector can be expressed as:

[0135] I out,n×1 =λ1λ2[B n×n ·a n×1 -a min (B n×n +Φ)+Φa n×1 ];

[0136] The result of matrix operations can be represented by the output value of the current circuit as follows:

[0137]

[0138] Considering the non-ideal nature of memristor array computation, the main impact on communication system performance lies in the increased bit error rate caused by the shrinkage of the constellation cluster towards the origin. The larger the mapping error of the memristors, the more significant the impact on communication system performance.

[0139] Therefore, in the embodiments of this application, the applicant proposes a memristor array equalization method based on Monte Carlo pilots to optimize system performance. Without considering channel frequency-selective fading, the transmitter adds known Monte Carlo pilots to the frequency domain signal, and the receiver uses the Monte Carlo method to analyze the received pilots, calculate the shrinkage coefficient, and equalize other received data.

[0140] For the same known pilot signal, the received pilot signal, after passing through a Gaussian channel, will exhibit a two-dimensional Gaussian distribution centered on the original pilot signal. However, as... Figure 3 As shown in section (a), the signal amplitude decreases and the constellation points shrink inward due to the non-ideal nature of the memristor array.

[0141] According to the Monte Carlo method, the in-phase and quadrature components of the received pilot signal points are equalized separately. Based on this, the average convergent pilot signal points can be approximated, and their accuracy depends on the number of received pilot points, such as... Figure 3 As shown in section (b).

[0142] Then, the contraction coefficient is obtained by the ratio of the in-phase and quadrature components of the average pilot signal. Figure 3 As shown in section (c), the pilot signal can be equalized using a contraction coefficient. Its expression can be:

[0143]

[0144] Among them, e I e represents the horizontal axis shrinkage coefficient. Q The vertical axis contraction coefficient is represented by i, the number of known pilot points is represented by j, and the number of pilot signals received at each known pilot point is represented by s. i,I s represents the I-axis coordinate of the i-th sample of a known pilot point received by the receiver. i,Q Let represent the Q-axis coordinate of the i-th sample of the known pilot point received by the receiver, a represent the correct I-axis coordinate of the known pilot point, and c represent the correct Q-axis coordinate of the known pilot point.

[0145] Therefore, the received signal can be equalized to compensate for the constellation point shrinkage problem caused by memristor array calculation.

[0146] The output current in step S102 is determined by Ohm's law and Kirchhoff's law, and can be expressed by the following formula: In the embodiments of this application, the output current can be converted into a current signal and finally modulated into an output voltage signal, which is equivalent to the result of a matrix operation.

[0147] The mapping process for the memristor array is detailed in steps S201-S202. In the embodiments of this application, a memristor array mapping matrix is ​​used. Each memristor mapping matrix A single element is used to perform precise matrix operations.

[0148] In the embodiments of this application, the mapping relationship between the elements in the matrix and the memristor conductance values ​​can be expressed as follows:

[0149]

[0150] Where B represents the conductance array of the memristor array, and λ1 represents the scaling factor used to map the operation matrix to the memristor conductance range. Φ represents the movement matrix, used to indicate the movement distance of each element in the operation matrix. B max and B min G represents the conductance range of the memristors in the memristor array. max and G min This represents the maximum and minimum element values ​​of the operation matrix.

[0151] In the above mapping expression, setting Φ ensures that the memristor conductance values ​​are all within a positive range. The memristor conductance range is set based on the resistance R_on in the on-state and R_off in the off-state, and can be a value close to R_on and R_off. The scaling factor is used to map the matrix value range to the memristor conductance range.

[0152] It is understandable that this method can be executed by any device, equipment, platform, or cluster of devices with computing and processing capabilities.

[0153] It should be noted that the methods of one or more embodiments of this application can be executed by a single device, such as a computer or server. The methods of this embodiment can also be applied in a distributed scenario, where multiple devices cooperate to complete the process. In such a distributed scenario, one of these devices may execute only one or more steps of the methods of one or more embodiments of this application, and the multiple devices will interact with each other to complete the method described.

[0154] It should be noted that the above description describes specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than that shown in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0155] Based on the same inventive concept, and corresponding to any of the above embodiments, this application also provides a signal processing device based on a memristor array.

[0156] like Figure 2 As shown, the above-mentioned device includes:

[0157] The first mapping module 11 is used to map the input signal into an input voltage signal and input the input voltage signal to the mapped memristor array;

[0158] The mapped memristor array 12 is used to obtain the output current based on the input voltage signal;

[0159] The mapped memristor array is obtained through the following steps:

[0160] Determine the discrete Fourier transform expression for signal conversion: X = W N x, where x represents the input signal, X represents the output signal, and W N Indicates the rotation factor;

[0161] Convert it into a complex matrix-vector multiplication expression;

[0162]

[0163] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0164] Operation matrix The mapped memristor array is obtained by mapping the mapped memristor array.

[0165] In embodiments of this application, it may further include:

[0166] Signal conversion module 13 is used to convert the output current into a voltage signal;

[0167] The signal output module 14 is used to modulate the voltage signal into an output voltage signal.

[0168] In embodiments of this application, it may further include:

[0169] The single-pole double-throw switch 15 is used to switch between memristor array operation and conductance modulation.

[0170] In embodiments of this application, it may further include:

[0171] Transimpedance amplifier 16 is used to facilitate cascading between memristors by converting current into voltage.

[0172] The computing unit circuit structure based on memristor arrays in one or more embodiments of this application is as follows: Figure 4 As shown.

[0173] Figure 4 Part (a) is the first mapping module, which can consist of at least one programmable memristor unit, used for mapping the input voltage signal. According to the input voltage mapping expression above:

[0174]

[0175] The output voltage of this module can be expressed as:

[0176]

[0177] in, an Indicates the input signal. v ab,n =V in .

[0178] In the embodiments of this application, such as Figure 5 As shown, the programmable memristor unit includes four metal-oxide-semiconductor field-effect transistors (MOSFETs), labeled a, b, c, and d. The two MOSFETs on the left (a and c) are P-type MOSFETs, and the two MOSFETs on the right (b and d) are N-type MOSFETs. These MOSFETs are controlled by a control voltage introduced from the top and bottom, connected to the gates of the P-type and N-type MOSFETs, respectively. The magnitude of the applied control voltage determines which side of the switch is activated. When the control voltage is lower than the threshold voltage of the P-type MOSFET, a and c are turned on, while b and d are turned off. This means that the P-type MOSFET is turned on at low voltage, and current can flow through the paths of a and c, forming a circuit. This mechanism can be viewed as two double-throw switches (SPDTs), allowing the circuit to dynamically change its connection paths, thereby achieving programmable functionality.

[0179] This application uses the aforementioned programmable memristor unit to replace a conventional resistor to represent the resistance R. f The reason is that λ2 in this application may differ in different communication computing scenarios, requiring resistance R... f It can be adjusted flexibly.

[0180] Figure 4 Part (b) is a memristor array, in which memristors store mapped conductance information. During the memristor conductance modulation stage, C... b,1 C controls the conductance modulation process of the corresponding columns of the memristor array. b,2 The control memristor array is isolated from the external circuitry. Pulse-modulated signals and conductance measurement signals are transmitted from terminal V. set Input, simultaneously from terminal I read The current signal is read to determine the corresponding memristor conductance. During the calculation phase, the memristor conductance does not need to be changed.

[0181] Figure 4Part (c) includes a transimpedance amplifier and a single-pole double-throw switch. The transimpedance amplifier can be used to facilitate cascading between memristors by converting current to voltage. Since the memristor acts as a feedback resistor, its calculation and conductance modulation functions must be implemented separately. Therefore, this application improves the transimpedance amplifier using a programmable memristor unit, achieving separation of memristor calculation and conductance modulation via a single-pole double-throw switch, thereby enabling adjustable feedback gain within the transimpedance amplifier.

[0182] Figure 4 The transimpedance amplifier in section (d) with adjustable feedback gain converts the output current of the memristor array into a voltage signal. The conversion relationship is: v d,n =-I out,n R d R d =1 / λ1λ2.

[0183] Figure 4 Parts (e) and (f) are used to calculate the final output voltage signal. The calculation expression for part (e) is:

[0184]

[0185] in,

[0186] The above formula can also be expressed as:

[0187] The calculation expression for part (f) is:

[0188] v out,n =-(v e +v d,n +V f,n );

[0189] Another V f =[V f,1 V f,2 ,…,V f,n ],

[0190] The above formula can be expressed as:

[0191]

[0192] I is a unit vector.

[0193] V f The calculation only needs to be performed once after each conductance modulation of the memristor array.

[0194] Therefore, a voltage signal equivalent to the matrix operation result can be obtained at the output terminal.

[0195] The overall circuit architecture diagram of one or more DFT (or IDFT) devices in this application is as follows: Figure 6 As shown, the device includes a control module for modulating the memristors of the memristor array and programmable memristor units, so that adjustments to the memristor array are avoided during subsequent calculations; only the programmable memristor units need to be fine-tuned according to the mapping of the input data. Random access memory is used to store complex-valued data, which is then transferred to the twiddle factor processing unit. The twiddle factor processing unit mainly undertakes two tasks: combining the real and imaginary parts of the complex data into a column vector [Re(x), Im(x)] T Alternatively, in a basis composition operation, the corresponding twiddle factor can be retrieved from read-only memory, and the result can be compared with [Re(x), Im(x)]. T The product is multiplied and then output. Once the calculation unit completes the calculation, the data is transferred back to the random access memory. All of the above operations are controlled by the central control unit.

[0196] For ease of description, the above apparatus is described in terms of its functions, divided into various modules. Of course, when implementing one or more embodiments of this application, the functions of each module can be implemented in one or more software and / or hardware.

[0197] The apparatus described above is used to implement the corresponding methods in the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0198] Figure 7 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0199] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0200] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this application are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0201] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0202] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0203] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0204] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this application, and not necessarily all the components shown in the figures.

[0205] The electronic devices described above are used to implement the corresponding methods in the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0206] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0207] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0208] Additionally, to simplify the description and discussion, and to avoid obscuring one or more embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be illustrated in block diagram form to avoid obscuring one or more embodiments of this application, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which one or more embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that one or more embodiments of this application may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0209] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0210] One or more embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this application should be included within the protection scope of this disclosure.

Claims

1. A signal processing method based on a memristor array, characterized in that, include: The input signal is mapped to an input voltage signal, and the input voltage signal is input to the mapped memristor array; The mapped memristor array obtains the output current based on the input voltage signal; The mapped memristor array is obtained through the following steps: Determine the discrete Fourier transform expression for signal transformation , Indicates the input signal. Indicates the output signal. Indicates the rotation factor; Convert it into a complex matrix-vector multiplication expression; ； Represents the real part of a complex number. Represents the imaginary part of a complex number; Operation matrix Mapping onto the memristor array yields the mapped memristor array; Operation matrix Mapping to the memristor array includes: According to the operation matrix The calculated value of the element is obtained by calculating the conductance of the memristor in the memristor array using the following formula; ； in, This represents the conductance array of the memristor array. This represents a scaling factor used to map the computation matrix to the memristor conductance range. , This represents the movement matrix, used to indicate the movement distance of each element in the operation matrix. , and This indicates the range of conductance values ​​for the memristors in the memristor array. and This represents the maximum and minimum element values ​​of the operation matrix.

2. The method according to claim 1, characterized in that, The input signal includes a time-domain signal or a frequency-domain signal.

3. The method according to claim 2, characterized in that, Mapping the input signal to an input voltage signal includes: Based on the input signal, the input voltage signal is obtained using the following formula; ； in, Indicates the input signal. Indicates the mapping scaling factor. This indicates the numerical range of the input signal.

4. The method according to claim 3, characterized in that, The mapped memristor array obtains the output current based on the input voltage signal, including: The mapped memristor array obtains the output current based on the input voltage signal using the following formula; 。 5. The method according to claim 3, characterized in that, Mapping the input signal to an input voltage signal includes: Based on the input signal, the input voltage signal is obtained using the following formula; ； in, This represents the minimum value of the input voltage.

6. The method according to claim 5, characterized in that, The mapped memristor array obtains the output current based on the input voltage signal, including: The mapped memristor array obtains the output current based on the input voltage signal using the following formula; 。 7. The method according to claim 1, characterized in that, Mapping the input signal to an input voltage signal includes: The input signal is equalized using a contraction coefficient to obtain an equalized input signal. The equalized input signal is mapped to an input voltage signal; The shrinkage coefficient is obtained through the following steps: Receive pilot signals; Based on the pilot signal, the shrinkage coefficient is calculated using the following formula, where the shrinkage coefficient includes a horizontal axis shrinkage coefficient and a vertical axis shrinkage coefficient. ； ； in, This represents the horizontal axis shrinkage coefficient. This represents the longitudinal axis contraction coefficient. This indicates the number of known pilot points. This indicates the number of pilot signals received at each of the known pilot points. This indicates the known pilot point received by the receiver. one sample Axis coordinates This indicates the known pilot point received by the receiver. one sample Axis coordinates Indicates the correctness of the known pilot point Axis coordinates Indicates the correctness of the known pilot point Axis coordinates.

8. A signal processing device based on a memristor array, characterized in that, include: The first mapping module is used to map the input signal into an input voltage signal, and input the input voltage signal to the mapped memristor array; The mapped memristor array is used to obtain the output current based on the input voltage signal; The mapped memristor array is obtained through the following steps: Determine the discrete Fourier transform expression for signal transformation , Indicates the input signal. Indicates the output signal. Indicates the rotation factor; Convert it into a complex matrix-vector multiplication expression; ； Represents the real part of a complex number. Represents the imaginary part of a complex number; Operation matrix Mapping onto the memristor array yields the mapped memristor array; Operation matrix Mapping to the memristor array includes: According to the operation matrix The calculated value of the element is obtained by calculating the conductance of the memristor in the memristor array using the following formula; ； in, This represents the conductance array of the memristor array. This represents a scaling factor used to map the computation matrix to the memristor conductance range. , This represents the movement matrix, used to indicate the movement distance of each element in the operation matrix. , and This indicates the range of conductance values ​​for the memristors in the memristor array. and This represents the maximum and minimum element values ​​of the operation matrix.

9. The apparatus according to claim 8, characterized in that, Also includes: A signal conversion module is used to convert the output current into a voltage signal; A signal output module is used to modulate the voltage signal into an output voltage signal.

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