Dynamic memory structure and operation method thereof

Abstract

The invention discloses a dynamic memory structure and an operation method thereof, and relates to the field of memorizers, the dynamic memory structure comprises a write gating device, a read gating device and a capacitor; the first end of the write gating device, the first end of the read gating device and the first end of the capacitor are connected together; the second end of the write gating device is a data write-in end; the second end of the read gating device is a data read-out end; the second end of the capacitor is a gating end, and the second end of the capacitor is connected to a word line; the write gating device and the read gating device are both in one-way conduction, and the conduction modes of the write gating device and the read gating device are threshold opening; wherein the conduction threshold voltage of the write gating device is smaller than the conduction threshold voltage of the read gating device. According to the invention, the gating devices are respectively prepared for writing and reading, and the conduction threshold voltage of the writing gating device is smaller than that of the reading gating device, so that the subthreshold leakage current of the reading gating device can be greatly reduced, and the data retention time of the memory is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a dynamic memory structure and an operation method thereof. Background Art

[0002] As the demand for higher performance and smaller size of electronic devices continues to grow, the design and manufacture of dynamic random access memory (DRAM) faces unprecedented challenges. DRAM relies on capacitors to store data, but as the size continues to shrink, it becomes increasingly difficult to maintain sufficient storage capacity and stability. Density problem: As Moore's Law advances, the density of memory needs to grow exponentially. However, when DRAM's capacitors are reduced to the nanoscale, they face quantum tunneling effects, which may cause data loss. In addition, the reduction in the physical size of capacitors also limits their ability to store charge, thus affecting storage density. Size miniaturization dilemma: In order to increase integration and reduce costs, the manufacturing process of DRAM needs to be continuously miniaturized. However, when the size is reduced to a certain extent, the complexity and cost of the manufacturing process will increase significantly. For example, the photolithography technology in the manufacturing process will encounter resolution limitations at a smaller scale, resulting in increased manufacturing difficulty.

[0003] In 2022, Huazhong University of Science and Technology disclosed a new type of dynamic storage device structure (CN2021112803491), which provides a feasible solution for the next generation of high-density dynamic memory. Its basic structure is 1S1C, which consists of an OTS gate tube in series with a capacitor. OTS is used to control the charging and discharging of the capacitor to realize the function of data storage. Thanks to its simple structure and loose material conditions, it can achieve three-dimensional stacking similar to the 3D NAND structure. However, due to the large leakage current of the OTS gate tube itself, its data retention time is less than 1ms. This shortcoming may limit its further application. Summary of the invention

[0004] The purpose of the present invention is to provide a dynamic memory structure and an operation method thereof, which can solve the problem of short data retention time faced by the current 1S1C memory.

[0005] To achieve the above object, the present invention provides the following solution.

[0006] In a first aspect, the present invention provides a dynamic memory structure, which includes: a write enable device, a read enable device and a capacitor.

[0007] The first end of the write enable device, the first end of the read enable device and the first end of the capacitor are connected together; the second end of the write enable device is the data writing end; the second end of the read enable device is the data reading end; the second end of the capacitor is the enable end, and the second end of the capacitor is connected to the word line.

[0008] The write enable device and the read enable device are both unidirectionally conductive, and the conduction modes of the write enable device and the read enable device are both threshold-on; the threshold-on means that only when the potential of the second end of the write enable device is higher than the potential of the first end of the write enable device by the conduction threshold voltage of the write enable device, the write enable device will be turned on, and the current will flow from the second end of the write enable device to the first end of the write enable device, otherwise the write enable device will remain in the closed state; only when the potential of the first end of the read enable device is higher than the potential of the second end of the read enable device by the conduction threshold voltage of the read enable device, the read enable device will be turned on, and the current will flow from the first end of the read enable device to the second end of the read enable device, otherwise the read enable device will remain in the closed state; wherein, the conduction threshold voltage of the write enable device is less than the conduction threshold voltage of the read enable device.

[0009] Optionally, when data writing is required, a write pulse signal is applied between the second end of the write enable device and the second end of the capacitor; the potential of the second end of the write enable device is higher than the potential of the second end of the capacitor; and the difference between the write pulse signal and the capacitor voltage in the initial state is higher than the turn-on threshold voltage of the write enable device.

[0010] Optionally, when data reading is required, a read pulse signal is applied between the second end of the read enable device and the second end of the capacitor; the potential of the second end of the read enable device is less than the potential of the second end of the capacitor; and when the capacitor stores the capacitor voltage after data writing is completed, current will be generated at both ends of the capacitor, and when the capacitor stores the capacitor voltage in the initial state, no current will be generated at both ends of the capacitor.

[0011] Optionally, the stored information is stored in the capacitor in the form of electric charge.

[0012] Optionally, the write-enabling device has a first holding voltage in a conduction direction, and the first holding voltage is less than or equal to a conduction threshold voltage of the write-enabling device.

[0013] Optionally, the read gating device has a second holding voltage in the conduction direction, and the second holding voltage is less than or equal to a conduction threshold voltage of the read gating device.

[0014] Optionally, the write gating device and the read gating device are gating devices with unidirectional threshold switching characteristics.

[0015] In a second aspect, the present invention provides an operating method for a dynamic memory structure, the operating method for the dynamic memory structure comprising: when data writing is required, applying a write pulse signal between the second end of the write enable device and the second end of the capacitor; the potential of the second end of the write enable device is higher than the potential of the second end of the capacitor; and the difference between the write pulse signal and the capacitor voltage in the initial state is higher than the turn-on threshold voltage of the write enable device.

[0016] When data reading is required, a read pulse signal is applied between the second end of the read enable device and the second end of the capacitor; the potential of the second end of the read enable device is less than the potential of the second end of the capacitor; and when the capacitor stores the capacitor voltage after data writing is completed, current will be generated at both ends of the capacitor, and when the capacitor stores the capacitor voltage in the initial state, no current will be generated at both ends of the capacitor.

[0017] Optionally, after the data writing is completed, the voltage calculation formula of the capacitor is: Vc1=Vwrite-Vhold1.

[0018] Wherein, Vc1 is the capacitor voltage after data writing is completed, Vwrite is the write pulse signal, and Vhold1 is the first holding voltage.

[0019] Optionally, when a data read operation is required, the read voltage pulse satisfies the following relationship: Vread+Vc0<Vth2.

[0020] Vread+Vc1>Vth2.

[0021] Wherein, Vread is a read voltage pulse, Vc0 is a capacitor voltage in an initial state, Vc1 is a capacitor voltage after data writing is completed, and Vth2 is a turn-on threshold voltage of a read-enabling device.

[0022] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: The present invention provides a dynamic memory structure and an operation method thereof, wherein the dynamic memory structure comprises: a write gating device, a read gating device and a capacitor; the first end of the write gating device, the first end of the read gating device and the first end of the capacitor are connected together; the second end of the write gating device is a data writing end; the second end of the read gating device is a data reading end; the second end of the capacitor is a gating end, and the second end of the capacitor is connected to a word line; the write gating device and the read gating device are both unidirectionally conductive, and the conduction modes of the write gating device and the read gating device are both threshold-on; wherein the conduction threshold voltage of the write gating device is less than the conduction threshold voltage of the read gating device. The present invention improves the structure of the traditional 1S1C memory, in which data writing and reading originally share the same gating device, so the gating device must be bidirectionally conductive, and there are very few types of bidirectionally conductive gating devices, so there are very few types of gating devices that can be selected for the 1S1C memory. The present invention configures dedicated gating devices for writing and reading respectively, and the gating devices only need to have unidirectional threshold switching characteristics, which greatly increases the types of gating devices that can be selected by the memory. In addition, the conduction threshold voltage of the write gating device is made smaller than the conduction threshold voltage of the read gating device, so that the subthreshold leakage current of the read gating device can be greatly reduced, so that the charge in the capacitor can be stored for a longer time, and the data retention time of the memory is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A structural diagram of a dynamic storage unit provided in accordance with an embodiment of the present invention.

[0025] Figure 2 A schematic diagram of IV curves of a write enable device and a read enable device provided in one embodiment of the present invention.

[0026] Figure 3 A comparison diagram of data retention time achieved by a device structure provided in an embodiment of the present invention.

[0027] Reference numerals: 1-the second end of the write enable device, 2-the second end of the read enable device, 3-the second end of the capacitor, 4-the write enable device, 5-the read enable device, 6-the capacitor. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] In an exemplary embodiment, Figure 1 As shown, the present invention provides a dynamic memory structure, which includes: a write gating device 4, a read gating device 5 and a capacitor 6.

[0031] The first end of the write enable device, the first end of the read enable device and the first end of the capacitor are connected together, and the connection point of these three endpoints is the storage node (SN) of the memory. Logical information is stored on the capacitor in the form of charge. The second end 1 of the write enable device is the data writing end; the second end 2 of the read enable device is the data reading end; the second end 3 of the capacitor is the enable end, and the second end 3 of the capacitor is connected to the word line.

[0032] The write enable device 4 and the read enable device 5 are both unidirectionally conductive, and the conduction modes of the write enable device 4 and the read enable device 5 are both threshold-on; the threshold-on means that only when the potential of the second end 1 of the write enable device is higher than the potential of the first end of the write enable device 4 by the conduction threshold voltage of the write enable device 4, the write enable device 4 will be turned on, and the current will flow from the second end 1 of the write enable device to the first end of the write enable device 4, otherwise the write enable device 4 will remain in the closed state; only when the potential of the first end of the read enable device 5 is higher than the potential of the second end 2 of the read enable device by the conduction threshold voltage of the read enable device 5, the read enable device 5 will be turned on, and the current will flow from the first end of the read enable device 5 to the second end 2 of the read enable device, otherwise the read enable device 5 will remain in the closed state; wherein, the conduction threshold voltage of the write enable device 4 is less than the conduction threshold voltage of the read enable device 5.

[0033] The on-threshold voltage of the read enable device 5 is greater than the on-threshold voltage of the write enable device 4, which means that under the same voltage load, the leakage current of the read enable device 5 is less than the leakage current of the write enable device 4, thereby extending the storage time of the charge in the capacitor and reducing the refresh time of the dynamic memory.

[0034] The traditional 1S1C dynamic memory uses only one gating device to control the charging and discharging of the capacitor. When data is written, the charge flows into the capacitor through the gating device to realize the information storage function. When data is read, the charge flows out of the capacitor through the gating device to realize the information reading function. Therefore, the gating device must be able to conduct forward to write data and conduct reverse to read data. The gating device needs to have the ability of bidirectional threshold conduction. At present, the only device that can achieve bidirectional threshold conduction is the OTS gating tube. The forward and reverse threshold voltages of the OTS gating tube are basically consistent with the subthreshold curve, and the subthreshold leakage current of the OTS gating tube cannot be ignored. When data information is stored in the capacitor, the end of the capacitor connected to the OTS gating tube will have a high potential. The high potential will cause the OTS gating tube to generate a large subthreshold leakage. Therefore, the information stored in the written capacitor will gradually be lost with the subthreshold leakage. Therefore, it is usually necessary to rewrite the information stored in the capacitor once every 1ms.

[0035] The present invention improves the structure of the traditional 1S1C memory, and special gating devices are respectively configured for writing and reading. The write gating device 4 and the read gating device 5 can use all gating devices with unidirectional threshold switching characteristics, which greatly improves the types of gating devices that can be selected by the memory, such as: pn junction, CBTS device, unidirectionally conductive OTS device, etc., all of which have the ability of unidirectional threshold conduction. By adjusting the threshold voltage of the read gating device 5 and the write gating device 4, the conduction threshold voltage of the write gating device 4 is made smaller than the conduction threshold voltage of the read gating device 5. In this way, the information written into the capacitor through the write gating device 4 will generate a smaller subthreshold leakage in the read gating device 5, thereby improving the retention time of the charge in the capacitor, reducing the refresh frequency of the dynamic memory, and improving the performance of the dynamic memory.

[0036] Both the write gating device 4 and the read gating device 5 can only be unidirectionally conductive, which means that when a voltage is applied in a direction opposite to the conductive direction of the gating device, the gating device will always be in an off state, a high-impedance state.

[0037] The conduction modes of the write gating device 4 and the read gating device 5 are both threshold-on. Threshold-on means that in the conduction direction of the gating device, when the applied voltage reaches the threshold voltage, a current jump phenomenon will occur.

[0038] In an exemplary embodiment, when data writing is required, a write pulse signal is applied between the second terminal 1 of the write gate device and the second terminal 3 of the capacitor; the potential of the second terminal 1 of the write gate device is higher than the potential of the second terminal 3 of the capacitor; and the difference between the write pulse signal and the capacitor voltage in the initial state is higher than the conduction threshold voltage of the write gate device 4. The write pulse signal can turn on the write gate device 4, and the write gate device 4 becomes a low-resistance state, so that the capacitor 6 can be charged and information can be written.

[0039] The write pulse signal minus the capacitor voltage in the initial state should be higher than the turn-on threshold voltage of the write gate device 4. At this time, the write gate device 4 is turned on to charge the capacitor and complete the data writing. After the writing is completed, the calculation formula of the capacitor voltage is: Vc1=Vwrite-Vhold1.

[0040] Wherein, Vc1 is the capacitor voltage after data writing is completed, Vwrite is the write pulse signal, and Vhold1 is the first hold voltage. The capacitor voltage in the initial state and the capacitor voltage after data writing are completed correspond to two stored logic states respectively.

[0041] In an exemplary embodiment, when data reading is required, a read pulse signal is applied between the second end 2 of the read enable device and the second end 3 of the capacitor; the potential of the second end 2 of the read enable device is less than the potential of the second end 3 of the capacitor; and when the capacitor 6 stores the capacitor voltage after data writing is completed, a current will be generated across the capacitor 6, and when the capacitor 6 stores the capacitor voltage in the initial state, no current will be generated across the capacitor 6.

[0042] When a data read operation is required, the read voltage pulse satisfies the following relationship: Vread+Vc0<Vth2.

[0043] Vread+Vc1>Vth2.

[0044] Wherein, Vread is a read voltage pulse, Vc0 is a capacitor voltage in an initial state, Vc1 is a capacitor voltage after data writing is completed, and Vth2 is a turn-on threshold voltage of a read-enabling device.

[0045] When the storage unit stores the capacitor voltage state after data is written, the read pulse signal can turn on the read enable device 5, and a current will be generated at both ends of the storage unit. When the storage unit stores the capacitor voltage state in the initial state, the read pulse signal cannot turn on the read enable device 5, and no current will be generated at both ends of the storage unit. The information stored in the memory can be determined by judging whether a read current is generated. At the same time, the information stored in the dynamic memory is stored in the capacitor 6 in the form of charge, and the storage state can be determined by distinguishing the amount of charge stored in the capacitor 6.

[0046] In an exemplary embodiment, the stored information is stored in the capacitor 6 in the form of electric charge, and the storage state can be determined by distinguishing the amount of electric charge stored in the capacitor 6 .

[0047] In an exemplary embodiment, the write gating device 4 has a first holding voltage in the conduction direction, and the first holding voltage is less than or equal to the conduction threshold voltage of the write gating device 4. The read gating device 5 has a second holding voltage in the conduction direction, and the second holding voltage is less than or equal to the conduction threshold voltage of the read gating device 5.

[0048] In another exemplary embodiment of the present invention, a method for operating a dynamic memory structure is provided, the method comprising: when data writing is required, applying a write pulse signal between the second end 1 of the write gate device and the second end 3 of the capacitor; the potential 1 of the second end of the write gate device is higher than the potential of the second end 3 of the capacitor; and the difference between the write pulse signal and the capacitor voltage in the initial state is higher than the conduction threshold voltage of the write gate device 4. The write pulse signal can turn on the write gate device 4, and the write gate device 4 becomes a low-resistance state, so that the capacitor 6 can be charged and information can be written.

[0049] When data reading is required, a read pulse signal is applied between the second end 2 of the read enable device and the second end 3 of the capacitor; the potential of the second end 2 of the read enable device is less than the potential of the second end 3 of the capacitor; and when the capacitor 6 stores the capacitor voltage after data writing is completed, current will be generated at both ends of the capacitor 6, and when the capacitor 6 stores the capacitor voltage in the initial state, no current will be generated at both ends of the capacitor 6.

[0050] As an optional implementation, after the data writing is completed, the voltage calculation formula of the capacitor is: Vc1=Vwrite-Vhold1.

[0051] Wherein, Vc1 is the capacitor voltage after data writing is completed, Vwrite is the write pulse signal, and Vhold1 is the first hold voltage. The capacitor voltage in the initial state and the capacitor voltage after data writing are completed correspond to two stored logic states respectively.

[0052] As an optional implementation, when a data read operation is required, the read voltage pulse satisfies the following relationship: Vread+Vc0<Vth2.

[0053] Vread+Vc1>Vth2.

[0054] Wherein, Vread is a read voltage pulse, Vc0 is a capacitor voltage in an initial state, Vc1 is a capacitor voltage after data writing is completed, and Vth2 is a turn-on threshold voltage of a read-enabling device.

[0055] When the storage unit stores the capacitor voltage state after data is written, the read pulse signal can turn on the read enable device 5, and a current will be generated at both ends of the storage unit. When the storage unit stores the capacitor voltage state in the initial state, the read pulse signal cannot turn on the read enable device 5, and no current will be generated at both ends of the storage unit. The information stored in the memory can be determined by judging whether a read current is generated. At the same time, the information stored in the dynamic memory is stored in the capacitor 6 in the form of charge, and the storage state can be determined by distinguishing the amount of charge stored in the capacitor 6.

[0056] The structure of the traditional 1S1C memory is improved in the present invention. Originally, data writing and reading share the same gating device, so the gating device must be bidirectionally conductive, and there are very few types of bidirectionally conductive gating devices, resulting in few types of gating devices that can be selected for the 1S1C memory. The present invention configures special gating devices for writing and reading respectively, and the gating devices only need to have unidirectional threshold switching characteristics, which greatly increases the types of gating devices that can be selected for the memory. And the conduction threshold voltage of the write gating device is made smaller than the conduction threshold voltage of the read gating device, so that the subthreshold leakage current of the read gating device can be greatly reduced, so that the charge in the capacitor can be stored for a longer time, and the data retention time of the memory is improved.

[0057] The following is further described in detail in conjunction with the preferred embodiments: like Figure 2 The IV characteristic curves of the write enable device and the read enable device using the 2S1C unit structure proposed in the present invention are shown, wherein Sw is the write enable device and Sr is the read enable device; the threshold voltage of the Sw write enable device is about 1.75V and the holding voltage is about 1.3V, the threshold voltage of the Sr read enable device is about 2.75V and the holding voltage is about 2.1V, the threshold voltage of the read enable device is higher than the threshold voltage of the write enable device, and under the same bias conditions, the read enable device has a smaller leakage current than the write enable device; when When performing a write operation, a 2.5V write voltage is applied between the second end of the write gate device and the second end of the capacitor, and the voltage of the write capacitor is 2.5V-1.3V=1.2V. After the write is completed, for the bias generated by the capacitor potential, the write gate device is in a reverse cutoff state at this time, with a very low leakage current. Therefore, the data retention time of the storage unit mainly depends on the read gate device. For the read gate device, it is in a forward bias at this time, and the leakage current is about 10nA. Therefore, the storage unit will have a relatively long data retention time, such as Figure 3 As shown, the data loss of the storage unit is determined when the capacitor voltage decays to 0.2V, and the storage unit can achieve a data retention time of 23ms.

[0058] If the traditional 1S1C structure is used, after the data is written, the voltage of the capacitor is 1.2V. For the bias voltage generated by the capacitor potential, the leakage current of the gating device is about 100nA at this time, so the storage unit will have a shorter data retention time, such as Figure 3 As shown, the data retention time is less than 1 ms. Therefore, by adopting the novel memory cell structure proposed by the present invention, the data retention time of the novel dynamic memory can be greatly improved.

[0059] The present invention also provides an application scenario, which applies the operation method of the above-mentioned dynamic memory structure. Specifically: The operation method of the dynamic memory structure provided in this embodiment can be applied in the memory read and write scenario. The memory read and write scenario includes: a data writing link and a data reading link; when data needs to be written, a write pulse signal is applied between the second end of the write enable device and the second end of the capacitor; the potential of the second end of the write enable device is higher than the potential of the second end of the capacitor; and the difference between the write pulse signal and the capacitor voltage in the initial state is higher than the conduction threshold voltage of the write enable device. When data needs to be read out, a read pulse signal is applied between the second end of the read enable device and the second end of the capacitor; the potential of the second end of the read enable device is less than the potential of the second end of the capacitor; and when the capacitor stores the capacitor voltage after the data is written, a current will be generated at both ends of the capacitor, and when the capacitor stores the capacitor voltage in the initial state, no current will be generated at both ends of the capacitor.

[0060] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A dynamic memory structure, characterized in that: The dynamic memory structure includes: a write gating device, a read gating device and a capacitor; The first end of the write gating device, the first end of the read gating device and the first end of the capacitor are connected together; the second end of the write gating device is a data writing end; the second end of the read gating device is a data reading end; the second end of the capacitor is a gating end, and the second end of the capacitor is connected to the word line; The write enable device and the read enable device are both unidirectionally conductive, and the conduction modes of the write enable device and the read enable device are both threshold-on; the threshold-on means that only when the potential of the second end of the write enable device is higher than the potential of the first end of the write enable device by the conduction threshold voltage of the write enable device, the write enable device will be turned on, and the current will flow from the second end of the write enable device to the first end of the write enable device, otherwise the write enable device will remain in the closed state; only when the potential of the first end of the read enable device is higher than the potential of the second end of the read enable device by the conduction threshold voltage of the read enable device, the read enable device will be turned on, and the current will flow from the first end of the read enable device to the second end of the read enable device, otherwise the read enable device will remain in the closed state; wherein, the conduction threshold voltage of the write enable device is less than the conduction threshold voltage of the read enable device.

2. The dynamic memory structure according to claim 1, characterized in that: When data writing is required, a write pulse signal is applied between the second end of the write enable device and the second end of the capacitor; the potential of the second end of the write enable device is higher than the potential of the second end of the capacitor; and the difference between the write pulse signal and the capacitor voltage in the initial state is higher than the turn-on threshold voltage of the write enable device.

3. The dynamic memory structure according to claim 1, characterized in that: When data reading is required, a read pulse signal is applied between the second end of the read enable device and the second end of the capacitor; the potential of the second end of the read enable device is less than the potential of the second end of the capacitor; and when the capacitor stores the capacitor voltage after data writing is completed, current will be generated at both ends of the capacitor, and when the capacitor stores the capacitor voltage in the initial state, no current will be generated at both ends of the capacitor.

4. The dynamic memory structure according to claim 1, characterized in that: The stored information is stored in the form of electric charge in the capacitor.

5. The dynamic memory structure according to claim 1, characterized in that: The write gate device has a first holding voltage in a conduction direction, and the first holding voltage is less than or equal to a conduction threshold voltage of the write gate device.

6. The dynamic memory structure according to claim 1, characterized in that: The read gating device has a second holding voltage in a conducting direction, and the second holding voltage is less than or equal to a conduction threshold voltage of the read gating device.

7. The dynamic memory structure according to claim 1, characterized in that: The write gating device and the read gating device are gating devices with unidirectional threshold switching characteristics.

8. An operating method based on the dynamic memory structure according to any one of claims 1 to 7, characterized in that: The operation method of the dynamic memory structure includes: When data writing is required, a write pulse signal is applied between the second end of the write gate device and the second end of the capacitor; the potential of the second end of the write gate device is higher than the potential of the second end of the capacitor; and the difference between the write pulse signal and the capacitor voltage in the initial state is higher than the conduction threshold voltage of the write gate device; When data reading is required, a read pulse signal is applied between the second end of the read enable device and the second end of the capacitor; the potential of the second end of the read enable device is less than the potential of the second end of the capacitor; and when the capacitor stores the capacitor voltage after data writing is completed, current will be generated at both ends of the capacitor, and when the capacitor stores the capacitor voltage in the initial state, no current will be generated at both ends of the capacitor.

9. The method for operating a dynamic memory structure according to claim 8, characterized in that: After the data is written, the voltage calculation formula of the capacitor is: Vc1=Vwrite-Vhold1; Wherein, Vc1 is the capacitor voltage after data writing is completed, Vwrite is the write pulse signal, and Vhold1 is the first holding voltage.

10. The method for operating a dynamic memory structure according to claim 8, characterized in that: When a data read operation is required, the read voltage pulse satisfies the following relationship: Vread+Vc0<Vth2; Vread+Vc1>Vth2; Wherein, Vread is a read voltage pulse, Vc0 is a capacitor voltage in an initial state, Vc1 is a capacitor voltage after data writing is completed, and Vth2 is a turn-on threshold voltage of a read-enabling device.

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