A dynamic random access memory and its preparation method

Abstract

This invention relates to a dynamic random access memory (DRAM) that integrates vertical-channel thin-film transistors (TFTs) and capacitors. The low leakage current of TFTs improves the data retention time of the DRAM, while the vertical channel achieves 4F... 2 The invention also relates to a method for fabricating the aforementioned dynamic random access memory (DRAM).

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and more specifically to a dynamic random access memory and its fabrication method. Background Technology

[0002] Traditional Dynamic Random Access Memory (DRAM) uses a 1-transistor-1-capacitor (1T-1C) structure as the chip's memory cell. The transistor is a horizontal-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Through continuous architectural evolution, the area of ​​a modern DRAM memory cell is now 6F. 2 (F is the feature size). However, with the continuation of Moore's Law, the area reduction of traditional DRAM has encountered a bottleneck.

[0003] To reach 4F 2 To reduce the storage cell area, researchers proposed a cell structure comprising one silicon-based vertical nanowire transistor and one capacitor. However, this nanowire transistor exhibits significant leakage current, resulting in a short data retention time for the DRAM.

[0004] Therefore, there is a need to develop a new 1T-1C dynamic random access memory (DRAM) with low transistor leakage current and a storage cell area of ​​up to 4F. 2 . Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a dynamic random access memory (DRAM) that integrates vertical-channel thin-film transistors (TFTs) and capacitors. The low leakage current characteristic of TFTs improves the data retention time of the DRAM, while the vertical channel achieves 4F... 2 The area of ​​the storage unit.

[0006] Another object of the present invention is to provide a method for preparing the dynamic random access memory.

[0007] To achieve the above objectives, the present invention provides the following technical solution.

[0008] A dynamic random access memory, comprising:

[0009] Substrate;

[0010] A first insulating layer is disposed on the upper surface of the substrate;

[0011] The first electrode layer is disposed on the upper surface of the first insulating layer;

[0012] A dielectric layer is disposed on the upper surface of the first electrode layer;

[0013] A second electrode layer is disposed on the upper surface of the dielectric layer;

[0014] One or more sandwich structures, each sandwich structure covering a portion of the upper surface of the second electrode layer, each sandwich structure comprising: a second insulating layer, a gate layer, and a third insulating layer stacked sequentially from bottom to top;

[0015] A gate dielectric layer covering the side surface of the gate layer;

[0016] A channel layer, covering a portion of the upper surface of the second electrode layer and in contact with the gate dielectric layer; and

[0017] The third electrode layer covers the upper surface of the channel layer.

[0018] This invention also provides a method for preparing a dynamic random access memory, comprising:

[0019] Provide substrate;

[0020] A first insulating layer is formed on the upper surface of the substrate;

[0021] A first electrode layer is formed on the upper surface of the first insulating layer;

[0022] A dielectric layer is formed on the upper surface of the first electrode layer;

[0023] A second electrode layer is formed on the upper surface of the dielectric layer;

[0024] A second insulating layer, a gate layer, and a third insulating layer are formed sequentially from bottom to top on the upper surface of the second electrode layer;

[0025] The second insulating layer, the gate layer, and the third insulating layer are etched to make the three layers conformal, and a portion of the upper surface of the second electrode layer is exposed to form a first window;

[0026] A gate dielectric layer is deposited at the first window such that the gate dielectric layer covers the side surface of the gate layer;

[0027] The gate dielectric layer is etched to expose a portion of the upper surface of the second electrode layer, forming a second window, wherein the sidewall of the second window is a part of the gate dielectric layer;

[0028] A channel layer is formed at the second window, covering a portion of the upper surface of the second electrode layer and contacting the gate dielectric layer; and

[0029] A third electrode layer is formed on the upper surface of the channel layer.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] 1. This invention provides a dynamic random access memory (DRAM) that integrates vertical-channel thin-film transistors (TFTs) and capacitors. The low leakage current characteristic of TFTs improves the data retention time of the DRAM, while the vertical channel achieves 4F... 2 The area of ​​the storage unit.

[0032] 2. The present invention uses the second electrode layer of the capacitor as the source or drain of the thin film transistor, which can further reduce the area of ​​the memory cell and minimize the vertical height occupied.

[0033] 3. The capacitor of the present invention is disposed below the thin-film transistor in the vertical channel, so the capacitor can be fabricated first and then the thin-film transistor can be fabricated. This helps to avoid the adverse effects of the high-temperature process of the capacitor on the electrical characteristics of the thin-film transistor, and thus helps to improve the electrical characteristics of the DRAM memory cell.

[0034] 4. The capacitor of the present invention can be made of hafnium oxide-based ferroelectric materials such as HfZrO or HfAlO, which have a high dielectric constant.

[0035] 5. Compared with existing silicon-based vertical nanowire transistors, the vertical channel thin film transistor of the present invention has a simpler fabrication process and lower production cost. Attached Figure Description

[0036] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0037] Figure 1 This is a schematic diagram of the structure of the dynamic random access memory of the present invention.

[0038] Figure 2 for Figure 1 The diagram shows the storage principle of the structure shown.

[0039] Figure 3-12 The diagram shows the structure obtained in each step of the preparation method provided by this invention.

[0040] Explanation of reference numerals in the attached figures

[0041] 100 is the substrate, 200 is the first insulating layer, 300 is the first electrode layer, 400 is the dielectric layer, 500 is the second electrode layer, 600 is the second insulating layer, 700 is the gate layer, 800 is the third insulating layer, 900a is the first gate dielectric layer, 900b is the second gate dielectric layer, 1000 is the channel layer, 1100 is the third electrode layer, 1200 is the first window, 1300 is the second window, and 1400 is the sandwich structure. Detailed Implementation

[0042] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0043] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0044] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0045] Existing storage cell area reaches 4F 2 The dynamic random access memory uses a silicon-based vertical nanowire transistor and a capacitor as the storage unit. This nanowire transistor has a large leakage current, and the data retention time of DRAM is relatively short.

[0046] Therefore, the present invention provides, as follows Figure 1The illustrated dynamic random access memory includes: a substrate 100; a first insulating layer 200 disposed on the upper surface of the substrate 100; a first electrode layer 300 disposed on the upper surface of the first insulating layer 200; a dielectric layer 400 disposed on the upper surface of the first electrode layer 300; a second electrode layer 500 disposed on the upper surface of the dielectric layer 400; one or more sandwich structures, each sandwich structure covering a portion of the upper surface of the second electrode layer 500, each sandwich structure including: a second insulating layer 600, a gate layer 700, and a third insulating layer 800 stacked sequentially from bottom to top; a gate dielectric layer covering the side surface of the gate layer 700; a channel layer 1000 covering a portion of the upper surface of the second electrode layer 500 and in contact with the gate dielectric layer; and a third electrode layer 1100 covering the upper surface of the channel layer 1000.

[0047] The dynamic random access memory (DRAM) of this invention integrates vertical-channel thin-film transistors (TFTs) and capacitors. The low leakage current characteristic of TFTs improves the data retention time of the DRAM, while the vertical channel achieves 4F... 2 The area of ​​the storage unit.

[0048] The dynamic random access memory (DRAM) of this invention can be functionally divided into three regions from bottom to top: a substrate, a capacitor, and a thin-film transistor (TFT). The capacitor includes a first electrode layer 300, a dielectric layer 400, and a second electrode layer 500. The TFT includes a second insulating layer 600, a gate layer 700, a third insulating layer 800, gate dielectric layers 900a and 900b, a channel layer 1000, and a third electrode layer 1100. The second electrode layer 500 in the capacitor also serves as the source or drain of the TFT, meaning the capacitor and TFT share a single electrode. This arrangement further reduces the area of ​​the memory cell, minimizing the vertical height occupied.

[0049] The substrate 100 of the present invention can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon, germanium, germanium silicon, or gallium arsenide.

[0050] In terms of material selection, each layer of the dynamic random access memory of the present invention can be made of any material that can realize its basic function, but in order to further improve the electrical performance and performance of the memory, each layer has its preferred material.

[0051] For example, the first insulating layer 200, the second insulating layer 600, and the third insulating layer 800 can be dielectric materials such as oxides and nitrides, such as typical SiO2 or Si3N4. The first insulating layer 200, the second insulating layer 600, and the third insulating layer 800 are preferably silicon oxide, which facilitates large-area deposition.

[0052] The dielectric layer 400 serves as insulation and charge storage between the first electrode layer 300 and the second electrode layer 500. It is preferably made of a wide bandgap and high dielectric constant material, or a material suitable for fabricating extremely small devices, such as one or more combinations of HfO2, Al2O3, La2O3 and ZrO2, or the gate dielectric layer is a ferroelectric material with a dielectric constant of 30-60; preferably, the ferroelectric material is HfZrO or HfAlO.

[0053] The gate dielectric layers 900a and 900b can be dielectric materials such as oxides and nitrides, for example, typical SiO2. Of course, the gate dielectric layers can also be materials with wide bandgap and high dielectric constant, or materials suitable for fabricating extremely small devices, such as one or more combinations of SiO2, HfO2, Al2O3, La2O3, and ZrO2. The gate dielectric layer can be made of the same or different materials as the second insulating layer 600 and the third insulating layer 800.

[0054] The channel layer 1000 can be indium gallium zinc oxide (IGZO), zinc oxide, or indium aluminum zinc oxide, preferably IGZO. Because IGZO thin-film transistors have very low off-state leakage current, the information stored in the node can be retained for a relatively long time.

[0055] The first electrode layer 300, the second electrode layer 500, the third electrode layer 1100, and the gate layer 700 serve as electrodes to be connected to a power source, and are preferably made of materials with good conductivity. Common high-performance conductive materials include, but are not limited to, Mo, Ti, W, or titanium nitride.

[0056] Considering the speed and stability of current transfer between electrodes, the first electrode layer 300, the second electrode layer 500, and the third electrode layer 1100 use the same electrode material. In some specific embodiments, the first electrode layer 300, the second electrode layer 500, the third electrode layer 1100, and the gate layer 700 use the same electrode material.

[0057] In some specific embodiments, the channel layer 1000 is flush with the upper surface of the third insulating layer 800 and the gate dielectric layer.

[0058] In a preferred embodiment of the present invention, the dynamic random access memory includes two sandwich structures 1400; the gate dielectric layer includes a first gate dielectric layer 900a and a second gate dielectric layer 900b, the first gate dielectric layer 900a covering one side surface of the gate layer 700 in one sandwich structure 1400, and the second gate dielectric layer 900b covering one side surface of the gate layer 700 in the other sandwich structure 1400; the two side surfaces of the channel layer 1000 are in contact with the first gate dielectric layer 900a and the second gate dielectric layer 900b, respectively, such that one sandwich structure 1400, the first gate dielectric layer 900a, the channel layer 1000, the second gate dielectric layer 900b, and the other sandwich structure 1400 form a sandwich structure. This arrangement allows the channel layer 1000 to be controlled by the voltage of the gate layer 700 in the two sandwich structures, which can effectively improve the control capability of the gate electrode.

[0059] In a preferred embodiment of the present invention, the channel layer may be cylindrical or square, the gate dielectric layer surrounds the channel layer, and the sandwich structure surrounds the gate dielectric layer.

[0060] The working principle of the dynamic random access memory of the present invention is as follows: Figure 2 As shown, the dynamic random access memory (DRAM) consists of two parts: a capacitor and a MOSFET. The capacitor, as a charge storage unit, can store 1 bit of data. The amount of charge (potential level) after charging and discharging corresponds to binary data 0 and 1, respectively. The MOSFET, as a selector, controls the charging and discharging of the capacitor. The voltage level of the word line (WL) controls the switching of the MOSFET, storing information from the bit line (BL) into the capacitor or reading information from the capacitor to the bit line (BL).

[0061] This invention also provides a method for preparing a dynamic random access memory, combined with... Figure 3-12 The specific process is as follows.

[0062] First, a substrate 100 is provided, such as Figure 3 As shown.

[0063] Then, a first insulating layer 200 is formed on the upper surface of the substrate 100, resulting in a structure as shown in Figure 100. Figure 4 As shown.

[0064] The first insulating layer 200 can be formed by physical vapor deposition or chemical vapor deposition.

[0065] Subsequently, a first electrode layer 300 is formed on the upper surface of the first insulating layer 200, resulting in the structure shown below. Figure 5 As shown.

[0066] The first electrode layer 300 can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0067] Next, a dielectric layer 400 is formed on the upper surface of the first electrode layer 300, resulting in the structure shown below. Figure 6 As shown.

[0068] Atomic layer deposition can be used to form the dielectric layer 400.

[0069] Then, a second electrode layer 500 is formed on the upper surface of the dielectric layer 400, resulting in a structure as shown in Figure 500. Figure 7 As shown.

[0070] The second electrode layer 500 can be formed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0071] In some specific embodiments, the method for forming the dielectric layer 400 includes: depositing HfZrO or HfAlO using atomic layer deposition; and after forming the second electrode layer 500, the preparation method further includes rapid thermal annealing to give HfZrO or HfAlO ferroelectric properties.

[0072] Subsequently, a second insulating layer 600, a gate layer 700, and a third insulating layer 800 are sequentially formed from bottom to top on the upper surface of the second electrode layer 500, resulting in the structure shown below. Figure 8 As shown.

[0073] The second insulating layer 600 and the third insulating layer 800 can be formed by physical vapor deposition or chemical vapor deposition.

[0074] The gate layer 700 can be formed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0075] Next, the second insulating layer 600, the gate layer 700 and the third insulating layer 800 are etched to make the three layers conformal, and a portion of the upper surface of the second electrode layer 500 is exposed to form the first window 1200.

[0076] In this step, the etching process employs photolithography and etching techniques. In some specific embodiments, the second insulating layer 600, the gate layer 700, and the third insulating layer 800 are etched to make the three layers conformal and form two sandwich structures 1400; each sandwich structure 1400 covers a portion of the upper surface of the second electrode layer 500, and each sandwich structure 1400 includes: the second insulating layer 600, the gate layer 700, and the third insulating layer 800 stacked sequentially from bottom to top, and a first window 1200 is located between the two sandwich structures 1400, resulting in the following structure: Figure 9As shown. In some other embodiments, the second insulating layer 600, the gate layer 700, and the third insulating layer 800 are etched to make the three layers conformal and form an annular sandwich structure; the annular sandwich structure covers part of the upper surface of the second electrode layer 500, and the annular sandwich structure includes: the second insulating layer 600, the gate layer 700, and the third insulating layer 800 stacked sequentially from bottom to top, and a first window 1200 is located inside the annular sandwich structure, the first window 1200 being circular or square.

[0077] Subsequently, a gate dielectric layer is deposited at the first window 1200, such that the gate dielectric layer covers the side surface of the gate layer 700, resulting in the structure shown below. Figure 10 As shown.

[0078] In this step, the deposition process employs physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0079] Then, the gate dielectric layer is etched to expose a portion of the upper surface of the second electrode layer 500, forming a second window 1300, the sidewall of which is part of the gate dielectric layer.

[0080] In this step, the etching process employs photolithography and etching techniques. In some specific embodiments, such as Figure 11 As shown, the second window 1300 is a groove that exposes part of the upper surface of the second electrode layer 500.

[0081] Next, a channel layer 1000 is formed at the second window 1300, covering a portion of the upper surface of the second electrode layer 500 and contacting the gate dielectric layer.

[0082] The channel layer 1000 can be formed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In some specific embodiments, such as... Figure 12 As shown, the channel layer 1000 is flush with the upper surfaces of the third insulating layer 800, the first gate dielectric layer 900a, and the second gate dielectric layer 900b.

[0083] Finally, a third electrode layer 1100 is formed on the upper surface of the channel layer 1000, resulting in the structure shown below. Figure 1 As shown.

[0084] The third electrode layer 1100 can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0085] The capacitor of the present invention is disposed below the thin-film transistor in the vertical channel, so the capacitor can be fabricated first and then the thin-film transistor can be fabricated. This helps to avoid the adverse effects of the high-temperature process of the capacitor on the electrical characteristics of the thin-film transistor, and thus helps to improve the electrical characteristics of the DRAM memory cell.

[0086] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dynamic random access memory, characterized in that, include: Substrate; A first insulating layer is disposed on the upper surface of the substrate; Capacitor; The capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer; The first electrode layer is disposed on the upper surface of the first insulating layer; A dielectric layer is disposed on the upper surface of the first electrode layer; A second electrode layer is disposed on the upper surface of the dielectric layer; Thin-film transistors; The second electrode layer of the capacitor serves as the source or drain of a thin-film transistor. The thin-film transistor includes: One or more sandwich structures, each sandwich structure covering a portion of the upper surface of the second electrode layer, each sandwich structure comprising: a second insulating layer, a gate layer, and a third insulating layer stacked sequentially from bottom to top; A gate dielectric layer covering the side surface of the gate layer; A channel layer that covers a portion of the upper surface of the second electrode layer and is in contact with the gate dielectric layer; and a third electrode layer that covers the upper surface of the channel layer.

2. The dynamic random access memory according to claim 1, characterized in that, Includes two of the aforementioned sandwich structures; The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer covers one side surface of the gate layer in one of the sandwich structures, and the second gate dielectric layer covers one side surface of the gate layer in the other sandwich structure. The two side surfaces of the channel layer are in contact with the first gate dielectric layer and the second gate dielectric layer, respectively, such that one of the sandwich structures, the first gate dielectric layer, the channel layer, the second gate dielectric layer and the other sandwich structure are formed into a sandwich structure.

3. The dynamic random access memory according to claim 1 or 2, characterized in that, The channel layer can be cylindrical or square, the gate dielectric layer surrounds the channel layer, and the sandwich structure surrounds the gate dielectric layer.

4. The dynamic random access memory according to claim 1 or 2, characterized in that, The first electrode layer, the second electrode layer, the third electrode layer, and the gate layer are one or more combinations of Mo, Ti, W, and titanium nitride, respectively.

5. The dynamic random access memory according to claim 1 or 2, characterized in that, The first insulating layer, the second insulating layer, and the third insulating layer are SiO2 or Si3N4, respectively; The dielectric layer is one or more of HfO2, Al2O3, La2O3 and ZrO2, or the gate dielectric layer is a ferroelectric material with a dielectric constant of 30-60. The gate dielectric layer is one or more of SiO2, HfO2, Al2O3, La2O3 and ZrO2; The channel layer is indium gallium zinc oxide, indium zinc oxide, indium tungsten oxide, zinc oxide, or indium aluminum zinc oxide.

6. The dynamic random access memory according to claim 5, characterized in that, The ferroelectric material is HfZrO or HfAlO.

7. A method for fabricating a dynamic random access memory, characterized in that, include: Provide substrate; A first insulating layer is formed on the upper surface of the substrate; A first electrode layer is formed on the upper surface of the first insulating layer; A dielectric layer is formed on the upper surface of the first electrode layer; A second electrode layer is formed on the upper surface of the dielectric layer; A second insulating layer, a gate layer, and a third insulating layer are formed sequentially from bottom to top on the upper surface of the second electrode layer; The second insulating layer, the gate layer, and the third insulating layer are etched to make the three layers conformal, and a portion of the upper surface of the second electrode layer is exposed to form a first window; A gate dielectric layer is deposited at the first window such that the gate dielectric layer covers the side surface of the gate layer; The gate dielectric layer is etched to expose a portion of the upper surface of the second electrode layer, forming a second window, wherein the sidewall of the second window is a part of the gate dielectric layer; A channel layer is formed at the second window, covering a portion of the upper surface of the second electrode layer and contacting the gate dielectric layer; as well as A third electrode layer is formed on the upper surface of the channel layer.

8. The preparation method according to claim 7, characterized in that, The second insulating layer, the gate layer, and the third insulating layer are etched to make the three layers conformal and form two sandwich structures; each sandwich structure covers a portion of the upper surface of the second electrode layer, and each sandwich structure includes: a second insulating layer, a gate layer, and a third insulating layer stacked sequentially from bottom to top, and the first window is located between the two sandwich structures.

9. The preparation method according to claim 7, characterized in that, The second insulating layer, the gate layer, and the third insulating layer are etched to make the three layers conformal and form a ring sandwich structure; The annular sandwich structure covers part of the upper surface of the second electrode layer. The annular sandwich structure includes a second insulating layer, a gate layer, and a third insulating layer stacked sequentially from bottom to top. The first window is located inside the annular sandwich structure and is circular or square.

10. The preparation method according to any one of claims 7-8, characterized in that, The first insulating layer, the second insulating layer, and the third insulating layer are formed using physical vapor deposition or chemical vapor deposition. The dielectric layer and the gate dielectric layer are formed using atomic layer deposition (ALD). The first electrode layer, the second electrode layer, the third electrode layer, the gate layer, and the channel layer are formed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

11. The preparation method according to any one of claims 7-8, characterized in that, The method for forming the dielectric layer includes: depositing HfZrO or HfAlO using atomic layer deposition; and after forming the second electrode layer, the preparation method further includes rapid thermal annealing to give HfZrO or HfAlO ferroelectric properties.

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