Pre-doping process test structure, manufacturing method thereof and pre-doping process test method

Abstract

The application provides a pre-doping process test structure, a manufacturing method thereof and a pre-doping process test method. The pre-doping process test structure comprises: a substrate, the substrate is defined with an active region, and the active region comprises a first region and a second region; a pre-doping gate is formed on the surface of the active region of the first region, the pre-doping gate extends along a first direction and has a first critical dimension along a second direction; wherein the first direction and the second direction form an included angle; a non-pre-doping gate is formed on the surface of the active region of the second region, the non-pre-doping gate extends along the first direction and has a second critical dimension along the second direction; wherein by testing the first critical dimension and the second critical dimension, a critical dimension deviation caused by the pre-doping process can be obtained. The above technical solution measures the first critical dimension and the second critical dimension by setting two regions in one pre-doping process test structure, and obtains the critical dimension deviation caused by the doping process to monitor the etching deviation.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a pre-doped process test structure and its fabrication method, as well as a pre-doped process test method. Background Technology

[0002] Polysilicon depletion refers to the phenomenon where a voltage applied to the gate attracts minority carriers to the interface between the dielectric and the channel, causing carrier accumulation at the polysilicon-dielectric interface and resulting in the depletion of charge in the nearby semiconductor region. For example... Figure 1 As shown, charge depletion is equivalent to the formation of a depletion layer 13 at the interface between polysilicon 11 and dielectric layer 12, leading to an increase in the electrical thickness of dielectric layer 11 and a decrease in drive current capability. Therefore, when using Poly as the gate, NMOS Poly pre-doping is used to increase the depletion region capacitance and enhance gate control capability. In the 90nm to 40nm process nodes, most only NMOS uses pre-doping, while PMOS does not. However, common critical dimension bars (CD bars) and NMOS test keys only have one type of pre-doping design, such as... Figure 2 As shown, traditional CD bar designs can only monitor CDs with full pre-doping or non-pre-doping Poly Etching (ET) processes.

[0003] Therefore, optimizing the test structure to simultaneously monitor the critical dimensions of both pre-doped and undoped materials is a problem that needs to be solved. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to optimize the test structure to simultaneously monitor the critical dimensions of pre-doped and non-pre-doped processes, and to provide a pre-doped process test structure and its fabrication method, as well as a pre-doped process test method.

[0005] To address the aforementioned problems, this invention provides a pre-doped process test structure, comprising: a substrate having an active region defined therein, the active region including a first region and a second region; a pre-doped gate formed on the surface of the active region in the first region, the pre-doped gate extending along a first direction and having a first critical dimension along a second direction; wherein the first direction and the second direction form an angle; and a non-pre-doped gate formed on the surface of the active region in the second region, the non-pre-doped gate extending along the first direction and having a second critical dimension along the second direction; wherein, by testing the first critical dimension and the second critical dimension, the critical dimension deviation caused by the pre-doping process can be obtained.

[0006] To address the aforementioned problems, this invention provides a method for fabricating a pre-doped test structure. The method includes the following steps: providing a substrate in which an active region is defined, the active region comprising a first region and a second region; forming a dielectric layer on the surface of the active region and depositing a polysilicon layer on the surface of the dielectric layer; performing a pre-doping process on the polysilicon layer of the first region; patterning the polysilicon layer to form a pre-doped gate on the surface of the active region of the first region and a non-pre-doped gate on the surface of the active region of the second region, wherein the pre-doped gate extends along a first direction and has a first critical dimension along a second direction, and the non-pre-doped gate extends along the first direction and has a second critical dimension along the second direction, the first direction and the second direction forming an angle.

[0007] To address the aforementioned problems, this invention provides a pre-doping process testing method, comprising the following steps: providing a first testing unit, wherein the first testing unit adopts the first testing unit described in this invention; measuring a first critical dimension of the pre-doped gate and a second critical dimension of the non-pre-doped gate; obtaining the difference between the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate to obtain the critical dimension deviation caused by the pre-doping process.

[0008] The above technical solution sets two regions in a pre-doped process test structure to measure the first critical dimension and the second critical dimension respectively, obtains the difference between the first critical dimension and the second critical dimension to obtain the critical dimension deviation caused by the doping process, and then obtains a pre-doped gate and a non-pre-doped gate with consistent critical dimensions by setting the deviation value in advance in the etching process.

[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the accompanying drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0011] Figure 1 This is a schematic diagram of polysilicon depletion in transistors in the prior art.

[0012] Figure 2This is a schematic diagram of the structure of a key dimension test unit in the prior art.

[0013] Figure 3 This is a schematic diagram of the first embodiment of the pre-doped process test structure described in this invention.

[0014] Figure 4 This is a flowchart illustrating the steps of an embodiment of the method for fabricating a pre-doped test structure according to the present invention.

[0015] Figure 5A This is a schematic diagram of a substrate structure provided as an embodiment of the method for fabricating a pre-doped test structure according to the present invention.

[0016] Figure 5B This is a schematic diagram of a polycrystalline silicon layer deposited on the substrate surface, representing an embodiment of the method for fabricating a pre-doped test structure according to the present invention.

[0017] Figure 5C This is a schematic diagram of the structure of the polycrystalline silicon layer in the first region being subjected to a pre-doping process, according to an embodiment of the method for fabricating the pre-doped test structure of the present invention.

[0018] Figure 5D This is a graphical schematic diagram of the polycrystalline silicon layer, representing an embodiment of the method for fabricating a pre-doped test structure according to the present invention.

[0019] Figure 6 This is a schematic diagram of the second embodiment of the pre-doped process test structure described in this invention.

[0020] Figure 7 This is a schematic diagram of the third embodiment of the pre-doped process test structure described in this invention.

[0021] Figure 8 This is a schematic diagram of the edge shading in the pre-doping process in the prior art.

[0022] Figure 9 This is a schematic diagram of the fourth embodiment of the pre-doped process test structure described in this invention.

[0023] Figure 10 This is a flowchart illustrating the steps of the first embodiment of the pre-doping process testing method described in this invention.

[0024] Figure 11 This is a flowchart illustrating the steps of a second embodiment of the pre-doping process testing method described in this invention.

[0025] Figure 12 This is a flowchart illustrating the steps of the third embodiment of the pre-doping process testing method described in this invention.

[0026] Figure 13This is a flowchart illustrating the steps of the fourth embodiment of the pre-doping process testing method described in this invention. Detailed Implementation

[0027] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Please see Figure 3 This is a schematic diagram of the first embodiment of the pre-doped process test structure described in this invention. Figure 3 As shown, the pre-doped process test structure includes: a substrate 30, an active region AA, a pre-doped gate 31, and a non-pre-doped gate 32. The active region AA is defined in the substrate 30, and includes a first region 301 and a second region 302. The pre-doped gate 31 is formed on the surface of the active region AA in the first region 301. The pre-doped gate 31 extends along a first direction D1 and has a first critical dimension CD1 along a second direction D2; wherein the first direction D1 and the second direction D2 form an angle. The non-pre-doped gate 32 is formed on the surface of the active region AA in the second region 302. The non-pre-doped gate 32 extends along the first direction D1 and has a second critical dimension CD2 along the second direction D2. By testing the first critical dimension CD1 and the second critical dimension CD2, the critical dimension deviation caused by the pre-doping process can be obtained.

[0029] In this embodiment, the first critical dimension CD1 is the critical dimension of any of the pre-doped gates 31 (i.e., the width of the pre-doped gate 31 along the second direction D2), and the second critical dimension CD2 is the critical dimension of any of the non-pre-doped gates 32 (i.e., the width of the non-pre-doped gate 32 along the second direction D2). In other embodiments, the first critical dimension is the average of the critical dimensions of all the pre-doped gates 31; and the second critical dimension is the average of the critical dimensions of all the non-pre-doped gates 32.

[0030] In this embodiment, two regions are set in a pre-doped process test structure to form a pre-doped gate 31 and a non-pre-doped gate 32, respectively. By measuring the first critical dimension CD1 of the pre-doped gate 31 and the second critical dimension CD2 of the non-pre-doped gate 32, the difference between the first critical dimension CD1 and the second critical dimension CD2 is obtained to obtain the critical dimension deviation caused by the doping process. Then, by setting the deviation value in advance in the etching process, a pre-doped gate and a non-pre-doped gate with consistent critical dimensions can be obtained.

[0031] Please see Figure 4 This is a flowchart illustrating the steps of an embodiment of the method for fabricating a pre-doped test structure according to the present invention. Figure 4 As shown, the fabrication method of the pre-doped test structure includes the following steps: Step S41, providing a substrate, wherein an active region is defined in the substrate, the active region including a first region and a second region; Step S42, forming a dielectric layer on the surface of the active region and depositing a polysilicon layer on the surface of the dielectric layer; Step S43, performing a pre-doping process on the polysilicon layer of the first region; Step S44, patterning the polysilicon layer to form a pre-doped gate on the surface of the active region of the first region and a non-pre-doped gate on the surface of the active region of the second region, wherein the pre-doped gate extends along a first direction and has a first critical dimension along a second direction, the non-pre-doped gate extends along the first direction and has a second critical dimension along the second direction, and the first direction and the second direction form an angle.

[0032] Please refer to Figure 5A And in step S41, a substrate 50 is provided, wherein an active region AA is defined in the substrate 50, and the active region AA includes a first region 501 and a second region 502. In this embodiment, the substrate 50 is a single-crystal silicon layer.

[0033] Please refer to Figure 5B In step S42, a dielectric layer 508 is formed on the surface of the active region AA, and a polysilicon layer 510 is deposited on the surface of the dielectric layer 508. In this embodiment, the dielectric layer 508 is a silicon oxide layer. The dielectric layer 508 is formed on the surface of the active region AA along the third direction D3.

[0034] Please refer to Figure 5C And in step S43, a pre-doping process is performed on the polysilicon layer 510 of the first region 501.

[0035] Please refer to Figure 3 and Figure 5D In step S44, the polysilicon layer 510 is patterned to form a pre-doped gate 51 on the surface of the active region AA in the first region 501 and a non-pre-doped gate 52 on the surface of the active region AA in the second region 502. The pre-doped gate 51 extends along a first direction D1 and has a first critical dimension CD1 along a second direction D2. The non-pre-doped gate 52 extends along the first direction D1 and has a second critical dimension CD2 along the second direction D2. The first direction D1 and the second direction D2 form an angle. The plane formed by the first direction D1 and the second direction D2 forms an angle with the third direction D3.

[0036] Please continue reading. Figure 3 In some embodiments, the pre-doped process test structure includes a first test unit 100, which includes a first region 301 and a second region 302 arranged side-by-side along the second direction D2. The first region 301 has a plurality of pre-doped gates 31, which extend along the first direction D1 and are arranged along the second direction D2. The second region 302 has a plurality of non-pre-doped gates 32, which also extend along the first direction D1 and are arranged along the second direction D2.

[0037] Please see Figure 6 This is a schematic diagram of the second embodiment of the pre-doped process test structure described in this invention. Figure 3 The embodiment shown differs in that the pre-doped process test structure includes a second test unit 200, which includes a plurality of first regions 601 and a plurality of second regions 602 arranged alternately along the second direction D2; a pre-doped gate 61 is formed in each first region 601; and a non-pre-doped gate 62 is formed in each second region 602. The pre-doped gate 61 extends along the first direction D1 and has a first critical dimension CD1 along the second direction D2; the non-pre-doped gate 62 extends along the first direction D1 and has a second critical dimension CD2 along the second direction D2. Figure 6 The second test unit 200 shown can also obtain the critical dimension deviation caused by the pre-doping process by testing the first critical dimension and the second critical dimension.

[0038] Please see Figure 7 This is a schematic diagram of the third embodiment of the pre-doped process test structure described in this invention. Figure 4 The embodiment shown differs from the one described above in that... Figure 7 In the second test unit 200 shown: multiple pre-doped gates 71 are connected in parallel to a first pad 731, and multiple non-pre-doped gates 72 are connected in parallel to a second pad 732. By applying test voltages to the first pad 731 and the second pad 732, the electrical parameters measured can be used to determine whether the pre-doping process has an electrical impact. Specifically, if the electrical parameters of the pre-doped gates 71 and the non-pre-doped gates 72 are the same, it is determined that the pre-doping process has no electrical impact; if the electrical parameters of the pre-doped gates 71 are different from those of the non-pre-doped gates 72, it is determined that the pre-doping process has an electrical impact. In this embodiment, multiple pre-doped gates 71 are connected in parallel to form the interdigitated gate of a multi-finger gate transistor, and multiple non-pre-doped gates 72 are connected in parallel to form the interdigitated gate of a multi-finger gate transistor.

[0039] In some embodiments, within the second test unit 200: a virtual gate 74 is formed in at least one second region 702 located at the edge of the active region AA, and the virtual gate 74 is electrically connected to a third pad 733; by applying a test voltage to the second pad 732 and the third pad 733, the validity of the test result can be determined based on the measured electrical parameters. If the difference between the electrical parameters of the virtual gate 74 and the electrical parameters of the undoped gate 72 is less than a preset threshold, the test result is deemed valid, and the determination of whether the predoping process has an electrical influence can continue. In this embodiment, the virtual gate 74 is a single transistor and can be used as a control group for the electrical testing of multi-finger gate transistors. In other embodiments, the virtual gate 74 may not be provided.

[0040] In some embodiments, the second test unit 200 further includes: a contact structure column located between the pre-doped gate 71 and the undoped gate 72, each contact structure column including a plurality of contact structures 75 arranged along a first direction. The contact structures 75 are conventional electrical structures, and the spacing between each contact structure 75 and an adjacent pre-doped gate 71 or undoped gate 72 is fixed and equal. In this embodiment, the contact structures 75 are located within the second region 702. In other embodiments, the contact structures 75 may also be located within the first region 701.

[0041] like Figure 8 As shown, in step S43 of the pre-doping process test structure fabrication method, when performing a pre-doping process on the polysilicon layer 89 of the first region 801, the proximity effect at the edge of the pre-doped region may affect the ion implantation amount due to the presence of the photoresist layer 88. Figure 8 As shown in reference numeral 87, the electrical optimization effect is not obvious. Therefore, the pre-doping process test structure of the present invention also provides a fourth embodiment to test whether the edge shading of the pre-doping process has an electrical effect.

[0042] Please see Figure 9 This is a schematic diagram of the fourth embodiment of the pre-doped process test structure described in this invention. Figure 9As shown, the pre-doped process test structure includes a third test unit 300, which includes a plurality of first regions 901 arranged at intervals along the second direction D2. A pre-doped gate 91 is formed in each first region 901, and there is a first distance from the edge of the pre-doped gate 91 to the edge of the first region 901 in the second direction D2. The first distances in the plurality of first regions 901 gradually increase. The value of the first distance in one of the first regions 901 is a standard value X1, and the value of the first distance in the other first regions 901 is a scaled value of the standard value X1 (such as 0.8*X1, 0.9*X1, 1.05*X1, etc.). By testing the electrical parameters of each pre-doped gate 91 in the third test unit 300, it is determined whether there is an electrical influence from the edge shadow of the pre-doped process.

[0043] If the first distance of the third test unit 300 with the optimal electrical parameters is the standard value X1, it is determined that the edge shadow of the pre-doping process has no effect on the electrical properties of the semiconductor structure; if the first distance of the third test unit with the optimal electrical parameters is a scaled value of the standard value X1 (such as 0.9*X1), it is determined that the edge shadow of the pre-doping process has an effect on the electrical properties of the semiconductor structure, and the value of the first distance is modified to the scaled value (i.e., 0.9*X1).

[0044] Wherein, the standard value X1 is the first distance obtained through existing technology. The above technical solution verifies whether there is an electrical influence on the edge shadow of the pre-doped process by setting scaling values ​​of multiple standard values ​​and measuring the electrical properties of multiple test structures, and obtains the optimal value of the first distance through testing.

[0045] Based on the same inventive concept, some embodiments of the present invention also provide a pre-doping process testing method.

[0046] Please see Figure 10 This is a flowchart illustrating the steps of the first embodiment of the pre-doping process testing method described in this invention. Figure 10 As shown, the pre-doping process testing method includes the following steps: Step S101, providing a first test unit, wherein the first test unit adopts the first test unit described in this invention; Step S102, measuring the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate; Step S103, obtaining the difference between the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate, so as to obtain the critical dimension deviation caused by the pre-doping process.

[0047] Please refer to Figure 3 And in step S101, a first test unit 100 is provided, the first test unit 100 employing the present invention. Figure 3The first test unit 100 is shown. In other embodiments, it may also be used. Figure 6 The second test unit 200 shown executes steps S102 to S103.

[0048] Please refer to Figure 3 And in step S102, the first critical dimension CD1 of the pre-doped gate 31 and the second critical dimension CD2 of the non-pre-doped gate 32 are measured.

[0049] Please refer to Figure 3 And in step S103, the difference between the first critical dimension of the pre-doped gate 31 and the second critical dimension CD2 of the non-pre-doped gate 32 is obtained to obtain the critical dimension deviation caused by the pre-doping process. In a pre-doping process test structure, two regions are set to form the pre-doped gate 31 and the non-pre-doped gate 32 respectively. By measuring the first critical dimension CD1 of the pre-doped gate 31 and the second critical dimension CD2 of the non-pre-doped gate 32, the difference between the first critical dimension CD1 and the second critical dimension CD2 is obtained to obtain the critical dimension deviation caused by the doping process. Then, by setting the deviation value in advance in the etching process, a pre-doped gate and a non-pre-doped gate with consistent critical dimensions can be obtained.

[0050] Please see Figure 11 This is a flowchart illustrating the steps of a second embodiment of the pre-doping process testing method described in this invention. Figure 11 As shown, the pre-doping process testing method further includes the following steps: Step S111, providing a second test unit, wherein the second test unit adopts the second test unit described in this invention; Step S112, applying a test voltage at the first pad and the second pad to measure the electrical parameters of the pre-doped gate and the non-pre-doped gate; Step S113, determining whether the pre-doping process has an electrical effect based on the electrical parameters of the pre-doped gate and the non-pre-doped gate.

[0051] Please refer to Figure 7 And in step S111, a second test unit 200 is provided, the second test unit 200 employing the present invention. Figure 7 The second test unit 200 is shown.

[0052] Please refer to Figure 7 And in step S112, a test voltage is applied at the first pad 731 and the second pad 732 to measure the electrical parameters of the pre-doped gate 71 and the undoped gate 72. In some embodiments, the electrical parameters are capacitance, breakdown voltage, or saturation current.

[0053] Please refer to Figure 7And in step S113, it is determined whether the predoping process has an electrical impact based on the electrical parameters of the predoped gate 71 and the undoped gate 72. In some embodiments, if the electrical parameters of the predoped gate 71 and the undoped gate 72 are the same, it is determined that the predoping process has no electrical impact; if the electrical parameters of the predoped gate 71 are different from those of the undoped gate 72, it is determined that the predoping process has an electrical impact. In this embodiment, multiple predoped gates 71 are connected in parallel to form the interdigitated gate of a multi-finger gate transistor, and multiple undoped gates 72 are connected in parallel to form the interdigitated gate of a multi-finger gate transistor.

[0054] In some embodiments, within the second test unit 200: a virtual gate 74 is formed in at least one second region 702 located at the edge of the active region AA, and the virtual gate 74 is electrically connected to a third pad 733; before step S112, the following steps are further included: applying a test voltage at the second pad 732 and the third pad 733 to measure electrical parameters; if the difference between the electrical parameters of the virtual gate 74 and the electrical parameters of the undoped gate 72 is less than a preset threshold, the test result is determined to be valid; and then step S112 is executed. In this embodiment, the virtual gate 74 is a single transistor, which can be used as a control group for the electrical testing of multi-finger gate transistors.

[0055] Please see Figure 12 This is a flowchart illustrating the steps of the third embodiment of the pre-doping process testing method described in this invention. Figure 12 As shown, the pre-doping process testing method further includes the following steps: Step S121, providing a plurality of second test units, wherein the pre-doped gates of the plurality of second test units have different doping amounts; Step S122, testing the electrical parameters of the pre-doped gates of the plurality of second test units respectively; Step S123, statistically analyzing the doping amounts of the second test units corresponding to the electrical parameters that meet the process requirements, so as to obtain the process window for the doping amount.

[0056] Please refer to Figure 7 And in step S121, multiple second test units 200 are provided, and the pre-doped gates 71 of the multiple second test units 200 have different doping amounts. The second test units 200 employ... Figure 7 The second test unit 200 is shown.

[0057] Please refer to Figure 7 And in step S122, the electrical parameters of the pre-doped gates 71 of the plurality of second test units 200 are tested respectively. In some embodiments, the electrical parameters of the pre-doped gates 71 are measured by applying a test voltage at the first pad 731. The electrical parameters are capacitance, breakdown voltage, or saturation current.

[0058] Please refer to Figure 7 And in step S123, the doping amount of the second test unit 200 corresponding to the electrical parameters that meet the process requirements is calculated to obtain the process window for the doping amount.

[0059] Please see Figure 13 This is a flowchart illustrating the steps of the fourth embodiment of the pre-doping process testing method described in this invention. Figure 13 As shown, the pre-doping process testing method further includes the following steps: Step S131, providing a third test unit, wherein the third test unit adopts the third test unit described in this invention; Step S132, testing the electrical parameters of each pre-doped gate of the third test unit respectively, and determining whether there is an electrical influence from the edge shadow of the pre-doping process.

[0060] Please refer to Figure 9 And in step S131, a third test unit 300 is provided, wherein the third test unit 300 adopts the present invention. Figure 9 The third test unit 300 is shown. The edge of the pre-doped gate 91 of the third test unit 300 has a first distance to the edge of the first region 901. The first distances in multiple first regions 901 gradually increase. One of the first regions 901 has a first distance value of a standard value X1, while the other first regions 901 have first distances valued as scaled values ​​of the standard value X1 (e.g., 0.8*X1, 0.9*X1, 1.05*X1, etc.).

[0061] Please refer to Figure 9 Step S132: Test the electrical parameters of each pre-doped gate 91 in the third test unit 300 to determine whether the edge shadow of the pre-doping process has an electrical effect. In some embodiments, if the first distance of the third test unit 300 with the optimal electrical parameters is the standard value X1, then it is determined that the edge shadow of the pre-doping process has no electrical effect; if the first distance of the third test unit 300 with the optimal electrical parameters is a scaled value of the standard value X1 (e.g., 1.05*X1), then it is determined that the edge shadow of the pre-doping process has an electrical effect, and the value of the first distance is modified to the scaled value (i.e., 1.05*X1).

[0062] Wherein, the standard value X1 is the first distance obtained through existing technology. The above technical solution verifies whether there is an electrical influence on the edge shadow of the pre-doped process by setting scaling values ​​of multiple standard values ​​and measuring the electrical properties of multiple test structures, and obtains the optimal value of the first distance through testing.

[0063] The above technical solutions can also be extended to the electrical effects of SRAM bit cells, wells, lightly doped drains (LDD), heavily doped (Plus), and pre-doped mask boundary checks.

[0064] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0065] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.

[0066] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0067] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pre-doped process test structure, characterized in that, include: A substrate, wherein an active region is defined in the substrate, the active region including a first region and a second region; A pre-doped gate is formed on the surface of the active region in the first region, extending along a first direction and having a first critical dimension along a second direction; wherein the first direction and the second direction form an angle; a non-pre-doped gate is formed on the surface of the active region in the second region, extending along the first direction and having a second critical dimension along the second direction; wherein, by testing the first critical dimension and the second critical dimension, the critical dimension deviation caused by the pre-doping process can be obtained; a second test unit is included, the second test unit including a plurality of first regions and a plurality of second regions arranged alternately along the second direction, a pre-doped gate is formed in each first region, and a non-pre-doped gate is formed in each second region; in the second test unit: the plurality of pre-doped gates are connected in parallel to a first pad, and the plurality of non-pre-doped gates are connected in parallel to a second pad, and by applying a test voltage at the first pad and the second pad, the presence of an electrical effect of the pre-doping process can be determined based on the measured electrical parameters.

2. The pre-doped process test structure according to claim 1, characterized in that, The test unit includes a first test unit comprising a first region and a second region arranged side-by-side along a second direction; the first region has a plurality of pre-doped gates, which extend along the first direction and are arranged along the second direction; the second region has a plurality of non-pre-doped gates, which extend along the first direction and are arranged along the second direction.

3. The pre-doped process test structure according to claim 1 or 2, characterized in that, The first critical dimension is the critical dimension of any of the pre-doped gates, or the first critical dimension is the average of the critical dimensions of all the pre-doped gates; the second critical dimension is the critical dimension of any of the non-pre-doped gates, or the second critical dimension is the average of the critical dimensions of all the non-pre-doped gates.

4. The pre-doped process test structure according to claim 1, characterized in that, Within the second test unit: a virtual gate is formed in at least one second region located at the edge of the active region, and the virtual gate is electrically connected to a third pad; by applying a test voltage to the second pad and the third pad, the validity of the test result can be determined based on the measured electrical parameters.

5. The pre-doped process test structure according to claim 1, characterized in that, The second test unit further includes: a contact structure column located between the pre-doped gate and the non-pre-doped gate, each contact structure column including a plurality of contact structures arranged along a first direction.

6. The pre-doped process test structure according to claim 1, characterized in that, The test includes a third test unit comprising a plurality of first regions spaced apart along a second direction; a pre-doped gate is formed in each of the first regions, and in the second direction, the edge of the pre-doped gate is at a first distance from the edge of the first region. The first distances in the plurality of first regions gradually increase, with the first distance in one of the first regions being a standard value and the first distances in the other first regions being scaled-down values ​​of the standard value. By testing the electrical parameters of the pre-doped gate in each of the third test units, it is determined whether the edge shadow of the pre-doping process has an electrical effect.

7. A method for testing pre-doped processes, characterized in that, The method includes the following steps: providing a second test unit, wherein the second test unit adopts the second test unit in the pre-doping process test structure as described in claim 1; measuring the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate; obtaining the difference between the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate to obtain the critical dimension deviation caused by the pre-doping process; applying a test voltage at the first pad and the second pad to measure the electrical parameters of the pre-doped gate and the non-pre-doped gate; and determining whether the pre-doping process has an electrical effect based on the electrical parameters of the pre-doped gate and the non-pre-doped gate.

8. The method according to claim 7, characterized in that, If the electrical parameters of the pre-doped gate and the non-pre-doped gate are the same, it is determined that the pre-doping process has no electrical effect; if the electrical parameters of the pre-doped gate are different from those of the non-pre-doped gate, it is determined that the pre-doping process has an electrical effect.

9. The method according to claim 7, characterized in that, Within the second test unit: a virtual gate is formed in at least one second region located at the edge of the active region, the virtual gate being electrically connected to a third pad; prior to the step of applying test voltages at the first and second pads to measure the electrical parameters of the pre-doped gate and the undoped gate, the following steps are further included: applying test voltages at the second and third pads to measure the electrical parameters; if the difference between the electrical parameters of the virtual gate and the electrical parameters of the undoped gate is less than a preset threshold, the test result is determined to be valid, and the step of applying test voltages at the first and second pads to measure the electrical parameters of the pre-doped gate and the undoped gate is executed.

10. The method according to claim 7, characterized in that, The method further includes the following steps: providing a plurality of second test units, wherein the pre-doped gates of the plurality of second test units have different doping amounts; testing the electrical parameters of the pre-doped gates of the plurality of second test units respectively; and statistically analyzing the doping amount of the second test units corresponding to the electrical parameters that meet the process requirements to obtain the process window for the doping amount.

11. The method according to claim 7, characterized in that, The electrical parameters are capacitance, breakdown voltage, or saturation current.

12. The method according to claim 7, characterized in that, The method also includes the following steps: providing a third test unit, wherein the third test unit adopts the third test unit in the pre-doped process test structure as described in claim 6; testing the electrical parameters of each pre-doped gate of the third test unit respectively, and determining whether there is an electrical influence from the edge shadow of the pre-doped process.

13. The method according to claim 12, characterized in that, If the first distance of the third test unit with the optimal electrical parameters is the standard value, it is determined that the edge shadow of the pre-doped process has no electrical effect; if the first distance of the third test unit with the optimal electrical parameters is a scaled value of the standard value, it is determined that the edge shadow of the pre-doped process has an electrical effect, and the value of the first distance is modified to the scaled value.

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