A fully differential class-d power amplifier circuit

Abstract

The application discloses a kind of full differential class-d power amplifier circuit, including error correction input circuit, triangular wave generation circuit, PWM modulation and digital shake-off circuit, full-bridge drive and filter output circuit and feedback network;The input of the error correction input circuit is connected with the output of the feedback network, and the output of the error correction input circuit and the triangular wave generation circuit is respectively connected with the input of the PWM modulation and digital shake-off circuit, the output of the PWM modulation and digital shake-off circuit is connected with the input of the full-bridge drive and filter output circuit, and the output of the full-bridge drive and filter output circuit is connected with the input of the feedback network.The application has the advantages of high power utilization efficiency, strong expansibility, large output power, low distortion, less noise and the like when amplifying low-frequency signal.

Description

Technical Field

[0001] This invention relates to the technical field of Class D power amplifiers, and in particular to a fully differential Class D power amplifier circuit. Background Technology

[0002] Most audio system design engineers are well aware of the power efficiency advantages of Class D amplifiers compared to Class A, Class B, and Class AB linear audio amplifiers. In Class AB linear amplifiers, the linear operation of the bias components and output transistors results in significant power losses, while in Class D amplifiers, the transistors are simply used as switches to direct current through the load, minimizing power loss in the output stage. Any power loss associated with Class D amplifiers is primarily attributable to the on-resistance of the output transistors, switching losses, and quiescent current overhead. Most of the power lost in the amplifier is dissipated as heat. Because Class D amplifiers can significantly reduce or eliminate the need for heatsinks, they are ideal for compact, high-power applications.

[0003] In the past, the power efficiency advantage of traditional PWM-based Class-D amplifiers compared to linear amplifiers was overshadowed by the cost of external filter components, EMI / EMC compatibility, and poor THD+N performance. However, most current-generation Class-D amplifiers utilize advanced modulation and feedback techniques to mitigate these issues.

[0004] With appropriate circuit parameter selection, noise shaping feedback technology and advanced topologies can be used to transfer PWM noise at the output of a Class-D amplifier to a higher frequency without altering the input low-frequency signal, thus achieving signal-noise separation. Furthermore, compared to integrated Class-D amplifiers, Class-D amplifiers built using discrete components can output higher voltages, have greater power, and offer greater circuit scalability. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a fully differential Class-D power amplifier circuit that is structurally adjustable, highly scalable, high-performance, high-output-power, and low-noise. Based on existing Class-D power amplifiers, a Class-D power amplifier utilizing a fully differential circuit, full-bridge output, fully closed-loop feedback, and noise shaping loop is built using discrete components. This achieves advantages such as high power efficiency, strong scalability, high output power, low distortion, and low noise. Furthermore, this circuit uses the error shaping principle. After passing through the loop, PWM modulation noise is concentrated at high frequencies in the frequency spectrum, while the input signal is concentrated at low frequencies. Therefore, adding a low-pass filter to the output circuit can effectively filter out modulation noise and reduce circuit distortion.

[0006] To achieve the above objectives, the technical solution provided by this invention is as follows: a fully differential Class-D power amplifier circuit, comprising an error correction input circuit, a triangular wave generation circuit, a PWM modulation and digital debouncing circuit, a full-bridge drive and filter output circuit, and a feedback network; the input of the error correction input circuit is connected to the output of the feedback network, the outputs of the error correction input circuit and the triangular wave generation circuit are respectively connected to the inputs of the PWM modulation and digital debouncing circuit, the output of the PWM modulation and digital debouncing circuit is connected to the input of the full-bridge drive and filter output circuit, and the output of the full-bridge drive and filter output circuit is connected to the input of the feedback network;

[0007] The error correction input circuit is a double-integral error correction circuit, comprising an external positive input voltage, an external negative input voltage, first resistors for positive and negative terminals, first capacitors for positive and negative terminals, second resistors for positive and negative terminals, second capacitors for positive and negative terminals, a first fully differential operational amplifier, a second fully differential operational amplifier, and positive and negative feedback voltages. The external positive input voltage is connected to the negative input terminal of the first fully differential operational amplifier through the first positive resistor. The first positive capacitor is connected between the negative input terminal and the positive output terminal of the first fully differential operational amplifier. The positive output terminal is connected to the negative input terminal of the second fully differential operational amplifier through the second positive resistor. The second positive capacitor is connected between the negative input terminal and the positive output terminal of the second fully differential operational amplifier. The positive feedback voltage is then fed from the positive output terminal of the second fully differential operational amplifier. A positive output voltage is obtained at the output terminal; the external negative input voltage is connected to the positive input terminal of the first fully differential operational amplifier through a negative terminal first resistor, a negative terminal first capacitor is connected between the positive input terminal and the negative output terminal of the first fully differential operational amplifier, the negative output terminal is connected to the positive input terminal of the second fully differential operational amplifier through a negative terminal second resistor, a negative terminal second capacitor is connected between the positive input terminal and the negative output terminal of the second fully differential operational amplifier, and a negative output voltage is obtained from the negative output terminal of the second fully differential operational amplifier; the reference voltage pins of the first and second fully differential operational amplifiers are connected to half of the external control circuit power supply voltage; the negative feedback voltage taken from the feedback network is directly connected to the negative input terminal of the first fully differential operational amplifier, and the positive feedback voltage is directly connected to the positive input terminal of the first fully differential operational amplifier.

[0008] Furthermore, the triangular wave generating circuit includes fourth and fifth resistors for voltage division, third and fourth capacitors for voltage regulation, a third operational amplifier, a sixth resistor, a fifth capacitor, a first comparator, and seventh and eighth resistors. The external control circuit power supply voltage is connected to one end of the fourth resistor and one end of the third capacitor, and the other end of the fourth resistor is connected to the other end of the third resistor, and then grounded through the parallel fifth resistor and fourth capacitor. The common intermediate terminal of the fourth and fifth resistors and the third and fourth capacitors obtains the bias voltage, which is connected to the positive input terminal of the third operational amplifier and the negative input terminal of the first comparator. The positive input terminal of the first comparator is connected to one end of the seventh and eighth resistors, the other end of the seventh resistor is connected to the output of the first comparator, the other end of the eighth resistor is connected to the output of the third operational amplifier, the negative input terminal of the third operational amplifier is connected to one end of the sixth resistor and one end of the fifth capacitor, the other end of the sixth resistor is connected to the output of the first comparator, and the other end of the fifth capacitor is connected to the output of the third operational amplifier.

[0009] Furthermore, the PWM modulation and digital debouncing circuit includes second and third comparators, first and second four-channel NAND gate digital circuit chips, and first and second SR latches. The positive output voltage of the error correction input circuit is connected to the positive input terminal of the second comparator, and the negative output voltage is connected to the positive input terminal of the third comparator. The output of the third operational amplifier of the triangular wave generator circuit is connected to the negative input terminals of the second and third comparators. The output of the second comparator is connected to one input of the first NAND gate and two inputs of the third NAND gate of the first four-channel NAND gate digital circuit chip. The output of the third comparator is connected to one input of the first NAND gate and two inputs of the third NAND gate of the second four-channel NAND gate digital circuit chip. The other internal connections of the first and second four-channel NAND gate digital circuit chips are the same, specifically: First, The other input of the first NAND gate of the second four-channel NAND gate digital circuit chip is connected to the common end of the sixth and seventh resistors of the triangular wave generator circuit. The outputs are connected to the S input pins of the first and second SR latches respectively. All input pins of the second NAND gate of the first and second four-channel NAND gate digital circuit chips are connected to the common end of the sixth and seventh resistors of the triangular wave generator circuit. The output pins are connected to one input of the fourth NAND gate of the first and second four-channel NAND gate digital circuit chips respectively. The outputs of the third NAND gate of the first and second four-channel NAND gate digital circuit chips are connected to the other input of the fourth NAND gate of the first and second four-channel NAND gate digital circuit chips respectively. The outputs of the fourth NAND gate of the first and second four-channel NAND gate digital circuit chips are connected to the R pins of the first and second SR latches respectively.

[0010] Ultimately, the positive output of the first SR latch generates a positive control voltage at the positive terminal and the negative output generates a negative control voltage at the positive terminal, while the positive output of the second SR latch generates a positive control voltage at the negative terminal and the negative output generates a negative control voltage at the negative terminal.

[0011] Furthermore, the full-bridge drive and filter output circuit includes positive and negative half-bridge drive chips, fifteenth resistors for positive and negative high and low ends, sixteenth resistors for positive and negative ends, tenth capacitors for positive and negative high and low ends for filtering, eleventh, twelfth, and thirteenth capacitors for positive and negative ends for power supply regulation, dead-time adjustment resistors and capacitors for positive and negative ends, fourteenth capacitors for output bootstrapping, fifteenth capacitors for positive and negative ends for voltage regulation, fast recovery diodes for positive and negative ends, Schottky diodes for positive and negative high and low ends, and positive and negative high and low ends... The circuit consists of an NMOS transistor, a sixteenth capacitor for high-voltage regulation, a first inductor for low-pass filtering, a seventeenth capacitor for low-pass filtering, a seventeenth resistor for both positive and negative terminals, and an eighteenth resistor for current limiting at the positive, negative, and low terminals. The positive control voltage output from the PWM modulation and digital debouncing circuit is connected to the fifteenth resistor at the positive high terminal, the fifteenth resistor at the positive low terminal, the fifteenth resistor at the negative high terminal, and the fifteenth resistor at the negative low terminal.

[0012] The internal connection relationship between the full-bridge driver and the two half-bridge drivers of the filter output circuit is consistent, specifically:

[0013] The 15th resistor on the positive high end is connected to the INA pin of the positive half-bridge driver chip, and then grounded through the 10th capacitor on the positive high end. The 15th resistor on the positive low end is connected to the negative input terminal INB of the positive half-bridge driver chip, and then grounded through the 10th capacitor on the positive low end.

[0014] The DIS pin of the positive half-bridge driver chip is grounded through the sixteenth resistor on the positive side. At the same time, the positive dead time adjustment resistor and the positive dead time adjustment capacitor are connected in parallel. One end of the parallel connection is connected to the DT pin of the positive half-bridge driver chip, and the other end is grounded to adjust the dead time.

[0015] The positive half-bridge driver chip's pin VDDA is connected to the cathode of the positive fast recovery diode, and simultaneously connected to the positive half-bridge driver chip's pin VSSA through the fourteenth positive capacitor. The anode of the positive fast recovery diode is connected to the external bootstrap supply voltage through the seventeenth positive resistor. The positive half-bridge driver chip's pin VOUTA is connected to the gate of the positive high-side NMOS transistor through the eighteenth positive high-side resistor. The anode of the positive high-side Schottky diode is connected to the gate of the positive high-side NMOS transistor, and the cathode is connected to the positive half-bridge driver chip's pin VOUTA.

[0016] The positive half-bridge driver chip's pin VDDB is connected to the external bootstrap power supply voltage, and simultaneously connected to the positive half-bridge driver chip's pin VSSB through the fifteenth capacitor on the positive side. Pin VSSB is grounded. The positive half-bridge driver chip's pin VOUTB is connected to the gate of the positive low-side NMOS transistor through the eighteenth resistor on the positive low side. The anode of the positive low-side Schottky diode is connected to the gate of the positive low-side NMOS transistor, and the cathode is connected to the positive half-bridge driver chip's pin VOUTB. The positive half-bridge driver chip's pin VCCI is connected to the external chip power supply, and then grounded through the eleventh, twelfth, and thirteenth capacitors on the positive side. The external half-bridge power supply voltage is connected to the drain of the positive high-side NMOS transistor, and simultaneously grounded through the sixteenth capacitor on the positive side. The source of the positive high-side NMOS transistor is connected to the positive half-bridge driver chip's pin VSSA and the drain of the positive low-side NMOS transistor, and the source of the positive low-side NMOS transistor is grounded.

[0017] The VSSA pin of the positive half-bridge driver chip is connected to one end of the first positive inductor, and the other end of the first positive inductor is grounded through the seventeenth positive capacitor to form a low-pass filter; the positive voltage before filtering is obtained from the VSSA pin of the positive half-bridge driver chip, and the positive high voltage output voltage after filtering is obtained from the common connection point of the first positive inductor and the seventeenth positive capacitor.

[0018] The 15th resistor on the negative high end is connected to the INA pin of the negative half-bridge driver chip, and then grounded through the 10th capacitor on the negative high end. The 15th resistor on the negative low end is connected to the negative input terminal INB of the negative half-bridge driver chip, and then grounded through the 10th capacitor on the negative low end.

[0019] The negative half-bridge driver chip's pin DIS is grounded through the sixteenth resistor on the negative side. At the same time, the negative dead time adjustment resistor and the negative dead time adjustment capacitor are connected in parallel. One end of the parallel connection is connected to the negative half-bridge driver chip's pin DT, and the other end is grounded to adjust the dead time.

[0020] The negative half-bridge driver chip's pin VDDA is connected to the cathode of the negative fast recovery diode, and simultaneously connected to the negative half-bridge driver chip's pin VSSA through the fourteenth negative capacitor. The anode of the negative fast recovery diode is connected to the external bootstrap supply voltage through the seventeenth negative resistor. The negative half-bridge driver chip's pin VOUTA is connected to the gate of the negative high-side NMOS transistor through the eighteenth negative high-side resistor. The anode of the negative high-side Schottky diode is connected to the gate of the negative high-side NMOS transistor, and the cathode is connected to the negative half-bridge driver chip's pin VOUTA.

[0021] The VDDB pin of the negative half-bridge driver chip is directly connected to the external bootstrap power supply voltage, and is also connected to the VSSB pin of the negative half-bridge driver chip through the fifteenth capacitor of the negative terminal. The VSSB pin is grounded. The VOUTB pin of the negative half-bridge driver chip is connected to the gate of the negative low-side NMOS transistor through the eighteenth resistor of the negative low-side. The anode of the negative low-side Schottky diode is connected to the gate of the negative low-side NMOS transistor, and the cathode is connected to the VOUTB pin of the negative half-bridge driver chip. The VCCI pin of the negative half-bridge driver chip is connected to the external chip power supply, and then grounded through the eleventh, twelfth, and thirteenth capacitors of the negative terminal. The external half-bridge power supply voltage is connected to the drain of the negative high-side NMOS transistor, and is also grounded through the sixteenth capacitor of the negative terminal. The source of the negative high-side NMOS transistor is connected to the VSSA pin of the negative half-bridge driver chip and the drain of the negative low-side NMOS transistor, and the source of the negative low-side NMOS transistor is grounded.

[0022] The VSSA pin of the negative half-bridge driver chip is connected to one end of the negative first inductor, and the other end of the negative first inductor is grounded through the negative seventeenth capacitor to form a low-pass filter; the negative voltage before filtering is obtained from the VSSA pin of the negative half-bridge driver chip, and the negative high voltage output voltage after filtering is obtained from the terminal where the negative first inductor and the negative seventeenth capacitor are connected.

[0023] Furthermore, the feedback network includes a symmetrical resistor network composed of the ninth to twelfth resistors on both positive and negative terminals, the sixth to eighth capacitors for voltage regulation, the thirteenth and fourteenth resistors on both positive and negative terminals, and the ninth capacitor on both positive and negative terminals. The pre-filter voltage from the full-bridge drive and filter output circuit is taken and connected to one end of the ninth capacitor on the positive terminal. The other end of the ninth capacitor is connected to one end of the fourteenth resistor on the positive terminal, and the other end of the fourteenth resistor is connected to one end of the thirteenth resistor on the positive terminal. The other end of the thirteenth resistor is grounded. The high-voltage output voltage after filtering on the positive terminal is connected to one end of the twelfth resistor on the positive terminal. The other end of the twelfth resistor is connected to one end of the eighth capacitor and simultaneously to one end of the eleventh resistor on the positive terminal. The other end of the eleventh resistor is connected to one end of the seventh capacitor and simultaneously to one end of the tenth resistor on the positive terminal. The other end of the tenth resistor is connected to one end of the sixth capacitor and simultaneously to one end of the ninth resistor on the positive terminal. The other end of the resistor is connected to the common interface of the thirteenth and fourteenth resistors on the positive side, from which the positive feedback voltage is drawn. The voltage before filtering on the negative side is connected to one end of the ninth capacitor on the negative side. The other end of the ninth capacitor on the negative side is connected to one end of the fourteenth resistor on the negative side. The other end of the fourteenth resistor on the negative side is connected to one end of the thirteenth resistor on the negative side, and the other end of the thirteenth resistor on the negative side is grounded. The high-voltage output voltage after filtering on the negative side is connected to one end of the twelfth resistor on the negative side. The other end of the twelfth resistor on the negative side is connected to the other end of the eighth capacitor, and also to one end of the eleventh resistor on the negative side. The other end of the eleventh resistor on the negative side is connected to the other end of the seventh capacitor, and also to one end of the tenth resistor on the negative side. The other end of the tenth resistor on the negative side is connected to the other end of the sixth capacitor, and also to one end of the ninth resistor on the negative side. The other end of the ninth resistor on the negative side is connected to the common interface of the thirteenth and fourteenth resistors on the negative side, from which the negative feedback voltage is drawn.

[0024] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0025] This invention uses a novel Class-D power amplifier error correction technology, namely noise shaping technology, which shapes the noise of PWM modulation to a high frequency domain, so that it can be filtered out by the output low-pass filter. In addition, since this fully differential Class-D power amplifier circuit is designed using discrete components, the circuit has strong adjustability and has a higher output voltage compared to integrated Class-D power amplifiers, which is worth promoting. Attached Figure Description

[0026] Figure 1 This is the schematic diagram of a fully differential Class-D power amplifier circuit.

[0027] Figure 2 This is a schematic diagram of the error correction input circuit.

[0028] Figure 3 This is a schematic diagram of a triangular wave generator circuit.

[0029] Figure 4 This is a schematic diagram of a PWM modulation circuit.

[0030] Figure 5 This is a schematic diagram of a digital debouncing circuit.

[0031] Figure 6 This is a schematic diagram of the half-bridge drive output.

[0032] Figure 7 This is a schematic diagram of a feedback network.

[0033] Figure 8 The diagram shows the s-domain for error correction and noise shaping.

[0034] Figure 9 This is a schematic diagram of the comparator output signal error.

[0035] Figure 10 This is a diagram showing the derivation of the truth table for a digital circuit.

[0036] Figure 11 This is a schematic diagram showing the zero-pole location of the zero-input loop gain in the s-domain. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0038] This embodiment discloses a fully differential Class-D power amplifier circuit, employing novel Class-D power amplifier technology. Based on existing Class-D power amplifiers, it utilizes discrete components to build a Class-D power amplifier with a fully differential circuit, full-bridge output, fully closed-loop feedback, and noise shaping loop. This achieves advantages such as high power efficiency, strong scalability, high output power, low distortion, and low noise. Furthermore, the circuit employs error shaping principles. After passing through the loop, PWM modulation noise is concentrated at high frequencies in the frequency spectrum, while the input signal is concentrated at low frequencies. Therefore, adding a low-pass filter to the output circuit effectively filters out modulation noise and reduces circuit distortion.

[0039] like Figure 1 As shown, the fully differential Class-D power amplifier circuit includes an error correction input circuit I, a triangular wave generator circuit II, a PWM modulation and digital debouncing circuit III, a full-bridge drive and filter output circuit IV, and a feedback network V. The input of the error correction input circuit I is connected to the output of the feedback network V. The outputs of the error correction input circuit I and the triangular wave generator circuit II are respectively connected to the inputs of the PWM modulation and digital debouncing circuit III. The output of the PWM modulation and digital debouncing circuit III is connected to the input of the full-bridge drive and filter output circuit IV. The output of the full-bridge drive and filter output circuit IV is connected to the input of the feedback network V.

[0040] like Figure 2 As shown, the error correction input circuit I is a double-integral error correction circuit, which includes an external positive input voltage V. inP External negative input voltage V inN The first resistor R at the positive and negative terminals 1P R 1N The first capacitor C at the positive and negative terminals 1P C 1N The second resistor R at the positive and negative terminals 2P R 2N The second capacitor C at the positive and negative terminals 2P C 2N The first fully differential op-amp A1, the second fully differential op-amp A2, and the positive and negative feedback voltages V fbP V fbN External positive input voltage V inP Through the first resistor R at the positive terminal 1P Connect the negative input terminal of the first fully differential operational amplifier A1, and connect the positive terminal of the first fully differential operational amplifier A1 with a first capacitor C connected between the negative input terminal and the positive output terminal. 1P The positive output terminal is connected to the second positive resistor R. 2P Connect the negative input terminal of the second fully differential operational amplifier A2, and connect the positive terminal of the second fully differential operational amplifier A2 between the negative input terminal and the positive output terminal. 2P The positive output voltage V is obtained from the positive output terminal of the second fully differential operational amplifier A2. outP The external negative input voltage V inN Through the first resistor R at the negative terminal 1N Connect the positive input terminal of the first fully differential operational amplifier A1, and connect the negative terminal of the first fully differential operational amplifier A1 to the negative terminal of the first capacitor C. 1N The negative output terminal is connected to the second negative resistor R. 2N Connect the positive input terminal of the second fully differential operational amplifier A2, and connect the negative terminal of the second fully differential operational amplifier A2 between the positive input terminal and the negative output terminal. 2N The negative output voltage V is obtained from the negative output terminal of the second fully differential operational amplifier A2. outN The reference voltage pins of the first and second fully differential operational amplifiers A1 and A2 are connected to the external control circuit power supply voltage V. CC Half of; the negative feedback voltage V taken from the feedback network V. fbN Directly connected to the negative input terminal of the first fully differential op-amp A1, with positive feedback voltage V fbP It is directly connected to the positive input terminal of the first fully differential op-amp A1.

[0041] Through the above circuit connection, the circuit can realize the input of differential signals and perform differential feedback, which can play the role of error correction input and noise shaping.

[0042] like Figure 3 As shown, the triangular wave generating circuit II includes fourth and fifth resistors R4 and R5 for voltage division, third and fourth capacitors C3 and C4 for voltage regulation, third operational amplifier A3, sixth resistor R6, fifth capacitor C5, first comparator A4, and seventh and eighth resistors R7 and R8; the external control circuit power supply voltage V CC The resistors are connected to one end of the fourth resistor R4 and one end of the third capacitor C3, respectively. The other end of the fourth resistor R4 is connected to the other end of the third resistor C3. Then, the resistors are grounded through the fifth resistor R5 and the fourth capacitor C4 connected in parallel. The bias voltage V is obtained from the midpoint of the common connection between the fourth and fifth resistors R4 and R5 and the third and fourth capacitors C3 and C4. bias The bias voltage V bias The positive input terminal of the third operational amplifier A3 and the negative input terminal of the first comparator A4 are respectively connected; the positive input terminal of the first comparator A4 is connected to one end of the seventh and eighth resistors R7 and R8, the other end of the seventh resistor R7 is connected to the output of the first comparator A4, and the other end of the eighth resistor R8 is connected to the output of the third operational amplifier A3. The negative input terminal of the third operational amplifier A3 is connected to one end of the sixth resistor R6 and the fifth capacitor C5, the other end of the sixth resistor R6 is connected to the output of the first comparator A4, and the other end of the fifth capacitor C5 is connected to the output of the third operational amplifier A3.

[0043] like Figure 4 and Figure 5 As shown, the PWM modulation and digital debouncing circuit III includes second and third comparators A5 and A6, first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002, and first and second SR latches 74HCT741 and 74HCT742; the positive output voltage V of the error correction input circuit I is converted into voltage V. outP When connected to the positive input terminal of the second comparator A5, the negative output voltage V is obtained. outN Connect the positive input terminal of the third comparator A6, and connect the output of the third operational amplifier A3 of the triangular wave generator circuit II to the negative input terminals of the second and third comparators A5 and A6; connect the output of the second comparator A5 to the first NAND gate N of the first four-channel NAND gate digital circuit chip 74HC001. 11 An input and a third NAND gate N 13 The two inputs and the output of the third comparator A6 are connected to the first NAND gate of the second four-channel NAND gate digital circuit chip 74HC002. 21 An input and a third NAND gate N 23 The two inputs, the first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002, have the same internal connection relationship as other circuits. Specifically, the first NAND gate N of the first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002...11 N 21 The other input is connected to the shared end of the sixth resistor R6 and the seventh resistor R7 of the triangular wave generator circuit II. The outputs are connected to the S input pins of the first and second SR latches 74HCT741 and 74HCT742, respectively, and the N pins of the second NAND gates of the first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002. 12 N 22 All input pins are connected to the common end of the sixth resistor R6 and the seventh resistor R7 of the triangular wave generator circuit II. The output pins are respectively connected to the fourth NAND gate N of the first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002. 14 N 24 One input, the third NAND gate of the first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002 13 N 23 The outputs are respectively connected to the fourth NAND gate of the first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002. 14 N 24 Another input is the fourth NAND gate of the first and second four-channel NAND gate digital circuit chips 74HC001 and 74HC002. 14 N 24 The outputs are respectively connected to the R pins of the first and second SR latches 74HCT741 and 74HCT742;

[0044] Finally, the positive control voltage V is obtained from the positive output of the first SR latch 74HCT741. P+ The negative output obtains the negative control voltage V at the positive terminal. P- The negative control voltage V is obtained from the positive output of the second SR latch 74HCT742. N+ The negative output obtains the negative control voltage V at the negative terminal. N- .

[0045] like Figure 3 As shown, the square wave voltage U1 is the output of the first comparator A4, and the triangular wave voltage U2 is the output of the third operational amplifier A3. The square wave voltage U1 and the triangular wave voltage U2 are in the same period. These two voltages are used to debouncing the subsequent PWM modulator, and the noise at the critical change point of the comparator is suppressed to a certain extent by using the principle of digital circuit.

[0046] When the PWM modulation is compared with the comparator output in the digital debouncing circuit III, if the input signal is affected by noise interference from the triangular wave generator circuit II or external sources, the output square wave may experience waveform sag. Since the signals here are either 0 or 5V square waves, the electrical signals can be considered as a series of digital signals. Therefore, the waveform sag problem can be eliminated by using digital circuitry.

[0047] like Figure 9 As shown, the square wave voltage U1 is a square wave synchronized with the triangular wave voltage U2 in the triangular wave generator circuit II. When the square wave voltage U1 is high, the triangular wave voltage U2 is in the falling phase; when the square wave voltage U1 is low, the triangular wave voltage U2 is in the rising phase. outP This is the output waveform at the positive output terminal of the second operational amplifier A2 in the error correction input circuit I. Since the oscillation frequency of the triangular wave generator circuit II is much greater than the frequency of the input signal, U can be considered to be within several triangular wave oscillation cycles. outP It is a constant signal. cmpP The second comparator A5 will convert U outP The output obtained after comparing with the triangular wave voltage U2. Figure 9 The two obvious indentations in the middle are the noise signals when the input of the comparator is interfered with.

[0048] In the triangular wave generator circuit II, the rise and fall of the square wave and the triangular wave are synchronized. The high and low levels of the square wave voltage U1 correspond to the fall and rise of the triangular wave voltage U2, respectively. Since the positive terminals of the second and third comparators A5 and A6 in the triangular wave generator circuit II are respectively input to the voltages output by the integrators at the positive and negative output terminals of the second comparator A2 in the error correction circuit I, and the negative terminal is input to the triangular wave voltage U2, under normal circumstances, the comparator's output signal should change from low to high when the triangular wave voltage U2 rises, and from high to low when the triangular wave voltage U2 falls. Furthermore, the comparator's output will only change from low to high when the square wave voltage U1, which is synchronized with the triangular wave voltage U2, is high, and from high to low when it is low.

[0049] according to Figure 9 The location of the waveform dip can be used to list the output of the second comparator A5 and the square wave voltage U2 within one cycle, the true value Q of the current digital circuit output, and the true value Q of the next round of digital circuit output. * The table relationships, and combined with Figure 9 This can be summarized into a binary truth table, such as... Figure 10 As shown, suppose the output voltage U of the second comparator A5 at a certain moment is... cmpP The true value of the voltage is U cmp The true value of the square wave voltage U1 is U1. Based on the truth table, the digital circuit equations for the corresponding SR latch can be summarized as follows:

[0050] Q * =(U1+U cmp )Q+U1U cmp

[0051] Based on the input / output relationship of the SR latch:

[0052]

[0053] The true voltage values ​​corresponding to the S and R pins triggered by a low level can be obtained. It should be:

[0054]

[0055] In the above formula, a horizontal line above a character indicates that the true value is logically inverted. Using the result of the final formula (1), debouncing can be achieved through the designed digital circuit. The digital circuit used in the third comparator A6 is exactly the same as that used in the second comparator A5. In summary, using two 74LS00 chips, the outputs of the two comparators can be debounced.

[0056] The full-bridge drive and filter output circuit IV includes positive and negative half-bridge driver chips UCC21520. P UCC21520 N The fifteenth resistor R at the positive, negative high, and low ends 15PH R 15PL R 15NH R 15NL The sixteenth resistor R at both positive and negative terminals 16P R 16N The tenth capacitor C used for filtering, with positive, negative high, and low terminals. 10PH C 10PL C 10NH C 10NL The eleventh, twelfth, and thirteenth capacitors C are used for power supply voltage regulation. 11P C 12P C 13P C 11N C 12N C 13N The dead time adjustment resistor and capacitor R at the positive and negative terminals DTP R DTN C DTP C DTN The fourteenth capacitor C is used for the positive and negative terminals of the output bootstrap. 14P C 14N The fifteenth capacitor C, used for voltage regulation, has positive and negative terminals. 15P C 15N Fast recovery diodes D at positive and negative terminals 1P D 1N Positive, negative, high- and low-side Schottky diodes D2P D 3P D 2N D 3N Positive, negative, high-side, and low-side NMOS transistors Q 1P Q 2P Q 1N Q 2N The sixteenth capacitor C, used for high voltage regulation, is connected to the positive and negative terminals. 16P C 16N The first inductor L at the positive and negative terminals of the low-pass filter 1P L 1N The seventeenth capacitor C, used for low-pass filtering, is located at both the positive and negative terminals. 17P C 17N The seventeenth resistor R at both positive and negative terminals 17P R 17N and the eighteenth resistor R used for current limiting at the positive, negative high, and low ends. 18PH R 18PL R 18NH R 18NL The positive control voltage V output from the PWM modulation and digital debouncing circuit III is... P+ Connect the fifteenth resistor R on the positive high end 15PH Positive terminal negative control voltage V P- Connect the fifteenth resistor R at the positive low end 15PL The negative terminal controls the voltage V. N+ Connect the fifteenth resistor R to the negative high end 15NH Negative control voltage V at the negative terminal N- Connect the fifteenth resistor R to the negative low end 15NL ;

[0057] The internal connection relationship between the full-bridge driver and the two half-bridge drivers of the filter output circuit IV is consistent, specifically:

[0058] The fifteenth resistor R on the positive high end 15PH Connect to the positive half-bridge driver chip UCC21520 P The INA pin is then connected to the tenth capacitor C on the positive high-side. 10PH Grounded, the fifteenth resistor R at the positive low end 15PL Connect to the positive half-bridge driver chip UCC21520 P The negative input terminal INB, and then through the tenth capacitor C at the positive low end. 10PL Grounding;

[0059] Positive half-bridge driver chip UCC21520 P The DIS pin is connected to the sixteenth resistor R at the positive terminal. 16P Grounding, and simultaneously adjusting the positive dead time resistor R DTP and positive terminal dead time adjustment capacitor C DTPThe parallel connection is achieved by connecting one end of the parallel connection to the positive half-bridge driver chip UCC21520. P The dead time is adjusted by setting the DT pin to ground on the other end.

[0060] Positive half-bridge driver chip UCC21520 P The VDDA pin is connected to the positive terminal of the fast recovery diode D. 1P The cathode, simultaneously through the fourteenth capacitor C at the positive terminal. 14P Connect to the positive half-bridge driver chip UCC21520 P The pin VSSA, the positive terminal fast recovery diode D 1P The anode is connected to the positive terminal of the seventeenth resistor R. 17P Connect to external bootstrap power supply voltage V IN Positive half-bridge driver chip UCC21520 P The VOUTA pin is connected to the eighteenth resistor R on the positive high end. 18PH Connect to the positive high-side NMOS transistor Q 1P The gate of the high-side Schottky diode D 2P The anode of the NMOS transistor Q is connected to the positive high-side. 1P The gate and cathode are connected to the positive half-bridge driver chip UCC21520. P The VOUTA pin;

[0061] Positive half-bridge driver chip UCC21520 P The VDDB pin is connected to an external bootstrap power supply voltage V. IN Simultaneously, through the fifteenth capacitor C at the positive terminal 15P Connect to the positive half-bridge driver chip UCC21520 P The VSSB pin is grounded, and the positive half-bridge driver chip is UCC21520. P The VOUTB pin is connected to the eighteenth resistor R at the positive low end. 18PL Connect the positive low-side NMOS transistor Q 2P The gate of the Schottky diode D at the positive low end. 3P The anode of the NMOS transistor Q is connected to the positive low-side. 2P The gate and cathode are connected to the positive half-bridge driver chip UCC21520. P The VOUTB pin; positive half-bridge driver chip UCC21520 P The VCCI pin is connected to an external chip power supply V. DD Then through the positive terminals of capacitors C11, 12, and 13. 11P C 12P C 13P Grounded, external half-bridge supply voltage V BUS Connect to the positive high-side NMOS transistor Q 1PThe drain of the capacitor simultaneously passes through the sixteenth capacitor C at the positive terminal. 16P Grounded, positive high-side NMOS transistor Q 1P The source terminal of the positive half-bridge driver chip UCC21520 is connected. P The pins VSSA and the positive low-side NMOS transistor Q 2P The drain of the NMOS transistor Q is at the positive low end. 2P The source is grounded;

[0062] Positive half-bridge driver chip UCC21520 P The VSSA pin is connected to the positive terminal of the first inductor L. 1P One end, the positive terminal of the first inductor L 1P The other end is connected to the seventeenth capacitor C at the positive terminal. 17P Grounding forms a low-pass filter; the positive half-bridge driver chip UCC21520 P The positive terminal voltage V before filtering is obtained from the VSSA pin. outPpre From the positive terminal of the first inductor L 1P and the seventeenth capacitor C at the positive terminal 17P The common connection terminals obtain the high voltage output voltage V after positive terminal filtering. outPfilt ;

[0063] The fifteenth resistor R on the negative high end 15NH Access to negative half-bridge driver chip UCC21520 N The INA pin, and then through the negative high-side tenth capacitor C 10NH Grounded, negative low-side fifteenth resistor R 15NL Access to the negative half-bridge driver chip UCC21520 N The negative input terminal INB, and then through the tenth capacitor C at the negative low end. 10NL Grounding;

[0064] Negative half-bridge driver chip UCC21520 N The pin DIS is connected to the negative terminal via the sixteenth resistor R. 16N Grounding, and simultaneously adjusting the negative dead time resistor R DTN and the negative terminal dead time adjustment capacitor C DTN Parallel connection, with one end connected to the negative half-bridge driver chip UCC21520. N The dead time is adjusted by setting the DT pin to ground on the other end.

[0065] Negative half-bridge driver chip UCC21520 N The VDDA pin is connected to the negative terminal of the fast recovery diode D. 1N The cathode, and simultaneously through the fourteenth capacitor C at the negative terminal. 14N Access to negative half-bridge driver chip UCC21520 N The pin VSSA, the negative terminal fast recovery diode D1N The anode passes through the negative terminal of the seventeenth resistor R. 17N Connect to external bootstrap power supply voltage V IN Negative-side half-bridge driver chip UCC21520 N The VOUTA pin is connected to the negative high-side eighteenth resistor R. 18NH Connecting the negative high-side NMOS transistor Q 1N The gate of the negative high-side Schottky diode D 2N The anode of the NMOS transistor Q is connected to the negative high-side. 1N The gate and cathode are connected to the negative half-bridge driver chip UCC21520. N The VOUTA pin;

[0066] Negative half-bridge driver chip UCC21520 N The VDDB pin is directly connected to the external bootstrap power supply voltage V. IN Simultaneously, through the fifteenth capacitor C at the negative terminal 15N Access to negative half-bridge driver chip UCC21520 N The VSSB pin is grounded, and the negative half-bridge driver chip is UCC21520. N The VOUTB pin is connected to the negative low-side eighteenth resistor R. 18NL Connect the negative low-side NMOS transistor Q 2N The gate of the negative low-side Schottky diode D 3N The anode of the NMOS transistor Q is connected to the negative low-side. 2N The gate and cathode are connected to the negative half-bridge driver chip UCC21520. N The VOUTB pin; the negative half-bridge driver chip UCC21520 N The VCCI pin is connected to the external chip power supply V. DD Then through the negative terminals of capacitors C11, 12, and 13. 11N C 12N C 13N Grounded, external half-bridge supply voltage V BUS Connecting the negative high-side NMOS transistor Q 1N The drain of the capacitor, and simultaneously through the sixteenth capacitor C at the negative terminal. 16N Grounded, negative high-side NMOS transistor Q 1N The source terminal of the negative half-bridge driver chip UCC21520 is connected. N The pins VSSA and negative low-side NMOS transistor Q 2N The drain of the negative low-side NMOS transistor Q 2N The source is grounded;

[0067] Negative half-bridge driver chip UCC21520 N The VSSA pin is connected to the negative terminal of the first inductor L. 1NOne end, the negative end of the first inductor L 1N The other end is connected to the negative terminal of the seventeenth capacitor C. 17N Grounding forms a low-pass filter; the negative half-bridge driver chip UCC21520 is used. N The negative terminal voltage V is obtained from the VSSA pin before filtering. outNpre From the negative terminal, the first inductor L 1N and the seventeenth capacitor C at the negative terminal 17N The common connection endpoints obtain the negative terminal filtered high voltage output voltage V. outNfilt .

[0068] Due to the capacitive effect of MOSFETs, they require a certain amount of time to fully turn on and off. This results in power loss through the MOSFETs, therefore a certain dead time is needed between the turn-on and turn-off of the upper and lower MOSFETs. Figure 6 As shown, capacitor C is connected to the DT pin of the UCC21520 chip. DT The capacitance value needs to be greater than or equal to 2.2nF, and the resistor R DT The resistor value connected to the DT pin in the UCC21520 chip is used to adjust the dead time t of the two MOSFETs. DT Dead time t DT (ns) is in nanoseconds, and its calculation formula is given by equation (2).

[0069] t DT (ns)≈10×R DT (2)

[0070] The external power supply V is connected to the VCCI pin of the UCC21520 chip. DD A suitable 12V power supply can be selected, and capacitor C can be used. 11 C 12 and C 13 To stabilize the power supply voltage.

[0071] Next, we'll explain the principle of the bootstrap capacitor. At a certain moment, the low-side NMOS transistor is turned on, and the high-side NMOS transistor is turned off. At this time, the capacitor connected to the high-side NMOS transistor pulls the midpoint between the two transistors to ground, and the fast recovery diode charges the bootstrap capacitor. After a period of time, the low-side NMOS transistor turns off, and the fast recovery diode also turns off. At this point, the bootstrap capacitor of the high-side NMOS transistor acts as a voltage source, serving as the power supply for the chip's internal drive, controlling the high-side NMOS transistor. Regardless of changes in the source voltage of the high-side NMOS transistor, the chip's internal drive can use the bootstrap circuit to turn the high-side NMOS transistor on.

[0072] like Figure 6 As shown, an eighteenth resistor R for current limiting is connected to the base of the high-side and low-side NMOS transistors. 18The circuit includes high-side and low-side Schottky diodes D2 and D3, and a current-limiting resistor to mitigate the surge voltage from the gate-drain capacitor when the NMOS transistor is turned on. The Schottky diodes also help to release the charge from the gate-drain capacitor when the NMOS transistor is turned off. Finally, an LC filter is used to implement low-pass filtering, resulting in a smoother system output.

[0073] like Figure 7 As shown, the feedback network V includes resistors R from the ninth to the twelfth terminals at both the positive and negative ends. 9P R 9N R 10P R 10N R 11P R 11N R 12P R 12N The symmetrical resistor network consists of capacitors C6, C7, and C8 (sixth to eighth terminals) used for voltage regulation, and resistors R (thirteenth and fourteenth terminals) for positive and negative terminals. 13P R 13N R 14P R 14N and the ninth capacitor C at both positive and negative terminals 9P C 9N The positive terminal voltage V before filtering is taken from the full-bridge drive and filter output circuit IV. outPpre Connect to the ninth capacitor C at the positive terminal 9P One end, the positive terminal of the ninth capacitor C 9P The other end is connected to the fourteenth resistor R at the positive terminal. 14P One end, the fourteenth resistor R at the positive terminal 14P The other end is connected to the positive terminal of the thirteenth resistor R. 13P One end, the positive terminal, the thirteenth resistor R 13P The other end is grounded; the high-voltage output voltage V after filtering at the positive end outPfilt Connect to the twelfth resistor R at the positive terminal 12P One end, the positive terminal, the twelfth resistor R 12P Connect the other end to one end of the eighth capacitor C8, and simultaneously connect the positive terminal of the eleventh resistor R. 11P One end, the eleventh resistor R at the positive terminal 11P Connect the other end to one end of the seventh capacitor C7, and simultaneously connect the positive terminal of the tenth resistor R. 10P One end, the tenth resistor R (positive terminal) 10P Connect the other end to one end of the sixth capacitor C6, and simultaneously connect it to the positive terminal of the ninth resistor R. 9P One end, the positive terminal, the ninth resistor R 9P The other end is connected to the thirteenth and fourteenth resistors R at the positive terminal. 13P R 14P A common interface from which a positive feedback voltage V is derived. fbP The voltage V before filtering at the negative terminal outNpreConnect to the negative terminal of the ninth capacitor C 9N One end, the negative terminal of the ninth capacitor C 9N The other end is connected to the negative terminal of the fourteenth resistor R. 14N One end, the negative end, the fourteenth resistor R 14N The other end is connected to the negative terminal of the thirteenth resistor R. 13N One end, the negative end, the thirteenth resistor R 13N The other end is grounded; the high-voltage output voltage V after filtering at the negative end. outNfilt Connect to the twelfth resistor R at the negative terminal 12N One end, the negative end, the twelfth resistor R 12N Connect the other end to the other end of the eighth capacitor C8, and simultaneously connect the negative terminal of the eleventh resistor R. 11N One end, the negative terminal, the eleventh resistor R 11N Connect the other end to the other end of the seventh capacitor C7, and simultaneously connect the negative terminal of the tenth resistor R. 10N One end, the negative terminal, the tenth resistor R 10N Connect the other end to the other end of the sixth capacitor C6, and simultaneously connect the negative terminal of the ninth resistor R. 9N One end, the negative end, the ninth resistor R 9N The other end is connected to the negative terminal, resistors thirteenth and fourteenth, R. 13N R 14N A common interface from which the negative feedback voltage V is derived. fbN .

[0074] The error correction input circuit I, combined with the feedback network V, utilizes noise shaping technology. To explain this principle, the entire circuit needs to be abstracted into a block diagram of a Laplace transform. In the Laplace transform domain (hereinafter referred to as the s-domain, where s = σ + jω is an arbitrary complex number, σ is a real number, ω is a real angular frequency, and j is an imaginary number), j... 2 The analysis is performed in the range of -1). To simplify the analysis, a single-ended input signal V is used here. inP The analysis shows that the feedback signal is taken from the negative output, which is V. fbN Analysis yields the following results: Figure 8 The s-domain block diagram shown has two integrators (represented by 1 / s) at the input, which are integrated circuits built from differential operational amplifiers. The scaling factor K is the amplification factor of the subsequent full-bridge output. The first resistor R at the positive and negative terminals... 1P R 1N The resistance value is R1, and the second resistor R is at the positive and negative terminals. 2P R 2N The resistance is R2, and the first capacitor C is at both the positive and negative terminals. 1P C 1N The capacitance value is C1, and the second capacitor C is located at both the positive and negative terminals. 2P C 2NThe capacitance value is C2. The modulation noise introduced by the PWM modulation and digital debouncing circuit after converting the input signal into a square wave is V. n V out The output voltage is given by the feedback impedance Z of the feedback network V. f It is also the reciprocal of the circuit feedback coefficient, F = 1 / Z f After calculation, the transfer functions of the block diagram abstracted from this circuit can be obtained as follows:

[0075] Input signal V inP transfer function H signal (s):

[0076]

[0077] Modulation noise V n transfer function H noise (s):

[0078]

[0079] Analysis of the frequency characteristics of these two transfer functions reveals that the transfer function of the modulation noise is a high-pass filter. Therefore, using an LC filter at the output can effectively filter out the noise generated during the modulation process. The transfer function of the input signal, however, is a low-pass filter, and the amplification factor of the input signal at low frequencies is Re{Z}. f} / R1,Re{Z f} represents Z f The real part of the amplification factor of this fully differential Class-D power amplifier circuit can be adjusted by changing the feedback impedance value Z of the feedback network. f To make adjustments.

[0080] Feedback networks can adjust the feedback coefficient F = 1 / Z of the feedback path. f This affects the value of the expression for the forward signal transfer function, which can then be used to adjust the closed-loop gain. Furthermore, observing the aforementioned transfer function equation (1), it can be found that if Z... f If ω = 0, then the transfer function diverges at the angular frequency ω = 0, and the system is unstable at this point. By connecting a set of capacitor networks and adjusting the feedback coefficient F = 1 / Z... f Let F be a set of feedback coefficients with imaginary parts composed of capacitor networks, then the position of the denominator poles in equation (1) can be adjusted to improve the stability of the system.

[0081] Next, we analyze the stability of the loop. Through loop analysis, if the feedback capacitor C in the feedback network... 9P C 9N The value is C f The resistor R connected in series with the capacitor 14P R 14NThe value is R Cf With resistors R9 and R 10 R 11 R 12 The series resistance is R f Let H(s) be the forward path system function and G(s) be the feedback path system function. The open-loop transfer function of this feedback loop is:

[0082]

[0083] From equation (5) above, we can see that the feedback system has 3 poles and 1 zero. The two poles located at s=0 produce a 180° phase difference, but, as Figure 11 As shown, since the zero point is always to the right of the other pole, the phase shift of this system at low frequencies is far from 180° and can never reach 180°. At high frequencies, its amplitude is less than 1. Therefore, theoretical analysis shows that this system is loop-stable at angular frequencies ω≠0. Simulation and experimental tests confirm that the system is also stable at angular frequencies ω=0, thus this feedback network provides high stability for the system.

[0084] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A fully differential class-d power amplifier circuit, characterized by: It includes error correction input circuit (I), triangular wave generating circuit (II), PWM modulation and digital dithering circuit (III), full-bridge drive and filter output circuit (IV) and feedback network (V); the output of the feedback network (V) is connected to the input of the error correction input circuit (I), the outputs of the error correction input circuit (I) and the triangular wave generating circuit (II) are respectively connected to the inputs of the PWM modulation and digital dithering circuit (III), the output of the PWM modulation and digital dithering circuit (III) is connected to the input of the full-bridge drive and filter output circuit (IV), and the output of the full-bridge drive and filter output circuit (IV) is connected to the input of the feedback network (V); The error correction input circuit (I) is a double integral error correction circuit, which comprises external positive input voltage (V inP ), external negative input voltage (V inN ), positive and negative first resistance (R 1P , R 1N ), positive and negative first capacitance (C 1P , C 1N ), positive and negative second resistance (R 2P , R 2N ), positive and negative second capacitance (C 2P , C 2N ), first full differential operational amplifier (A1), second full differential operational amplifier (A2) and positive and negative feedback voltage (V fbP , V fbN ). The external positive input voltage (V inP ) is connected to the negative input end of the first full differential operational amplifier (A1) through the positive first resistance (R 1P ), the negative input end of the first full differential operational amplifier (A1) is connected with the positive output end through the positive first capacitance (C 1P ), the positive output end is connected to the negative input end of the second full differential operational amplifier (A2) through the positive second resistance (R 2P ), the negative input end of the second full differential operational amplifier (A2) is connected with the positive output end through the positive second capacitance (C 2P ), and the positive output voltage (V outP ) is obtained from the positive output end of the second full differential operational amplifier (A2); the external negative input voltage (V inN ) is connected to the positive input end of the first full differential operational amplifier (A1) through the negative first resistance (R 1N ), the positive input end of the first full differential operational amplifier (A1) is connected with the negative output end through the negative first capacitance (C 1N ), the negative output end is connected to the positive input end of the second full differential operational amplifier (A2) through the negative second resistance (R 2N ), the positive input end of the second full differential operational amplifier (A2) is connected with the negative output end through the negative second capacitance (C 2N ), and the negative output voltage (V outN ) is obtained from the negative output end of the second full differential operational amplifier (A2); the reference voltage pin of the first and second full differential operational amplifiers (A1, A2) is connected to half of the external control circuit power supply voltage (V CC ); the negative feedback voltage (V fbN ) taken from the feedback network (V) is directly connected to the negative input end of the first full differential operational amplifier (A1), and the positive feedback voltage (V fbP ) is directly connected to the positive input end of the first full differential operational amplifier (A1). The triangular wave generating circuit (II) includes fourth and fifth resistors (R4, R5) for voltage division, third and fourth capacitors (C3, C4) for voltage regulation, a third operational amplifier (A3), a sixth resistor (R6), a fifth capacitor (C5), a first comparator (A4), and seventh and eighth resistors (R7, R8); the external control circuit power supply voltage (V CC The first two resistors (R4 and R5) are connected to one end of the fourth resistor (R4) and the second end of the third capacitor (C3), respectively. The second end of the fourth resistor (R4) is connected to the other end of the third resistor (C3), and then grounded through the fifth resistor (R5) and the fourth capacitor (C4) connected in parallel. The bias voltage (V) is obtained at the midpoint of the common connection of the fourth and fifth resistors (R4 and R5) and the third and fourth capacitors (C3 and C4). bias The bias voltage (V) bias The first and second operational amplifiers (A3 and A4) are connected to the positive input terminal of the third operational amplifier (A3) and the negative input terminal of the first comparator (A4), respectively. The positive input terminal of the first comparator (A4) is connected to one end of the seventh and eighth resistors (R7 and R8), the other end of the seventh resistor (R7) is connected to the output of the first comparator (A4), and the other end of the eighth resistor (R8) is connected to the output of the third operational amplifier (A3). The negative input terminal of the third operational amplifier (A3) is connected to one end of the sixth resistor (R6) and the fifth capacitor (C5), respectively. The other end of the sixth resistor (R6) is connected to the output of the first comparator (A4), and the other end of the fifth capacitor (C5) is connected to the output of the third operational amplifier (A3). The PWM modulation and digital anti-shake circuit (III) comprises a second and third comparator (A5, A6), a first and second four-channel NAND digital circuit chip (74HC001, 74HC002) and a first and second SR latch (74HCT741, 74HCT742); the positive output voltage (V outP ) of the error correction input circuit (I) is connected to the positive input end of the second comparator (A5), the negative output voltage (V outN ) is connected to the positive input end of the third comparator (A6), the output of the third operational amplifier (A3) of the triangular wave generation circuit (II) is connected to the negative input end of the second and third comparator (A5, A6); the output of the second comparator (A5) is connected to one input of the first NAND gate (N 11 ) and two inputs of the third NAND gate (N 13 ) of the first four-channel NAND digital circuit chip (74HC001), the output of the third comparator (A6) is connected to one input of the first NAND gate (N 21 ) and two inputs of the third NAND gate (N 23 ) of the second four-channel NAND digital circuit chip (74HC002), the other internal connection relationship of the first and second four-channel NAND digital circuit chip (74HC001, 74HC002) is consistent, specifically: the other input of the first and second NAND gate (N 11 , N 21 ) of the first and second four-channel NAND digital circuit chip (74HC001, 74HC002) is connected to one end of the sixth resistor (R6) and the seventh resistor (R7) of the triangular wave generation circuit (II), the outputs are connected to the S input pin of the first and second SR latch (74HCT741, 74HCT742) respectively, all the input pins of the second NAND gate (N 12 , N 22 ) of the first and second four-channel NAND digital circuit chip (74HC001, 74HC002) are connected to one end of the sixth resistor (R6) and the seventh resistor (R7) of the triangular wave generation circuit (II), the output pins are connected to one input of the fourth NAND gate (N 14 , N 24 ) of the first and second four-channel NAND digital circuit chip (74HC001, 74HC002) respectively, the outputs of the third NAND gate (N 13 , N 23 ) of the first and second four-channel NAND digital circuit chip (74HC001, 74HC002) are connected to the fourth NAND gate (N 14 , N 24 ) and the output of the fourth NAND gate (N4) of the first, second, third and fourth NAND gate digital circuit chip (74HC001, 74HC002) is connected to the R pin of the first and second SR latch (74HCT741, 74HCT742) respectively. 14 , N 24 ) and the output of the fourth NAND gate (N4) of the first, second, third and fourth NAND gate digital circuit chip (74HC001, 74HC002) is connected to the R pin of the first and second SR latch (74HCT741, 74HCT742) respectively. Finally, the positive end positive control voltage (V P+ ) is obtained from the positive output of the first SR latch (74HCT741), the positive end negative control voltage (V P- ) is obtained from the negative output, the negative end positive control voltage (V N+ ) is obtained from the positive output of the second SR latch (74HCT742), and the negative end negative control voltage (V N- ) is obtained from the negative output.

2. The fully differential class-d power amplifier circuit of claim 1, wherein: The full-bridge drive and filter output circuit (IV) includes positive and negative half-bridge drive chips (UCC21520 P , UCC21520 N ), positive and negative high and low end fifteenth resistors (R 15PH , R 15PL , R 15NH , R 15NL ), positive and negative sixteenth resistors (R 16P , R 16N ), positive and negative high and low end tenth capacitors (C 10PH , C 10PL , C 10NH , C 10NL ) for filtering, positive and negative eleventh, twelfth, and thirteenth capacitors (C 11P , C 12P , C 13P , C 11N , C 12N , C 13N ) for power supply voltage stabilization, positive and negative dead time adjustment resistors and capacitors (R DTP , R DTN , C DTP , C DTN ), positive and negative fourteenth capacitors (C 14P , C 14N ) for output bootstrap, positive and negative fifteenth capacitors (C 15P , C 15N ) for voltage stabilization, positive and negative fast recovery diodes (D 1P , D 1N ), positive and negative high and low end Schottky diodes (D 2P , D 3P , D 2N , D 3N ), positive and negative high and low end NMOS transistors (Q 1P , Q 2P , Q 1N , Q 2N ), positive and negative sixteenth capacitors (C 16P , C 16N ) for high voltage stabilization, positive and negative first inductors (L 1P , L 1N ) for low pass filtering, positive and negative seventeenth capacitors (C 17P , C 17N ) for low pass filtering, positive and negative seventeenth resistors (R 17P , R 17N ), and positive and negative high and low end eighteenth resistors (R 18PH , R 18PL , R 18NH , R 18NL ); the PWM modulation is connected with the positive end positive control voltage (V P+ ) output by the digital anti-jitter circuit (III) to the positive high end fifteenth resistor (R 15PH ), the positive end negative control voltage (V P- ) is connected to the positive low end fifteenth resistor (R 15PL ), the negative end positive control voltage (V N+ ) is connected to the negative high end fifteenth resistor (R 15NH ), and the negative end negative control voltage (V N- ) is connected to the negative low end fifteenth resistor (R 15NL ). The internal connection relationship of the two half-bridge drives of the full-bridge drive and filter output circuit (IV) is consistent, specifically as follows: Positive high end fifteenth resistor (R 15PH ) is connected to the pin INA of the positive end half bridge drive chip (UCC21520 P ), and then connected to the ground through the positive high end tenth capacitor (C 10PH ); the positive low end fifteenth resistor (R 15PL ) is connected to the negative input end INB of the positive end half bridge drive chip (UCC21520 P ), and then connected to the ground through the positive low end tenth capacitor (C 10PL ); The pin DIS of the positive terminal half-bridge driving chip (UCC21520 P ) is grounded through the positive terminal sixteenth resistor (R 16P ), and the positive terminal dead time adjusting resistor (R DTP ) and the positive terminal dead time adjusting capacitor (C DTP ) are connected in parallel, one end of which is connected to the pin DT of the positive terminal half-bridge driving chip (UCC21520 P ) and the other end is grounded to adjust the dead time. pin VDDA of a positive end half-bridge drive chip (UCC21520 P ) is connected to the cathode of a positive end fast recovery diode (D 1P ), and pin VSSA of the positive end half-bridge drive chip (UCC21520 14P ) is connected to the positive end fourteenth capacitor (C P ), the anode of the positive end fast recovery diode (D 1P ) is connected to the positive end seventeenth resistor (R 17P ) for connecting to an external bootstrap supply voltage (V IN ), pin VOUTA of the positive end half-bridge drive chip (UCC21520 P ) is connected to the gate of a positive high end NMOS tube (Q 18PH ) through a positive high end eighteenth resistor (R 1P ), the anode of a positive high end Schottky diode (D 2P ) is connected to the gate of the positive high end NMOS tube (Q 1P ), and the cathode is connected to pin VOUTA of the positive end half-bridge drive chip (UCC21520 P ). Positive half-bridge driver chip (UCC21520) P The VDDB pin of the ) is connected to an external bootstrap power supply voltage (V IN Simultaneously, through the fifteenth capacitor (C) at the positive terminal... 15P ) Connect to the positive half-bridge driver chip (UCC21520) P The VSSB pin is grounded, and the positive half-bridge driver chip (UCC21520) is connected. P The VOUTB pin is connected to the eighteenth resistor (R) on the positive low side. 18PL Connect to the positive low-side NMOS transistor (Q) 2P The gate of the ) and the positive low-side Schottky diode (D) 3P The anode of the NMOS transistor (Q) is connected to the positive low-side of the transistor. 2P The gate and cathode of the UCC21520 half-bridge driver chip are connected to the positive terminal. P The VOUTB pin of the positive half-bridge driver chip (UCC21520) is used. P The VCCI pin is connected to an external chip power supply (V). DD Then, through the positive terminals of capacitors eleventh, twelfth, and thirteenth (C) 11P C 12P C 13P Grounding, external half-bridge supply voltage (V) BUS Connect to the positive high-side NMOS transistor (Q) 1P The drain of the capacitor is connected to the sixteenth capacitor (C) at the positive terminal. 16P Grounded, positive high-side NMOS transistor (Q) 1P The source terminal of the half-bridge driver chip (UCC21520) is connected to the positive terminal. P The pins of VSSA and the positive low-side NMOS transistor (Q) 2P The drain of the NMOS transistor (Q) at the positive low end. 2P The source of the electrode is grounded; The pin VSSA of a positive end half-bridge driving chip (UCC21520 P ) accesses one end of a positive end first inductor (L 1P ), and the other end of the positive end first inductor (L 1P ) is grounded through a positive end seventeenth capacitor (C 17P ) to form a low-pass filter; A positive terminal filter front voltage (V outPpre ) is obtained from a pin VSSA of a positive terminal half-bridge drive chip (UCC21520 P ), and a positive terminal filter rear high voltage output voltage (V outPfilt ) is obtained from a terminal point of a positive terminal first inductor (L 1P ) and a positive terminal seventeenth capacitor (C 17P ) connected together. A negative high-end fifteenth resistor (R 15NH ) is connected to the pin INA of a negative end half-bridge drive chip (UCC21520 N ), and then connected to ground through a negative high-end tenth capacitor (C 10NH ); a negative low-end fifteenth resistor (R 15NL ) is connected to the negative input end INB of the negative end half-bridge drive chip (UCC21520 N ), and then connected to ground through a negative low-end tenth capacitor (C 10NL ); The pin DIS of the negative terminal half-bridge driving chip (UCC21520 N ) is grounded through the negative terminal sixteenth resistor (R 16N ), and the negative terminal dead time adjusting resistor (R DTN ) and the negative terminal dead time adjusting capacitor (C DTN ) are connected in parallel, one end of which is connected to the pin DT of the negative terminal half-bridge driving chip (UCC21520 N ) and the other end is grounded to adjust the dead time. Pin VDDA of the negative half-bridge drive chip (UCC21520 N ) is connected to the cathode of the negative fast recovery diode (D 1N ), and pin VSSA of the negative half-bridge drive chip (UCC21520 14N ) is connected to the negative fourteenth capacitor (C N ), the anode of the negative fast recovery diode (D 1N ) is connected to the negative seventeenth resistor (R 17N ) for external bootstrap supply voltage (V IN ), pin VOUTA of the negative half-bridge drive chip (UCC21520 N ) is connected to the gate of the negative high-end NMOS tube (Q 18NH ) through the negative high-end eighteenth resistor (R 1N ), the anode of the negative high-end Schottky diode (D 2N ) is connected to the gate of the negative high-end NMOS tube (Q 1N ), and the cathode is connected to pin VOUTA of the negative half-bridge drive chip (UCC21520 N ). Negative half-bridge driver chip (UCC21520) N The VDDB pin of the ) is directly connected to the external bootstrap power supply voltage (V IN Simultaneously, through the fifteenth capacitor (C) at the negative terminal... 15N ) Connect to the negative half-bridge driver chip (UCC21520) N The VSSB pin is grounded, and the negative terminal is connected to the half-bridge driver chip (UCC21520). N The VOUTB pin is connected to the negative low-side eighteenth resistor (R). 18NL Connect to the negative low-side NMOS transistor (Q) 2N The gate of the ) and the negative low-side Schottky diode (D) 3N The anode of the NMOS transistor (Q) is connected to the negative low-side junction. 2N The gate and cathode of the half-bridge driver chip (UCC21520) are connected to the negative end. N The VOUTB pin of the negative half-bridge driver chip (UCC21520) is used. N The VCCI pin is connected to the external chip power supply (V). DD Then, through capacitors eleventh, twelfth, and thirteenth at the negative terminal (C) 11N C 12N C 13N Grounding, external half-bridge supply voltage (V) BUS Connect to the negative high-side NMOS transistor (Q) 1N The drain of the capacitor is connected to the negative terminal through the sixteenth capacitor (C). 16N Grounded, negative high-side NMOS transistor (Q) 1N The source terminal of the negative half-bridge driver chip (UCC21520) is connected to the source terminal. N The pins of VSSA and the negative low-side NMOS transistor (Q) 2N The drain of the NMOS transistor (Q) is the negative low-side transistor. 2N The source of the electrode is grounded; The pin VSSA of the negative half-bridge driving chip (UCC21520 N ) is connected to one end of the negative first inductor (L 1N ), the other end of the negative first inductor (L 1N ) is grounded through the negative seventeenth capacitor (C 17N ) to form a low-pass filter; the negative pre-filtering voltage (V outNpre ) is obtained from the pin VSSA of the negative half-bridge driving chip (UCC21520 N ), and the negative post-filtering high voltage output voltage (V outNfilt ) is obtained from the common connection point of the negative first inductor (L 1N ) and the negative seventeenth capacitor (C 17N ).

3. The fully differential class-d power amplifier circuit of claim 2, wherein: The feedback network (V) includes resistors (R) from the ninth to the twelfth terminals at both the positive and negative ends. 9P R 9N R 10P R 10N R 11P R 11N R 12P R 12N A symmetrical resistor network consisting of capacitors C6, C7, and C8 for voltage regulation, and resistors R13 and R24 for positive and negative terminals. 13P R 13N R 14P R 14N ) and the ninth capacitor (C) at both positive and negative terminals 9P C 9N ); Take the positive terminal voltage before filtering (V) from the full-bridge drive and filter output circuit (IV). outPpre Connect to the ninth capacitor (C) at the positive terminal 9P One end of the capacitor (C) is the positive terminal of the ninth capacitor. 9P The other end is connected to the fourteenth resistor (R) at the positive terminal. 14P One end of the resistor (R) is the fourteenth resistor on the positive terminal. 14P Connect the other end to the positive terminal of the thirteenth resistor (R). 13P One end of the resistor (R) is the positive terminal, and the thirteenth resistor (R) is the negative terminal. 13P The other end is grounded; the positive terminal filtered high voltage output voltage (V) outPfilt Connect to the twelfth resistor (R) at the positive terminal 12P One end of the resistor (R) is the positive terminal, and the twelfth resistor is the negative terminal. 12P Connect one end of the capacitor (C8) to one end of the other end of the capacitor, and simultaneously connect the positive terminal of the eleventh resistor (R). 11P One end of the resistor, the positive terminal of the eleventh resistor (R) 11P Connect one end of the capacitor (C7) to one end of the seventh capacitor, and simultaneously connect the positive terminal of the tenth resistor (R) to the other end. 10P One end of the resistor (R) is the positive terminal, and the tenth resistor is the negative terminal. 10P Connect one end of the capacitor (C6) to one end of the other end of the capacitor, and simultaneously connect the positive terminal of the ninth resistor (R). 9P One end of the resistor (R) is the positive terminal, and the ninth resistor is the negative terminal. 9P The other end is connected to the thirteenth and fourteenth resistors (R) at the positive terminal. 13P R 14P A common interface from which a positive feedback voltage (V) is derived. fbP ); Voltage before filtering at the negative terminal (V) outNpre Connect to the ninth capacitor (C) at the negative terminal 9N One end of the capacitor (C) is the negative terminal, and the ninth capacitor (C) is the negative terminal. 9N Connect the other end of the resistor to the negative terminal of the fourteenth resistor (R). 14N One end of the resistor, the negative end, is the fourteenth resistor (R). 14N Connect the other end to the negative terminal of the thirteenth resistor (R). 13N One end of the resistor, the negative end of the thirteenth resistor (R) 13N The other end is grounded; the negative end is filtered to produce a high-voltage output voltage (V). outNfilt Connect to the twelfth resistor (R) at the negative terminal 12N One end of the resistor (R) is the negative end. 12N Connect the other end of the capacitor (C8) to the other end of the capacitor, and simultaneously connect the negative terminal of the eleventh resistor (R). 11N One end of the resistor, the negative end of the eleventh resistor (R) 11N Connect the other end of the capacitor (C7) to the other end of the seventh capacitor, and simultaneously connect the negative terminal of the tenth resistor (R). 10N One end of the resistor (R) is the negative end. 10N Connect the other end of the capacitor (C6) to the other end of the sixth capacitor, and simultaneously connect the negative terminal of the ninth resistor (R). 9N One end of the resistor (R) is the negative end. 9N The other end is connected to the negative terminal of resistors thirteenth and fourteenth (R). 13N R 14N A common interface from which a negative feedback voltage (V) is derived. fbN ).

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